JPH0487423A - Decoding circuit - Google Patents

Abstract

PURPOSE:To draw out an optimal compression effect for every image which becomes an object by a simple circuit configuration by down-loading an optimal code table at every image which becomes an object, and thereafter, comparing the data set to a shift register and all code data in the code table, and reading out decoding data at the time when a pattern coincides. CONSTITUTION:Variable length code data is shifted by one bit each by a shift register 6, its shifted number of times is set as code length, and code data set to the shift register and all code data stored in a code data memory 3 in advance are compared successively by pattern matching at every code length by a pattern comparator 17. Subsequently, when the code data whose pattern coincidence is detected, at that time point, decoding data corresponding to its code data is read out of a decoding data memory 26 and an encoding processing related to one code data is finished, and in the case the code data whose pattern coincidence is not detected, furthermore, the code data is shifted by one bit, and it is compared with all code data of the next code length.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a decoding circuit that decodes variable length code data.

(Prior Art) Conventional variable-length code data decoding circuits generally handle a fixed code table of one type.
A decoding table having a tree structure is prepared in advance, and the tree structure is reversely searched while shifting code data bit by bit, and decoded data corresponding to the code data is finally found.

Therefore, although this conventional decoding circuit is capable of decoding by high-speed reverse search, on the other hand, since it has only one type of code table, it is not always possible to Optimal compression effect,
There is a problem in that the amount of code for image compression is not reduced very efficiently.

Therefore, in recent years, efforts have been made to improve coding efficiency by creating an optimal code table for each target image and mutually using the code tables, rather than necessarily limiting the code data to one type. This is something that is being considered.

If a conventional decoding circuit is to be operated according to this principle, it becomes necessary to prepare a large number of tree-structured decoding tables as described above for each information source to be handled.

In that case, not only does it take a huge amount of time and effort to create the decoding table, but it also requires the preparation of software and hardware for the processing, making the circuit structure complicated and large-scale.

(Problem to be Solved by the Invention) In this way, the conventional decoding circuit described above decodes encoded data by reverse searching a decoding table consisting of a tree structure. When trying to achieve the optimal compression effect, it is necessary to create a new decoding table consisting of a tree structure each time according to the target information, and the decoding circuit requires preparation of software and hardware for this purpose. The problem was that it was complicated and large-scale.

An object of the present invention is to provide a decoding circuit that can be implemented with the simplest possible configuration in order to eliminate this problem and provide optimal compression effects for each type of information.

[Structure of the invention]

(Means for Solving the Problems) A decoding circuit of the present invention includes a shift register that sequentially shifts and holds code data to be decoded, and a shift register that sequentially shifts and holds code data to be decoded, in a decoding circuit that decodes variable-length code data. a code length counter that counts the code length of , a code data storage means that stores the counted code data for each predetermined code length, a decoded data storage means that stores decoded data corresponding to the code data, and a stored code. data pattern comparing means for comparing patterns of data and code data held in the shift register for each same code length; and decoded data reading means for reading out decoded data corresponding to the code data with matching data patterns from the decoded data storage means. and comparison end detection means for detecting the end of comparison in the data pattern comparison means.

(Function) In the decoding circuit of the present invention, variable-length code data is shifted one bit at a time in a shift register, and the number of shifts is used as the code length, and the code data set in the shift register and the code data are stored in advance in the code data storage means. All the code data obtained are sequentially compared by pattern matching for each code length.

If code data with a matching pattern is detected, at that point, the decoded data corresponding to the code data is read out and the encoding process for one code data is completed,
If a code pig that matches the pattern is not detected, the code data is further shifted by one bit and compared with all code pigs of the next code length.

According to the decoding circuit of the present invention, a necessary amount of code data that can be applied to compression of various types of information is prepared in advance in the code data storage means for each code length, and this data can be sequentially downloaded and used. It can be operated by

Therefore, there is no need to create a decoding table for tree search each time as in the past, and the software and hardware for the processing can be kept to the minimum necessary.

(Example) Hereinafter, an example of the present invention will be described in detail based on the accompanying drawings.

First, FIG. 1 is a block diagram showing an embodiment of a decoding circuit according to the present invention.

The main components of this decoding circuit include a decoding control section 1
, code length memory 2, code data memory 3, code length counter 4, comparison code number counter 5, shift register 6, data shift F/F (flip-flop) 9, pattern comparator 17, data buffer 20-1.20- 2.20-
3. Decoded data memory 26, memory address selector 2
7-1.27-2, there is a decoded data F/F 30.

Next, its operation will be explained.

First, before starting the decoding operation, the decoding is controlled by the bus switching signal 21 to the memory address selector 27 (27-1, 27-2) and the data bus buffer 20 (20-1, 20-2, 2O-3). The memory address 22 and data bus 23 from the section 1 are connected to the code length data memory 2,
A data write signal 24 and a memory select signal 2 are supplied to the encoded data memory 3 and the decoded data memory 26, and are further supplied from the decoding control unit 1 in accordance with the timing.
5 (25-1, 25-2, 25-3), data is written into each of the memories 2, 3, and 26, respectively.

Examples of data downloaded to each memory 2, 3, and 26 by this process are shown in FIGS. 2 to 4.

Of these, FIG. 2 shows an example of the data contents of the code length data memory 2.

This code length data memory 2 stores the number of code data for each same code length, and in the case of this embodiment, 1
The number of bit code length decoded data is 0, 2 bits,
It can be seen that the numbers of decoded data of 3-bit code length and 12-bit code length are 2, 2, and 44, respectively.

Further, FIG. 3 shows an example of the data contents of the code data memory 3.

This code data memory 3 stores code data for each predetermined code length, and the code length is assigned to the upper part of the memory address, and the number of comparison codes is assigned to the lower part of the memory address.
A maximum of 255 pieces of 2-bit code length data can be stored in the 2-bit code data save area represented by address l**J.

In the case of this embodiment, it can be seen that two pieces of encoded data have been downloaded in advance to addresses 101 and 102 by the decoding control unit 1.

Further, FIG. 4 shows an example of the data contents of the decoded data memory 26.

In this decoded data memory 26, like the code data memory 3, a code length is assigned to the upper part of the memory address, and a comparison code number is assigned to the lower part of the memory address.

In the case of this embodiment, for example, each decoded data of 2-bit code length data is downloaded by the decoding control unit 1 to addresses 101 and 102 in one-to-one correspondence with the memory address of the code data memory 3. I understand.

After this download process is completed, the bus switching signal 21
Accordingly, each output of the code length counter 4 and the comparison code number counter 5 is supplied to each of the memories 2, 3, and 26.

Thereafter, the code length counter 4 is further controlled by the initialization signal 19.
The shift register 6 is initialized, and a series of decoding operations is started.

The shift register 6 is supplied with serial code data 7 and a transfer lock 8 .

First, when the 1-bit code data 7 is transferred to the shift register 6 and shifted by the lock 8, the data shift F/F
9 sets the data shift completion flag 10, and the decoding control unit 1
Instructs to temporarily stop data shifting.

At this time, the code length counter 4 is counting the transfer locks 8, and the counter output 11 becomes "1".

As a result, the code length data memory 2 outputs the number of code lengths of "1" bit as the comparison code number 12,
This output is set in the comparison code number counter 5 by the comparison code number setting signal 13.

In the case of this embodiment, since the contents of the code length data memory 2 in FIG. 2 indicate the number of data with a 1-bit code length "0",
If the comparison code number counter 5 operates in the down mode, the borrow flag 14 will be set immediately after setting.

As a result, the decoding control unit 1 determines that 1-bit code length data does not exist.

After that, the decoding control unit 1 resets the data shift F/F 9 and the comparison code number counter 5 by the flag clear signal 15, resumes the shift operation of the code data 7 that had been stopped at -, and starts the next code data 7. Transfer to shift register 6.

As a result, the counter output of the code length counter 4 becomes "2", and the data shift F/F 9 sets the data shift completion flag 10 again to instruct the decoding control unit 1 to temporarily stop data shifting.

At this time, the counter output 11 of the code length counter 4 is "2".
As a result, the code length data memory 2 outputs the number of data with a code length of "2" bits corresponding to the output as the comparison code number 12, and this output is sent to the comparison code number counter 5 for comparison. It is set by the code number signal 13.

The comparison code number counter 5 is supplied with a comparison clock 16, and the comparison clock 16 sequentially updates the comparison memory address 33 which is its output.

During this time, the pattern comparator 17 compares the code pattern 31 specified in the code data memory 3 with the code data 32 set in the shift register 6 according to the comparison memory address 33.

In the case of this embodiment, the number of bit code length data "2" from the code length data memory 2 is set to the comparison code number counter 5.
2'' is set, the comparison between the code pattern 31 and the code data 32 in the pattern comparator 17 will be performed twice.

If the code pattern 31 specified in the code data memory 3 and the code data 32 set in the shift register 6 do not match in the first comparison of the two data with the comparison code number "2", the comparison After updating the comparison memory address 33 of the comparison code number counter 5 by the clock 16,
The next code data 7 is read out from the code data memory 3 and the comparison operation is performed again.

Here, if the two match, the pattern comparator 17 outputs a pattern matching signal 18.

The decoding control unit 1 converts the decoded data signal 28, which is the output signal of the decoded data memory 26, into the decoded data F/F 3 using the decoded data latch signal 29 using the pattern matching signal 18.
Latch to 0.

This completes the decoding operation, resets the code length counter 4 and shift register 6 with the initialization signal 19, and
Prepare again for the start of the next decoding operation.

In this embodiment, recognition of the completion of comparison in the pattern comparator 17 is performed using the code length data memory 2 which records the number of readout of code patterns having the same code length from the code data memory 3 and the number of comparisons for each of the same code lengths. An example was shown in which this is done by comparing the values, but instead of using the number of comparisons for each same code length, there is a means to store a flag that indicates the end of the comparison at the same code length, and until that flag is detected. Of course, it can be configured to perform a comparison operation.

〔Effect of the invention〕

As explained above, according to the decoding circuit of the present invention, after downloading the optimum code table for each target image, the data set in the shift register and all the code data in the code table are sequentially transferred into a pattern. Since the decoding is performed by comparing by matching and reading out the decoded data when the patterns match, there is no need to create a complex tree-structured decoding table each time, and it is simple with just a shift register and a comparator. It has the excellent advantage of being able to bring out the optimum compression effect for each target image with a simple circuit configuration.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the decoding circuit according to the present invention, and Fig. 2 shows the data contents of the code length data memory 2 in the decoding circuit shown in Fig. 1. Figure showing an example, 3rd
The figure shows an example of the data contents of the code data memory 3 in the decoding circuit shown in FIG. 1, and FIG. 4 shows an example of the data contents of the decoded data memory 26 in the decoding circuit shown in FIG. FIG. 1... Decoding control unit, 2... Code length data memory, 3
... code data memory, 4 ... code length counter, 5
....

Claims (3)

[Claims] (1) A decoding circuit that decodes variable-length code data includes a shift register that sequentially shifts and holds the code data to be decoded, a code length counter that counts the code length of the shifted code data, and a code length counter that counts the code length of the shifted code data. code data storage means for storing code data for each predetermined code length; decoded data storage means for storing decoded data corresponding to the code data; data pattern comparing means for comparing patterns for each length; decoded data reading means for reading decoded data corresponding to code data with matching data patterns from the decoded data storage means; and a comparison for detecting completion of comparison in the data pattern comparing means. A decoding circuit comprising: end detection means. (2) The decoded data reading means reads the decoded data from the decoded data storage means by specifying an address based on the number of shifts and the number of times the coded data is read from the coded data storage means. (1) The decoding circuit described. (3) A claim characterized in that the encoded data storage means and the decoded data storage means each consist of a memory that can be written/read at any time, and the data is rewritten in each storage means prior to the decoding process. The decoding circuit according to item (1) or (2).