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JPH0465844A - Semiconductor element mounting method - Google Patents

Semiconductor element mounting method

Info

Publication number
JPH0465844A
JPH0465844A JP2178721A JP17872190A JPH0465844A JP H0465844 A JPH0465844 A JP H0465844A JP 2178721 A JP2178721 A JP 2178721A JP 17872190 A JP17872190 A JP 17872190A JP H0465844 A JPH0465844 A JP H0465844A
Authority
JP
Japan
Prior art keywords
semiconductor element
light
substrate
interference fringes
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2178721A
Other languages
Japanese (ja)
Inventor
Katsunori Nishiguchi
勝規 西口
Atsushi Miki
淳 三木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2178721A priority Critical patent/JPH0465844A/en
Priority to CA002044649A priority patent/CA2044649A1/en
Priority to AU78464/91A priority patent/AU652156B2/en
Priority to US07/717,015 priority patent/US5212880A/en
Priority to KR1019910010166A priority patent/KR950002186B1/en
Priority to EP91110072A priority patent/EP0462596A1/en
Publication of JPH0465844A publication Critical patent/JPH0465844A/en
Priority to US08/031,502 priority patent/US5262355A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize sure face down bonding in a semiconductor element having fine bumps, by moving a bonding head in accordance with the state of detected interference fringes, and adjusting the parallelism between the surface of a sucked semiconductor element on which a bump electrode is formed and the surface of the substrate on which the semiconductor element is bonded. CONSTITUTION:A bonding tool 2 is set in the state capable of observing interference fringes, by adjusting the rotation angle thetax in the X-axis direction and the rotation angle thetay in the Y-axis direction. The rotation angle of the tool 2 in the X-axis direction and the rotation angle of the tool 2 in the Y-axis direction are subjected to fine adjustment in the manner in which the interval (w) of the interference fringes to be observed is widened. The interval of the interference fringes becomes wide, as the inclination angle of the bonding tool 2 to the semiconductor element mounting surface 3a of the substrate 3 becomes smaller. When the surfaces become completely parallel, the interfere fringes are not observed. In the state that the interference fringes disappear in the visual field of a microscope 7, the angle adjustment of the bonding tool 2 is interrupted, and the angle of the bonding tool 2 is fixed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子実装方法に関し、特に詳細には、半
導体素子をフェースダウンボンディングで基板上に実装
する半導体素子実装方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor element mounting method, and more particularly to a semiconductor element mounting method for mounting a semiconductor element on a substrate by face-down bonding.

〔従来技術〕[Prior art]

近年、半導体素子を基板上に実装する際、実装密度及び
作業性の点からフェースダウン方式において、フリップ
チップ実装技術が注目されるようになってきた。この方
法は、「エレクトロニック・パッケイジング・テクノロ
ジー」の1989年12月号に掲載された「フリップチ
ップ実装の技術動向」と題する文献に記載されている。
In recent years, when mounting semiconductor elements on a substrate, flip-chip mounting technology has been attracting attention as a face-down method from the viewpoint of mounting density and workability. This method is described in a document entitled "Technical Trends in Flip Chip Mounting" published in the December 1989 issue of Electronic Packaging Technology.

そして、フリップチップをフェースダウン方式で基板上
に実装する際、半導体素子を実装する基板面に対して平
行に保った状態でフェースダウンしなければならない。
When a flip chip is mounted on a substrate using a face-down method, the flip chip must be mounted face-down while being kept parallel to the surface of the substrate on which the semiconductor element is mounted.

しかし、従来は実装装置の最初の調節の際、ボンディン
グヘッドと基板面との平行度を調整した後は、調節をお
こなわずフェースダウンボンディングを実施していた。
However, conventionally, during the first adjustment of the mounting apparatus, after adjusting the parallelism between the bonding head and the substrate surface, face-down bonding was performed without making any adjustment.

このような方法では、半導体素子を基板面に対して確実
にボンディングできない場合があった。そこで、フェー
スダウンボンディング中に半導体素子を吸着保持したツ
ールの真横に設けたTVカメラ等で、半導体素子を観察
し、ツールと基板との平行度を観察しつつフェースダウ
ンを行っていた。
With such a method, there are cases where the semiconductor element cannot be reliably bonded to the substrate surface. Therefore, during face-down bonding, the semiconductor element was observed with a TV camera or the like installed right next to the tool that held the semiconductor element by suction, and the parallelism between the tool and the substrate was observed while performing face-down bonding.

[発明が解決しようとする課題〕 しかし、上記のような従来の方法では、バンプが設けら
れた半導体素子とこれがボンディングされる基板との間
では、10mm当たり数μm程度の平行度しか実現でき
ず、その結果、フリップチップのバンプ高さが10μm
以下となるような高密度化に伴う微細化に十分対応する
ことができなかった。
[Problems to be Solved by the Invention] However, in the conventional method as described above, parallelism of only a few μm per 10 mm can be achieved between the semiconductor element provided with bumps and the substrate to which it is bonded. As a result, the bump height of the flip chip is 10 μm.
It has not been possible to adequately respond to the miniaturization that accompanies higher density as described below.

本発明は上記課題を解決し、高密度化に伴い微細化に対
応できる半導体素子実装装置を提供することを目的とす
る。
An object of the present invention is to solve the above problems and provide a semiconductor element mounting apparatus that can cope with miniaturization as the density increases.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体素子実装方法は、片面にハンプ電極が形
成されている半導体素子を反対向でボンディングヘット
上の吸着面に吸着させて保持する工程と、吸着面の周囲
に形成されたボンディングヘッドの光反射面に対して、
半導体素子かボンディングされる光反射性の基板の表面
側から可干渉性の光を照射する光照射工程と、光照射工
程で照射した光のうち、光反射面で反射した光と、この
反射光が前記基板表面で反射し、再度光反射面で反射し
た光とを互いに干渉させて、干渉縞を検出する検出工程
と、検出工程で検出された干渉縞の状態に応して前記ボ
ンディングヘッドを移動し、吸着した半導体素子のバン
プ電極か形成されている面と基板の半導体素子がボンデ
ィングされる面との平行度を調節し、半導体素子を前記
基板上にフェースダウンボンデングする工程とを備えた
ことを特徴とする。
The semiconductor device mounting method of the present invention includes the steps of adsorbing and holding a semiconductor device having a hump electrode formed on one side on a suction surface on a bonding head in the opposite direction; Against the light-reflecting surface,
A light irradiation process in which coherent light is irradiated from the surface side of a light-reflective substrate to which a semiconductor element is bonded; the light reflected in the light reflection surface in the light irradiation process; and this reflected light. a detection step of detecting interference fringes by causing the light reflected by the substrate surface and reflected again by the light reflecting surface to interfere with each other; and a detection step of detecting the interference fringes detected in the detection step. adjusting the parallelism between the surface of the moved and attracted semiconductor element on which the bump electrode is formed and the surface of the substrate to which the semiconductor element is bonded, and bonding the semiconductor element face-down onto the substrate. It is characterized by:

〔作用〕[Effect]

本発明の半導体素子実装方法では、ボンディングヘッド
上の光反射面に対して基板表面側より可干渉性の光を照
射している。そして、ボンディングヘッド上の光反射面
で反射した光と、この反射光が基板表面で反射し、再度
光反射面で反射した光とを互いに干渉させ、半導体素子
表面と基板表面との平行度を正確に検出している。この
検出結果にしたがって、ボンディングヘッドを動かし、
半導体素子表面と基板表面とを互いに平行になるように
調節している。
In the semiconductor device mounting method of the present invention, coherent light is irradiated onto the light reflecting surface on the bonding head from the substrate surface side. Then, the light reflected by the light reflecting surface on the bonding head, the reflected light reflected by the substrate surface, and the light reflected again by the light reflecting surface are made to interfere with each other, and the parallelism between the semiconductor element surface and the substrate surface is adjusted. Detected accurately. Move the bonding head according to this detection result,
The semiconductor element surface and the substrate surface are adjusted to be parallel to each other.

〔実施例〕〔Example〕

以下、図面を参照しつつ本発明に従う実施例を説明して
いく。
Embodiments according to the present invention will be described below with reference to the drawings.

第1図は本発明に従う半導体装方法の一実施例で使用す
る半導体素子実装装置の構成図である。
FIG. 1 is a block diagram of a semiconductor element mounting apparatus used in an embodiment of the semiconductor mounting method according to the present invention.

第1図に示すように、半導体素子実装装置はボンディン
グツール2を備え、このボンディングツール2の先端部
には、半導体素子1を吸着固定する平面2g(吸着面)
が形成されている。そして、この平面2aの中央部には
、真空ポンプ10に接続された貫通口2bが形成されて
いる。この吸着面の周囲は、そこに真空吸着される半導
体素子のバンプ電極形成面に平行な鏡面部2C(光反射
面)が形成されている。この鏡面部2cは貫通口2bの
周囲に、例えば光反射性の良好な材料からなる部材を埋
め込み、これを研磨することにより形成する。更に、ボ
ンディングツール2は、実装装置に装着される光反射性
の基板3の半導体素子搭載面3aをXY平面としたとき
、このXY平面に対して直交する方向Zに移動可能であ
り、更に、このXY平面に平行で、平面2a上の貫通孔
2bの中心を通る平面を規定するX7両軸に対してそれ
ぞれ回転角θx1θy方向に調節可能である。
As shown in FIG. 1, the semiconductor element mounting apparatus includes a bonding tool 2, and the tip of the bonding tool 2 has a flat surface 2g (suction surface) on which the semiconductor element 1 is fixed by suction.
is formed. A through hole 2b connected to the vacuum pump 10 is formed in the center of this plane 2a. A mirror surface portion 2C (light reflecting surface) is formed around this suction surface, which is parallel to the bump electrode forming surface of the semiconductor element to be vacuum suctioned thereon. The mirror surface portion 2c is formed by, for example, embedding a member made of a material with good light reflectivity around the through hole 2b and polishing the member. Further, the bonding tool 2 is movable in a direction Z perpendicular to the XY plane, when the semiconductor element mounting surface 3a of the light reflective substrate 3 mounted on the mounting apparatus is an XY plane, and further, The rotation angles can be adjusted in the θx1θy directions with respect to both X7 axes that are parallel to the XY plane and define a plane passing through the center of the through hole 2b on the plane 2a.

この半導体素子実装装置の基板保持部4は、基板3をそ
の下面全面で支持する平面部を備えている。更にこの基
板保持部4は、そこに搭載する光反射性の基板3を固定
する固定機構(図示せず)を備えている。
The substrate holding section 4 of this semiconductor element mounting apparatus includes a flat section that supports the substrate 3 on its entire lower surface. Furthermore, this substrate holding section 4 is equipped with a fixing mechanism (not shown) for fixing the light reflective substrate 3 mounted thereon.

この基板保持部4の基板支持表面の上方には、傾斜測定
装置20か設けられている。この傾斜測定装置20は、
ボンディングツール2と基板保持部4との間の第1の位
置と、ボンディングツール2と基板保持部4との間から
外れた第2の位置との間で移動可能となるように、手動
または自動の移動装置(図示せず)に装着されている。
A tilt measuring device 20 is provided above the substrate supporting surface of the substrate holder 4. This inclination measurement device 20 is
Manually or automatically so as to be movable between a first position between the bonding tool 2 and the substrate holder 4 and a second position removed from between the bonding tool 2 and the substrate holder 4. is attached to a moving device (not shown).

この移動方法は、回転移動でも平行移動でもよい。この
傾斜測定装置20は、一対のハーフミラ−5a。
This movement method may be rotational movement or parallel movement. This inclination measuring device 20 includes a pair of half mirrors 5a.

5bを備え、この一対のハーフミラ−5a、5bはそれ
ぞれ、この傾斜測定装置20が第1の位置にあるとき、
基板保持部4の基板支持平面に対してそれぞれ±45度
の角度を成すよう配置されている。そしてハーフミラ−
5a、5b同士は90度の角度をもって、それらの一端
か接続するように構成配置されている。上側のハーフミ
ラ−5aの側方には、ハーフミラ−5aの面に対して4
5度の角度で可干渉性の平行光を出射する光源6、例え
ばレーザ発光装置か設けである。更に、下側のハーフミ
ラ−5bの光源6とは反対側の側方には、ハーフミラ−
5bで反射した光の干渉状態、具体的には干渉縞を観測
できる観7111j装置、例えば、顕微鏡7か設けであ
る。そして、この顕微ff17は、光源6からハーフミ
ラ−5aに発した平行光の進行方向であって、ハーフミ
ラ−5bの傾斜面に対応する位置に設けられている。こ
のように構成しておくことにより、光源6より発した平
行光がハーフミラ−5aて上方に反射され、ホンディン
グツール2の鏡面部2cて反射され、更にハーフミラ−
5bで顕微鏡7側に反射された光と、光源6より発した
平行光かハーフミラ−5aて上方に反射され、ホンディ
ングツール2の鏡面部2cで反射され、ハーフミラ−5
a、5bを透過し、基板で反射され、その反射光かハー
フミラ−5a。
5b, and each of the pair of half mirrors 5a, 5b is configured such that when the inclination measuring device 20 is in the first position,
They are arranged so as to form an angle of ±45 degrees with respect to the substrate support plane of the substrate holder 4, respectively. And half mirror
5a and 5b are configured and arranged such that they are connected at one end at an angle of 90 degrees. On the side of the upper half mirror 5a, there are 4
A light source 6, such as a laser emitting device, is provided which emits coherent parallel light at an angle of 5 degrees. Furthermore, a half mirror is provided on the side opposite to the light source 6 of the lower half mirror 5b.
A viewing device 7111j, for example, a microscope 7, is provided to observe the interference state of the light reflected by the light beam 5b, specifically interference fringes. The microscope ff17 is provided at a position corresponding to the inclined surface of the half mirror 5b in the traveling direction of the parallel light emitted from the light source 6 to the half mirror 5a. With this configuration, the parallel light emitted from the light source 6 is reflected upward by the half mirror 5a, reflected by the mirror surface portion 2c of the honding tool 2, and further reflected by the half mirror.
The light reflected to the microscope 7 side by the light source 6 and the parallel light emitted from the light source 6 are reflected upward by the half mirror 5a, reflected by the mirror surface part 2c of the honding tool 2, and then reflected by the half mirror 5.
a, 5b, and is reflected by the substrate, and the reflected light is the half mirror 5a.

5bを透過し、再度鏡面部2cて反射され、更にハーフ
ミラ−5bで顕微鏡7側に反射した光との干渉状態か観
察できる。この光導波経路を第2図に示す。この第2図
において、点線で示した光と実線で示した光との干渉状
態か顕微鏡7て観察される。そして、これらのハーフミ
ラ−5a、5b。
5b, is reflected again by the mirror surface 2c, and is further reflected by the half mirror 5b toward the microscope 7. Interference with the light can be observed. This optical waveguide path is shown in FIG. In FIG. 2, the state of interference between the light indicated by the dotted line and the light indicated by the solid line is observed using a microscope 7. And these half mirrors 5a and 5b.

光源6及び顕微鏡7の相互間の位置は不変であり、一体
で移動できるように構成されている。
The mutual positions of the light source 6 and the microscope 7 remain unchanged, and they are configured to be able to move together.

次に、上記装置を使用して、半導体索子1を光反射性の
基板3上の半導体素子搭載面3a上にフェースダウンボ
ンディングする方法について説明する。
Next, a method of face-down bonding the semiconductor cable 1 onto the semiconductor element mounting surface 3a of the light-reflective substrate 3 using the above-mentioned apparatus will be described.

ます、基板3を基板保持部4上のボンディングツール2
に対応する位置に固定する。次に、バンプ電極が形成さ
れている面の反対面がボンディングツール2の貫通孔2
bを覆うように半導体素子1をセットし、真空ポンプ1
oで貫通孔2b内を真空吸引して、半導体素子1をボン
ディングツール2の先端部に吸着固定する。
Then, place the board 3 on the bonding tool 2 on the board holder 4.
Fix it in the position corresponding to. Next, the surface opposite to the surface on which the bump electrode is formed is the through hole 2 of the bonding tool 2.
Set the semiconductor element 1 so as to cover the
The inside of the through hole 2b is vacuum-suctioned at o, and the semiconductor element 1 is suctioned and fixed to the tip of the bonding tool 2.

次に、ボンディングツール2と基板3との間の第1の位
置に傾斜測定装置20を固定する。次に、光源6を点灯
し、レーザ光をハーフミラ−5aに対して出射させる。
Next, the inclination measuring device 20 is fixed at a first position between the bonding tool 2 and the substrate 3. Next, the light source 6 is turned on to emit laser light to the half mirror 5a.

そして基板3の表面3aての反射光と、ボンディングツ
ール2の鏡面部2cでの反射光との干渉状態を顕微鏡7
て観測する。しかし、ボンディングツール2の鏡面部2
cが基板3の半導体素子搭載面3aに対して大きく傾斜
しているときは、第3図(a)に示すように、干渉縞の
多すぎるため干渉縞は観測できない。その場合にはボン
ディングツール2をX軸方向の回転角θX及びY軸方向
の回転角θyを調整し、第3図(b)に示すように干渉
縞が観411jてきる状態にする。
Then, the state of interference between the reflected light from the surface 3a of the substrate 3 and the reflected light from the mirror surface portion 2c of the bonding tool 2 is observed using a microscope.
Observe. However, the mirror surface part 2 of the bonding tool 2
When c is greatly inclined with respect to the semiconductor element mounting surface 3a of the substrate 3, as shown in FIG. 3(a), there are too many interference fringes and no interference fringes can be observed. In that case, the rotation angle θX in the X-axis direction and the rotation angle θy in the Y-axis direction of the bonding tool 2 are adjusted so that interference fringes are visible 411j as shown in FIG. 3(b).

そして、次に、第3図(c)に示すように、観察される
千6縞の間隔Wか拡がるようにボンディングツール2の
X軸方向の回転角θx、Y軸方向の回転角θyを微調整
する。基板3の半導体素子搭載面3aに対してボンディ
ングツール2の傾斜角度が小さくなるほと干渉縞の間隔
は広くなり、完全に平行になったとき干渉縞は観、01
されなくなる。顕微鏡7の観察視野内に、干渉縞が無く
なった状態で、ボンディングツール2の角度調整を停止
し、ボンディングツール2の角度を固定する。
Next, as shown in FIG. 3(c), the rotation angle θx in the X-axis direction and the rotation angle θy in the Y-axis direction of the bonding tool 2 are finely adjusted so that the interval W between the observed 1,600 stripes increases. adjust. As the inclination angle of the bonding tool 2 becomes smaller with respect to the semiconductor element mounting surface 3a of the substrate 3, the interval between the interference fringes becomes wider, and when they become completely parallel, the interference fringes become 01
It will no longer be done. When there are no interference fringes within the observation field of the microscope 7, the angle adjustment of the bonding tool 2 is stopped and the angle of the bonding tool 2 is fixed.

このように干渉縞か観測されない状態では、例えば観察
領域をボンディングツール2の鏡面部2cて10mmと
し、使用する可干渉性の光を波長0.63μmのHe−
Neレーザの光を使用すると、干渉縞は、光路長差か0
,63μm毎に発生する。このためボンディングツール
2の鏡面部2cと基板3の半導体素子搭載面3aとの平
行度は] Ommの距離で0.3μm以下となる。
In this state where no interference fringes are observed, for example, the observation area is set to 10 mm on the mirror surface 2c of the bonding tool 2, and the coherent light used is He-
When using Ne laser light, interference fringes are created by optical path length difference or 0.
, occurs every 63 μm. Therefore, the parallelism between the mirror surface portion 2c of the bonding tool 2 and the semiconductor element mounting surface 3a of the substrate 3 is 0.3 μm or less at a distance of 0.0 mm.

そして、傾斜測定装置20を第2の位置に移動し、ボン
ディングツール2と基板との間から退避させる。そして
ボンディングツール2を−Z方向に移動(下降)させ、
フェースダウンボンディングを行う。
Then, the inclination measuring device 20 is moved to the second position and evacuated from between the bonding tool 2 and the substrate. Then, move the bonding tool 2 in the -Z direction (downward),
Perform face down bonding.

このようにして、半導体素子1のバンプ電極が形成され
ている面と、基板の半導体素子搭載面3aとの平行度を
簡単にかつ精度よく検出でき、この検出結果に基づいて
、ボンディングツール2の傾斜を調整することにより、
高精度なフェースダウンボンディングを実施することが
できる。
In this way, the parallelism between the surface on which the bump electrodes of the semiconductor element 1 are formed and the semiconductor element mounting surface 3a of the substrate can be easily and accurately detected, and based on this detection result, the bonding tool 2 is adjusted. By adjusting the slope,
Highly accurate face-down bonding can be performed.

本発明は上記実施例に限定されず種々の変形例が考えら
れ得る。
The present invention is not limited to the above embodiments, and various modifications may be made.

具体的には、上記実施例で使用する装置ては、可干渉性
の光としてレーザ光を使用しているが、これに限定され
ず、可干渉性を有している光であればどのような光であ
ってもよい。また、レーザ光としてHe−Neレーザを
使用しているか、これに限定されない。
Specifically, the apparatus used in the above example uses a laser beam as the coherent light, but the invention is not limited to this, and any coherent light can be used. It may be light. Moreover, whether or not a He-Ne laser is used as the laser beam is not limited thereto.

この鏡面部2Cを形成する際、ボンディングツール2の
平面2aを研磨しているが、この代わりに光反射部材を
貼り付けるようにしてもよい。
When forming this mirror surface portion 2C, the flat surface 2a of the bonding tool 2 is polished, but a light reflecting member may be attached instead.

〔発明の効果〕 本発明の半導体素子実装方法では、先に説明したように
、光の干渉を利用して、半導体素子と基板との平行度を
精度よく検出しているので、微細なバンプを有する半導
体素子においても確実なフェースダウンボンディングを
行うことができる。
[Effects of the Invention] As explained above, the semiconductor device mounting method of the present invention uses optical interference to accurately detect the parallelism between the semiconductor device and the substrate, so it is possible to eliminate minute bumps. Reliable face-down bonding can be performed even in semiconductor elements having the above structure.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体素子実装方法の一実施例で使用
する半導体素子実装装置の構成を示す図、第2図は第1
図に示す半導体素子実装装置における光の経路を示す図
、及び第3図は実施例の方法で半導体素子を実装する際
の顕微鏡の観察状態を示す図である。 1・・・半導体素子、2・・・ボンディングツール、3
・・・基板、4・・・基板保持部、5a、5b・・・/
X−フミラー 6・・・光源、7・・・顕微鏡。
FIG. 1 is a diagram showing the configuration of a semiconductor device mounting apparatus used in an embodiment of the semiconductor device mounting method of the present invention, and FIG.
FIG. 3 is a diagram showing a light path in the semiconductor element mounting apparatus shown in the figure, and FIG. 3 is a diagram showing an observation state using a microscope when a semiconductor element is mounted by the method of the embodiment. 1... Semiconductor element, 2... Bonding tool, 3
...Substrate, 4...Substrate holding part, 5a, 5b.../
X-Fumirar 6...Light source, 7...Microscope.

Claims (1)

【特許請求の範囲】  片面にバンプ電極が形成されている半導体素子を反対
面でボンディングヘッド上の吸着面に吸着させて保持す
る工程と、 前記吸着面の周囲に形成されたボンディングヘッドの光
反射面に対して、前記半導体素子がボンディングされる
光反射性の基板の表面側から可干渉性の光を照射する光
照射工程と、 前記光照射工程で照射した光のうち、前記光反射面で反
射した光と、この反射光が前記基板表面で反射し、再度
前記光反射面で反射した光とを互いに干渉させて、干渉
縞を検出する検出工程と、前記検出工程で検出された干
渉縞の状態に応じて前記ボンディングヘッドを移動し、
前記吸着した半導体素子のバンプ電極が形成されている
面と前記基板の半導体素子がボンディングされる面との
平行度を調節し、前記半導体素子を前記基板上にフェー
スダウンボンデングする工程とを備えた半導体素子実装
方法。
[Scope of Claims] A step of adsorbing and holding a semiconductor element having bump electrodes formed on one side on an adsorption surface on a bonding head on the opposite side, and reflecting light of the bonding head formed around the adsorption surface. a light irradiation step of irradiating the surface with coherent light from the surface side of a light-reflecting substrate to which the semiconductor element is bonded; a detection step of detecting interference fringes by causing the reflected light and the light reflected by the substrate surface and reflected again by the light reflecting surface to interfere with each other; and interference fringes detected in the detection step. moving the bonding head according to the state of the
adjusting the parallelism between the surface of the adsorbed semiconductor element on which the bump electrode is formed and the surface of the substrate to which the semiconductor element is bonded, and bonding the semiconductor element face-down onto the substrate. Semiconductor element mounting method.
JP2178721A 1990-06-19 1990-07-06 Semiconductor element mounting method Pending JPH0465844A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2178721A JPH0465844A (en) 1990-07-06 1990-07-06 Semiconductor element mounting method
CA002044649A CA2044649A1 (en) 1990-06-19 1991-06-14 Method and apparatus for packaging a semiconductor device
AU78464/91A AU652156B2 (en) 1990-06-19 1991-06-18 Method and apparatus for packaging semiconductor device
US07/717,015 US5212880A (en) 1990-06-19 1991-06-18 Apparatus for packaging a semiconductor device
KR1019910010166A KR950002186B1 (en) 1990-06-19 1991-06-19 Method and apparatus for mounting semiconductor device
EP91110072A EP0462596A1 (en) 1990-06-19 1991-06-19 Method and apparatus for packaging a semiconductor device
US08/031,502 US5262355A (en) 1990-06-19 1993-03-15 Method for packaging a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2178721A JPH0465844A (en) 1990-07-06 1990-07-06 Semiconductor element mounting method

Publications (1)

Publication Number Publication Date
JPH0465844A true JPH0465844A (en) 1992-03-02

Family

ID=16053411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2178721A Pending JPH0465844A (en) 1990-06-19 1990-07-06 Semiconductor element mounting method

Country Status (1)

Country Link
JP (1) JPH0465844A (en)

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