Nothing Special   »   [go: up one dir, main page]

JPH0461184A - Surface luminescent semiconductor laser and manufacture thereof - Google Patents

Surface luminescent semiconductor laser and manufacture thereof

Info

Publication number
JPH0461184A
JPH0461184A JP16440290A JP16440290A JPH0461184A JP H0461184 A JPH0461184 A JP H0461184A JP 16440290 A JP16440290 A JP 16440290A JP 16440290 A JP16440290 A JP 16440290A JP H0461184 A JPH0461184 A JP H0461184A
Authority
JP
Japan
Prior art keywords
semiconductor
film
groove
layer
quantum well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16440290A
Other languages
Japanese (ja)
Other versions
JP2689694B2 (en
Inventor
Mitsunori Sugimoto
杉本 満則
Noboru Hamao
浜尾 昇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2164402A priority Critical patent/JP2689694B2/en
Publication of JPH0461184A publication Critical patent/JPH0461184A/en
Application granted granted Critical
Publication of JP2689694B2 publication Critical patent/JP2689694B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To provide a low threshold current high light emission efficiency surface emitting semiconductor laser with the high yield by forming a semiconductor column as a light emitting region surrounded by a groove reaching a quantum well active layer, and further forming a modified layer on a semiconductor side surface of the groove. CONSTITUTION:There are crystal grown on an n-type GaAs semiconductor substrate 1 a first conductivity type semiconductor multilayered reflecting film 2 comprising 23 periods of n-type AlAs 802 Angstrom /n type GaAs 670 Angstrom , a quantum well structure active layer 3 comprising Al0.5 Ga0.5As 1430 Angstrom , a second conductivity type semiconductor multilayered reflection film 4, and a p<+> type GaAs 30 Angstrom capping layer 15. Further, a ring-shaped groove 7 issoformed by photoetching that it reaches the active later 3. Thereupon, a semiconductor column 6 is formed as a light emitting region. Then, an SiO2 film 5 as a mutual diffusion promoting film is formed over the entire surface of the substrate, and the SiO2 film 5 is etched using dry etching 12. Further, a modified layer (disordered region) 8 is formed only in the vicinity of the SiO2 film 5 on the side surface of the ring-shaped groove 7 by a heat treatment.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は光交換や光情報処理に用いられる面発光半導体
レーザに関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a surface emitting semiconductor laser used for optical exchange and optical information processing.

(従来の技術) 光交換、光コンピュータ、光情報処理等の分野では2次
元集積化が可能な面発光レーザが必要であり、盛んに研
究開発されている。その−例が、J、 L。
(Prior Art) In fields such as optical switching, optical computers, and optical information processing, surface-emitting lasers that can be two-dimensionally integrated are required, and are being actively researched and developed. An example is J.L.

JewellやY、 H,Lee等によるエレクトロニ
クスレターズ(Electronics Letter
s)25巻1123〜1124頁及び、1377〜13
78J4に記載されている。1〜5pm径の面発光レー
ザが1〜2mAの閾電流で発振したと報告されている。
Electronics Letters by Jewell, Y, H, Lee, etc.
s) Volume 25, pages 1123-1124 and 1377-13
78J4. It has been reported that a surface emitting laser with a diameter of 1 to 5 pm oscillated with a threshold current of 1 to 2 mA.

またその製造方法は半導体層形成後、金、Niを蒸着し
、Niを数/im径の円形にパターニングしNiをマス
クとしてドライエツチングにより、数pm径の半導体柱
を形成し°(いた。
The manufacturing method was such that after forming a semiconductor layer, gold and Ni were vapor-deposited, Ni was patterned into a circle with a diameter of several micrometers, and semiconductor pillars with a diameter of several micrometers were formed by dry etching using Ni as a mask.

(発明が解決しようとする課題) 前述の面発光レーザでは閾値電流が1mA程度であり、
閾値電流密度IK、A、/cmから引算される閾値電流
2□m直径で3O□Aと比べると非常に大きい。この理
由はメザ側面での活性層側面が人気(゛露:i3 t、
、+ ′1.−構造となっており、更にドライ−Jツー
ヂングによる半導体柱を形成時のダメージが加下表if
+iにあり、ここでの表面非発光再結合を介し/−1無
効電!Lが1mA程度あるためど考えられる3、まグー
数(im径の半導体柱は機械的な強度が弱く、プロセス
丁、程中(、−破損し歩留りが低下゛したり、発光領域
Gパスl−L、スがかかり発光効率が低下するU!j題
があっ/、−3、オf:同様の理由で成長表面側にヒー
 I・シンクを融着することが困難であるため、連続発
振時の特−性が、男、゛いという問題があった6、 本発明の目的は、表面再結合により無効電!*を低減す
ることにより、低閾値電流、高発光効率の面発光半導体
レーザを、及びその歩留り良い製造]j法を提供するこ
とにある。
(Problem to be solved by the invention) In the surface emitting laser described above, the threshold current is about 1 mA,
The threshold current, which is subtracted from the threshold current density IK, A, /cm, has a diameter of 2□m, which is very large compared to 3O□A. The reason for this is that the active layer side on the meza side is popular (Russia: i3t,
, + '1. - structure, and furthermore, the damage caused when forming semiconductor pillars by dry J-tooling is reduced if
+i and through surface non-radiative recombination here /-1 reactive charge! Since L is about 1 mA, it is possible that the semiconductor pillar with a diameter of im has weak mechanical strength and may be damaged during the process, resulting in a decrease in yield, or the light emitting area G pass l -L, There is a problem that the luminous efficiency decreases due to heat/, -3, Off: For the same reason, it is difficult to fuse the heat sink to the growth surface side, so continuous wave However, the object of the present invention is to reduce the reactive charge* by surface recombination, thereby creating a surface-emitting semiconductor laser with low threshold current and high luminous efficiency. and its high-yield production].

(課題を解決゛するための手段) 本発明の面発光半導体レーザは、コ1′、導体基板七に
、第1導電型の半導体多層反射膜と、少なくとも1つの
量子井戸構造をもつ量r−井戸rb性層と、第2導電型
の半導体多層反射膜とを少なくとも備え、前記量子井戸
活性層に達する溝で囲まれた発光領域となる半導体柱を
有し、前記溝の半導体側面に変成層を備えることを特徴
とする。
(Means for Solving the Problems) The surface emitting semiconductor laser of the present invention has a semiconductor multilayer reflective film of a first conductivity type on a conductive substrate 7, and a quantum well structure having at least one quantum well structure. It has a semiconductor column that is a light emitting region and is surrounded by a groove that reaches the quantum well active layer, and includes at least a well RB layer and a semiconductor multilayer reflective film of a second conductivity type, and a metamorphic layer on the semiconductor side surface of the groove. It is characterized by having the following.

あるいは上記の本発明の面発光レーザの溝をボッイミド
等の樹脂で埋めてプレーナ化した面発光レーザあるいは
レーザアレイであることを特徴とす゛る。
Alternatively, the present invention is characterized in that it is a planar surface-emitting laser or laser array in which the grooves of the surface-emitting laser of the present invention are filled with a resin such as boimide.

本発明の面発光半導体レーザ製造方法は、半導体基板上
に、第1導電型の半導体多層反射膜と、少なくとも1つ
の量子井戸構造をもつ量子井戸活性層と、第2導電型の
半導体多層反則膜とを、少なくとも備える半導体層を形
成する工程と、前記量子井戸活性層に達する溝をエツチ
ングにより形成し、該溝で囲まれた発光領域となる半導
体柱を形成する工程と、少なくとも絶縁膜を含む相互拡
散促進膜を半導体表面に形成する工程と、前記溝の側面
を除いて、指向性のあるドライエツチングにより、前記
相互拡散促進膜を除去する工程と、熱処理により前記溝
の側面の半導体層において相互拡散を行なう工程とを、
備えることを特徴とする。
A surface emitting semiconductor laser manufacturing method of the present invention includes a semiconductor multilayer reflective film of a first conductivity type, a quantum well active layer having at least one quantum well structure, and a semiconductor multilayer reflective film of a second conductivity type, on a semiconductor substrate. a step of forming a semiconductor layer comprising at least a semiconductor layer; a step of forming a groove reaching the quantum well active layer by etching and forming a semiconductor column serving as a light emitting region surrounded by the groove; a step of forming an interdiffusion promoting film on the semiconductor surface; a step of removing the interdiffusion promoting film by directional dry etching except for the side surfaces of the groove; and the process of mutual diffusion.
It is characterized by being prepared.

また、第2の製造方法は、半導体基板上−に、第1導電
型の半導体多層反射膜と、少なくとも1つの量子井戸構
造をもつt丁−井戸活性層と、第2導電型の半導体多層
反射膜とを、少なくとも備える半導体層を形成する工程
と、前記FA子井/j活性層に達する溝をエツチングに
より形成し、該溝で囲まれた発光領域どなる半導体柱を
形成づる]:1r−1ど、少なくとも絶縁膜を含む相互
拡散促進膜を半導体表面に形成する工程と、該相互拡散
促進膜1−にノオトレジストを前記溝が平坦になるよう
に塗布する工程と、前記溝部を除いてエツチングにより
、前記相互拡散促進膜を除去する工程と、熱処理、によ
り、前記溝部において相互拡散を行ない半導体変成層を
形成する工程とを、備えることを特徴とする。
Further, the second manufacturing method includes, on a semiconductor substrate, a semiconductor multilayer reflective film of a first conductivity type, a t-well active layer having at least one quantum well structure, and a semiconductor multilayer reflective film of a second conductivity type. a step of forming a semiconductor layer comprising at least a film; forming a groove reaching the FA active layer by etching, and forming a semiconductor column having a light emitting region surrounded by the groove]: 1r-1 A step of forming an interdiffusion promoting film including at least an insulating film on the semiconductor surface, a step of applying a nootresist to the interdiffusion promoting film 1- so that the groove becomes flat, and etching except for the trench. The method is characterized by comprising the steps of removing the interdiffusion promoting film, and performing interdiffusion in the groove by heat treatment to form a semiconductor metamorphic layer.

(作用) 表面非発光再結合により無効電流を低減するにはへテロ
接合を用いれば良く、この−実現手段として不純物導入
等による無秩序化の技術がある。
(Function) A heterojunction may be used to reduce the reactive current by surface non-radiative recombination, and as a means of achieving this, there is a technique of disordering by introducing impurities or the like.

これは量子井戸構造からなる活性層に不純物を導人1−
 &:、、:す、熱応力を力[l父る、−どにより、量
子−井1−]構造の構成、了1、素の相互−拡散を促進
I7、量子井戸構造を無秩序化1ノで、はぼ−様組成の
半導体とづるものである17、二の無秩序化された領域
を変成層と呼ぶ1、これにより活性層の側面を活1″A
層よりも禁制帯幅の広い半導体とする、二とによって、
ヘテLU接合効果により表面再結合の抑制をするもので
ある。この技術を面発光tかザに適用4−るには問題が
あった。即ち、面発光1/−ザの発光部は、8半導体社
どな・・、)でいるが、この全面に不純物又は熱応力を
導入し、て−無秩序化すると、半導体の頂19部付近の
十へ導体多層膜も無秩序化され、反射率が低下り、 !
、T +)、頂」二部に形成さ才′1か電極の抵抗が増
大[,5、レーザ特性が悪化し″(シまう。そこで本発
明の構造(:1無秩序化された変成層を溝の側mにのみ
形成した構造となっ−Cいる。
This is done by introducing impurities into the active layer consisting of a quantum well structure.
&:、、:SU、Thermal stress is applied to the composition of the quantum well structure. This disordered region is called a metamorphic layer1, which is referred to as a semiconductor with a wafer-like composition.
By making a semiconductor with a wider bandgap than the layer,
Surface recombination is suppressed by the hetero-LU junction effect. There were problems in applying this technology to surface emitting devices. In other words, the light emitting part of the surface emitting device is made of 8 semiconductors, etc., but if impurities or thermal stress are introduced into the entire surface to make it disordered, the area near the top 19 of the semiconductor The conductive multilayer film also becomes disordered and its reflectance decreases!
, T+), the resistance of the electrode increases [,5] and the laser characteristics deteriorate. The structure is formed only on the side m of the groove.

更に、発光領域σ戸1ニー導体朴の周りに溝を形成1−
だ構造なので、従来のJ:うな発光部が突出した構造と
違い、1了の機械的強度が保たれ、製造上程や実装[積
に破損づ゛ることはなく、発光領域に不用なストレスが
かからない構造とな−)ている。
Furthermore, a groove is formed around the light emitting region σ door 1 knee conductor 1-
Unlike the conventional structure with a protruding light-emitting part, this structure maintains its mechanical strength and prevents damage during the manufacturing process and mounting process, reducing unnecessary stress on the light-emitting area. It has a structure that does not apply.

本発明の製造方法によれば上述の横送を容易に歩留り高
く製作することができる。本発明の請求項2の製造ノ5
法′Qは、半導体柱を−〕−ソチングにより形成後、S
iO等の相互拡散促進膜を全面に指向性の良いド・ンイ
エップング法、例えば反広キイオンビーノ・Jエツチン
グ(RIBE))去により、」′導体表面の平坦部のS
iO2膜のみをよノチングする。これにJり半導体1+
の側面のSiO□膜は残り、゛1′、導体朴の頂上部等
の平坦部のSiOは除去される。こうし−ζ半導体柱側
面にのみ相″!1−拡赦促進膜を形成後、熱処理するこ
とにより、多層反射膜や電極の劣化なし。
According to the manufacturing method of the present invention, the above-described cross-feeding can be easily manufactured with high yield. Manufacture No. 5 of Claim 2 of the present invention
In method 'Q, after forming semiconductor pillars by -]-soching, S
By removing an interdiffusion promoting film such as iO on the entire surface using a highly directional D-N-E etching method, such as anti-broadband etching (RIBE), S
Only the iO2 film is etched. Jri semiconductor 1+ to this
The SiO□ film on the side surfaces of ``1'' remains, and the SiO on flat areas such as the top of the conductor block ``1'' is removed. 1- After forming the amplification promoting film, heat treatment is performed, so there is no deterioration of the multilayer reflective film or electrodes.

に、側面にのみ変成層を形成できる6、請求項3の製造
ノブ法は、相互拡散促進膜を全面に形成する]二部まで
、請求項2と同様Cある。その後、フォトレジストを塗
布し、で表面を平坦にする。溝の部分はつ、ゴハー全体
に比べ面積が小さいので容易に平坦に塗布することがで
きる。次にドライエツチング等により均一・にエツチン
グをするど、半導体表面の平1g部では溝の部分よりフ
ォトレジストが薄いので、〒、くフォトレジストされる
。次にエツチングにより平坦部で相7ラー拡散促進膜を
除去する。溝の部分はフォトレジストがエツチングされ
たたけで相互拡散促進膜は保存されている。この後フォ
トレジストを洗浄により除き、熱処理をすることにより
、溝の中の部分のみ不純物又は空孔等が導入され、変成
層が形成され。このようにして半導体柱の側面の量子井
戸活性層を無秩序化できる。この方法でも反射膜や電極
の劣化、それに伴なう電気抵抗の増大はない。
6. The manufacturing knob method of claim 3, in which the metamorphic layer can be formed only on the side surfaces, forms the interdiffusion promoting film on the entire surface] up to two parts, as in claim 2. Then, apply photoresist and flatten the surface. The area of the grooves is smaller than the entire Gohar, so it can be easily applied evenly. Next, the photoresist is uniformly etched by dry etching or the like, but since the photoresist is thinner in the flat 1g portion of the semiconductor surface than in the groove portion, the photoresist is thinner. Next, the phase 7 color diffusion promoting film is removed from the flat portion by etching. In the groove portions, the photoresist is simply etched, but the interdiffusion promoting film is preserved. Thereafter, the photoresist is removed by cleaning and heat treatment is performed to introduce impurities or pores only into the grooves, forming a metamorphic layer. In this way, the quantum well active layer on the side surface of the semiconductor pillar can be disordered. Even with this method, there is no deterioration of the reflective film or electrode, and no accompanying increase in electrical resistance.

更に、本発明では、周囲に溝を形成することにより、半
導体柱を形成しているので、溝をポリイミドで容易に埋
めこみプレーナ化できる。特に周囲の溝の幅を一定とす
ることにより、ポリイミドの埋め込み形状が−・定とな
り、再現良く平坦化できる。埋め込み後半導体柱の頂上
部のポリイミドは、ドライエツチングにより再現良く均
一に除去することが可能である。多数の面発光レーザを
集積したレーザアレイでは各々を独立駆動するために、
多数の配線をしなければならない。従来のレーザアレイ
ではプレーナ化が難しく、半導体柱の高さが2/,m程
度あるため、配線の段切れが起こり易く歩留りが低F 
していた。本発明は、ブし・−す化が容易であり、レー
ザの数が増えでも容易に細かい配線がO]能で、高密度
集積面発光レーザアレイに最適である。
Furthermore, in the present invention, since the semiconductor pillar is formed by forming a groove around the periphery, the groove can be easily filled with polyimide to form a planar structure. In particular, by making the width of the surrounding groove constant, the shape of the polyimide embedded becomes constant and can be flattened with good reproducibility. After embedding, the polyimide on the top of the semiconductor pillar can be uniformly removed with good reproducibility by dry etching. In a laser array that integrates a large number of surface emitting lasers, in order to drive each one independently,
A lot of wiring has to be done. With conventional laser arrays, it is difficult to planarize them, and the height of the semiconductor pillars is about 2/, m, so wiring breaks easily occur and the yield is low.
Was. The present invention is easy to bus, and allows fine wiring even when the number of lasers increases, making it ideal for high-density integrated surface emitting laser arrays.

(実施例) 次に本発明の実施例について図面を用いて詳細に説明す
る。第1図(a)〜(d)は本発明σルー実施例の製造
工程を示す断面図である。まず、第1図(a)示す様に
n型GaAs半導体基板1上に、n型AIAs802人
In型GaAs670人の23周期からなる第1導電型
の半導体多層反射膜2、A1o5Gao5As 143
0人/Ino2Gao8As10o入/A1o5Gao
5As1430人からなる量子井戸構造の活性層3、p
型GaAs67O人jp型AIAs802人10周期の
第2導電型の半導体多層反射膜4、p型GaAs30人
のキャップ層15を結晶成長する。ここで活性層3内部
のIno.2Gao.sAS層は正単一量子井戸の活性
層である。
(Example) Next, an example of the present invention will be described in detail using the drawings. FIGS. 1(a) to 1(d) are cross-sectional views showing the manufacturing process of the σ-roux embodiment of the present invention. First, as shown in FIG. 1(a), on an n-type GaAs semiconductor substrate 1, a semiconductor multilayer reflective film 2 of the first conductivity type consisting of 23 periods of 802 n-type AIAs and 670 in-type GaAs, 143 A1o5Gao5As, is formed.
0 people/Ino2Gao8As10o included/A1o5Gao
Active layer 3 with quantum well structure consisting of 1430 5As, p
A semiconductor multilayer reflective film 4 of the second conductivity type with 10 cycles of 670 type GaAs and 802 types of AIA, and a cap layer 15 of 30 types of p-type GaAs are crystal-grown. Here, Ino. inside the active layer 3. 2Gao. The sAS layer is a positive single quantum well active layer.

次に通常のフォトエツチング技術によってリング状溝7
を形成する。この時のエツープング深さは活性層構造3
まで達する様にする。エツチング方法は、反応性イオン
ビームエツチング(RIBE法)や反J:ii・性イオ
ンエツチング法(RIE法)等の指向性のあるもので垂
直な側面が得られる様に4る。この時に、発光領域とな
る2〜5/、m径の半導体柱6が形成される。
Next, a ring-shaped groove 7 is formed using a normal photo-etching technique.
form. The etupung depth at this time is active layer structure 3
Make sure that it reaches. The etching method is a directional method such as reactive ion beam etching (RIBE method) or anti-J:II reactive ion etching method (RIE method) so that vertical side surfaces can be obtained. At this time, a semiconductor column 6 having a diameter of 2 to 5/m is formed as a light emitting region.

次に相互拡散促進膜の5i02膜(厚さ1,000〜2
000人)を全面に形成する。
Next, the mutual diffusion promoting film 5i02 film (thickness 1,000~2
000 people) on the entire surface.

次に、再び指向性のあるドライエツチングを用いて5膜
02月莫5を、]ニニラチンする。ニラチン・グガスと
してCF、等が用いられる。エツチング方法は、やはり
RIBE法やRIE法を用いれば良い。この時にエツチ
ングビーム12が指向性があるためにリング状溝7の側
面に形成されたSiO2膜5のエツチング速度は極めて
遅い。このため第1図(b)に示す様に、平坦部のSi
O・2膜5のみをエツチングする事が出来Z)。次に、
As雰囲気において850°C1時間〜10時間程度の
熱処理を行なう。このとき、GaAs表面からのAsの
脱離を防ぐため、H2雰囲気中でGaAs基板で表面を
保護する方法(フェイストゥフェイス法)や石英アンプ
ル内部にAs粉末とレーリ′ウーLバー を同局に真゛
警(月じ切る事によってAs雰囲気を実現する方法等を
どると良い。この熱処理によってリング状溝7狽11面
のSiO2膜5の近傍のみ変成層(無秩序化領域)8を
形成する事が出来る。5i02膜5近傍で結晶が皿秩序
化・1−る理由は、結晶内部のA[原子が動きやt<3
102”AK 5を還元づるためど考えられているが訂
細な機構は明らかでは無い。この方法の他に、従来から
知られているSi拡散の方法を用いても良い1、この場
△−にはSiO□膜5の代わりにSiN膜/Si膜の2
層構造を用い(やはり第1図(b)の様に゛T’川、用
トのみ、これらの層をエツチング除去する。
Next, the 5-layer film is etched using directional dry etching again. CF, etc. are used as niratin gas. As the etching method, the RIBE method or the RIE method may be used. At this time, since the etching beam 12 is directional, the etching speed of the SiO2 film 5 formed on the side surface of the ring-shaped groove 7 is extremely slow. Therefore, as shown in FIG. 1(b), the Si
Only the O.2 film 5 can be etched (Z). next,
Heat treatment is performed at 850° C. for about 1 hour to 10 hours in an As atmosphere. At this time, in order to prevent As from being desorbed from the GaAs surface, there is a method of protecting the surface with a GaAs substrate in an H2 atmosphere (face-to-face method), and a method of applying As powder and a Lely wool bar inside the quartz ampoule.゛It is recommended to follow a method such as creating an As atmosphere by cutting the ring-shaped groove 7. By this heat treatment, a metamorphic layer (disordered region) 8 can be formed only in the vicinity of the SiO2 film 5 on the surface of the ring-shaped groove 7. The reason why the crystal becomes dish-ordered near the 5i02 film 5 is due to the movement of A [atoms inside the crystal and t<3
102" AK5 is thought to be reduced, but the detailed mechanism is not clear. In addition to this method, the conventionally known method of Si diffusion may be used. In this case, SiN film/Si film 2 is used instead of SiO□ film 5.
Using a layered structure (again, as shown in FIG. 1(b), only the "T'" layer is used), and these layers are removed by etching.

次に850°Cで1時間〜10時間程度の熱処理する事
によ−〕で81拡散がリング状溝7の側面のSiN膜/
Si膜の近傍のみで生じ、n型の無秩序化領域8が形成
される。この場合には、第1導電型半導体多層反射膜2
及び半導体基板1をp型として、第2導電型半導体多層
反射膜4をn型とした方が、半導体柱の頂に部にpn接
合が露出しないため都合が良い。又、SiN膜/Si膜
の代わりにZnドープスピンオングラス膜、Zn do
pe 5pin on Glass膜(SOG膜)を用
いる事も出来る。この場合は無秩序化領域はp型となる
Next, heat treatment is performed at 850°C for about 1 to 10 hours to cause 81 diffusion to occur in the SiN film on the side surface of the ring-shaped groove 7.
This occurs only in the vicinity of the Si film, and an n-type disordered region 8 is formed. In this case, the first conductivity type semiconductor multilayer reflective film 2
It is convenient to make the semiconductor substrate 1 a p-type and to make the second conductivity type semiconductor multilayer reflective film 4 an n-type because the pn junction is not exposed at the top of the semiconductor pillar. Also, instead of SiN film/Si film, Zn doped spin-on glass film, Zn do
A PE 5 pin on glass film (SOG film) can also be used. In this case, the disordered region becomes p-type.

次に第1図(e)のようにポリイミド13を、全面に汗
と坦となるよう塗布する。次に酸素ガスを用いたドライ
エツチングを用いて半導体柱6の頂上部のに達するまで
エツチングする。この時リング状溝70幅をほぼ一定と
することによって半導体柱6の頂上部の上にポリイミド
13の厚みウェハー内で均一とする事が出来る。このた
めポリイミドのドライエツチングにより、半導体柱6の
頂上部を歩留まり良く露出させる事が出来る。次にSi
N膜9を形成し、通常のフォトエツチングによって電極
をとるための窓を形成しp型電極10を形成する。この
場合、ポリイミドによる平坦化が実現さ、れているため
、p型電極10の段切れは生じない。最後にn型電極1
1を形成し、フォトエツチングによって、光出力取り出
し窓14を形成する。この様にして第1図(d)の本発
明の面発光レーザが完成する。
Next, as shown in FIG. 1(e), polyimide 13 is applied to the entire surface so that it is even with the sweat. Next, dry etching using oxygen gas is performed until the top of the semiconductor pillar 6 is reached. At this time, by making the width of the ring-shaped groove 70 substantially constant, the thickness of the polyimide 13 on the top of the semiconductor pillar 6 can be made uniform within the wafer. Therefore, by dry etching polyimide, the top portions of the semiconductor pillars 6 can be exposed with a high yield. Next, Si
An N film 9 is formed, a window for forming an electrode is formed by ordinary photoetching, and a p-type electrode 10 is formed. In this case, since planarization is achieved using polyimide, no breakage occurs in the p-type electrode 10. Finally, n-type electrode 1
1 is formed, and a light output extraction window 14 is formed by photoetching. In this way, the surface emitting laser of the present invention shown in FIG. 1(d) is completed.

本実施例においては、活性層構造としてAlo5Gao
5As/In、2Gao8As/Alo5Gao、As
の単一量子井戸構造としたが、材料や構造はこれに限ら
J″、多重量子井戸構造や単一層構造を用いても良い。
In this example, the active layer structure is Alo5Gao.
5As/In, 2Gao8As/Alo5Gao, As
Although the single quantum well structure is used, the material and structure are limited to J'', and a multiple quantum well structure or a single layer structure may also be used.

ただし、単一層構造の場合には、無秩序化の効果が弱く
なるため、層厚は100OA以下が好ましい。又、本実
施例ではギヤツブ層を用いたが、第2半導体多層反射膜
表面近傍を十分高濃度(p>10 cm  )にすれば
、ギャップ層を設けなくでも良い。又、半導体多層反射
膜としてGaAs67O人/AlAs802人のものを
用いたが、これに限らず発振光の波長λらに対して異な
る屈折率ni 、 n2を有し厚みが各々λ/4n、λ
/4n2の層の交互積層構造であれば他の組成及び厚み
でも良い。又、本実施例では、半導体柱の周りの溝パタ
ーンとして同心円状のリングパターンを用いたが、これ
に限らず四角形や他の図形のリング状パターンで溝の幅
がほぼ一定となっていれば、本発明が有効に適用出来る
However, in the case of a single layer structure, the disordering effect is weakened, so the layer thickness is preferably 100 OA or less. Furthermore, although a gap layer is used in this embodiment, it is not necessary to provide a gap layer if the concentration near the surface of the second semiconductor multilayer reflective film is made sufficiently high (p>10 cm2). Further, as the semiconductor multilayer reflective film, 670 GaAs/802 AlAs were used, but the invention is not limited thereto.
Other compositions and thicknesses may be used as long as the structure is an alternately laminated structure of /4n2 layers. Further, in this embodiment, a concentric ring pattern is used as the groove pattern around the semiconductor pillar, but the pattern is not limited to this, and a ring pattern of a rectangular or other shape may be used as long as the width of the groove is approximately constant. , the present invention can be effectively applied.

次に本発明の第2の実施例につい゛C図面を参照して詳
細に説明する。第2図(a)〜(e)は本発明の面発光
半導体レーザの一実施例の製造工程を説明するための断
面図である。
Next, a second embodiment of the present invention will be described in detail with reference to drawing C. FIGS. 2(a) to 2(e) are cross-sectional views for explaining the manufacturing process of one embodiment of the surface-emitting semiconductor laser of the present invention.

まずl〕型GaAs半導体基板1才にn型A]、As層
夕び11型GaAs層名々厚さλ/4n(λ:活性層の
禁止帯幅でほぼ決まるレーザ発振波長:n:半導体各層
の17酎J]率)で−文斤に約20周期積層したn型’
+、導体多層反射膜2ど厚さ500人〜17ymのn型
A、lXGa1−XA5(x=0.3−0.7)のn型
クラッド層16とNさ約100人のIn、、、Ga、 
、、。
First, a 1] type GaAs semiconductor substrate, an n type A] As layer, and an 11 type GaAs layer with a nominal thickness of λ/4n (λ: laser oscillation wavelength determined approximately by the forbidden band width of the active layer; n: each semiconductor layer) n-type layered with about 20 cycles of - Bunko at a rate of 17
+, conductive multilayer reflective film 2, n-type A with a thickness of 500 ~ 17ym, n-type cladding layer 16 of lXGa1-XA5 (x = 0.3-0.7), and N with a thickness of about 100 mm,... Ga,
,,.

As(y=0.05〜0.5)tilt子井戸層と厚F
 30〜200人のGaAs閉に込め層からなる量子−
井戸活性層3と厚さ500人〜1/1mのP型A17.
Ga1.As(z=0.3−0.7)p型クラッド層1
7ど、p型AlAs層どp型GaAs層を各々厚? A
/4nrで交互に約10〜20周期積層したp型半導体
多層反射1!に4ど厚さ10〜1000人のp型GaA
、sキャラ1層15とを分子線ユ、ピタギシ−(MBE
)法を用いて形成した1、次に成長した基板上にSiO
、SiN等の絶縁膜あるいはフォー・レジストを約30
00A〜5□m形成し7、フォー・リソグラフィ法によ
り、内径1/、m〜100./、m、外径約10μm〜
150μm程度のドーナツツ状の領域を除去し、同心円
状のマスク18を形成する。その後このマスク18を用
いてC1□プラズマによる反応性イオノビームエツチン
グ(RIBE)法等のドライエツチング技術にJす、少
なくとも量子用e”i耐l″′1層:3が露1゛1目−
るまでエツチングを行い講7を形成する(第2図(a)
)。
As (y=0.05~0.5) tilt well layer and thickness F
Quantum consisting of 30 to 200 GaAs confinement layers
Well active layer 3 and P type A17 with thickness 500 ~ 1/1 m.
Ga1. As (z=0.3-0.7) p-type cladding layer 1
7. How thick is the p-type AlAs layer and p-type GaAs layer? A
/4nr p-type semiconductor multilayer reflective layer alternately stacked for about 10 to 20 cycles 1! p-type GaA with a thickness of 10 to 1000
, s character 1 layer 15 and molecular beam Yu, Pitagishi (MBE
) method, and then SiO on the grown substrate.
, an insulating film such as SiN or a resist film of about 30
00A~5□m was formed 7, and the inner diameter was 1/m~100. /, m, outer diameter approximately 10 μm ~
A donut-shaped region of about 150 μm is removed to form a concentric mask 18. Thereafter, using this mask 18, a dry etching technique such as reactive ion beam etching (RIBE) using C1□ plasma is applied, so that at least the quantum layer 3 is exposed.
Etching is performed until the surface is completely etched to form a pattern 7 (Fig. 2(a)).
).

、−の時、この講7に囲まれた円柱;仄の発光領域6が
形成されるが、この発光領域6は講7をはさんで、コソ
チングされずに残っている′!導体層ζ川用5:に:h
でいるため、半導体(1の発光領域6にかかるストt2
スは著[7く軽減される。次に相互拡散促進膜となる5
102又はSiN膜等の絶縁膜5を全1111に形成I
5、その後フォトレジスト19を溝7が埋まる」)に箭
nii、″′塗布する。この時溝7iJつl/)−:♀
一体じ、付12、て、著しく小さいため、フt l−レ
ジスト・19はその粘性によりほぼ?τ′坦に塗布され
る(第2図(b))。次に酸素・イオン20を用いた反
+、:2:、性イ23>、□]ソーブング(RIE)等
のドライエツチング技術を用い、成長表面」二〇祁1縁
膜5が露出するまでノ第1・レジストをJノチング除去
Jる(第2図(C))。この後成長表向に露出しl−絶
縁膜5のみf、Jツチングで除去1.7、その後溝の中
の1.・シストを洗浄で除去リ−る。次に、例えばGa
As基板を保護基板として用いるフj−、イストウーフ
J−イス法等を用い、7008C〜900°Cで熱処理
を施−4゜この1−程により絶縁膜5中から不純物また
は空孔等が導入され溝7の部分のみに半導体変成層8が
形成され、発光領域6の側面の量子井フーコ活性層3は
無秩序化され、そこでは禁制帯幅が大きくなるので、実
効的に埋め込み構造が形成される(第2図(d))。こ
の時、絶縁膜5は成長表面には存在しないので、成長表
向からは不純物等が導入されず、発光効・rの低減、直
列抵抗の増大等の問題は生じない。尚、相互拡散促進膜
や熱処理方法は第1の実施例の中で示し7だ他の方法で
もよい。この後に、p側電極10としてAuを全面に形
成1〜だ後に、フォトリソグラフィ法により発光領域以
外のAuをエツチング除去する。最後にn型GaAs基
板1の裏面の発光領域6以外の部分にnull電極Ga
As基板11としてAuGeNi/ AuNiを形成し
第2図(e)に示す面発光半導体レーザが完成する。。
, -, a cylinder surrounded by this column 7; a second light-emitting region 6 is formed, but this light-emitting region 6 remains without being cosotched across the column 7'! Conductor layer ζ river 5: to: h
Therefore, the stress t2 applied to the light emitting region 6 of the semiconductor (1)
This is significantly reduced by 7 times. Next, 5 becomes a mutual diffusion promoting film.
An insulating film 5 such as 102 or SiN film is formed on the entire 1111 I
5. After that, apply photoresist 19 to the groove 7, which will be filled in. At this time, apply the photoresist 19 to the groove 7.
Since it is extremely small, the resist 19 is almost the same due to its viscosity. It is applied evenly (Fig. 2(b)). Next, a dry etching technique such as anti-irradiation (RIE) using oxygen/ions 20 is used to dry the growth surface until the edge film 5 is exposed. First, remove the resist by notching (FIG. 2(C)). After this, only the L-insulating film 5 exposed on the growth surface is removed by f and J cutting, and then the 1.7 insulating film in the groove is removed.・Remove the cyst by washing. Next, for example, Ga
Heat treatment is performed at 7008C to 900°C using the FJ method, Istwouf JIS method, etc. using an As substrate as a protective substrate.During this step 1, impurities or vacancies are introduced from the insulating film 5. A semiconductor metamorphic layer 8 is formed only in the groove 7, and the quantum I-Fuco active layer 3 on the side surface of the light emitting region 6 is disordered, and the forbidden band width becomes large there, so that a buried structure is effectively formed. (Figure 2(d)). At this time, since the insulating film 5 does not exist on the growth surface, impurities etc. are not introduced from the growth surface, and problems such as reduction in luminous efficiency and r, increase in series resistance, etc. do not occur. Note that the mutual diffusion promoting film and the heat treatment method may be other than those shown in the first embodiment. Thereafter, after forming Au on the entire surface as the p-side electrode 10, the Au is etched away from areas other than the light emitting region by photolithography. Finally, a null electrode Ga is formed on the back surface of the n-type GaAs substrate 1 other than the light emitting region 6.
AuGeNi/AuNi is formed as the As substrate 11, and the surface emitting semiconductor laser shown in FIG. 2(e) is completed. .

この実施例においても量子井戸活性層は単一量子井戸と
したが、これにかぎらず多重量子井戸であっても本発明
は適用できる。
In this embodiment as well, the quantum well active layer is a single quantum well, but the present invention is applicable not only to this but also to multiple quantum wells.

これにかぎらず、第1の実施例と同様にSi膜やZnド
ープ5OG(Spin−on−Glass)等を用いた
不純物導入による無秩序化を用いる場合においても本発
明は適用できる。
The present invention is not limited to this, and the present invention can also be applied to cases where disordering is used by introducing impurities using a Si film, Zn-doped 5OG (Spin-on-Glass), etc., as in the first embodiment.

以↓゛、2つの実施例で示した面発光レー リ゛では、
いずれも従来に比べ、無効電流を1/10以トにでき、
低しきい値での発振が司能である。また、製作工程や実
装時の破損もなく高歩留りで製作できる。
↓゛In the surface-emitting Rayleigh shown in the two examples,
In both cases, the reactive current can be reduced to more than 1/10 compared to conventional methods.
Oscillation at a low threshold is the main function. In addition, there is no damage during the manufacturing process or mounting, and the product can be manufactured at a high yield.

本発明の2つの実施例において材料系はGaAs/Al
GaAs系としたがこれに限らず他の材料系、例えばI
n、GaAs/InP系においCも本発明は適用できる
In two embodiments of the invention the material system is GaAs/Al
Although the material is GaAs-based, it is not limited to this, and other materials such as I
The present invention is also applicable to C in the GaAs/InP system.

(発明の効果) 本発明の面発光l、”−ザとぞの製造方法によれば表面
角結合の無効電流成分がほぼなくなり、低閾値電流で発
振する面発光レーザが高歩留りに製作出来る。しかも発
光領域に機械的ストレスがかかりにくく、素子特性の低
下や製造工程の歩留りの低干−もない。またブレーナ化
が容易であり、ブレーナ化することにより複数の電極配
線が容易で、細い配線でも段切れすることなく良好に形
成できるので、レーザアレイや集積素子に適している。
(Effects of the Invention) According to the method for manufacturing a surface emitting laser according to the present invention, the reactive current component due to surface angle coupling is almost eliminated, and a surface emitting laser that oscillates at a low threshold current can be manufactured with high yield. Moreover, mechanical stress is less likely to be applied to the light-emitting region, and there is no deterioration of device characteristics or low production process yields.Also, it is easy to form a brainer, and by forming a brainer, it is easy to wire multiple electrodes, and thin wiring is possible. However, since it can be formed well without step breaks, it is suitable for laser arrays and integrated devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜・(+i)は本発明にJ、る面発光甲、
導体1.・−ザの第1の実施例の製作1L程を示す断面
図である3、第2図(Fl)〜(e)は本発明の面発光
半、導体1.、−・ザの第2の実施例の製作工程を示−
9IN而しjである。 図において、1.・・・半導体基板、2・・・第1導電
型崖導体多層反躬)191.:3・・・活性層、4・・
・第2導電型半導体多層反躬膜、5・・・5102膜ま
t:は絶H膜、6・・伴導体社(発光領域)、711.
溝、8・、、!1’−導体変成層(無秩序化領域)、9
−−−8iN膜、1o−p型電棒、1F、、−n型電極
、12−−−−T−ツ(ングビーム、13・・・ポリイ
ミド、14・・・光出力取り高1゜窓、15・・・Aヤ
ソブ層、16・・・n型クラッド層、17=、、p型ク
ラッド層、18・・・\′スク、19・・・ソオトレジ
スト、20・・・酸素・fオ)3゜
FIG. 1(a) to (+i) are J, surface-emitting insteps according to the present invention,
Conductor 1. 3, which is a cross-sectional view showing about 1L of fabrication of the first embodiment of the present invention, and FIGS. , - shows the manufacturing process of the second embodiment of -
It's 9IN. In the figure, 1. . . . semiconductor substrate, 2 . . . first conductivity type cliff conductor multilayer reflection) 191. :3...active layer, 4...
・Second conductivity type semiconductor multilayer anti-reflective film, 5...5102 film, 6. Ban conductor company (light emitting area), 711.
Groove, 8...! 1'-conductor metamorphic layer (disordered region), 9
---8iN film, 1o-p type electric rod, 1F, -n type electrode, 12---T-shaped beam, 13...polyimide, 14...light output height 1° window, 15 ... A Yasobu layer, 16... N-type cladding layer, 17=,, P-type cladding layer, 18...\'Screw, 19... Sotoresist, 20... Oxygen/fO) 3°

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板上に、第1導電型の半導体多層反射膜
と、少なくとも1つの量子井戸構造をもつ量子井戸活性
層と、第2導電型の半導体多層反射膜とを少なくとも備
え、前記量子井戸活性層に達する溝で囲まれた発光領域
となる半導体柱を有し、前記溝の半導体側面に変成層を
備えることを特徴とする面発光半導体レーザ。
(1) At least a semiconductor multilayer reflective film of a first conductivity type, a quantum well active layer having at least one quantum well structure, and a semiconductor multilayer reflective film of a second conductivity type are provided on a semiconductor substrate, and the quantum well 1. A surface-emitting semiconductor laser comprising a semiconductor column serving as a light emitting region surrounded by a groove reaching an active layer, and a metamorphic layer provided on a semiconductor side surface of the groove.
(2)半導体基板上に、第1導電型の半導体多層反射膜
と、少なくとも1つの量子井戸構造をもつ量子井戸活性
層と、第2導電型の半導体多層反射膜とを少なくとも備
える半導体層を形成する工程と、前記量子井戸活性層に
達する溝をエッチングにより形成し、該溝で囲まれた発
光領域となる半導体柱を形成する工程と、少なくとも絶
縁膜を含む相互拡散促進膜を半導体表面に形成する工程
と、前記溝の側面を除いて、指向性のあるドライエッチ
ングにより、前記相互拡散促進膜を除去する工程と、熱
処理により前記溝の側面の半導体層において相互拡散を
行なう工程とを、備えることを特徴とする面発光半導体
レーザの製造方法。
(2) Forming on a semiconductor substrate a semiconductor layer comprising at least a semiconductor multilayer reflective film of a first conductivity type, a quantum well active layer having at least one quantum well structure, and a semiconductor multilayer reflective film of a second conductivity type. forming a groove reaching the quantum well active layer by etching to form a semiconductor pillar that becomes a light emitting region surrounded by the groove; and forming an interdiffusion promoting film including at least an insulating film on the semiconductor surface. a step of removing the interdiffusion promoting film by directional dry etching except for the side surfaces of the groove; and a step of performing interdiffusion in the semiconductor layer on the side surfaces of the groove by heat treatment. A method of manufacturing a surface emitting semiconductor laser, characterized in that:
(3)半導体基板上に、第1導電型の半導体多層反射膜
と、少なくとも1つの量子井戸構造をもつ量子井戸活性
層と、第2導電型の半導体多層反射膜とを、少なくとも
備える半導体層を形成する工程と、前記量子井戸活性層
に達する溝をエッチングにより形成し、該溝で囲まれた
発光領域となる半導体柱を形成する工程と、少なくとも
絶縁膜を含む相互拡散促進膜を半導体表面に形成する工
程と、該相互拡散促進膜上にフォトレジストを前記溝が
平坦になるように塗布する工程と、前記溝部を除いてエ
ッチングにより、前記相互拡散促進膜を除去する工程と
、熱処理により、前記溝部において相互拡散を行ない半
導体変成層を形成する工程とを、備えることを特徴とす
る面発光半導体レーザの製造方法。
(3) A semiconductor layer comprising at least a semiconductor multilayer reflective film of a first conductivity type, a quantum well active layer having at least one quantum well structure, and a semiconductor multilayer reflective film of a second conductivity type, on a semiconductor substrate. forming a groove that reaches the quantum well active layer by etching and forming a semiconductor pillar that becomes a light emitting region surrounded by the groove; and forming an interdiffusion promoting film including at least an insulating film on the semiconductor surface. a step of applying a photoresist on the mutual diffusion promoting film so that the groove becomes flat; a step of removing the mutual diffusion promoting film by etching except for the groove portion; and a step of removing the mutual diffusion promoting film by heat treatment. A method for manufacturing a surface emitting semiconductor laser, comprising the step of performing interdiffusion in the groove to form a semiconductor metamorphic layer.
JP2164402A 1990-06-22 1990-06-22 Manufacturing method of surface emitting semiconductor laser Expired - Lifetime JP2689694B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2164402A JP2689694B2 (en) 1990-06-22 1990-06-22 Manufacturing method of surface emitting semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2164402A JP2689694B2 (en) 1990-06-22 1990-06-22 Manufacturing method of surface emitting semiconductor laser

Publications (2)

Publication Number Publication Date
JPH0461184A true JPH0461184A (en) 1992-02-27
JP2689694B2 JP2689694B2 (en) 1997-12-10

Family

ID=15792453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2164402A Expired - Lifetime JP2689694B2 (en) 1990-06-22 1990-06-22 Manufacturing method of surface emitting semiconductor laser

Country Status (1)

Country Link
JP (1) JP2689694B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000016861A (en) * 1998-06-30 2000-01-18 Inax Corp Easily processable pottery plate and board using the same
US7435604B2 (en) * 2003-09-08 2008-10-14 Epistar Corporation Method of making light emitting diode
JP2012505541A (en) * 2008-10-14 2012-03-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Vertical cavity surface emitting laser with improved mode selectivity
JP2014135371A (en) * 2013-01-10 2014-07-24 Ricoh Co Ltd Surface emitting laser, surface emitting laser array and optical scanning device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936988A (en) * 1982-08-26 1984-02-29 Agency Of Ind Science & Technol Vertical oscillation type semiconductor laser
JPS63153878A (en) * 1986-12-18 1988-06-27 Fujitsu Ltd Manufacture of semiconductor light-emitting device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936988A (en) * 1982-08-26 1984-02-29 Agency Of Ind Science & Technol Vertical oscillation type semiconductor laser
JPS63153878A (en) * 1986-12-18 1988-06-27 Fujitsu Ltd Manufacture of semiconductor light-emitting device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000016861A (en) * 1998-06-30 2000-01-18 Inax Corp Easily processable pottery plate and board using the same
US7435604B2 (en) * 2003-09-08 2008-10-14 Epistar Corporation Method of making light emitting diode
US7704760B2 (en) 2003-09-08 2010-04-27 Epistar Corporation Method of making light emitting diode with irregular surface and independent valleys
JP2012505541A (en) * 2008-10-14 2012-03-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Vertical cavity surface emitting laser with improved mode selectivity
JP2014135371A (en) * 2013-01-10 2014-07-24 Ricoh Co Ltd Surface emitting laser, surface emitting laser array and optical scanning device

Also Published As

Publication number Publication date
JP2689694B2 (en) 1997-12-10

Similar Documents

Publication Publication Date Title
JP3672678B2 (en) Quantum semiconductor device and manufacturing method thereof
US7983319B2 (en) Surface-emitting type semiconductor laser that controls polarization directions of laser light and method for manufacturing the same
CN113396486B (en) Indium phosphide VCSEL with dielectric DBR
US20060187991A1 (en) Laterally oxidized vertical cavity surface emitting lasers
US7668219B2 (en) Surface emitting semiconductor device
JP2005086170A (en) Surface light emitting semiconductor laser and manufacturing method of the same
JP3271291B2 (en) Surface emitting semiconductor laser
JPH0461184A (en) Surface luminescent semiconductor laser and manufacture thereof
JP3459003B2 (en) Semiconductor device and manufacturing method thereof
JP2001068783A (en) Surface-emission laser and manufacture thereof
JPH06252504A (en) Surface-emission laser and manufacture thereof
JP2002299761A (en) Semiconductor light-emitting device of surface-emitting type, and method of manufacturing the same
JP2023094519A (en) Photon source and method of manufacturing photon source
JP2004335964A (en) Surface-emission semiconductor laser element and its manufacturing method
JP2000012962A (en) Surface emitting semiconductor laser and its manufacture
JPS6289383A (en) Semiconductor laser
JP2002217492A (en) Surface-emitting semiconductor laser and its manufacturing method
US20050230694A1 (en) Optical device and method of fabricating an optical device
JP2003017806A (en) Compound semiconductor light-emitting element, manufacturing method therefor, and the compound semiconductor light-emitting device
JPS63179590A (en) Algainp semiconductor light emitting element
WO2022097513A1 (en) Vertical resonator type surface-emitting laser element and method for manufacturing vertical resonator type surface-emitting laser element
JPH02128481A (en) Manufacture of light emitting device
JPH0414276A (en) Surface-emitting semiconductor laser element
JPH04275478A (en) Manufacture of surface light emitting semiconductor laser
JP2005026625A (en) Surface-emitting laser and its manufacturing method

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070829

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080829

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080829

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090829

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090829

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100829

Year of fee payment: 13

EXPY Cancellation because of completion of term