JPH0457560A - Thermosensing head controller - Google Patents

Abstract

PURPOSE:To reduce the time for propagating a print enable data by providing a gate means to an input stage comprising plural prescribed flip-flops and allowing flip-flop gate means of next and succeeding stages to skip the print enable data when a non-print data is inputted. CONSTITUTION:A print enable data shifter 3 consists of plural flip-flops 3a-3n connected in cascade. Then gate means 23a-23n-k-1 (kin) receiving a print data and a print enable data are connected to each input stage of plural prescribed flip-flops among the plural flip-flops 3a-3n. The gate means 23a-23n-k-1 do not input a print enable data to a flip-flop just after the connection of the gate means thereto when the print data is a non-print data but allow the gate means for the flip-flops of next and succeeding stages to skip the print enable data. Thus, the time for enabling print is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thermal head control device that improves printing speed.

[Background of the Invention] In a thermal head used in a thermal printer, etc., divisional printing is performed in order to save power on the power to drive the thermal head, but when performing such divisional printing, Problems have been pointed out, such as a decrease in recording density at the ends of the divided printing sections and unevenness in the printing results at the boundaries of the divided sections.

A means to solve such power supply capacity problems and density changes at the ends of divided printing sections is disclosed in ``Japanese Unexamined Patent Publication No. 1-264''.
No. 861 Publication,'' etc.

A conventional example of such a thermal head control device will be explained with reference to FIGS. 6 and 7.

The number of thermal head control devices shown in FIG. 6 is N (N=204
8) heating resistor 1, a two-man powered NAND gate 2 that controls energization to these, a printing data latch 4 that provides print data to be input to one terminal of the two-man powered NAND gate 2, and a A printing data shifter 5 for serial input in a dual system, a printing permission data shifter 3 for providing printing permission data to be input to the other terminal of the two-man NAND gate 2, and a printing permission data shifter 3 for facilitating control of printing permission data. It consists of 6 AND-OR gates. 2-man power NAND gate 2 is printing permission data shifter 3
It also functions as part of.

Next, the operation will be explained with reference to the timing chart of FIG.

First, when the power supply VH rises, the printing data shifter 5
To reset all the contents to 0, reset 4g No. R
Enter ESET. This prevents the heating resistor 1 from accidentally generating heat.

Next, N pieces of print data for one line are conveyed to the data terminal of the print data shifter 5 and input in synchronization with the lock CLK. When the input of the print data is completed, the print data latch 4 latch pulse LATCH is supplied to latch the print data.

Next, the printing permission data is conveyed and inputted to the PDATAI terminal in synchronization with the lock PCLK, and in order to enable reuse of the printing permission data input at the same time, a cycle signal CY
Set CE to "1".

In addition, the printing permission data is "1" indicating printing permission (therefore,
(black image), and printing is prohibited at [0] (white image).

Here, the number of consecutive print permission data "1" is set according to the power supply capacity of the thermal head. -As an example, it is about =N/4.

After inputting the printing permission data, it is sufficient to keep the cycle signal CYCE at "1" and continue inputting the transport lock PCLK until the heating resistor 1 generates heat to a specified temperature. This is because the final stage output PENB-N of the printing permission data shifter 3 is fed back to the printing permission data PDATA.

Next, when recording the next line of print data that has already been set in the print data shifter 5 while recording one line,
After supplying the latch pulse LATCH, parameters such as the above-mentioned K are reset.

Now, FIG. 8 shows a partial configuration example of the printing permission data shifter 3 and the printing data latch 4. As shown in FIG.

The printing permission data shifter 3 is composed of N flip-flops 3a, 3b, . . . , 3n connected in series. The figure shows only two of them, 3a and 3b.

Similarly, the print data latch 4 also includes N flip-flops 48 to 4n.
Print data Do, Dl, . . . Dn obtained from the print data shifter 5 are supplied to each data terminal 4n.

The latched print data is input to the print permission data shifter 3. The printing permission data PDATA is input to the first-stage flip-flop 3a constituting the printing permission data shifter 3, and is sequentially sent to the succeeding-stage flip-flops 3b, . . . , 3n in synchronization with the transport lock PCLK.

And each flip-flop 3a, 3b,...
The output of printing permission data PDATA which is the output of 3n,
The heating resistors 1, that is, R1, R2, . . . , Rn are driven by the NAND output with the printing data.

As is clear from this configuration, the printing permission data PDATA
are cascaded flip-flops 3a, 3b, . . . , 3
While propagating n sequentially, the signal propagates from the left end to the right end of one line.

[Problems to be Solved by the Invention] By the way, when the printing permission data shifter 3 is configured with flip-flops in a cascade configuration as described above, it is necessary to sequentially shift the input printing permission data PDATA while changing the logic between the printing permission data and the printing data. The heat generating resistor 1 is controlled by the heat generating resistor 1. In this way, since printing is performed while shifting the timing for each pixel, there is no consideration at all as to how many black pixels are actually printed. Regarding pixels from end to end of one line,
The time required to start printing is determined by the product of the number of pixels in one line and the time interval of the shift.

Therefore, even if there is a section of continuous white pixels that does not actually need to be printed, printing is permitted for that section using the printing permission data, which requires wasted time. .

For this reason, the printing speed cannot be improved in the conventional configuration.

Therefore, the present invention solves these conventional problems, and proposes a thermal head control device that can achieve power saving and particularly improve printing speed, as described above.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention includes a printing data shifter, a printing data latch, and controlling the output of the latched printing data while sequentially shifting printing permission data. The printing permission data shifter is composed of a printing permission data shifter, and a heating resistor to which printing data output from the printing permission data shifter is supplied. At the same time, a gate means to which print data and printing permission data are supplied is connected to the input stage of a predetermined flip-flop, so that when non-print data is input, the gate means is connected to the input stage of a predetermined flip-flop. The present invention is characterized in that the printing permission data is skipped to the subsequent flip-flop gate means.

[Function] Also in the present invention, the printing permission data shifter 3 includes a plurality of cascade-connected flip-flops 3a.

It is composed of 3b, . . . , 3n. And these plurality of flip-flops 3a, 3b, . . .
3n, gate means 23a, 23b, ``'''', 23n- to -1(
kin) are connected and configured.

These gate means 23a, 23b, ..., 23n
In -1, when the printing data is non-printing data, the printing permission data is not input to the flip-flop immediately after the gate means is connected, but the gate means for the next flip-flop is used. This printing permission data is skipped.

By doing this, when the printing data is "o", that is, a white image, even if the printing permission data is "1", it is skipped and the printing permission data PDATA is transmitted to the gate means of the next flip-flop. Ru.

In this way, by skipping the flip-flop to which print data of "1" is input, the delay in propagation speed caused by the flip-flop is eliminated. In particular, when one line is all white, the printing permission data is sequentially propagated backwards without passing through the flip-flop. ) The time t2 (see FIG. 3) from when PDATAI is obtained until the final stage output PENB-N is output is shortened.

This time t2 is much shorter than the time t1 of the conventional example shown in FIG. As a result, printing permission data PDAT
As the time it takes for A to reach the end is significantly shortened, the printing time for one line is shortened. And with k◆1 conventional flip-flop, t2>tk,
The time for feeding back and using the output of the final stage output PENB-N can be secured.

[Embodiment] Next, a case in which an example of the thermal head control device according to the present invention is applied to a thermal printer will be described in detail with reference to FIG. 1 and subsequent figures.

FIG. 1 is a configuration diagram showing an example of a thermal head control device according to the present invention, and in the present invention, as in the conventional case, N heat generating resistors 1 and a circuit system for driving and controlling them are shown. Consists of.

That is, it is composed of a print data latch 4 that latches a print data shifter, and a print permission data shifter 3 that can be supplied with print data latched by the print data latch 4 and print permission data PDATA. The printing permission data shifter 3 includes gate means 23g and 23b as shown in FIG.
, ..., -1 (kin, about k=n/4) can be connected to 23n-.

These gate means 23a, 23b, ..., 23n
- flip-flops 3a, 3b, . . .
. . , 3n- to -1, the output thereof is connected to the heating resistor 1 through inverters 13a+13b, . . . , 13n- to -1.

That is, in the present invention, n-
−1 flip-flop 3a, 3b,..., 3
Gate means 23a, 23b are provided only at the n- to -1 input stage.
, ..., -1 is connected to 23n-.

-1 to gate means 23a, 23b, . . . 23n-
is supplied with printing data and printing permission data respectively, and when the data is not to be printed (non-printing data), instead of inputting the printing permission data to the flip-flop connected to this gate means, the next The logic configuration is such that printing permission data is propagated to gate means provided in predetermined flip-flops after the stage.

FIG. 1 is an example of this, and in this example, flip-flops 38 to 3 corresponding to -1 to the heat generating resistors R1 to Rn-, respectively, are connected to the input stages of -1 to n- from the first stage. -1 is provided to the gate means 238 to 23n-.

After that, ◆ until one heating resistor Rn- = RN,
This is the same as the conventional configuration. That is, the input stages of .about.3n are directly connected to each flip-flop 3n- without using gate means.

FIG. 2 shows details of the main part of the configuration in FIG. 1.

The explanation of the same parts as the configuration shown in FIG. 8 will be omitted, but each of the flip-flops from the first stage flip-flop 3a to the n-1st stage (in the figure, up to the second stage is illustrated). Gate means 23a and 23b as shown in the figure are connected to the data input stage of.

To explain the first stage gate means 23a, the printing permission data PDATA and the printing data corresponding to the first pixel output from the printing data latch 4 are connected to the AND gate 3.
3a, and its output is supplied to the data terminal of flip-flop 3a.

In addition, the printing permission data PDATA and the inverter 53a
The print data DO supplied via the AND gate 4
3a, and its AND output is fed to flip-flop 3
The OR output is supplied to the OR gate 63a together with the output of a, and the OR output is supplied to the gate means 23b of the next stage as printing permission data for the next stage.

Furthermore, the outputs of the flip-flops 3a and 3b can be supplied to the heating resistors R1 and R2 via inverters 13a and 13b.

When such a configuration is adopted, when the print data obtained at the terminals Do and DI are both "1" (that is, a black image) and the print permission data PD and ATA are "1", the AND gate of the gate means 23a is 33a is opened and printing data DO is input to the flip-flop 3a, which is supplied to the heating resistor R1 via the inverter 13a in synchronization with the transport lock PCLK. Printing is performed in this way.

At this time, since the AND gate 43a is off, only the printing permission data PDATA is supplied via the OR gate 63a. Therefore, the next stage gate means 2
3b, the AND gate 33b is opened and a signal having the same polarity as the printing permission data is output from the flip-flop 3b, thereby driving the heating resistor R2.

Therefore, the printing permission data PDATA input in the first stage
are sequentially shifted to the right and transmitted.

On the other hand, when the print data obtained at terminals Do and DI are both "O" (that is, a white image),
Even if the printing permission data PDATA "1" is obtained in the gate means 23a, the AND gate 33a does not open and therefore the heating resistor R1 is not driven. In this case, the AND gate 438 is opened and the printing permission data PDATA is supplied to the next stage gate means 23b via the OR gate 63a.

Similar processing is performed in this gate means 23b, and the printing permission data PDATA supplied to the next stage is sent to a subsequent flip-flop block (not shown) via an OR gate 63b without passing through the flip-flop 3b. communicated.

In this way, print data is non-print data, that is, "0".
”, the printing permission data PDATA is “1”.
Even if it is, the printing permission data is propagated to the subsequent flip-flop by skipping the flip-flops 3a and 3b, so the printing permission data PDATA is
shift time can be reduced.

This shortening process is performed from the first stage to n-1 flip-flops, and after that, for +1 flip-flops, printing permission data is passed through each flip-flop as before. PDATA will be propagated.

Therefore, as shown in FIG. 3, after the original printing permission data PDATAI is obtained, the final stage output PENB
- Until N is obtained, change 1'alt2 to the conventional tl
can be significantly shortened. In addition, k
Since the +1 conventional flip-flops ensure a delay time such that t2>tk, the final stage output PENB-N can be fed back and used repeatedly as before.

If you create PDATA without using this feedback (for example, when M = tk), it goes without saying that t2 can be further shortened by applying shortening processing to k-1 conventional flip-flops as well. Nor.

Particularly when one line is all white data, the shift time is shortened, so the time required to move to the next line is significantly shortened. As a result, the overall printing time can be shortened, and the printing speed can be improved compared to the conventional method.

In the configuration shown in FIG. 2, the flip-flops 3a,
Gate means 23a, 2 provided between stages of 3b...
This is an example in which printing permission data PDATA is sequentially propagated via 3b...
printing permission data PDA that can be supplied to the output of the inverter 53a and the first-stage gate means 23a in units of
It is also possible to configure the AND output with TA to be supplied to the OR gate 63 provided in the Mth flip-flop 3.

An example is shown in FIG. 70 indicates an AND gate for this purpose.

In the case of this configuration, for example, all the print data from the first stage to the Mth print data DO to Dn are "O".
"In other words, if the image is white, the printing permission data P
When DATA becomes "1", the AND gate 70 immediately opens and the printing permission data PDATA is transmitted to the OR gate 63m.

With such a configuration, the printing permission data PD is immediately sent to the final OR gate 63■ without using a gate means or the like.
Since the ATA propagates, the propagation delay time can be further reduced than in the case of the configuration shown in FIG.

Furthermore, in the example shown in FIG. 1, a configuration has been described in which gate means are provided at the input stage of each of the flip-flops from the first stage to the n-1 stage, but it may also be configured as shown in FIG. be able to.

The example shown in FIG. 5 is a case where, for example, the configuration shown in FIG. 2 is adopted in units of four pixels.

In the figure, gate means are arranged in flip-flops for three pixels for four pixels.

With this configuration, compared to FIG. 1, it becomes possible to take measures against propagation delay using gate means and flip-flops.

For example, in the case of N=2048 and K=512,
Regarding the configuration in FIG. 1, if, for example, 1535 flip-flops are configured with gate means,
Assuming that the transport lock PCLK is 2 MHz, the allowable amount of delay time required for passage through one flip-flop is Q, about 32 nsec.

On the other hand, as shown in FIG. 5, when a plurality of flip-flops are used as a unit and some of them have gate means, the delay time per flip-flop is 5.00. /4nsec=125nsec
Since the circuit shown in FIG.

[Effects of the Invention] As explained above, in the present invention, a gate means is provided for the input stage of a plurality of predetermined flip-flops, and when non-printing data is input, the gate means for the next and subsequent stages of flip-flops is provided. The configuration is such that the printing permission data is skipped.

According to this, the time for propagating printing permission data can be significantly shortened, so that printing can be performed at high speed. Therefore, the thermal head control device according to the present invention is suitable for application to thermal printers and the like.

[Brief explanation of the drawing]

FIG. 2 is a configuration diagram showing an example, FIG. 3 is a waveform diagram for explaining its operation, FIG. 4 is a configuration diagram showing another example of FIG. 2, and FIG. 1, FIG. 6 is a configuration diagram showing an example of a conventional thermal head control device, FIG. 7 is an explanatory diagram of its operation, and FIG. 8 is a configuration diagram of main parts of FIG. 6. It is. 1...Heating resistor 3...Printing permission data shifter 4...Printing data latch 5...Printing data shifter 6...And-or gate 3a, 3b, ``..., 3n...Flip-flop 23a , 23b, ..., 23n... Gate means 33a, 33b, 43a, 43b... AND gate

Claims (1)

[Claims] (1) A printing data shifter, a printing data latch, a printing permission data shifter that controls the output of the latched printing data while sequentially shifting the printing permission data, and a printing permission data shifter that controls the printing data output from the printing permission data shifter. The print permission data shifter is composed of flip-flops in a cascade configuration corresponding to each heat-generating resistor, and the input stage of a predetermined flip-flop receives print data and print data. When the gate means to which permission data is supplied is connected and non-printing data is input, the printing permission data is skipped to the gate means for flip-flops from the next stage onward without inputting it to the immediately succeeding flip-flop. A thermal head control device characterized by the following features: