JPH0456575A - Picture display device - Google Patents

Abstract

PURPOSE:To reproduce and display both an analog picture such as television picture and a digital picture such as a computer picture with fidelity by providing a 2nd sampling pulse generating circuit having a delay line to the display device. CONSTITUTION:Plural display video signals 51, 52 are selected by a changeover circuit 50a and fed to a sample-and-hold circuits 31a--31n for a video signal, a sampling pulse output from a 1st sampling pulse generating circuit 54a and a 2nd sampling pulse generating circuit 54b having delay lines 55a, 55b is selected synchronously with display the video signals 51, 52, and a display video signal whose pattern is changed synchronously with a basic clock like an output picture of a computer is subject to sampling and holding by the 1st sampling pulse generating circuit 54a and the display video signal having no fundamental clock therein like a television pattern is subject to sample and holding by the 2nd sampling pulse generating circuit 54b. Thus, the video signal is reproduced and displayed with fidelity.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image display device for displaying television images and computer images.

2. Description of the Related Art The basic structure of a conventional image display device will be explained with reference to FIG.

This display element consists of a back electrode 1, a line cathode 2 as a beam source, a beam extraction electrode 3, a beam flow control electrode 4, a focusing electrode 5, a horizontal deflection electrode 6, a vertical deflection electrode 7, and a screen in order from the back to the anode side. A plate 8, etc. are arranged, and these are housed inside the vacuum container.

A line cathode 2 serving as a beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction.
A plurality of line cathodes 2 are further provided at intervals in the vertical direction (in this description, only seven line cathodes 2A to 2G are shown). In this configuration, the spacing between the line cathodes is 3cm and the number of line cathodes is 30, and the number of line cathodes is 2 to 27. The distance between the line cathodes cannot be freely increased, but is regulated by the distance between the vertical deflection electrode 7 and the screen 8, which will be described later. The configuration of these line cathodes 2 is 10~
An oxide cathode material is applied to the surface of a 30 μmφ tungsten rod. As will be described later, the line cathodes are controlled to sequentially emit electron beams from the upper line cathode 2a to the lower line cathode 27 for a fixed period of time. The back electrode 1 has the function of suppressing the generation of electron beams from line cathodes other than the corresponding line cathode, and also has the function of pushing the electron beams only toward the anode. Although the vacuum container is not shown in Figure 2,
It is also possible to use the back electrode 1 to form a structure that is integrated with the vacuum container. The beam extraction electrode 3 is a conductive plate 11 having a plurality of through holes 10 provided at regular intervals in the horizontal direction facing each of the line cathodes 2a to 27, and allows the electrons emitted from the line cathodes 2 to be the beam through its through hole 1
Take it out through o. Next, the control electrode 4 is connected to the line cathode 2-2.
The conductive plate 15 is made up of a vertically long conductive plate 15 having a through hole 14 at a position facing each of the conductive plates 7, and in a configuration in which a plurality of conductive plates 15 are arranged in parallel horizontally at a predetermined interval, the conductive plate 15 has 12 conductive plates.
Zero conductive plates 15a to 15n for control electrodes are provided (only eight are shown in FIG. 2). The control electrode 4 controls the amount of passage of each of the electron beams divided horizontally by the electric beam extraction electrode 3 in accordance with the picture elements of the video signal and in synchronization with the timing of horizontal deflection, which will be described later. .

The focusing electrode 5 focuses the electron beam on a conductive plate 17 having a through hole 16 at a position facing each through hole 14 provided in the control electrode 4 .

The horizontal deflection electrode 6 is composed of a plurality of conductive plates 18.18° arranged vertically along both horizontal sides of the through hole 16, and each conductive plate has a horizontal deflection plate. voltage is applied.

The electron beams for each picture element are each deflected in the horizontal direction, and in the zero-line configuration in which R, G, and B phosphors are sequentially irradiated on the screen 8 to emit light, each electron beam is deflected by two trios. ing. The vertical deflection electrode 7 is made up of a plurality of conductive plates 19 19 , which are arranged horizontally at vertically intermediate positions of the through holes 16 , and a vertical deflection voltage is applied to the conductive plates 19 , 19 . In the 0 line configuration, the electron beam generated from one line cathode is deflected by 8 lines in the vertical direction by a pair of electrodes 19.19''. By the deflection electrode 7, 30 wires corresponding to each of the 30 wire cathodes are
Pairs of vertical deflection conductors are constructed to draw 240 horizontal scanning lines in the vertical direction on the screen 8.

As explained above, in this configuration, a plurality of horizontal deflection electrodes 6 and a plurality of vertical deflection electrodes 7 are each arranged in a comb shape. Furthermore, by setting the distance to the screen 8 longer than the distance between the horizontal and vertical deflection electrodes, it becomes possible to irradiate the screen 8 with the electron beam with a small deflection amount.

This allows horizontal and vertical deflection electrodes I can do that.

As shown in FIG. 2, the screen 8 is constructed by coating the back surface of a glass plate 21 with phosphor 20 in stripes.

Although not shown, a metal back and carbon are also coated. The phosphor 20 is inserted into one through hole 14 of the at control pole 4.
By horizontally deflecting the electron beam penetrating R
, G, and B so as to irradiate two trios of phosphor pairs of three colors, and are applied vertically in stripes.

In FIG. 2, the broken lines drawn on the screen 8 indicate the vertical divisions displayed corresponding to each of the plurality of line cathodes 2, and the two-dot chain lines indicate the sections corresponding to each of the plurality of control electrodes 4. Indicates the horizontal division that will be displayed. FIG. 3 shows an enlarged view of one section partitioned by broken lines and two-dot chain lines.

As shown in Figure 3, in the horizontal direction, R and G for two trios.
, B has a width of 8 lines in the vertical direction. In this example, the size of one section is 1 square meter in the horizontal direction and 3 meters in the vertical direction.

Although the phosphors of each of the three colors R, G, and B are shown in stripes in FIG. 3, they may be arranged in a delta.

However, when arranged in a delta shape, it is necessary to apply horizontal and vertical deflection waveforms that are compatible with the arrangement.

In FIG. 3, for convenience of explanation, the aspect ratio is different from the image displayed on the actual screen.

Furthermore, in this configuration, two trios of R, G, and B phosphors are provided for one through hole 14 of the control electrode 4;
It may be composed of one trio or three or more trios. However, controll! One trio or three or more trios of R, G, and B video signals are sequentially separated on the electrode 4, and it is necessary to perform horizontal deflection in synchronization with these.

Next, the operation of the drive circuit for driving this display element will be explained with reference to FIG. First, a driving portion that irradiates the screen 8 with an electron beam to display an image will be explained.

The power supply circuit 22 is a circuit for applying a predetermined bias voltage to each electrode of the display element, including Vl to the back electrode 1, ■3 to the beam output electrode 3, V5 to the converging electrode 5, and V8 to the screen 8. Apply a DC voltage of Line cathode drive circuit 26
creates line cathode drive pulses (I-MA) using the vertical synchronization signal (1) and the horizontal synchronization signal (H). FIG. 5 shows the timing diagram.

Each line cathode 2a to 27 is as shown in FIG.
A current flows and heats up while the drive pulse is at a high potential, and the heated state is maintained such that electrons are emitted while the drive pulse (I to M) is at a low potential. As a result, electrons are emitted from the 30 line cathodes 2a to 27 only during eight horizontal scanning periods to which low-potential drive pulses (i to ma) are applied, respectively. During the period when a high potential is applied, the potential applied to the line cathodes 2-27 is lower than the potential around the line cathode 2 determined by the bias voltage applied to the back electrode 1 and the beam extraction 11ffi3. Since the line cathode becomes higher, no electrons are emitted from the line cathode.

To construct one screen, the potentials may be sequentially switched from the upper line cathode 2a to the lower line cathode 27 every 8 scanning periods.

Next, the deflection voltage generation circuit 40, whose deflection part will be explained, is as follows.
It is composed of a direct memory access roller (hereinafter referred to as a DMA controller) 41, a deflection voltage waveform storage memory (hereinafter referred to as a deflection memory) 42, a digital-to-analog converter (hereinafter referred to as a D/A converter) 43h, 43v, etc. , vertical deflection signal V.

Vo and horizontal deflection signal h' are generated.

In this configuration, 240 horizontal scanning periods are displayed in one field in consideration of overscanning regarding the vertical deflection signal. In addition, the memory address area that stores the vertical deflection position information corresponding to each line is
The field is divided into a field and a second field, each having one set of memory capacity. When displaying, data is read from the corresponding deflection memory 42, converted to an analog signal by the D/A converter 43v, and applied to the vertical deflection electrode 7.

The vertical deflection position information stored in the deflection memory 42 is composed of almost regular data for every 8 horizontal scanning periods, and the D/A converted waveform also becomes a vertical deflection signal of approximately 8 stages. However, as mentioned above, it has a memory capacity for two fields, so that the position can be finely adjusted for each horizontal scanning line.

Further, regarding the horizontal deflection signal, it is necessary to horizontally deflect the electron beam in six stages during one horizontal scanning period, and a memory is provided so that the deflection position can be finely adjusted for each horizontal scanning. Therefore, assuming that 480 horizontal scanning periods are displayed between one frame,
480× 6 =2880 bytes of memory are required, but since the data of the first field and the second field are shared, 1440 bytes of memory are actually used. During display, deflection information corresponding to each horizontal scanning line is read out from the deflection memory 42, converted into an analog signal by a D/A converter 43v, and applied to the horizontal deflection electrode 6. To summarize, during the display period excluding the vertical retrace period of the vertical period, the electron beam emitted from the line cathode to which a low-potential driving pulse is applied among the line cathodes 2A to 27 is beam extracted. 1 horizontally by electrode 3
It is divided into 20 sections and constitutes 120 electron beam rows. As will be described later, the amount of beam passing through the electron beam is controlled by the control electrode 4 for each section, and after being focused by the focusing electrode 5, as shown in FIG.
R1, CI, Bl and R2, G2 of the screen 8 during each horizontal display period by a pair of step-varying horizontal deflection signals, h' applied to the horizontal deflection electrodes 18.18°, etc.
．． The phosphors such as B2 are sequentially irradiated for each horizontal display period/6. Thus, for each of the 120 raster sections of each horizontal line, the electron beam is directed to R1, G1 . Bl and R2,
G2. By modulating the video signal corresponding to B2, a color image can be displayed on the screen 8.

Next, the modulation control portion of the electron beam will be explained.

First, in FIG. 4, signal input terminals 23R, 23G23
The R, G, and B video signals added to B are applied to 120 sample-and-hold circuit sets 31a to 31n. Each sample hold group 31a to 31n is R1
It is composed of six sample and hold circuits: 1, C1, B1, R2, G2, and B2. The sampling pulse generation circuit 34 has a horizontal period (63.5 μs
), during the horizontal display period (approximately 50 μs), the 120
R1 of each of the set of sample and hold circuits 31a to 31n
720 pieces (120X
6) The sampling pulses Ral to Rn2 are sequentially generated. Each of the 720 sampling pulses is 1
Six pixels are added to the sample and hold circuit sets 31a to 31n of 20&Il, and as a result, each sample and hold circuit set has R1, Gl, Bl, and R2 for each two picture elements when one line is divided into 120 pieces. , G2. Each B2 video signal is individually sampled and held.

120 sample-held pairs of R1, GIBl, R
2, G2. After the B2 video signal is sampled and held for one line, it is transferred all at once to 120 sets of memories 32a to 32n by a transfer pulse t, where it is held for the next one horizontal scanning period. The held signals are sent to 120 switching circuits 35a to 35n. The switching circuits 35a to 35n each have R1, G1 . Bl, R2
, G2. It is composed of a circuit having individual input terminals of B2 and a common output terminal that sequentially switches and outputs them, and the switching pulses rl, gl, bL r2゜g2 applied from the switching pulse generation circuit 36.
．． Switching is controlled simultaneously by B2.

The switching pulses rl, gl, bl, r2, g2
．． B2 divides each horizontal display period into 6, and divides each horizontal display period into 6 parts.
Switching the switching circuits 35a to 35n by 6 R1
, Gl, Bl, R2, G2. The B2 video signals are time-divided and sequentially output, and supplied to the pulse width modulation circuits 37a to 37n.

The output of each switching circuit 35a to 35n is connected to 120 sets of pulse width modulation (hereinafter referred to as PWM) circuits 37a to 37
n, R1, G1 . B1. The pulse width is modulated according to the magnitude of each video signal of R2, G2, and B2 and output. The outputs of the pulse width modulation circuits 37a to 37n are used as control signals for modulating the electron beam to control the display elements.
It is individually applied to each of the 120 conductive plates 15a to 15n of the t-pole 4.

Next, horizontal deflection and display timing will be explained. R1°Gl, B in switching circuits 35a to 35n
l, R2, G2. B2 video signal switching and electron beams R1, Gl, B1 . R
2, G2. The timing and order of switching the horizontal deflection to the B2 phosphor are synchronously controlled so that they completely match. As a result, when the R1 phosphor is irradiated with the electron beam, the irradiation amount of the electron beam is controlled by the R1 control signal, and the following Gl, Bl, R2, G2 . B2 is similarly controlled, and R1, G1B1 . R
2, G2. The light emission of each phosphor in B2 corresponds to R1, G of that picture element.
l, Bl, R2, G2. Each picture element is controlled by the B2 video signal, and each picture element is displayed by emitting light according to the input video signal. Such control is executed for 120 sets (2 pixels each) for one line, and
An image of 240 picture elements per line is displayed, and images are further displayed on the screen 8 by sequentially processing the 240 lines of one field starting from the upper line. Furthermore, the above operations are repeated for each field of the input video signal, and a television signal or the like is displayed on the screen 8.

The basic clock necessary for this configuration is supplied from the pulse generation circuit 39 shown in FIG. 4, and the horizontal synchronization signal H1
Problems to be Solved by the Invention of Controlling Timing with Vertical Synchronization Signals and Vertical Synchronization Signals For television images that do not limit the image quality, the higher the frequency of the sampling pulse that samples and holds the image, the higher the resolution of the displayed image can be obtained, but a large number of sample and hold circuits are required. Furthermore, for signals such as computer images in which the image signal changes in synchronization with the basic clock, a faithful image can be reproduced if the frequency of the sampling pulse is synchronized with the basic clock.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a display device that can faithfully reproduce and display both analog images such as television images and digital images such as computer images.

Means for Solving the Problems To achieve this object, the image display device of the present invention includes a switching circuit for a plurality of video signals, a sample hold circuit for a selected video signal, and a first sampling pulse generation circuit. , a second sampling pulse generation circuit including a delay line, and a switching circuit that switches the first and second sampling pulses in synchronization with the display video signal and supplies the switching circuit to the sample hold circuit.

Function: With this configuration, a plurality of display video signals are switched by a switching circuit, and in addition to the video signal sample and hold circuit, a first sampling pulse generation circuit that generates in synchronization with the display video signal and a first sampling pulse generation circuit that is provided with a delay line are installed. The sampling pulse output of the second sampling pulse generation circuit is switched in synchronization with the display video signal, and the display video signal whose image changes in synchronization with the basic clock, such as the output image of a computer, is switched during the first sampling. The pulse generation circuit samples and holds the image, and when displaying a video signal that does not have a basic clock, such as a television image, the second sampling pulse generation circuit can sample and hold the image, and both the video signals can be faithfully displayed. Can be played and displayed.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a basic block diagram of an image display device according to an embodiment of the present invention.

In FIG. 1, 22 is a power supply circuit, 26 is a line cathode drive circuit, 40 is a deflection voltage generation circuit, 41 is a DMA controller, 42 is a deflection memory, 43h and 43V are D/A converters, and h and h' are horizontal deflections. The output signal is applied to the conductive plate 18.18. v, v'' are vertical deflection output signals that are supplied to conductive plate 19.19''. 31a to 31n are sample and hold circuits, 32a to 32n are memories, and 35a to 35
n is a switching circuit, 36 is a switching pulse generation circuit, 37a to 37n are PWM circuits, and 39 is a pulse generation circuit, which are the same as the conventional blocks.

50a is a video signal switching circuit, 50b is a sync signal switching circuit, 51R, 51G, 51B, 51H, 51V are computer R, G, B, horizontal sync signal, vertical sync signal input terminals, 52R, 52G, 52B are input terminals for a vertical sync signal. TV R,G
,B, horizontal synchronization signal, vertical synchronization signal input terminal, 53a,
PLL circuits 53b each generate a basic clock that is a multiplication of the horizontal synchronizing signal. 54a and s4b are sampling pulse generation circuits, and sample hold circuits 31a~
31n. 55a is a G signal delay line, 55b is a B signal delay line, and 56 is a pulse switching circuit.

The operation of the image display device configured as described above will be described below.

First, when displaying a computer video signal, the switching circuits 50a, 50b and pulse switching circuit 56 are switched, and the signals at the terminals 51R, 510, 51B, 51H, and 51V are transferred to the sample and hold circuits 31a to 31n and the pulse generation circuit 53, respectively. supply to. The PLL circuit 53a multiplies the horizontal synchronization signal to create a basic clock synchronized with the video, and supplies it to the sampling pulse generation circuit 54a. The sampling pulse generation circuit 54a generates sampling clocks for phases a to n, for example, Ra 1.
Ga 1. The images of Ba 1 are sampled at the same timing.

When displaying a TV image for the above, switching circuit 5
0a, 50b, the pulse switching circuit 56 is switched, and the terminal 5
Signals of 2R, 52G, 52B, 52H, and 52V are supplied to a sample hold circuit and a pulse generation circuit 53, respectively. The PLL circuit 53b multiplies the horizontal synchronizing signal to create a basic clock synchronized with the video, and then changes the phases of R and CB through delay lines 55a and 55b. The sampling pulse generation circuit 54a is an
The phase is different up to the phase, and furthermore, Ra 1. Ga 1. Ba
1 as an example, the delay line 55a is
, 55b to sample and hold the sampling clocks having different phases.As described above, according to this embodiment, the display video signal is switched by the switching circuit 50a and the video signal is sampled and held by the video signal sample and hold circuit 3.
1a to 31n, the sampling pulse outputs of a first sampling pulse generation circuit 54a that is generated in synchronization with the display video signal and a second sampling pulse generation circuit 54b that includes delay lines 55a and 55b are used as the display video signal. For display video signals whose images change in synchronization with the basic clock, such as computer output images, the first sampling pulse generation circuit 54a samples and holds the image, for example, a television image. When displaying a video signal for which there is no basic clock, the second sampling pulse generation circuit 5 is used.
If you switch the sampling clock so that 4b samples and holds the image, you can reproduce a faithful image using a computer image. For television images, images with higher resolution can be displayed than when RGB signals are latched at the same timing.

Effects of the Invention As described above, according to the present invention, there is provided a switching circuit for switching a plurality of display video signals, a sample and hold circuit for display video signals, a first sampling pulse generation circuit, and a second sampling pulse generation circuit including a delay line. sampling pulse generation circuit,
By providing a switching circuit that switches between the first and second sampling pulses and supplies them to the sample and hold circuit, faithful images can be reproduced in computer images that output images synchronized with the basic clock, and basic images such as television images can be reproduced. Images without a clock can display high-resolution images, which has great practical effects.

[Brief explanation of drawings]

FIG. 1 is a basic block diagram of an image display device according to an embodiment of the present invention, FIG. 2 is an exploded perspective view showing the basic structure of a conventional image display element, and FIG. 3 is an enlarged view of a conventional phosphor. ,
Figure 4 is a block diagram showing the basic circuit configuration of the conventional example;
The figure is a timing diagram for explaining the operation of the conventional example. 31a to 31n...Sample hold circuit, 5
0a...,...Video signal switching circuit, 50b...
・Synchronization signal switching circuit, 53a 53b----PLL
Circuit, 54a, 54b ---Sampling pulse generation circuit, 55a, 55b... Delay line, 56... Pulse switching circuit. Name of agent Patent attorney Shigetaka Awano

Claims (1)

[Claims] A screen coated with a phosphor that emits light when irradiated with an electron beam, an electron beam source that generates an electron beam for each vertical division of the screen above the screen, and the electron beam source. separation means for separating the generated electron beam into each horizontal section and irradiating the screen onto the screen; a deflection electrode for deflecting; a beam flow control electrode for controlling the amount of light emitted from each pixel on the screen by controlling the amount of electron beams separated into the horizontal sections irradiated onto the screen; and each picture element. a focusing electrode that controls the size of light emitted by the electron beam on the phosphor surface;
a back electrode that controls the amount of electron beam from the electron beam source; a first switching circuit that switches a plurality of input display video signals; and a sample and hold circuit for display video signals;
A first sampling pulse generation circuit that generates in synchronization with the display video signal, a second sampling pulse generation circuit that includes a delay line, and switches the first and second sampling pulses in synchronization with the display video signal. , and a second switching circuit that supplies the sample and hold circuit to the sample and hold circuit, and the display video signal whose image changes in synchronization with the basic clock, such as the output image of a computer, is converted into an image by the first sampling pulse generation circuit. An image display apparatus characterized in that when displaying a video signal such as a television image in which a basic clock does not exist, the second sampling pulse generation circuit switches the image to be sampled and held.