JPH0436793A - Gradation display circuit for display device - Google Patents

Abstract

PURPOSE:To uniformly execute thinning operation over the whole display screen by thinning each dot, shifting the timing of thinning in each frame and always repeating said operation. CONSTITUTION:A dot clock DCK and a vertically synchronizing signal VSCY are respectively inputted to flip flop (FF) circuits 21, 22 and divided into 1/2 frequency signals, which are inputted to an exclusive OR circuit 23 to output a signal A. The signal DCK, VSYC are also respectively inputted to ternary ring counters and their output signals are turned to a signal B through AND circuits 8, 9, 10 and an OR circuit 11. When display data D3, D4 are inputted to a decoder circuit 12 and then inputted to AND circuits 14 to 16, thinning is executed 1/3, 1/2 and 2/3 times in accordance with the selection of decoding signals X0 to X3 and a no-thinning signal is outputted from an OR circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gradation display circuit for a flat display device.

[Summary of the Invention] The present invention aims to provide a gradation display circuit for displaying gradations without frizz by improving the driving method of a flat display device using a conventional two-gradation display method. It is. That is, by grouping multiple bits of display data for gradation expression and decomposing some of the display data, the gradation expression is weighted, and the number of times the display data is driven as display data within a unit time is calculated. Thinning rate control is executed to indicate the gradation level. The display data of multiple bits of other groups is inputted to a pulse width modulation or drive voltage modulation circuit, and the display data of the other groups is controlled by the thinning rate control signal to perform thinning rate control and pulse width modulation. Alternatively, by combining thinning rate control and drive voltage modulation, flicker, which has been a problem in the past, can be eliminated and a multi-gradation display method can be realized.

[Prior Art] FIG. 4 is a circuit configuration diagram showing a conventional two-gradation display type flat display device system. In Figure 4, 41
4 is a personal computer, 42 is an interface circuit, and 43 is a flat display device such as a liquid crystal display. Video signals such as display data Do-D2, horizontal synchronization signal Hsyc, and vertical synchronization signal Vsyc from the personal computer 41 are input to the interface circuit 42. The interface circuit 42 extracts data DATA necessary for operating the flat display device from the video signal.
and shift clock signal CL2, latch signal CLI,
This is a circuit for generating interface signals such as a frame signal FRM and a polarity inversion signal M. The flat display device 43 includes a liquid crystal display element, a display element using plasma, etc., and a drive circuit for driving the display element. The drive circuit of the flat display device 43 only performs a 0N10FF display drive operation on input display data, and does not itself have a gradation display function. Therefore, to display gradation, the dot 0
There is a density gradation method using N10FF display.Other methods for 0 gradation display include thinning out display data for each frame, varying the number of ON display drives to display gradations, and driving voltage modulation. There is a method using pulse width modulation.

[Problem B to be Solved by the Invention] As stated above, the present invention solves the problem of the conventional display dot 0N.
When a drive circuit for 10FF display operation was used, the amount of displayed information was not sufficient because gradation display operation could not be performed. When displaying gradations using drive voltage modulation, it is difficult to faithfully express gradations because distortion occurs in the input signal on large screen displays such as those used in OA equipment because analog voltage is input. difficult. In the case of digital input, it is necessary to prepare drive voltage levels corresponding to the number of gradations, so in the case of 32 gradations, 32 types of voltage levels must be prepared. In the case of pulse width modulation, there is a problem that crosstalk is likely to occur depending on the display pattern because the driving frequency distribution is widened depending on the display pattern. In addition, as a common problem with drive voltage modulation and pulse width modulation methods, colorization can be considered as a means of increasing the amount of displayed information, but in this case, the versatility of the drive circuit and interface circuit In addition to the above problems, other problems have arisen, such as the production of color filters, an increase in cost due to three times the number of drive circuits, a decrease in yield, and difficulties in mounting technology for connecting display elements and drive circuits.

The frame thinning method is effective for non-active liquid crystal display devices, but in the case of active devices with non-linear resistance two-terminal elements or TPT built-in,
Since the response speed is about 1/3 faster than that of non-active, flicker becomes noticeable and it cannot be used as a gradation display method, so it has not been realized.

[Means for Solving the Problems] The present invention has been made to solve the above-mentioned problems. The solution to this problem is not the conventional gradation control method using frequency modulation based on frame thinning (the amount of thinning is changed depending on the data in display dot units, and ON10
Drive voltage modulation that can display only 8 levels of gradation using FF data control means and 3-bit data;
Alternatively, by combining a pulse width modulation means, display of 32 gray levels, which is more than 8 gray levels, can be realized without flickering.

[Function] As mentioned above, since thinning is performed in units of display dots, which is the minimum time interval, gradation can be displayed without flickering as in conventional methods even in panels with fast response speeds such as nonlinear two-terminal active panels. It is intended to carry out the following. As mentioned above, the function of the drive circuit exceeds the limit of 8 gray levels with 3-bit data, and by combining the drive thinning rate, the gray level can be expanded to 32 gray levels.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1st
In the figure, 1 is a thinning pattern generation circuit. 2
3 is composed of a thinning drive control circuit and a display data control circuit. The discount pattern generation circuit 1 includes flip-flop circuits 21 and 22, and shift register circuits 4 and 5.
Exclusive OR circuit 23, NOR circuits 6, 7 . It is composed of AND circuits 8, 9° and 100R circuits 11. The thinning drive control circuit 2 also includes a decoder circuit 12 . AND
Circuit 141516, inverter circuit 13. OR circuit 17
, is composed of. Furthermore, the display data control circuit 3
is composed of AND circuits 18, 19, and 20. The operation of FIG. 1 will be explained below, where the gradation display data is DO to D405 bit data. The dot clonk DCK is input to the Furi-2 pflosop circuit 21 and
The frequency is divided by /2. Like the vertical synchronizing signal VSYCHA, it is input to a flip-flop circuit and frequency-divided by 172.

These output signals are input to an exclusive OR circuit 23, which outputs an output signal A. The dot clock signal DC
K is 3 consisting of a shift register circuit 4 and a NOR circuit 6.
input to the forward ring counter. Also, vertical synchronization signal v
syc is input to a ternary ring counter consisting of a shift register circuit 5 and a NOR circuit 7. These output signals described above are ANDed by AND circuits 8.9.10 and ORed by OR circuit 11. Inverter circuit 13
generates an inverted output signal B. FIG. 2 shows a waveform diagram of the output signal A=B in FIG. 1 described above.

In FIG. 2, A-1 of the output signal A shows a waveform diagram of an odd numbered frame, and A-2 shows a waveform diagram of an even numbered frame.
72 is repeated for each frame. B-1, B-2, and B-3 of output signal B are each 1
, 2° It shows the waveform in 3 frames, and it can be seen that thinning is performed 1/3 times, and the timing of thinning is shifted by 1 dot from 0 display data Do to D4
Among them, D3. D4 is 0 display data D3, which is an input signal to the thinning drive control circuit 20, and D4 is the input signal to the decoder circuit 1.
2, so the tecoder output signals XO, XI,
X2. By outputting X3 and inputting it to AND circuits 14, 15, and 16, the signals A, B, and
and selects the inverted signal of B. Therefore, the output signal of the OR circuit 17 is a signal with 1/3.1/2.2/3 decimation and no decimation in response to the selection of decode signals XO to X3. The output signal of this OR circuit 17 is inputted to AND circuits 18, 19°20, so that
Other display data DO1D1. It operates to control whether or not D2 is activated. Therefore, the decoder output signal
3 is signal "1", display data DO to D2 are always activated and signals BO, B1 . Output B2. Furthermore, when the decoder output signal XO is a signal "1", the display data DO to D2 are thinned out 1/3 times, so
Even if the values of D2 from display data DO are the same,
The contrast can be made different. Therefore, even if the drive circuit for drive voltage modulation or pulse width modulation has only a modulation capability of 8 gray levels when inputting 3 bits of display data, it can be expanded to modulation of 32 gray levels.

FIG. 3 is a circuit diagram showing an embodiment of a display system using the gradation display circuit of FIG. 2 according to the present invention. Third
In @, DCK is a dot clock signal. V
syc is a vertical synchronization signal. DATA is analog display data.

Display data DATA from the personal computer 31
is converted from digital display data DO to D4 by the A/D converter circuit 32 and input to the interface circuit 33. The interface circuit 33 is an interface circuit incorporating the above-mentioned gradation display circuit, and also receives the vertical synchronizing signal vsyc, horizontal synchronizing signal H3YC, and dot clock signal DCK. The interface circuit 33 receives a frame signal FRM, a latch signal CLI, a shift clock signal CL2. B2 is output from the AC signal M and the thinned-out display data BO to the flat display device 34. Since the flat display device 34 is equipped with a drive circuit for drive voltage modulation or pulse width modulation, it is possible to realize flicker-free gradation display.

[Effects of the Invention] As described above, according to the present invention, thinning is performed for each dot, which is the smallest time unit, and the thinning timing is shifted for each frame, and this is constantly repeated.
Can be thinned out uniformly across the entire display screen. Therefore, even on an active panel with a fast response speed, it is possible to perform 4-level gradation display without seeing flicker. Therefore, even if the gradation capacity of the drive circuit mounted on a flat display device is 8 levels, it is possible to expand the gradation display capacity to 32 levels, and by improving the gradation display level, it is possible to increase the gradation level. This has the great effect of making it possible to obtain display quality.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. Second
The figure is a diagram showing waveforms of the thinning pattern generation circuit. FIG. 3 is a diagram showing a display system showing one embodiment of the present invention. FIG. 4 is a diagram showing the system configuration of a conventional flat display device. 1: Thinning pattern generation circuit 2: Thinning drive control circuit 3: Display data control circuit DO, DI, B2. B3. B4: Display data 12: Decoder circuit 32: A/D converter circuit 33: Interface circuit with built-in gradation display circuit 34: Flat display device with gradation drive circuit mounted 41: Personal computer 42: Interface circuit 43: Plane Applicant for mold display device: Seiko Electronics Co., Ltd. Figure 2 Figure yf14 of conventional + internal mold display device

Claims (2)

[Claims] (1) In a display method in which gradation is displayed on a flat display device using a plurality of display data, a part of the plurality of display data is input to a thinning rate control means for thinning driving, and the thinning rate control means A gradation display circuit characterized in that the output of the circuit is configured to control a plurality of other display data. (2) A display method for displaying gradation on a flat display device using a plurality of display data includes display data consisting of a plurality of bits for expressing gradation, and a decoding means for decoding a part of the display data; A thinning rate control circuit comprising a plurality of thinning pattern generating means for generating a thinning pattern in units of dots, an output of the decoding means selecting an output of the thinning pattern generating means, and an output of the thinning rate control circuit. and a configuration for controlling other bits of the plurality of bits of display data.