JPH043531A - Automatic band control system - Google Patents
Automatic band control systemInfo
- Publication number
- JPH043531A JPH043531A JP2105077A JP10507790A JPH043531A JP H043531 A JPH043531 A JP H043531A JP 2105077 A JP2105077 A JP 2105077A JP 10507790 A JP10507790 A JP 10507790A JP H043531 A JPH043531 A JP H043531A
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- Prior art keywords
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- signal
- section
- reference voltage
- control
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- 238000010586 diagram Methods 0.000 description 6
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- 230000003287 optical effect Effects 0.000 description 3
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Abstract
Description
【発明の詳細な説明】
〔概 要〕
ディジタル伝送路の受信部の等化部に関し、信号伝送速
度および等化部の帯域のバラツキと変動に応じて等化フ
ィルタの高域遮断周波数を制御し、常に最適な帯域を有
する信号等化部を提供することを目的とし、
ディジタル信号の受信部において受信信号の等化・識別
を行うものにおいて、外部より制御信号を加えて増幅利
得を可変し、出力信号の帯域を変化させるように制御さ
れる帯域制御部と、該帯域制御部の出力信号の立ち上が
り時間と立ち下がり時間を検出し、該両時間に比例した
信号を出力する帯域検出部と、前記帯域制御部の出力信
号を識別レベルと比較して信号の中の“1”と“0”を
検出し、該検出結果をクロックにて打ち抜き再生を行う
識別部と、該識別部のクロック打ち抜き再生前信号とク
ロック打ち抜き再生後信号とを比較し、一定に保つ帯域
に対応した基準電圧を生成する基準電圧部と、該基準電
圧部と前記帯域検出部の両出力信号を比較して上記帯域
制御部に加える制御電圧を生成し、該制御電圧により前
記帯域制御部から送出される出力信号の立ち上がり時間
と立ち下がり時間が一定値になるように帰還をかける帰
還増幅器とを設け、等化されるディジタル信号の立ち上
がり時間と立ち下がり時間が常に一定になるように9域
を制御するように構成する。[Detailed Description of the Invention] [Summary] Regarding the equalization section of the reception section of a digital transmission path, the high cutoff frequency of the equalization filter is controlled according to the signal transmission speed and the dispersion and fluctuation of the band of the equalization section. , the purpose of which is to provide a signal equalization section that always has an optimal band, and which equalizes and identifies the received signal in the digital signal reception section, by adding a control signal from the outside to vary the amplification gain. a band control section that is controlled to change the band of the output signal; a band detection section that detects the rise time and fall time of the output signal of the band control section and outputs a signal proportional to the both times; an identification unit that compares the output signal of the band control unit with an identification level to detect “1” and “0” in the signal, and punches and reproduces the detection result using a clock; and a clock punching of the identification unit. a reference voltage section that compares the pre-regeneration signal and the clock punched and post-regeneration signal and generates a reference voltage corresponding to the band to be kept constant; and a reference voltage section that compares both output signals of the reference voltage section and the band detection section to determine the frequency range of the above band. A feedback amplifier is provided that generates a control voltage to be applied to the control section and applies feedback so that the rise time and fall time of the output signal sent from the band control section are constant values using the control voltage, and the output signal is equalized. The nine regions are controlled so that the rise time and fall time of the digital signal are always constant.
本発明は、ディジタル伝送路の受信部の等花器に関する
。The present invention relates to a receiver of a digital transmission line.
第3図は従来の一実施例の回路構成を示す図である。図
中、1は受光素子であり、また2は前置増幅器21と自
動利得制御増幅器(以下AGC増幅器と称す)22と等
化フィルタ23と第一比較回路24とピーク検波器25
と基準電圧26とを備える等化部である。なお3は第二
比較回路31と識別レベル32とFF回路33とを備え
る識別部である。FIG. 3 is a diagram showing a circuit configuration of a conventional embodiment. In the figure, 1 is a light receiving element, and 2 is a preamplifier 21, an automatic gain control amplifier (hereinafter referred to as AGC amplifier) 22, an equalization filter 23, a first comparison circuit 24, and a peak detector 25.
and a reference voltage 26. Note that 3 is an identification section including a second comparison circuit 31, an identification level 32, and an FF circuit 33.
第3図において、受光素子1にて受信された光強度変調
信号は、検波されて電気信号に変換されて等化部2に入
力する。なお受信される光信号は、例えば100Mbi
t/sの速度で1”と“0”よりなる信号である。等
化部では、該電気信号を前置増幅器21で低ノイズ増幅
を行い、AGC増幅器22で識別可能な所定レベルまで
増幅し、等化フィルタ23ではノイズ処理などの識別さ
れ易い信号になる等化処理を行って識別部3に出力する
。識別部3では、第二比較回路31において等化フィル
タ23の出力信号を識別レベル32の電圧値と比較して
“1”と“0”に識別し、フリソプフロンプ回路(以下
FF回路と称す)33でクロックによる打ち抜き再生を
行い、ジッタ等を押さえた出力データを送出する。更に
、等化部2では等化フィルタ23から出力される出力振
幅が一定となるように、等化フィルタ23に入力する信
号の振幅をピーク検波器25においてピーク検波をし、
該ピーク検波された電圧と基準電圧26の電圧値とが等
しくなるように第一比較回路24にて比較し、AGC増
幅器22に加えてAGC増幅器22の利得を自動的に制
御している。In FIG. 3, a light intensity modulated signal received by the light receiving element 1 is detected, converted into an electrical signal, and input to the equalization section 2. Note that the received optical signal is, for example, 100 Mbi.
It is a signal consisting of "1" and "0" at a speed of t/s. In the equalization section, the preamplifier 21 performs low noise amplification of the electrical signal, and the AGC amplifier 22 amplifies it to a predetermined level that can be identified. , the equalization filter 23 performs equalization processing such as noise processing to make the signal easy to identify, and outputs it to the identification section 3. In the identification section 3, the second comparison circuit 31 converts the output signal of the equalization filter 23 to the identification level. 32 and discriminates between "1" and "0", performs punching reproduction using a clock in a Frisopfromp circuit (hereinafter referred to as FF circuit) 33, and sends out output data with suppressed jitter etc.Furthermore, In the equalization unit 2, the amplitude of the signal input to the equalization filter 23 is peak-detected in a peak detector 25 so that the output amplitude output from the equalization filter 23 is constant,
The peak detected voltage and the voltage value of the reference voltage 26 are compared in a first comparison circuit 24 so that they become equal, and in addition to the AGC amplifier 22, the gain of the AGC amplifier 22 is automatically controlled.
等化部2の等化フィルタ23には、通常、低域通過フィ
ルタが使われる。これは、信号に含まれる高周波雑音を
除去するためである。従って等化フィルタ23の高域遮
断周波数(以下fchと称す)は広域ノイズを除去する
ために低ければ低い程よいが、通過する信号成分を除去
する位に低いと信号波形の立ち上がりと立ち下がりの劣
化を起こして符号量干渉が生じる。また前置増幅器21
およびAGC増幅器22にもfchが存在し、そのfc
hは素子のバラツキや周囲温度や電源電圧の変動等によ
り大きく変化し、等化フィルタ23に較べると安定性に
欠ける。このため等化部2のfchが等化フィルタ23
の低域通過フィルタで決定されるように、前置増幅器2
1およびAGC増幅器22の帯域は等化フィルタ23の
低域通過フィルタの帯域より十分広くしておく必要があ
る。なお通常の帯域は、入力信号が約100 Mbit
/sの場合、前置増幅器21とAGC増幅器22を含め
て200MHzに、また等化フィルタ23では60MH
zに選ばれている。The equalization filter 23 of the equalization section 2 typically uses a low-pass filter. This is to remove high frequency noise contained in the signal. Therefore, the lower the high cutoff frequency (hereinafter referred to as fch) of the equalization filter 23 is, the better in order to remove wide-band noise, but if it is low enough to remove passing signal components, the rising and falling edges of the signal waveform will deteriorate. This causes code amount interference. Also, the preamplifier 21
There is also an fch in the AGC amplifier 22, and the fc
h changes greatly due to variations in elements, ambient temperature, power supply voltage, etc., and is less stable than the equalization filter 23. Therefore, the fch of the equalization section 2 is equalized by the equalization filter 23.
preamplifier 2 as determined by the low-pass filter of
1 and the AGC amplifier 22 must be made sufficiently wider than the band of the low-pass filter of the equalization filter 23. Note that the normal band is an input signal of approximately 100 Mbit.
/s, the frequency including the preamplifier 21 and AGC amplifier 22 is 200MHz, and the equalization filter 23 is 60MHz.
It is selected by z.
従って、前置増幅器およびAGC増幅器の必要以上の帯
域は、消費電力の増加、発振や利得−周波数特性のピー
キング等の原因となり、また伝送速度に最適な等化フィ
ルタを選択して使用せねばならないという問題がある。Therefore, using a preamplifier and an AGC amplifier in a band larger than necessary causes increased power consumption, oscillation, peaking of gain-frequency characteristics, etc., and it is necessary to select and use an equalization filter that is optimal for the transmission speed. There is a problem.
本発明は、信号伝送速度および等化部の帯域のバラツキ
と変動に応して等化フィルタの高域遮断周波数を制御し
、常に最適な帯域を有する信号等化部を提供することを
目的とする。An object of the present invention is to control the high cutoff frequency of an equalization filter according to variations and fluctuations in the signal transmission speed and the band of the equalizer, and to provide a signal equalizer that always has an optimal band. do.
本発明は、ディジタル信号の受信部において受信した信
号の等化・識別を行うものにおいて、外部より制御信号
を加えて増幅利得を可変し、出力信号の帯域を変化させ
るように制御される帯域制御部4と、該帯域制御部4の
出力信号の立ち上がり時間と立ち下がり時間を検出し、
該両時間に比例した信号を出力する帯域検出部6と、前
記帯域制御部4の出力信号を識別レベルと比較して信号
の中の“1”と“0”を検出し、該検出結果をクロック
にて打ち抜き再生を行う識別部3と、該識別部3のクロ
ック打ち抜き再生前信号とクロック打ち抜き再生後信号
とを比較し、一定に保つ帯域に対応した基準電圧を生成
する基準電圧部5と、該基準電圧部5と前記帯域検出部
6の両出力信号を比較して上記帯域制御部4に加える制
御電圧を生成し、該制御電圧により前記帯域制御部4か
ら送出される出力信号の立ち上がり時間と立ち下がり時
間が一定値になるように帰還をかける帰還増幅器7とを
設け、等化されるディジタル信号の立ち上がり時間と立
ち下がり時間が常に一定になるように帯域を制御する構
成とするものである。The present invention is a device that equalizes and identifies a received signal in a digital signal receiving section, and the present invention is a band control device that is controlled to change the band of an output signal by adding a control signal from the outside to vary the amplification gain. detecting the rise time and fall time of the output signal of the band control unit 4 and the band control unit 4;
A band detecting section 6 outputs a signal proportional to both times, and the output signal of the band controlling section 4 is compared with the identification level to detect "1" and "0" in the signal, and the detection result is an identification section 3 that performs punching reproduction using a clock; and a reference voltage section 5 that compares a signal before clock punching reproduction and a signal after clock punching reproduction of the identification section 3 and generates a reference voltage corresponding to a band to be kept constant. , compares the output signals of the reference voltage section 5 and the band detection section 6 to generate a control voltage to be applied to the band control section 4, and uses the control voltage to control the rise of the output signal sent from the band control section 4. A feedback amplifier 7 is provided to apply feedback so that the time and fall time are constant values, and the band is controlled so that the rise time and fall time of the digital signal to be equalized are always constant. It is.
本発明では第1図に示すように、帯域検出部6において
、帯域制御部4の出力信号の立ち上がり時間と立ち下が
り時間を検出し、また基準電圧部5では、前記帯域制御
部4の出力信号の中の“1”と“0”を検出したのち該
検出結果をクロックにて打ち抜き再生し、該クロック打
ち抜き再生前信号とクロック打ち抜き再生後信号とを比
較して一定に保つ帯域に対応した基準電圧を生成して帰
還増幅器7に加えるようにしている。In the present invention, as shown in FIG. After detecting "1" and "0" in the clock, the detection result is punched and reproduced using a clock, and the signal before the clock punching and reproduction is compared with the signal after the clock punching and reproduction is kept constant. A voltage is generated and applied to the feedback amplifier 7.
従って、帰還増幅器7では、前記基準電圧部5と帯域検
出部6の両出力信号を比較することにより、上記帯域制
御部4に加える制御電圧を生成することかでき、この制
御電圧にて前記帯域制御部4から送出する出力信号の立
ち上がり時間と立ち下がり時間を一定値にするように帰
還をかけることができる。Therefore, in the feedback amplifier 7, by comparing both the output signals of the reference voltage section 5 and the band detection section 6, a control voltage to be applied to the band control section 4 can be generated. Feedback can be applied so that the rise time and fall time of the output signal sent from the control section 4 are set to constant values.
第1図は本発明の回路構成を示す図であり、第2図は本
発明の基準電圧部の動作を示す図である。FIG. 1 is a diagram showing the circuit configuration of the present invention, and FIG. 2 is a diagram showing the operation of the reference voltage section of the present invention.
図中、1〜3は従来例と同一回路であり、1は受光素子
であり、2は前置増幅器21と自動利得制御増幅器(以
下AGC増幅器と称す)22と第一比較回路24とピー
ク検波器25と基準電圧26とを備える等化部である。In the figure, 1 to 3 are the same circuits as the conventional example, 1 is a light receiving element, 2 is a preamplifier 21, an automatic gain control amplifier (hereinafter referred to as AGC amplifier) 22, a first comparison circuit 24, and a peak detection element. 25 and a reference voltage 26.
なお3は第二比較回路31と識別レベル32とFF回路
33とを備える識別部である。また4〜7は本発明の回
路であり、4は抵抗RとコンデンサCと等化AGC増幅
器41を備える帯域制御部、5は排他論理和演算を行う
EOR回路51と直流の平滑回路52と減衰器53とを
備える基準電圧部である。なお6は帯域検出部であり、
第一基準電圧61と第二基準電圧62と第三比較回路6
3と直流の平滑回路64とを備える。更に7は帰還増幅
器であり、差動増幅器71と低域信号を通過させる低域
フィルタ72とを備える。以下、該回路の詳細を説明す
る。Note that 3 is an identification section including a second comparison circuit 31, an identification level 32, and an FF circuit 33. In addition, 4 to 7 are circuits of the present invention, 4 is a band control section comprising a resistor R, a capacitor C, and an equalization AGC amplifier 41, and 5 is an EOR circuit 51 that performs an exclusive OR operation, a DC smoothing circuit 52, and an attenuation circuit. 53. Note that 6 is a band detection section,
First reference voltage 61, second reference voltage 62, and third comparison circuit 6
3 and a DC smoothing circuit 64. Furthermore, 7 is a feedback amplifier, which includes a differential amplifier 71 and a low-pass filter 72 that passes a low-frequency signal. The details of this circuit will be explained below.
第1図において、受信された光信号は受光素子1で検波
されて電気信号に変換して等化部2に入力する。なお受
信光信号は、例えば100Mbit/sの速度で“1”
と“0”の電気信号である。この電気信号は本発明の帯
域制御部4において、外部より入力する制御信号により
一定帯域に保たれるように制御が行われて識別部に入力
し、クロックによる打ち抜き再生を行って出力データを
送出する。In FIG. 1, a received optical signal is detected by a light receiving element 1, converted into an electrical signal, and inputted to an equalization section 2. Note that the received optical signal is "1" at a speed of 100 Mbit/s, for example.
and “0” electrical signals. This electric signal is controlled in the band control section 4 of the present invention so that it is maintained at a constant band by a control signal input from the outside, and then input to the identification section, where it is punched and reproduced using a clock and output data is sent out. do.
以下その回路動作を詳細に説明する。The circuit operation will be explained in detail below.
(1)帯域制御部4
等化AGC増幅器41の利得をAとすると、入力から出
力までの伝達関数Gは、
高域遮断周波数fchは、
fch= (Hz)2π
RC(1+A)
二こて、
R:抵抗値 〔Ω〕
C:容量値 CF’]
ω:角周波数(rad/sec )
となり、外部より制御信号を加えて等化AGC増幅器4
1の利得Aを制御することで帯域の制御が可能である。(1) Bandwidth control unit 4 When the gain of the equalization AGC amplifier 41 is A, the transfer function G from input to output is: The high cutoff frequency fch is fch= (Hz)2π
RC (1+A) 2 trowels, R: resistance value [Ω] C: capacitance value CF'] ω: angular frequency (rad/sec), and by adding a control signal from the outside, equalizing AGC amplifier 4
Bandwidth can be controlled by controlling the gain A of 1.
(2)帯域検出部6
帯域を直接に検出することは困難なため、帯域と一定の
関係を持つ立ち上がり時間(Tr)と立ち下がり時間(
Tf)を検出する。(2) Band detection unit 6 Since it is difficult to directly detect the band, the rise time (Tr) and fall time (Tr) and fall time (Tr), which have a certain relationship with the band, are difficult to detect directly.
Tf) is detected.
出力Vjには入力信号VfのTr、Tfの数に比例した
直流電圧が出力される。つまり、V j = n x
t p x V i −−−−−−−−−−−−−−−
−−−−−−−−−−−−−−(3)ここで、
n:1秒間のrr、]ゴの数〔個/5ec)tp:Tr
とTfの時間(sec 〕
Vi :第三比較回路63の出力リミッタ振幅(V)該
帯域制御部4の出力信号の立ち上がり時間と立ち下がり
時間を検出し、該立ち上がりと立ち下がりの両時間に比
例した信号Vjを出力する。A DC voltage proportional to the number of Tr and Tf of the input signal Vf is outputted to the output Vj. That is, V j = n x
t p x Vi −−−−−−−−−−−−−−
−−−−−−−−−−−−−(3) Where, n: rr for 1 second, number of [pieces/5ec] tp: Tr
and Tf time (sec) Vi: output limiter amplitude (V) of the third comparator circuit 63; detects the rise time and fall time of the output signal of the band control section 4, and is proportional to both the rise and fall times. outputs a signal Vj.
(3)識別部3と基準電圧部5
上記した帯域検出部6の出力には、Tr、Tfの時間以
外に、Tr、ゴfの数nに比例した電圧も含まれている
為、これを取り除くようにする。(3) Identification unit 3 and reference voltage unit 5 The output of the band detection unit 6 described above includes a voltage proportional to the number n of Tr and G, in addition to the time of Tr and Tf. Try to remove it.
このため識別部3と基準電圧部5では第1図に示すよう
に、第二比較回路31にて比較送出さた信号Vl はク
ロックVmにてF’ F回路33において打ち抜き再生
を行って出力データVnを送出する。この信号vi と
VnはEOR回路51で排他的論理和が象られ、振幅値
がVOでありかつパルス幅がクロック周期Tの1/2に
一敗する信号Voを送出し、平滑回路52で直流に平滑
されて減衰器53を通って信号Vqを送出する。なおこ
のVqは下記式%式%
n:1秒間のTr、TfO数〔個/5ec)tpo :
クロック周期の172の時間C5ec )Vo:EOR
回路51の出力リミッタ振幅(V)Att:減衰器53
の減衰量(入力/出力)前記帯域制御部4の出力信号V
fと識別レベルVkの比較をして入力信号の“1″と“
0”を検出した信号Vtを生成し2、該信号Vlをクロ
ックVmによる打ち抜き再生を行った信号Vnを送出し
、該信号Vlとを比較し、一定に保つ帯域に対応した基
準電圧Vqを生成する。Therefore, as shown in FIG. 1, in the identification section 3 and the reference voltage section 5, the signal Vl, which is compared and sent out by the second comparison circuit 31, is punched and reproduced in the F' F circuit 33 at the clock Vm and output data. Sends Vn. These signals vi and Vn are subjected to an exclusive OR in an EOR circuit 51, and a signal Vo having an amplitude value of VO and a pulse width of 1/2 of the clock period T is sent out. The signal Vq is smoothed and sent through an attenuator 53. This Vq is calculated using the following formula % n: Number of Tr, TfO per second [pcs/5ec) tpo:
172 hours of clock period C5ec) Vo:EOR
Output limiter amplitude (V) Att of circuit 51: attenuator 53
Attenuation amount (input/output) of the output signal V of the band control section 4
By comparing f and identification level Vk, the input signal “1” and “
0'' is detected, generates a signal Vt, 2, sends a signal Vn obtained by punching and reproducing the signal Vl using a clock Vm, compares it with the signal Vl, and generates a reference voltage Vq corresponding to a band to be kept constant. do.
(4)帰還増幅器7
帯域検出部6からの信号Vjと、基準電圧部5からの信
号Vqが等しくなるように帯域制御部4に制御信号Vc
を出力する。つまり、
(3)式と(4)式において、Vj=Vqとし、かつV
i =Voとおくと
tp = tp 0/Att −・−一一−−−−−
・・−・−−一一−−−−−−−−−−−−−−・−(
5)〔発明の効果〕
以上の説明から明らかなように本発明によれば、信号の
増幅を行う前置増幅器、AGC増幅器に必要以上の帯域
を持たせなくてもよいため、低消費電力化や利得−周波
数特性のピーキング等の障害の回避ができ、かつ帯域を
最適に保つことにより安定増幅を可能にした特性改善を
行うことができる。更に異なった伝送速度のシステムに
対しても回路変更なしで対処ができる。(4) Feedback amplifier 7 A control signal Vc is supplied to the band control unit 4 so that the signal Vj from the band detection unit 6 and the signal Vq from the reference voltage unit 5 are equal.
Output. In other words, in equations (3) and (4), Vj=Vq and V
If i = Vo, then tp = tp 0/Att -・-11------
・・−・−−11−−−−−−−−−−−−−−・−(
5) [Effects of the Invention] As is clear from the above description, according to the present invention, there is no need to provide a preamplifier and an AGC amplifier that amplify signals with a band larger than necessary, resulting in lower power consumption. It is possible to avoid obstacles such as peaking in gain-frequency characteristics, and to improve characteristics that enable stable amplification by keeping the band optimal. Furthermore, systems with different transmission speeds can be handled without changing the circuit.
第1図は本発明の回路構成を示す図、
第2図は本発明の基準電圧部の動作を示す図、第3図は
従来の一実施例の回路構成を示す図、である。
図において、
■は受光素子、 2は等化部、
3は識別部、 4は帯域制御部、5は基準電圧部
、 6は帯域検出部、
7は帰還増幅器、
を示す。
−ゼ÷
半発明り基律電圧舒nv屯亦す図
第2図FIG. 1 is a diagram showing the circuit configuration of the present invention, FIG. 2 is a diagram showing the operation of the reference voltage section of the present invention, and FIG. 3 is a diagram showing the circuit configuration of a conventional embodiment. In the figure, (2) is a light receiving element, 2 is an equalization section, 3 is an identification section, 4 is a band control section, 5 is a reference voltage section, 6 is a band detection section, and 7 is a feedback amplifier. -Z ÷ Semi-invented fundamental voltage y nv ts Figure 2
Claims (1)
を行うものにおいて、 外部より制御信号を加えて増幅利得を可変し、出力信号
の帯域を変化させるように制御される帯域制御部(4)
と、 該帯域制御部(4)の出力信号の立ち上がり時間と立ち
下がり時間を検出し、該両時間に比例した信号を出力す
る帯域検出部(6)と、 前記帯域制御部(4)の出力信号を識別レベルと比較し
て信号の中の“1”と“0”を検出し、該検出結果をク
ロックにて打ち抜き再生を行う識別部(3)と、 該識別部(3)のクロック打ち抜き再生前信号とクロッ
ク打ち抜き再生後信号とを比較し、一定に保つ帯域に対
応した基準電圧を生成する基準電圧部(5)と、 該基準電圧部(5)と前記帯域検出部(6)の両出力信
号を比較して上記帯域制御部(4)に加える制御電圧を
生成し、該制御電圧により前記帯域制御部(4)から送
出される出力信号の立ち上がり時間と立ち下がり時間が
一定値になるように帰還をかける帰還増幅器(7)とを
設け、 等化されるディジタル信号の立ち上がり時間と立ち下が
り時間が常に一定になるように帯域を制御することを特
徴とする自動帯域制御方式。[Claims] In a device that equalizes and identifies a received signal in a digital signal receiving section, a band that is controlled by applying an external control signal to vary the amplification gain and change the band of the output signal. Control part (4)
and a band detection section (6) that detects the rise time and fall time of the output signal of the band control section (4) and outputs a signal proportional to the both times, and the output of the band control section (4). an identification unit (3) that compares the signal with an identification level to detect “1” and “0” in the signal, and punches out and reproduces the detection result using a clock; and a clock punching of the identification unit (3). a reference voltage section (5) that compares the pre-reproduction signal and the clock punched and post-reproduction signal and generates a reference voltage corresponding to a band to be kept constant; and the reference voltage section (5) and the band detection section (6). A control voltage to be applied to the band control section (4) is generated by comparing both output signals, and the rise time and fall time of the output signal sent from the band control section (4) are set to constant values by the control voltage. This automatic band control method is characterized in that it is equipped with a feedback amplifier (7) that applies feedback so that
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2105077A JPH043531A (en) | 1990-04-19 | 1990-04-19 | Automatic band control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2105077A JPH043531A (en) | 1990-04-19 | 1990-04-19 | Automatic band control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH043531A true JPH043531A (en) | 1992-01-08 |
Family
ID=14397873
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2105077A Pending JPH043531A (en) | 1990-04-19 | 1990-04-19 | Automatic band control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH043531A (en) |
-
1990
- 1990-04-19 JP JP2105077A patent/JPH043531A/en active Pending
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