JPH04302223A - Circuit device - Google Patents

Abstract

PURPOSE: To provide an A/D converter which has the precision of A/D conversion approximately independent of the precision, the linearity, or the resolution of a D/A converter in a feedback loop and has a high speed and a high resolution. CONSTITUTION: Typically, sigma-delta oversampling analog/digital converter device 200 is provided with a linear modulator 212 which consists of a totalizer 202, an integrator 203, a multi-bit analog/digital converter 204, and a complementary digital/analog converter 205 in the feedback loop. A table lookup memory 211 is provided; and for the purpose of compensating the error caused in the feedback line, the digital value of the digital output signal of the multi-bit analog/digital converter 204 is substituted to improve the conversion precision, and an influence of the error upon the digital/analog converter 204 is eliminated to simplify the converter device 200.

Description

[Detailed description of the invention]

0001

[Background of the invention]

0002

[Relationship with related applications] The content of this application was filed in July 1990.
Inventor D. B. This invention is related to pending U.S. patent application Ser. The pending application, which has now been abandoned, is filed on April 6, 1990, No. 505,3.
No. 84 and No. 51 filed on April 23, 1990.
This is a continuation-in-part application of No. 3,452. All of these applications have been assigned to the applicant and are cited here.

0003

FIELD OF THE INVENTION This invention relates generally to oversampling analog-to-digital converters and, more particularly, to high speed, high resolution oversampling analog-to-digital converters.

0004

2. Description of the Prior Art Recent advances in the use of digital signal processing techniques, particularly for analog signals, have called for various improvements to the basic, well-known methods of analog-to-digital conversion. Analog-to-digital converter circuitry has also become highly advanced to perform such processes at high speed and with increased accuracy. Oversampling, or operating the modulator of an analog-to-digital converter at a speed many times higher than the Nyquist rate of the signal, and its complementary process, subtraction, It is commonly used in conjunction with analog integration and digital filtering to increase the resolution of the output samples of the . Typically, this increase is about 1-1/2 bits per octave of oversampling for first-order integrators, 2-1/2 bits of resolution for second-order integrators, and even higher resolution. The next integrator will have correspondingly more bits. Therefore, the resolution is significantly increased when the oversampling ratio is greater than 16:1. Such a process also reduces errors due to component mismatch, thus ensuring that information loss during conversion is minimized.

[0005] Known types of analog-to-digital converters are designed to increase accuracy in a manner commensurate with high speed operation.
Use a back loop. Such an analog-to-digital (hereinafter A/D) converter consists of an internal A/D converter with medium resolution and a complementary digital-to-digital (hereinafter referred to as D/D) converter in the feedback loop. A) converter is used. In theory, linearity or resolution errors due to the digital-to-analog converter are effectively added to the input signal and appear unattenuated at the output. in fact,
Although improving the performance of analog-to-digital converters, some intractable problems remain. The D/A converter must have both linearity and resolution accurate to match the required resolution of the output sample.
It is difficult to meet the condition that the D/A and A/D converters are exactly complementary to achieve accurate operation. For this purpose, the accuracy and linearity of the D/A converter must be
This requires equal to the transducer resolution, which is
As the resolution of the A/D converter increases, an even greater number of bits need to be converted. This can lead to a significant increase in circuit complexity and cost, and can cause problems such as hitting sampling speed limits. Balancing accuracy and linearity is also difficult. This is because the D/A converter is affected by noise, temperature fluctuations in the values of circuit components,
Another reason is that they use analog circuits that are subject to considerable component variations during manufacturing. Although feedback circuits are less sensitive to component value variations, accuracy is limited by the linearity and complementarity of the circuits forming the feedback path.

To address the problem of non-linear functions in digital circuits or sub-digital circuits, look-up tables are used to generate the desired result using the digital input or output signals of the device. or access another digital number that provides a corrected digital value. However, these schemes are limited to repeatedly replacing erroneous digital values with potentially accurate values.

In summary, A/D conversion and D/A conversion are electrically fundamentally different processes, and the differences between these processes result in artifacts and errors occurring in different ways in each process. , which is difficult to restore or otherwise compensate for in the other process. This is especially true when trying to match high-speed operations.

[0008]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to have a D/A converter in a feedback loop, so that the accuracy of the A/D conversion is equal to the accuracy, linearity, or resolution of the D/A converter. The object is to provide an A/D converter device that is almost unrelated.

Another object is to provide an improved high speed, high resolution A/D converter that can be manufactured at reduced cost.

Another objective is to provide an A/D with performance that is relatively insensitive to ambient conditions and manufacturing variations in the feedback circuit, while being capable of high-speed, high-resolution operation.
The purpose of the present invention is to provide a converter.

[0011] In order to achieve the above-mentioned objects of this invention,
A circuit arrangement is provided having a forward signal path for generating a digital output signal, a feedback signal path for providing an input signal to the forward signal path, and a converter coupled to the forward signal path. The converter replaces the digital values generated by the forward signal path with digital values that include correction values corresponding to errors in the feedback path.

In one aspect of the invention, a method is provided for correcting a digital output signal of a circuit having a forward signal path and a feedback signal path. The method stores a digital value corresponding to a possible output value of a feedback signal path, and stores a digital value of a forward signal path in a stored digital value corresponding to a possible output value of a feedback signal path. converting the digital output value of the forward signal path by substituting the value.

Further, in one aspect of the present invention, the feedback path includes a D/A converter with low resolution, and an A/D converter with low resolution is provided in the feedback path.
An A/D converter is provided having a ROM converter having data corresponding to the state of the D/A converter for each digital output signal of the converter. In this way, errors in both the D/A and A/D converters are compensated for simultaneously, including resolution and linearity mismatches between the two converters.

These and other objects, features and advantages will be understood from the following detailed description of the preferred embodiments of the invention with reference to the drawings.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 depicts one type of A/D converter apparatus 100, generally known in the art, as described above. For simplicity, the A/D converter device 100 is a first-order sigma delta A
/D converter. This is the primary modulator 1
This is because 12 is used. The A/D converter 104 and D/A converter 105 used in the modulator 112 are both 1-bit resolution circuits (e.g., simple comparators and coupling the comparator outputs to each of two reference voltages, respectively). It may be a circuit with a pair of switches) or a multi-bit circuit. Next, in order to facilitate understanding of the present invention, this circuit will be explained, assuming the latter case.

High speeds (eg speeds higher than 16:1)
The analog input signal oversampled at input terminal 10
1, and a summator 102 sums the feedback signal and the difference. This sum signal is applied to integrator 103. Since modulator 112 uses only one integrator 103, the modulator operates as a first order modulator. The output signal of the integrator 103 is sent to the analog-to-digital converter 10
4 into a multi-bit digital signal. This multi-bit digital signal is applied to digital filter 106 and the output signal produced by filter 106 is subtracted by subtractor 107 to match the desired sample rate at subtractor output 108. A/
The output signal of the D converter is also applied to the input of a D/A converter 105, which converts it into an analog signal that is ideally complementary to the operation of the A/D converter 104. and convert again. The difference between the converted analog signal and the input signal is summed again to obtain the error signal, which is calculated from the previous data.
It is integrated along with the samples and error values and converted to an updated digital value. This operation is repeated as long as the circuit is in operation.

In the configuration of FIG. 1, integrator 103 receives the output signal of difference summator 102 as an error signal. This error signal not only reflects aliasing errors due to changes in the input signal as well as resolution limitations of the A/D converter 104 (which is reflected in the D/A converted signal), but also It also reflects errors due to deviations from complementarity of the output signals generated by each of the converter 104 and the D/A converter 105. Integrator 103 accumulates all such errors, regardless of their origin. Therefore, to avoid a shift in the accumulated error value, the resolution and precision of the D/A conversion must be at least as large as the resolution and precision of the final reduced A/D conversion. In terms of hardware, the D/A converter 105 is the A/D converter 1 after filtering and subtraction.
A after filtering and subtraction with an accuracy greater than or equal to the value of the increment corresponding to the least significant bit (LSB) of the entire 00
At least the same number of bits as the entire /D converter 100 must be processed. This places severe constraints on the design, significantly complicating the circuit and increasing cost, as well as limiting sampling speed. Furthermore, manufacturing variations from component to component as well as ambient operating conditions (eg, temperature drift) make it difficult to manufacture circuits that reliably meet this criterion.

Even if the design constraints described above are carefully observed, the accuracy of the A/D conversion is less than optimal. this is,
If there is an error in the D/A conversion, it will be reflected in the output signal of the A/D converter, and since the D/A converter is directly added to the input signal, it cannot be corrected. That's because there isn't.

As shown in FIG. 2, the A/D converter 200 of the present invention also includes an input terminal 201, a difference summator 202 whose input of one sign is coupled to the terminal 201, and a summator 20.
an integrator 203 coupled to the output of the integrator 203, an A/D converter 204 coupled to the output of the integrator 203, and an A/D converter 2
04 to the opposite sign input of summer 202. Additional digital processing is provided by digital filter 206 and subtractor 207. This invention differs from the prior art as represented by the apparatus of FIG. 1 in that it includes a converting means 211. This is any device that can act as a table lookup device, or as we will explain, such a table.
The computing device may include a bull lookup device, but is preferably configured with a fixed memory (ROM). The digital output signal of A/D converter 204 is used to address this conversion means.

The invention takes advantage of the fact that the performance of the internal D/A converter is at least consistent and therefore can provide a correction signal with respect to the input signal. Furthermore, as mentioned above, the present invention takes advantage of the disadvantages of the conventional configuration in that it is not possible to correct errors in D/A conversion, and such errors are directly reflected in the output signal of the A/D converter. do.

For this reason, when the conversion means 211 is loaded with empirical data (which can be generated for each device) reflecting the actual response of the D/A converter 205, the ideal Even if there is a deviation from the standard performance, the deviation can be corrected accurately. The conversion means need only be capable of converting a quantified value, in particular a value corresponding to an actual value generated in response to a particular input state of the D/A converter. Digital output code of converter 211
D is not the quantization level of the A/D converter 204, but
Since it corresponds to the actual level generated by the /A converter 205, the integration in the digital domain performed during the subtraction is restored to match the integration performed in the analog domain by the integrator 203. Therefore, the digital signal can be made to correspond exactly to what is happening to the analog signal, and deviations from complementarity of the converters 204, 205 can be fully compensated for and corrected.

The actual data stored in the conversion means 211 is a digital value corresponding to the actual analog signal of the D/A converter 205, which can be determined empirically. Alternatively, if it is advantageous to do so, the deviation in the complementarity of the converters 204, 205 is quantified and expressed as the sum of the output signal of the A/D converter (input signal of the D/A converter) and the deviation. Values can be calculated. Yet another variation within the scope of the invention includes a pair of transducers 204, 205.
The performance of the pair of transducers can be measured or otherwise evaluated, and then a value representing a correction value for that pair of transducers can be stored in the transducer 211. In either case, the invention increases the accuracy of the entire transducer arrangement.

Such improved performance is achieved by the simplified hardware implementation provided by the present invention. As mentioned earlier, the conversion means 211 has digital values corresponding to the actual analog values representing the output state of the D/A converter. Therefore, if the resolution of the D/A converter is reduced, the accuracy and resolution of the entire A/D converter device 200 are not affected. This can be said because even if there is an error in the output signal of the D/A converter, that error is reflected in the output signal of the A/D converter. For example, if the output signal of an A/D converter has a resolution of 16 bits and the D/A converter has a resolution of only 4 bits, the lower 12
A plurality of digital output signals of the A/D converter with different bits correspond to one output value of the D/A converter. Although the magnitude of the error differs for each digital value, the magnitude of the error is known and can be accurately compensated for.

From this idea, the device of the invention can be made even simpler. In the previous configuration, the D/A converter 20
5 has lower resolution than the A/D converter 204, but different values were stored corresponding to only one value of the output of the D/A converter. The raw output signal of the A/D converter is directly replaced with these values. However, the output signal of the A/D converter not only reflects the error in the D/A output value, but also reflects the output value of the D/A converter due to the summation of the differences made by the summer 202. There is. Accordingly, the capacity, size and complexity of the memory contained in the conversion means 211 is correspondingly reduced and thus the A/D converter 20
The most significant bits of the four output signals allow access to this reduced set of values. At that time, the correction value for the output signal of the A/D converter is
It can be calculated from the value of the transducer response as well as the actual digital output signal of the A/D converter.

[0025] While reducing the complexity of the circuit in this way,
A method to increase the speed and accuracy of digital circuits is to
It can potentially be applied to any circuit that includes a back loop and has a digital output signal, and is not limited to A/D converters. However, the invention is particularly amenable to use in A/D converters operating in conjunction with subtractors, as previously discussed.

It should be appreciated that with either of the simplified forms described above the A/D converter shown in FIG. 2, there are practical limits to the reduction in resolution of the D/A converter. It is important to keep this in mind. Consider the case where a monotonically varying analog input signal is applied and a series of digital values are generated by A/D converter 204. When the bit corresponding to the resolution of the D/A converter 205 is reached, the D/A converter 205
A step change is generated in the output signal of the A converter and summed with the input signal. Although this step-like change is accurately reflected in the correction value, it affects the output signal of the integrator 203 over a finite period of time, thus introducing discontinuities in the digital output value and its waveform. However, these discontinuities are caused by the design of the integrator, and the D/A
It can also be minimized by analog filtering of the converter output signal or by digital processing of the digital output signal. Therefore, as will be apparent to those skilled in the art, the resolution of D/A converter 205 is fairly arbitrary, provided other parameters of circuit design and acceptable accuracy of the A/D converter are properly observed. It can be lowered.

In summary, as stated above, the present invention provides a simplified structure that reduces costs and reduces manufacturing tolerances while increasing the accuracy of A/D conversion at high resolution and high speed. This kind of performance can be obtained using the following. Further, although the invention has been described in the context of a first-order analog integrator, it can also be used in higher-order analog integrators, resulting in increased resolution as discussed above.

While only certain preferred features of the invention have been shown and described in the drawings, many modifications thereof will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications that fall within the scope of this invention.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a conventional D/A converter.

FIG. 2 is a circuit diagram showing the configuration of an A/D converter of the present invention.

[Explanation of symbols]

202 Totalizer 203 Integrator 204 A/D converter 205 D/A converter 211 Conversion means

Claims (16)

[Claims] 1. A forward signal path for generating a digital output signal; a feedback signal path for providing an analog input signal to the forward signal path; converting means for replacing the digital value generated by the signal path with a digital value comprising a correction value corresponding to the error of the feedback path. 2. The circuit arrangement of claim 1, wherein said converting means includes a look-up table memory having digital values corresponding to each possible output value on said feedback signal path. 3. The converting means, in response to each of the plurality of digital output values of the forward signal path, converts a lookup table having a digital value corresponding to an output value of the feedback signal path. Claim 1 comprising a bull memory
The circuit arrangement described. 4. The look-up table memory stores digital values corresponding to output values of the feedback signal path generated in response to each possible digital output value of the forward signal path. 4. The circuit device according to claim 3, comprising: 5. The circuit of claim 1, further comprising analog-to-digital circuitry, wherein the forward signal path includes an analog-to-digital converter and the feedback signal path includes a digital-to-analog converter. circuit device. 6. The device of claim 2, further comprising an analog-to-digital circuit arrangement, wherein the forward signal path includes an analog-to-digital converter and the feedback signal path includes a digital-to-analog converter. circuit device. 7. The device of claim 3, further comprising analog-to-digital circuitry, wherein the forward signal path includes an analog-to-digital converter and the feedback signal path includes a digital-to-analog converter. circuit device. 8. The device of claim 4, further comprising an analog-to-digital circuit arrangement, wherein the forward signal path includes an analog-to-digital converter and the feedback signal path includes a digital-to-analog converter. circuit device. 9. A forward signal path including an analog-to-digital converter circuit; a feedback signal path including a digital-to-analog converter circuit; coupled to the forward signal path; converting means for replacing the digital value generated by the converter with a digital value containing a correction value corresponding to the error in the feedback path. 10. The converting means is configured to convert the digital
10. The analog-to-digital converter apparatus of claim 9, including a look-up table memory having a digital value corresponding to each possible output value of the analog converter. 11. The lookup means for converting has a digital value corresponding to an output value of the digital-to-analog converter generated in response to each of a plurality of digital output values of the analog-to-digital converter. - An analog-to-digital converter arrangement according to claim 9, comprising a table memory. 12. The lookup table includes digital values corresponding to output values of the digital-to-analog converter generated in response to each possible digital output value of the analog-to-digital converter. 12. The analog-to-digital converter device according to claim 11. 13. The analog-to-digital converter apparatus of claim 9, wherein said converting means includes fixed memory. 14. The forward signal path of claim 9, wherein said forward signal path includes integrator means for providing an input signal to said analog-to-digital converter circuit, and difference summing means for providing an input signal to said integrator means. Analog to digital converter equipment. 15. The analog-to-digital converter apparatus of claim 14, wherein said converting means includes fixed memory. 16. A method of correcting a digital output signal produced by a circuit having a forward signal path and a feedback signal path, the method comprising: remember,
The digital output value of the forward signal path is
converting the digital output value of the forward signal path by substituting a digital value corresponding to a possible output value of the back signal path.