JPH0430119B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a memory device in which each memory cell can be accessed serially and at high speed with a simple circuit configuration.

Background of the Technology For example, some semiconductor memory devices such as dynamic random access memory are equipped with an auto-refresh function or a read-out function using nibble mode. The ability to access the data sequentially and serially is required. and,
In this case, it is necessary that serial access be performed at high speed, and it is also necessary that the number of circuit parts used for serial access be reduced, so that power consumption during serial access be reduced.

Prior Art and Problems Conventionally, in a dynamic random access memory device with an auto-refresh function,
During auto-refresh, the output of the refresh address counter is input to the address buffer for normal operation via the address switching circuit, and one target word line is selected by the row decoder, that is, the word decoder, and the refresh is performed. was going through the motions.

However, in such conventional memory devices, the address switching circuit, address buffer, and row decoder operate during auto-refresh as in normal operation, so auto-refresh requires a considerable amount of power. It becomes impossible to increase the speed of the auto-refresh operation faster than the normal access operation speed,
Therefore, there was a problem in that it was impossible to further increase the operating speed of the entire storage device.

In addition, some memory devices that perform serial access can operate in nibble mode, but conventional memory devices with nibble mode function transfer data from multiple memory cells via multiple data buses. The data was transferred to a data register in parallel, and the multiple bits of data stored in this data register were output serially.

However, in such a memory device, if it is necessary to increase the number of data bits read in one access, it is necessary to increase the number of data buses and the number of bits of data registers. This has the disadvantage that the amount of hardware becomes extremely large.

OBJECTS OF THE INVENTION In view of the problems with the conventional type described above, an object of the present invention is to provide a simple method based on the concept of providing a shift register in parallel with an address decoder in a semiconductor memory device and sequentially applying a selection signal from the shift register. The purpose of this invention is to enable serial access to be performed at high speed and to reduce power consumption during serial access through a circuit configuration.

Structure of the Invention The object of the invention is to provide a random access memory device having a structure for inputting and outputting data by selecting a row selection line and a column selection line to select a memory cell, and performing normal operation and refresh operation. A shift register is provided for sequentially selecting the row selection lines, and during refreshing, the row selection lines are sequentially selected by a signal from the shift register instead of a signal from the row decoder. This is achieved by providing a semiconductor memory device that achieves this goal.

Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings, while comparing them with conventional examples.

FIG. 1 partially shows the structure of a conventional dynamic random access memory having an auto-refresh function. In the figure, a memory cell array 1 includes a plurality of memory cells arranged at the intersections of a plurality of word lines WL and a plurality of bit lines BL.
It was composed by MC. 2 is a row decoder that selects a word line, 3 is a row decoder 2
An address buffer 4 inputs inverted and non-inverted address signals A, and a word drive circuit 4 applies a word drive signal WD to the row decoder 2. 5 is an address switching circuit, 6 is a row enable circuit, 7 is a refresh enable circuit, and 8 is a refresh address counter. Note that in FIG. 1, the column decoder and other parts are omitted.

In FIG. 1, in the case of a normal access operation, the row address strobe signal becomes low level, and the row enable signal RE is applied from the row enable circuit 6 to the word drive circuit 4 and address buffer 3. At this time, the refresh signal is at a high level, and the refresh enable circuit 7 does not output the refresh enable signal REF. Therefore, the address switching circuit 5 is switched to input the external address signal _AEXT to the address buffer 3. Then, the address buffer 3 _outputs non-inverted and inverted address signals A,
is input to the low decoder 2. Furthermore, the word drive circuit 4 is activated by the low enable signal RE.
operates to generate a word drive signal WD and input it to the row decoder 2. The row decoder 2 decodes the input non-inverted and inverted address signals A, selects a word line WL, and applies a word drive signal WD to the selected word line WL.
As a result, the selected word line WL and the bit line selected by a column decoder (not shown), etc.
Memory cell MC connected to BL is accessed.

On the other hand, during auto-refresh, the refresh signal becomes low level. As a result, the word drive circuit 4 and the address buffer 3 perform the same operations as described above, but the refresh enable circuit 7 receives the refresh enable signal because the refresh signal is at a low level.
RFE, is activated and applied to the address switching circuit 5. As a result, the address switching circuit 5 is switched to input the refresh address A _REF from the refresh address counter 8 to the address buffer 3. Therefore, address buffer 3 is a refresh address.
Non-inverted and inverted address signals A for each bit of A _REF are created and applied to the row decoder 2. Since the refresh address counter 8 sequentially updates the refresh address signal A _REF , each word line WL is sequentially selected by the row decoder 2, and a refresh operation is performed for each word line.

However, in the conventional storage device shown in FIG. 1, the address switching circuit 5, address buffer 3, row decoder 2, etc. are operated during auto-refresh in the same way as in normal operation, so the above-mentioned disadvantages occur. It was hot.

FIG. 2 partially shows a semiconductor memory device according to an embodiment of the present invention, which was devised to eliminate such disadvantages of the conventional type. In the figure, the memory cell array 1, address buffer 3, and refresh enable circuit 7 are the same as those used in the device of FIG. 1, and are designated by the same reference numerals. Reference numeral 9 is a word selection circuit including a row decoder and a shift register as a refresh address register. The word drive circuit 10 is controlled by a row enable signal RE inputted from the row enable circuit 11, as well as a refresh enable signal RFE inputted from the refresh enable circuit 7.
It supplies a word drive signal WD to the word selection circuit 9. In addition, the row enable circuit 11
outputs a row enable signal RE in response to input of a row address strobe signal. Note that the refresh address register in the word selection circuit 9 is provided in parallel with the row decoder, and has, for example, the same number of stages as the word lines WL, with each stage corresponding to each word line. The refresh address register operates in a so-called ring counter format, in which only one bit out of all bits is "1" and all others are "0". An auto-refresh operation is performed by sequentially selecting one target word line using this one bit that is "1".

In the memory device shown in FIG. 2, when a normal access operation is performed, the row address strobe signal is set to a low level and the refresh signal is held to a high level. As a result, the row enable signal RE, is output from the row enable circuit 11, and the word drive circuit 1
0 and address buffer 3. As a result, the address buffer 3 is activated, and the external address signal input to the address buffer 3 is activated.
Non-inverted and inverted address signals A corresponding to each bit of _AEXT are generated and input to the word selection circuit 9. Further, the word drive circuit 10 is also activated, and a word drive signal WD is generated and applied to the word selection circuit 9. In the word selection circuit 9, an internal row decoder decodes the input non-inverted and inverted address signals A, selects one word line WL, and applies the word drive signal WD. Further, the bit line BL is selected by a column decoder (not shown), and the selected word line is
The memory cell MC connected to WL and the selected bit line BL is accessed and data is read or written.

On the other hand, during auto-refresh, the refresh signal is set to a low level, and the refresh enable signal RFE is applied from the refresh enable circuit 7 to the word drive circuit 10 and the word selection circuit 9. As a result, the word drive circuit 10 receives the word drive signal WD.
is created and applied to the word selection circuit 9. The word selection circuit 9 also receives refresh enable signals RFE,
By applying RFE, a word line WL is selected by a signal from an internal shift register instead of a signal from a row decoder, and a word drive signal WD is applied to the selected word line WL. As a result, the word line WL is refreshed. In the shift register, that is, the refresh address register, data 1 is sequentially shifted and each word line WL is sequentially refreshed.

FIG. 3 shows details of a circuit provided in the word selection circuit 9 corresponding to one word line. The circuit shown in the figure includes a NOR gate 12 constituting a row decoder,
It includes a one-stage refresh address register circuit 13 constituting a refresh address register, and transistors Q ₁ , Q ₂ and Q ₃ .

In the circuit shown in FIG. 3, during a normal access operation, the refresh enable signal RFE is at a low level and the inverted refresh enable signal is at a high level. This allows transistor Q ₁
is cut off and transistor _Q2 is turned on.
Therefore, the NOR gate 12 of the row decoder circuit
The output of transistor _Q2 through transistor
Applied to the gate of Q ₃ . As a result, transistor _Q3 is turned on and word drive signal WD is applied to selected word line WL. On the contrary,
During auto-refresh, the refresh enable signal RFE is at a high level, the inverted refresh enable signal is at a low level, and the transistor _Q1 is turned on and the transistor _Q2 is turned off. Therefore, refresh address register circuit 1
3 is applied to the gate of transistor _Q3 via transistor _Q1 , and when the output of the refresh address register circuit 13 is "1", transistor _Q3 is turned on and the word drive signal WD becomes word drive signal WD. applied to line WL. if,
If the output of the refresh address register circuit 13 is "0", the transistor _Q3 remains off and the word drive signal is sent to the corresponding word line WL.
WD is not applied. In this way, only the word line WL whose output is "1" in each stage of the refresh address register is selected and the refresh operation is performed sequentially.

As mentioned above, in the memory device described with reference to FIGS. 2 and 3, the address buffer and word decoder do not need to operate during the refresh operation, and the word line selection signal is used in the refresh address register. Since the voltage is applied directly to the word line, high-speed operation can be expected and power consumption can be reduced. Furthermore, the refresh address register, that is, the shift register used in the word selection circuit 9 does not transfer random data, but only transfers one bit of "1".
Since it is a ring counter-type circuit that sequentially transfers only data, the circuit configuration can be significantly simplified compared to a conventional general shift register.

FIG. 4 shows a schematic structure of a dynamic random access memory having a conventional nibble mode function. In the same figure, 14 is, for example, 256×256
A memory cell array in which bit memory cells are arranged in a matrix; 15 is an input/output gate; 16 is an input/output gate;
is a column decoder, 17 is a 4-bit data register, 18 is a 4-bit shift register,
And 19 is an output buffer. Further, the input/output gate 15 and the data register 17 are connected by a data bus 20 consisting of, for example, four parallel signal lines.

In the storage device shown in FIG. 4, one word line is selected by a row decoder (not shown), and four bit lines, for example, are selected by a column decoder 16. In other words, each of the four transfer gates in the input/output gates 15 connected to these selected bit lines is driven. As a result, 4-bit data is read from the memory cell array 14 by the input/output gate 15 and transferred to the data bus DB.
The data are transferred to the data register 17 in parallel via the data register 17. Then, the 4 data transferred to the data register 17
The bit-parallel data is serially output by a transfer pulse generated from the shift register 18 and read out via the output buffer 19 as a data output D _OUT . With this configuration, 4-bit data is read out by accessing the memory cell array 14 only once, and this 4-bit data is sequentially output serially, resulting in higher speed than when accessing 1 bit at a time. Data can be read with . This mode of operation is called nibble mode, and is used in storage devices such as image memories that require serial data to be read out at high speed.

However, in the storage device shown in FIG. 4, when it is necessary to increase the number of bits of data read in one access, for example to 8 bits, 16 bits, or even 256 bits, the data bus 20 and It is necessary to increase the number of bits of the data register 17, etc., and there is an inconvenience that the amount of hardware becomes extremely large.

FIG. 5 shows the configuration of a memory device having a nibble mode function as a semiconductor memory device according to an embodiment of the present invention. 4, the memory cell array 14 and output buffer 19 are the same as in the device of FIG. 4 and are designated by the same reference numerals. The difference between the memory device shown in FIG. 5 and the one shown in FIG. 4 is that in the memory device shown in FIG. The second point is that the column decoder 22 is not provided, and the shift register 23 is provided in parallel with the column decoder 22. The shift register 23 uses a ring counter type similar to the refresh address register used in the storage device shown in FIG. All stages are made to output "0".

In the memory device shown in FIG. 5, in the case of a normal access operation, one word line is selected by a row decoder (not shown), and a column decoder 2
2 selects one bit of a plurality of memory cells connected to the selected word line, and input/output gate 21, data bus 24 and output buffer 19
is taken out as data output D _OUT via.

On the other hand, when serial reading is performed, one word line is selected by a row decoder (not shown), and one bit line is selected by a signal from the shift register 23. As a result, one bit of data is taken out via the input/output gate 21, data bus 24 and output buffer 19 as data output D _OUT . Then, while a row decoder (not shown) selects one word line, the data "1" in the shift register 23 is sequentially shifted, and the data from the memory cells connected to the selected word line are sequentially serialized in the same way. is read out.

By using the configuration shown in Figure 5,
It becomes possible to serially access data of many bits without being limited by the number of data buses and the number of bits of data registers. Although it has been explained that in the circuit shown in FIG. 5, there is one output data transfer path including the data bus 24, etc., for example, the data read speed can be further increased by providing two systems such as the data bus. It is also possible.

Effects of the Invention As described above, according to the present invention, by sequentially selecting row selection lines using signals from a shift register instead of signals from a row decoder during refreshing, refreshing in a semiconductor memory device (DRAM) is performed. This makes it possible to reduce power consumption during operation.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing the structure of a conventional semiconductor memory device having an auto-refresh function, and FIG. 2 is a block circuit diagram showing the structure of a semiconductor memory device having an auto-refresh function according to an embodiment of the present invention. 3 is a block circuit diagram showing the details of the word selection circuit in FIG. 2, FIG. 4 is a block circuit diagram showing the configuration of a conventional semiconductor memory device having a nibble mode function, and FIG. 5 is a block circuit diagram showing details of the word selection circuit in FIG. 1 is a block circuit diagram showing the configuration of a semiconductor memory device having a nibble mode function according to an embodiment of the invention; FIG. 1, 14...Memory cell array, 2...Row decoder, 3...Address buffer, 4,10...
word drive circuit, 5...address switching circuit,
6, 11...Row enable circuit, 7...Refresh enable circuit, 8...Refresh address counter, 9...Word selection circuit, 12...
NOR gate circuit, 13... Refresh address register circuit, 15, 21... Input/output gate,
16, 22... Column decoder, 17... Data register, 18... Shift register, 19... Output buffer, 20, 24... Data bus, 23...
...Shift register, WL...Word line, BL...
Bit line, MC...memory cell, Q ₁ , Q ₂ , Q ₃ ...
...transistor.

Claims (1)

[Scope of Claims] 1. A random access memory device that is configured to input and output data by selecting a row selection line and a column selection line to select a memory cell, and that performs normal operation and refresh operation. , a shift register for sequentially selecting row selection lines is provided, and during refresh, the row selection lines are sequentially selected by a signal from the shift register instead of a signal from a row decoder. Semiconductor storage device.