JPH04299837A - Manufacture of active matrix liquid-crystal display - Google Patents
Manufacture of active matrix liquid-crystal displayInfo
- Publication number
- JPH04299837A JPH04299837A JP3064581A JP6458191A JPH04299837A JP H04299837 A JPH04299837 A JP H04299837A JP 3064581 A JP3064581 A JP 3064581A JP 6458191 A JP6458191 A JP 6458191A JP H04299837 A JPH04299837 A JP H04299837A
- Authority
- JP
- Japan
- Prior art keywords
- film
- crystal display
- active matrix
- insulating film
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000011159 matrix material Substances 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000002245 particle Substances 0.000 claims abstract description 13
- 238000004140 cleaning Methods 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 65
- 238000000034 method Methods 0.000 claims description 24
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 18
- 239000010409 thin film Substances 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 9
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011651 chromium Substances 0.000 description 9
- 238000012545 processing Methods 0.000 description 9
- 229910001120 nichrome Inorganic materials 0.000 description 7
- 229910052804 chromium Inorganic materials 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000006864 oxidative decomposition reaction Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- JMOHEPRYPIIZQU-UHFFFAOYSA-N oxygen(2-);tantalum(2+) Chemical compound [O-2].[Ta+2] JMOHEPRYPIIZQU-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、アクティブマトリクス
液晶ディスプレイの製造方法、特に、アモルファスシリ
コン薄膜トランジスタアレイ基板の製造方法に特徴を有
するアクティブマトリクス液晶ディスプレイの製造方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an active matrix liquid crystal display, and more particularly, to a method for manufacturing an active matrix liquid crystal display characterized by a method for manufacturing an amorphous silicon thin film transistor array substrate.
【0002】0002
【従来の技術】図3はアモルファスシリコンを用いた薄
膜トランジスタ(以下、「a−SiTFT」という)を
内蔵したアクティブマトリクス液晶ディスプレイの断面
図であり、図4は従来のa−SiTFTアレイ基板の製
造工程のフロー図である。以下、図3及び図4に基づい
て従来のアクティブマトリクス液晶ディスプレイの製造
方法を説明する。2. Description of the Related Art FIG. 3 is a cross-sectional view of an active matrix liquid crystal display incorporating a thin film transistor (hereinafter referred to as "a-SiTFT") using amorphous silicon, and FIG. 4 shows a conventional manufacturing process of an a-SiTFT array substrate. FIG. Hereinafter, a method for manufacturing a conventional active matrix liquid crystal display will be described with reference to FIGS. 3 and 4.
【0003】まず、図4(a)に示すように、アクティ
ブマトリクス液晶ディスプレイの下側基板となるa−S
iTFT基板(下基板)は、ガラス基板1の上にクロム
(Cr)、タンタル(Ta)、モリブデン(Mo)より
なる金属層を、スパッタ又は蒸着により0.1〜0.3
μm程度成膜し、その後ホトリソエッチングより所定の
形状に加工することでゲート電極2を形成する。First, as shown in FIG. 4(a), a
The iTFT substrate (lower substrate) is made by depositing a metal layer of chromium (Cr), tantalum (Ta), and molybdenum (Mo) on the glass substrate 1 by sputtering or vapor deposition.
The gate electrode 2 is formed by depositing a film of about μm and then processing it into a predetermined shape by photolithography etching.
【0004】その後、図4(b)に示すように、ゲート
電極膜の所定の部分を所定の膜厚分だけ陽極化成するこ
とで、第一ゲート絶縁膜となるタンタル酸化物(TaO
x)3を0.1〜0.3μmの膜厚に形成する。なお、
このときの化成膜の誘電率は25〜30である。そして
、図4(c)に示すように、NH3 とSiH4 ガス
を主成分とするプラズマCVD法(以下、「PCVD」
法という)によりシリコン窒化膜(SiNx)を膜厚0
.1〜0.4μm基板全面に堆積させる。Thereafter, as shown in FIG. 4(b), a predetermined portion of the gate electrode film is anodized to a predetermined thickness to form tantalum oxide (TaO), which will become the first gate insulating film.
x) 3 is formed to a film thickness of 0.1 to 0.3 μm. In addition,
The dielectric constant of the chemically formed film at this time is 25 to 30. Then, as shown in Figure 4(c), a plasma CVD method (hereinafter referred to as "PCVD") using NH3 and SiH4 gases as main components was applied.
A silicon nitride film (SiNx) is deposited to a thickness of 0 using
.. It is deposited to a thickness of 1 to 0.4 μm over the entire surface of the substrate.
【0005】次に、図4(d)に示すように、SiH4
ガスを主成分とするPCVD法によりa−Siを膜厚
0.05〜0.2μm、オーミック接合を作るn+ 型
a−Siを0.003〜0.005μmそれぞれ基板全
面に堆積させる。そして、それらを所定の形状に加工す
ることでゲート絶縁膜4、a−Si半導体層5、及びn
+ 型a−Si層6を形成する。Next, as shown in FIG. 4(d), SiH4
A-Si is deposited to a thickness of 0.05 to 0.2 μm and n+ type a-Si to form an ohmic contact is deposited to a thickness of 0.003 to 0.005 μm over the entire surface of the substrate by a PCVD method using gas as the main component. Then, by processing them into a predetermined shape, the gate insulating film 4, the a-Si semiconductor layer 5, and the n-Si semiconductor layer 5 are formed.
A + type a-Si layer 6 is formed.
【0006】次に、図4(e)に示すように、アルミニ
ウム(Al)、クロム(Cr)、ニクロム(NiCr)
などよりなる金属層を、スパッタ又は蒸着により0.3
〜1.0μm程度成膜し、それを所定の形状に加工する
ことでソース電極7及びドレイン電極8を形成する。そ
して、図4(f)に示すように、PCVD法によりシリ
コン窒化膜(SiNx)などからなる絶縁膜を成膜し、
加工によりAl、Cr、NiCrなどによりなるソース
電極と後述のITO膜との接続用コンクタトホールを含
む所定の形状に形成することで表面保護膜9を形成する
。Next, as shown in FIG. 4(e), aluminum (Al), chromium (Cr), nichrome (NiCr)
A metal layer of 0.3
The source electrode 7 and the drain electrode 8 are formed by forming a film with a thickness of about 1.0 μm and processing it into a predetermined shape. Then, as shown in FIG. 4(f), an insulating film made of silicon nitride film (SiNx) or the like is formed by the PCVD method,
The surface protective film 9 is formed by processing into a predetermined shape including a contact hole for connecting a source electrode made of Al, Cr, NiCr, etc. and an ITO film to be described later.
【0007】最後に、図4(g)に示すように、ITO
膜(In2 O3 +SnO2 )を、スパッタ又は蒸
着により0.1μm程度成膜し、そして所定の形状に加
工することで表示用電極となる透明電極9を形成する。
以上の透明電極付a−SiTFTを、2次元的に配置す
ることで、a−SiTFTアレイ基板が完成する。そし
て、このTFTアレイ基板上に膜厚0.1μmのポリイ
ミドよりなる有機膜を形成し、ラビング処理することで
配向処理膜を形成する。その後、セル間隔を均一に形成
し、保持するために直径3〜10μmのスペーサ11を
配向処理膜上に散布することで下基板が完成する。Finally, as shown in FIG. 4(g), ITO
A film (In2O3 +SnO2) is formed to a thickness of about 0.1 μm by sputtering or vapor deposition, and then processed into a predetermined shape to form a transparent electrode 9 that will serve as a display electrode. By two-dimensionally arranging the above a-SiTFTs with transparent electrodes, an a-SiTFT array substrate is completed. Then, an organic film made of polyimide having a thickness of 0.1 μm is formed on this TFT array substrate, and a rubbing treatment is performed to form an alignment treatment film. Thereafter, in order to form and maintain uniform cell spacing, spacers 11 having a diameter of 3 to 10 μm are sprinkled on the alignment film to complete the lower substrate.
【0008】一方、上基板(対向電極側)は、以下に示
すように形成される。まず、ガラス基板12の上に光の
漏れを防止しコントラストを向上させるためのブラック
マトリクス層13を形成する。次に、印刷又は電着など
と加工により着色層14を形成する。次に、この上に平
坦化層15を形成後、対向電極として膜厚0.1μm程
度のITO膜よりなる対向透明電極16を、スパッタ又
は蒸着と加工により所定の形状に形成する。さらに、対
向電極16上に膜厚0.1μm程度のポリイミドよりな
る有機膜を形成し、ラビング処理することで配向処理膜
17を形成する。さらに、高分子材料絶縁材料(エポキ
シ系などの材料)にスペーサを混入させた材料を用いた
厚膜のスクリーン印刷法により膜厚5〜20μmのシー
ル層18を所定のパターンで形成することで上基板が完
成する。On the other hand, the upper substrate (counter electrode side) is formed as shown below. First, a black matrix layer 13 is formed on a glass substrate 12 to prevent light leakage and improve contrast. Next, the colored layer 14 is formed by printing, electrodeposition, or other processing. Next, after forming a flattening layer 15 thereon, a counter transparent electrode 16 made of an ITO film with a thickness of about 0.1 μm is formed into a predetermined shape by sputtering or vapor deposition and processing. Further, an organic film made of polyimide having a thickness of about 0.1 μm is formed on the counter electrode 16, and a rubbing process is performed to form an alignment film 17. Furthermore, a sealing layer 18 with a film thickness of 5 to 20 μm is formed in a predetermined pattern by a thick film screen printing method using a material in which a spacer is mixed into a polymeric insulating material (such as an epoxy material). The board is completed.
【0009】上下の基板が完成したら、シール層を挟ん
でシール層により上下基板を位置合わせして貼り合わせ
、加圧固定してシール層を加熱硬化させる。さらに、シ
ール層の内側を真空脱気した後、所定の注入口より液晶
19を注入する。最後に注入口を封止し偏光膜20を所
定の位置に貼りつけることでa−SiTFTを用いた液
晶ディスプレイが完成する。When the upper and lower substrates are completed, the upper and lower substrates are aligned and bonded together with the sealing layer in between, and the sealing layers are heated and cured by being fixed under pressure. Furthermore, after the inside of the seal layer is vacuum degassed, liquid crystal 19 is injected through a predetermined injection port. Finally, the injection port is sealed and the polarizing film 20 is pasted at a predetermined position, thereby completing a liquid crystal display using an a-SiTFT.
【0010】0010
【発明が解決しようとする課題】しかしながら、上記構
成のアクティブマトリクス液晶ディスプレイの製造方法
においては、表面画面の大型化や表示容量の増大に従っ
て成膜中でのパーティクル、工程途中での洗浄不良によ
る異物などが原因で、TFTの絶縁層や半導体層の膨れ
、半導体層と電極層の密着低下によるドレイン電極のオ
ープンが発生しやすくなる。その結果、液晶ディスプレ
イの表示欠陥(線欠陥、点欠陥)となるため、表示品質
の低下を招くという問題点があった。[Problems to be Solved by the Invention] However, in the method for manufacturing an active matrix liquid crystal display having the above structure, as the surface screen becomes larger and the display capacity increases, particles during film formation and foreign matter due to poor cleaning during the process are produced. For these reasons, the insulating layer and semiconductor layer of the TFT tend to bulge, and the drain electrode tends to open due to reduced adhesion between the semiconductor layer and the electrode layer. As a result, display defects (line defects, point defects) occur in the liquid crystal display, resulting in a problem of deterioration in display quality.
【0011】本発明は、上記従来の問題点を解決して、
パーティクル、有機異物などによるドレイン線欠陥のな
い表示品質が優れたアクティブマトリクス液晶ディスプ
レイの製造方法を提供することを目的とする。[0011] The present invention solves the above conventional problems, and
An object of the present invention is to provide a method for manufacturing an active matrix liquid crystal display with excellent display quality and free from drain line defects due to particles, organic foreign matter, etc.
【0012】0012
【課題を解決するための手段】前記問題点を解決するた
めに、本発明は、透光性絶縁基板上に順次、ゲート電極
、第一ゲート絶縁膜、第二ゲート絶縁膜、アモルファス
シリコン半導体層、ソース−ドレイン電極、透明電極、
表面保護膜を形成したアモルファスシリコン薄膜トラン
ジスタアレイを製造するアクティブマトリクス液晶ディ
スプレイの製造方法において、第二ゲート絶縁膜、半導
体層又はソース,ドレイン電極を形成する際、基板に紫
外線照射を行うことにより、成膜中でのパーティクル、
工程途中での洗浄不良により透明樹脂状の有機異物やレ
ジスト残さなど酸化分解するものである。[Means for Solving the Problems] In order to solve the above problems, the present invention provides a structure in which a gate electrode, a first gate insulating film, a second gate insulating film, and an amorphous silicon semiconductor layer are sequentially formed on a transparent insulating substrate. , source-drain electrode, transparent electrode,
In a method for manufacturing an active matrix liquid crystal display that manufactures an amorphous silicon thin film transistor array on which a surface protective film is formed, when forming a second gate insulating film, a semiconductor layer, or a source and drain electrode, the substrate is irradiated with ultraviolet rays. particles in the film,
Due to poor cleaning during the process, transparent resin-like organic foreign matter and resist residue are oxidized and decomposed.
【0013】[0013]
【作用】本発明によれば、以上のようにアクティブマト
リクス液晶ディスプレイの製造方法を構成したので、第
二ゲート絶縁膜、半導体層又はソース−ドレイン電極を
形成する際、基板に紫外線照射を行って発生させたオゾ
ンにより、成膜中でのパーティクル、工程途中での洗浄
不良により透明樹脂状の有機異物やレジスト残さなど酸
化分解する。[Operation] According to the present invention, since the method for manufacturing an active matrix liquid crystal display is configured as described above, when forming the second gate insulating film, the semiconductor layer, or the source-drain electrode, the substrate is irradiated with ultraviolet rays. The generated ozone oxidizes and decomposes particles during film formation, transparent resin-like organic foreign matter and resist residue due to poor cleaning during the process.
【0014】[0014]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図1は本発明の実施例によるa
−SiTFTアレイ基板の製造工程のフロー図である。
以下、図1及び図3に基づいて本発明の実施例によるア
クティブマトリクス液晶ディスプレイの製造方法を説明
するが、本実施例における成膜条件(方法、雰囲気、膜
厚等)は前記従来例と同じであるので、重複を避けるた
めその記載を一部省略する。Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a diagram according to an embodiment of the present invention.
- It is a flowchart of the manufacturing process of a SiTFT array substrate. Hereinafter, a method for manufacturing an active matrix liquid crystal display according to an embodiment of the present invention will be explained based on FIGS. 1 and 3. The film forming conditions (method, atmosphere, film thickness, etc.) in this embodiment are the same as in the conventional example. Therefore, some of the descriptions will be omitted to avoid duplication.
【0015】まず、図1(a)に示すように、ガラス基
板1の上にタンタル(Ta)膜を成膜し、その後ホトリ
ソエッチングにより所定の形状に加工することでゲート
電極2を形成する。その後、図1(b)に示すように、
ゲート電極膜2の所定の部分を所定の膜厚分だけ陽極化
成することで、第一ゲート絶縁膜となるタンタル酸化膜
(TaOx)3を形成する。このときの、化成膜の誘電
率は25〜30である。First, as shown in FIG. 1(a), a tantalum (Ta) film is formed on a glass substrate 1, and then processed into a predetermined shape by photolithography to form a gate electrode 2. . After that, as shown in FIG. 1(b),
By anodizing a predetermined portion of the gate electrode film 2 to a predetermined thickness, a tantalum oxide film (TaOx) 3, which will become a first gate insulating film, is formed. At this time, the dielectric constant of the chemically formed film is 25 to 30.
【0016】次に、第二ゲート絶縁膜4とa−Si半導
体層5及びn+ 型a−Si層6を成膜する前に、電力
密度(1.2W/cm2 〜2.4W/cm2 )で一
定時間(15〜30分)の紫外線を基板表面に照射する
。紫外線の照射により周囲の酸素から発生したオゾンが
パーティクル、洗浄不良による透明樹脂状の有機異物や
レジスト残さなどを化学反応(酸化分解)する。そして
、基板表面に窒素ガスを吹きつけて分解されたパーティ
クルや有機異物を排除した後、図1(d)に示すように
、第二ゲート絶縁膜4の成膜を行い、次いで図1(d)
に示すように、a−Si半導体層5、及びn+ 型a−
Si層6の成膜を行う。Next, before forming the second gate insulating film 4, the a-Si semiconductor layer 5, and the n+ type a-Si layer 6, it is heated at a power density (1.2 W/cm2 to 2.4 W/cm2). The substrate surface is irradiated with ultraviolet light for a certain period of time (15 to 30 minutes). Ozone generated from the surrounding oxygen when irradiated with ultraviolet rays causes a chemical reaction (oxidative decomposition) of particles, transparent resin-like organic foreign matter caused by poor cleaning, and resist residue. After blowing nitrogen gas onto the substrate surface to remove decomposed particles and organic foreign matter, the second gate insulating film 4 is formed as shown in FIG. 1(d). )
As shown in FIG.
A Si layer 6 is formed.
【0017】そして、それらを所定の形状に加工するこ
とでゲート絶縁膜4、a−Si半導体層5、及びn+
型a−Si層6を形成する。次に、成膜後において、先
程と同様な電力密度(1.2W/cm2 〜2.4Wc
m2 )で一定時間(15〜30分)の紫外線を照射し
てオゾンを発生させ、基板表面に付着した有機異物を酸
化分解して除去することで、表面を清潔に保ち、次に成
膜するアルミニウム(Al)、クロム(Cr)、ニクロ
ム(NiCr)などよりなる金属膜との密着性を向上さ
せる。Then, by processing them into a predetermined shape, the gate insulating film 4, the a-Si semiconductor layer 5, and the n+
A type a-Si layer 6 is formed. Next, after film formation, the same power density as before (1.2W/cm2 ~ 2.4Wc
m2) is irradiated with ultraviolet rays for a certain period of time (15 to 30 minutes) to generate ozone, which oxidizes and decomposes organic foreign matter adhering to the substrate surface and removes it, keeping the surface clean and then depositing the film. Improves adhesion to metal films made of aluminum (Al), chromium (Cr), nichrome (NiCr), etc.
【0018】以上の電力密度、時間は、工程上のスルー
プット、コストから短時間でかつ小電力が望ましいこと
は言うまでもない。しかしながら、電力密度が1.2W
/cm2 以下で、時間が15分以下ではパーティクル
、洗浄不良における透明樹脂状の有機異物やレジスト残
差などを完全に除去することは不可能である。次に、図
1(e)に示すように、Al,Cr,NiCrなどの金
属層を所定の形状に加工することで、ソース電極7及び
ドレイン電極8を形成する。It goes without saying that the above power density and time are preferably short and low power from the viewpoint of process throughput and cost. However, the power density is 1.2W
/cm2 or less and the time is less than 15 minutes, it is impossible to completely remove particles, transparent resin-like organic foreign matter due to poor cleaning, resist residuals, etc. Next, as shown in FIG. 1E, a source electrode 7 and a drain electrode 8 are formed by processing a metal layer such as Al, Cr, or NiCr into a predetermined shape.
【0019】そして、図1(f)に示すように、PCV
D法によりシリコン窒化膜(SiNx)などからなる絶
縁膜を成膜し、加工によりAl,Cr,NiCrなどに
よりなるソース電極と、後述のITO膜との接続用コン
タクトホールを含む所定の形状に形成することで表面保
護膜9を形成する。最後に、図1(g)に示すように、
ITO膜(In2 O3 +SnO2 )を、スパッタ
又は蒸着により成膜し、所定形状に加工することで表示
用電極となる透明電極10を形成する。以上の透明電極
付a−SiTFTを、2次元的に配置することで、a−
SiTFTアレイ基板が完成する。Then, as shown in FIG. 1(f), the PCV
An insulating film made of a silicon nitride film (SiNx) or the like is formed using the D method, and processed into a predetermined shape including a contact hole for connecting a source electrode made of Al, Cr, NiCr, etc. and an ITO film described later. By doing so, a surface protection film 9 is formed. Finally, as shown in Figure 1(g),
An ITO film (In2O3 +SnO2) is formed by sputtering or vapor deposition, and processed into a predetermined shape to form a transparent electrode 10 that becomes a display electrode. By arranging the above a-Si TFTs with transparent electrodes two-dimensionally, a-
The SiTFT array substrate is completed.
【0020】この後、下基板は従来技術を用いて、配向
処理膜、スペーサ散布を行う。一方、対向電極基板(上
基板)は、対向透明電極、ブラックマトリクス層、配向
処理膜を順次従来技術を用いて形成する。これ以後のセ
ル組立工程は、すべて従来技術と同一である。このよう
にして、液晶ディスプレイが完成する。Thereafter, the lower substrate is coated with an alignment film and spacers using conventional techniques. On the other hand, for the counter electrode substrate (upper substrate), a counter transparent electrode, a black matrix layer, and an alignment film are sequentially formed using a conventional technique. All subsequent cell assembly steps are the same as in the prior art. In this way, a liquid crystal display is completed.
【0021】図2は本発明の実施例により製造したa−
SiTFTと従来の製造方法により製造したa−SiT
FTの動作を示す特性図である。図の横軸はゲート電圧
VGで1目盛り5Vである。そして、右側の縦軸はドレ
イン電流IDで、1目盛り上がる毎に電流値が10倍に
なり、a1が従来技術により製造したもの、b1が本実
施例により製造したものを示す。また、左側の縦軸はド
レイン電流IDの平方根で、目盛りは等間隔であり、a
2が従来技術により製造したもの、b2が本実施例によ
り製造したものを示す。FIG. 2 shows a-
SiTFT and a-SiT manufactured by conventional manufacturing method
FIG. 3 is a characteristic diagram showing the operation of FT. The horizontal axis in the figure is the gate voltage VG, with each division being 5V. The vertical axis on the right side is the drain current ID, and the current value increases ten times with each increment. a1 indicates the drain current manufactured by the conventional technique, and b1 indicates the drain current ID manufactured by the present embodiment. The left vertical axis is the square root of the drain current ID, and the scale is equally spaced, a
2 shows the one manufactured by the conventional technique, and b2 shows the one manufactured by the present example.
【0022】図から明らかなように、本発明の実施例に
おいては従来例と比較して、ゲート電圧が正のときのド
レイン電流が多いからIonを増大することができ、ゲ
ート電圧が負のときのドレイン電流が少ないからIOf
f を低減させることができ、さらに、ドレイン電流が
0になるゲート電圧が低いからしきい値電圧(Vth)
を低減することができる。As is clear from the figure, in the embodiment of the present invention, compared to the conventional example, Ion can be increased because the drain current is large when the gate voltage is positive, and Ion can be increased when the gate voltage is negative. Since the drain current of is small, IOf
In addition, since the gate voltage at which the drain current becomes 0 is low, the threshold voltage (Vth) can be reduced.
can be reduced.
【0023】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づき種々の変形が可能で
あり、それらを本発明の範囲から排除するものではない
。It should be noted that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
【0024】[0024]
【発明の効果】以上詳細に説明したように、本発明によ
れば、紫外線照射を行うことで、成膜中でのパーティク
ル、工程途中での洗浄不良により透明樹脂状の有機異物
やレジスト残さなど酸化分解させ除去するので、次のよ
うな効果を奏する。
(1)工程中でのパーティクル、洗浄不良における透明
樹脂状の有機異物やレジスト残さなどによる膜欠陥、及
びゲート電極やドレイン電極のオープンやショートの発
生を低下させることができるので、歩溜りが向上する。As explained in detail above, according to the present invention, by performing ultraviolet irradiation, particles during film formation, transparent resin-like organic foreign matter and resist residue due to poor cleaning during the process can be removed. Since it is removed by oxidative decomposition, the following effects are achieved. (1) It can reduce film defects caused by particles during the process, transparent resin-like organic foreign matter due to poor cleaning, resist residue, etc., and the occurrence of opens and shorts in gate electrodes and drain electrodes, improving yields. do.
【0025】(2)膜と膜の密着性が向上するので、ホ
トリソエッチなどにより所定の形状に加工する際、膜間
の剥離を防止することができる。したがって、ゲート電
極やドレイン電極のオープンが原因で発生する線欠陥な
どの表示欠陥のない表示特性の良好なアクティブマトリ
クス液晶ディスプレイが得られる。
(3)第一ゲート絶縁膜と第二ゲート絶縁膜の膜界面を
紫外線照射することにより、クリーンな界面が形成でき
る。(2) Since the adhesion between the films is improved, peeling between the films can be prevented when processing into a predetermined shape by photolithography etching or the like. Therefore, an active matrix liquid crystal display with good display characteristics without display defects such as line defects caused by open gate electrodes or drain electrodes can be obtained. (3) By irradiating the film interface between the first gate insulating film and the second gate insulating film with ultraviolet rays, a clean interface can be formed.
【0026】(4)紫外線照射により、半導体層とドレ
イン電極間の接触抵抗を低減させることができる。
(5)オン電流Ionが大きく、オフ電流IOff が
小さく、かつしきい値電圧Vthが小さいアクティブマ
トリクス液晶ディスプレイが得られる。(4) Contact resistance between the semiconductor layer and the drain electrode can be reduced by ultraviolet irradiation. (5) An active matrix liquid crystal display having a large on-current Ion, a small off-current Ioff, and a small threshold voltage Vth can be obtained.
【図1】本発明の実施例によるa−SiTFTアレイ基
板の製造工程のフロー図である。FIG. 1 is a flow diagram of a manufacturing process of an a-Si TFT array substrate according to an embodiment of the present invention.
【図2】本発明の実施例によるa−SiTFTの動作を
示す特性図である。FIG. 2 is a characteristic diagram showing the operation of an a-SiTFT according to an embodiment of the present invention.
【図3】アクティブマトリクス液晶ディスプレイの断面
図である。FIG. 3 is a cross-sectional view of an active matrix liquid crystal display.
【図4】従来のa−SiTFTアレイ基板の製造工程の
フロー図である。FIG. 4 is a flow diagram of a conventional a-SiTFT array substrate manufacturing process.
1 ガラス基板 2 ゲート電極 3 第一ゲート絶縁膜 4 第二ゲート絶縁膜 5 a−Si半導体層 6 n+ 型a−Si層 7 ソース電極 8 ドレイン電極 9 表面保護膜 10 透明電極 1 Glass substrate 2 Gate electrode 3 First gate insulating film 4 Second gate insulating film 5 a-Si semiconductor layer 6 n+ type a-Si layer 7 Source electrode 8 Drain electrode 9 Surface protective film 10 Transparent electrode
Claims (3)
、第一ゲート絶縁膜、第二ゲート絶縁膜、アモルファス
シリコン半導体層、ソース−ドレイン電極、透明電極、
表面保護膜を形成したアモルファスシリコン薄膜トラン
ジスタアレイを製造するアクティブマトリクス液晶ディ
スプレイの製造方法において、前記第二ゲート絶縁膜、
アモルファスシリコン半導体層、又はソース−ドレイン
電極を形成する際に、前記基板に紫外線照射を行うこと
により膜形成工程中で発生するパーティクルや洗浄不良
による異物等を酸化分解することを特徴とするアクティ
ブマトリクス液晶ディスプレイの製造方法。1. A gate electrode, a first gate insulating film, a second gate insulating film, an amorphous silicon semiconductor layer, a source-drain electrode, a transparent electrode,
In the method for manufacturing an active matrix liquid crystal display, which manufactures an amorphous silicon thin film transistor array on which a surface protection film is formed, the second gate insulating film;
An active matrix characterized in that when forming an amorphous silicon semiconductor layer or a source-drain electrode, the substrate is irradiated with ultraviolet rays to oxidize and decompose particles generated during the film formation process and foreign matter due to poor cleaning. Method of manufacturing liquid crystal displays.
〜2.4W/cm2 であることを特徴とする請求項1
記載のアクティブマトリクス液晶ディスプレイの製造方
法。[Claim 2] Ultraviolet irradiation density is 1.2 W/cm2
Claim 1 characterized in that it is ~2.4 W/cm2.
The method of manufacturing the active matrix liquid crystal display described.
ることを特徴とする請求項1又は2記載のアクティブマ
トリクス液晶ディスプレイの製造方法。3. The method for manufacturing an active matrix liquid crystal display according to claim 1, wherein the ultraviolet irradiation time is 15 minutes to 30 minutes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3064581A JPH04299837A (en) | 1991-03-28 | 1991-03-28 | Manufacture of active matrix liquid-crystal display |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3064581A JPH04299837A (en) | 1991-03-28 | 1991-03-28 | Manufacture of active matrix liquid-crystal display |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04299837A true JPH04299837A (en) | 1992-10-23 |
Family
ID=13262356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3064581A Withdrawn JPH04299837A (en) | 1991-03-28 | 1991-03-28 | Manufacture of active matrix liquid-crystal display |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04299837A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6559066B2 (en) | 1996-08-02 | 2003-05-06 | Sharp Kabushiki Kaisha | Substrate for use in display element, method of manufacturing the same, and apparatus for manufacturing the same |
-
1991
- 1991-03-28 JP JP3064581A patent/JPH04299837A/en not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6559066B2 (en) | 1996-08-02 | 2003-05-06 | Sharp Kabushiki Kaisha | Substrate for use in display element, method of manufacturing the same, and apparatus for manufacturing the same |
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