JPH04287136A - Debugging system and emulator - Google Patents

Abstract

PURPOSE:To offer a technique to debug the software of a target system faithfully and more inexpensively. CONSTITUTION:Since a system program for debugging is integrated in a user program as the object of debugging and such a user program is executed by a user processor 6 mounted at a target system 4, it is not necessary to mount a chip for evaluation to an emulator 1 and therefore, the emulator 1 can be miniaturized and light in weight as well as reducing the price. Further, since a real chip is used in this way, the software can be debugged faithfully.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a debugging method for supporting the development of software for a target system and an emulator used therein. The present invention relates to a technique that is effective when applied to system debugging using an ASIC (Application Specific Integrated Circuit) as a target processor.

0002

[Prior Art] In the development of microcomputer application equipment (hereinafter simply referred to as target system), an emulator for performing system debugging and system evaluation is used to develop a microcomputer or microprocessor (hereinafter simply referred to as target microprocessor) included in the target system. It enables system debugging while acting on behalf of the functions of In order to facilitate such debugging, and to enable debugging of user programs even when a target system does not exist, a microprocessor equivalent to the target microprocessor (referred to as an evaluation chip or evaluation chip) is generally used. ) is installed in the emulator,
This debug-dedicated processor executes a user program to be debugged and controls the target system on its behalf. At this time, the content of the user program is arbitrarily changed via a host system such as a system development device, and its control status is traced.
It supports software debugging of the target system while making it possible to check the trace results at predetermined breakpoints. In this way, the emulator supports software debugging or system debugging while actually operating the target system using a user program.

[0003] The emulator also sets execution start conditions and breakpoint control conditions for the user program, transfers trace information obtained by executing the user program to the host system, and transfers the user program downloaded from the host system. Data transfer control is required to transfer data to the user memory space, and therefore the emulator must execute a system program in addition to the user program. Particularly in data transfer control performed by executing a system program, it is necessary to transfer data and user programs in a user memory space to the system memory space in order to provide them to the host system, and vice versa. That is, when controlling data transfer by a processor built in an emulator, it is necessary to selectively switch the memory space to be accessed to the user memory space or the system memory space.

[0004] An example of a document describing an emulator is Japanese Patent Application No. 61-276504.

[0005]

[Problem to be solved by the invention] ASIC aimed at reducing the development cost and shortening the development period of semiconductor integrated circuits
is a high-mix low-volume LSI, and emulators that target such LSIs require a dedicated evaluation chip to be created and installed for each LSI type, so the development period is relatively short. Long and accurate,
Because of the development costs involved, the evaluation chip installed in the emulator developed in this way is usually slightly different from the actual chip in terms of operating timing, etc. Therefore, the inventor has found that there are cases in which it is doubtful whether the emulation of the target system is being performed faithfully.

An object of the present invention is to provide a technique that allows software debugging of a target system to be performed faithfully and at a lower cost.

Another object of the present invention is to provide a technology that allows emulators to be developed at low cost and in a short period of time.

Another object of the present invention is to provide an emulator with excellent versatility.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

0010

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, the user program to be debugged and the system program for debugging are executed by a user processor as a real chip to be installed in the target system, and the information to be input/output by the user processor at that time is executed by an emulator. By monitoring, the user program can be debugged. At this time, the debugging system program includes a break interrupt request made to the user processor when the execution state of the user program matches a predetermined break condition, and an interrupt request on the user system during user program execution. The process may include a step of determining the following, and a step of proceeding to a corresponding predetermined processing routine based on the determination in this step. Further, as a device suitable for such software debugging, it is possible to connect to an IC socket of a target system, and when a user processor is connected to the target system, it is possible to detect information to be input/output by the processor. A CPU probe to
A user interface section is connected to the CPU probe via an interface cable, and the bus state of the user processor is monitored via this user interface section, and when the bus state matches a predetermined break condition, the user interface section is connected to the CPU probe. The emulator includes a break control circuit that requests a break interrupt to the processor.

0012

[Operation] According to the above-mentioned means, it is possible to incorporate a debugging system program into a user program to be debugged, and to have the user processor installed in the target system execute such a user program. This eliminates the need to install an evaluation chip, which makes it possible to reduce the price of the emulator, simplify the configuration, and achieve versatility of the emulator. Also, using such an emulator in software debugging allows software debugging of a target system to be performed more inexpensively. The use of a real chip in software debugging as described above allows software debugging of a target system to be performed faithfully.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an emulation system which is an embodiment of the present invention.

The emulation system shown in FIG. 1 consists of an emulator 1 and a host system 2. The emulator 1 can be connected to a desired target system 4 via a user interface 3, and can be connected via a system interface 5. The host computer 7 of the host system 2 can be coupled to the host computer 7 .

[0015] Here, the conventional emulator is equipped with an evaluation chip having the same control function as the user processor 6 for controlling the target system 4, so that it can be used to control the target system 4 through the user interface 3 while executing the user program. The emulator 1 is configured to act on behalf of the target system 4 and control the internals of the emulator 1 by executing a system program when the execution of the user program is stopped.The emulator 1 of this embodiment does not include such an evaluation processor. Not installed. That is, in this embodiment, the system program for debugging is incorporated into the user program to be debugged, and such a user program is executed by the user processor 6 installed in the target system 4, thereby debugging the program in the emulator. Evaluation chip is omitted.

The emulator 1 of this embodiment has a shared bus 1.
2 is formed, and this shared bus 12 includes, in addition to the user interface 3 and system interface 5,
The user processor 6 included in the target system 4 monitors the control state while executing the user program, and when the state reaches a preset state, executes the user program execution operation (emulation operation). A break control circuit 9 for breaking, a real-time trace circuit 10 for sequentially tracing and storing data, addresses, and control information given to the shared bus 12 when the user processor 6 is executing a user program are coupled to each other. be done.

The system interface 5 includes the shared memory 15 and an interface circuit 14. The shared memory 15 is readable and writable by the host computer 7 and the user processor 6. Further, the host computer 7 can control the break control circuit 9 and the trace circuit 10 (setting break and trace conditions) via the interface circuit 14. The host system 2 includes a host computer 7 as a general-purpose computer, a main memory 30 for storing host programs and various data, an input device 31 such as a keyboard, a display device 32 such as a CRT display device, and a magnetic It has an auxiliary storage device 34 such as a disk device. The host computer 7 runs a debugging program that allows the emulator 1 and thus the target system 4 to be controlled via the system interface 5 and the user interface 3.

The target system 4 is configured as follows.

The target system 4 is equipped with a user processor 6, which is an ASIC, a target memory 8, and various other necessary hardware. The target memory 8 has a storage area 8A for a user program for realizing a user application, a storage area 8B for user data, and a storage area 8C for a debugging system program. In a conventional emulator, the system program for debug control is stored in the system memory located within the emulator, but in this embodiment, the system program for debugging is stored in the user program in which the system program for debugging is embedded. , such a system program is stored in a predetermined storage area 8C of the target memory 8 in order to be executed by a user processor installed in the target system. With this configuration, when a user program is executed by the user processor 6 and a break condition set in advance in the break control circuit 9 is satisfied, the user program is executed in response to a break interrupt from the break control circuit 9. is transferred from execution to system program execution.

The emulator 1 and the target system 4 are connected by an interface cable 26, and the tip of the interface cable 26 has a cable as shown in FIG.
As shown in FIG. 2, a CPU probe 24 is provided that can detect the state of the bus 11 of the user processor 6 connected to the target system 4. This CPU probe 24 has a
A plurality of pins 25 are provided which can be coupled to the original IC socket 22 of the user processor 6, thereby allowing the IC to
It can be coupled to the socket 22. And this CPU
An IC socket 23 equivalent to the above IC socket 22 is provided on the upper surface of the probe 24, and the user processor 6 can be connected to it. All leads of user processor 6 are connected to I through pin 25 of CPU probe 24.
It is electrically connected to the C socket 22 and also to the user interface 3 via the interface cable 26. Thereby, in a state where the user processor 6 is coupled to the target system 4, the processor 6 is connected to the target system 4.
The state of the bus 11 can be detected by the break control circuit 9 and the trace circuit 10.

FIG. 3 shows the flow of the system program in the target system 4, particularly the series of flows from the initial state to the interruption of emulation execution (user program execution).

After the reset start (step 45), the target system 4 starts executing the system program, but the host computer 7 stores the packets (PA
A waiting state is entered until a predetermined command (instruction) is written to CKET (step 46). In this state, a debug program is activated on the host system 7 side, thereby making it possible to execute various debug commands. For example, when a memory dump command is input from the input device 31 such as a keyboard, the host computer 7
A memory read command is set in CKET. When a command is set in PACKET in this way, the target system 4, which has been in a waiting state until then, determines whether the command set in PACKET is an execution command of a user program (
Step 46, Step 47). For example, the above memory dump instruction is not a user program execution instruction, so
The determination in step 47 is "N", so that the target system 4 executes the memory read which is the command set in the PACKET (step 48). By executing this memory read instruction,
The read data is written to the shared memory 15. The host computer 7 then edits the information thus written into the shared memory 15 and displays it on the display device 32 such as a CRT display device. In the above explanation, the case where a memory dump command is given from the input device 31 is taken as an example, but the case where other debugging commands other than the user program execution command, which will be described later, is given from the input device 31 is also described. The command can be executed in the same manner as above.

Next, a case where emulation is executed and the execution is interrupted will be described.

Break conditions can be set from the input device 31. That is, when a desired break condition is input from the input device 31, the break condition is set in the break control circuit 9 by the host computer 7. After the break condition is set in this way, the host computer 7 stores the PACK in the shared memory 15.
When a user program execution command is set in ET, the target system 4, which has been in a waiting state until then, determines whether the command set in PACKET is a user program execution command (step 46, step 47), if it is determined that the command is a user program execution command (Y), execution of the user program is started in the user processor 6 (step 49). During execution of such a user program, the break control circuit 9 monitors the state of the processor bus 11 via the user interface 3, and if the state of the bus 11 matches a preset break condition, a break control circuit 9 executes a break. Setting the register BFLG to "1" indicates that a break state has been reached and requests the user processor 6 to issue a break interrupt.

When the break interrupt is accepted by the user processor 6, the execution of the user program is interrupted and the process proceeds to the interrupt processing routine of the system program (step 41). In this interrupt processing routine, in order to determine whether the above-mentioned interrupt is related to an interrupt request from the break control circuit 9 or an interrupt on the user system during user program execution (referred to as a user interrupt), the above-mentioned break control circuit Break register BFL at 9
The contents of G are checked. Such a check is possible depending on whether "1" is set in the break register BFLG. That is, the user processor 6, which is currently executing the system program, sets the break register BFLG in the break control circuit 9 to "
1" is set (step 42), and in this determination, break register BFLG is set.
If it is determined that ``1'' is set (Y), the process proceeds to a predetermined break process regarding the break interrupt (step 44). Although not particularly limited, the break processing herein includes processing for writing the state at the time of the break into the shared memory 15. Thereby, the host system 2 can read the information written in the shared memory 15 and display it on the display device 32.

In addition, in the determination at step 42, the break register BFLG is not set to "1" (
In other words, if the break register BFLG is set to "0", the above interrupt request is treated as a user interrupt rather than a break interrupt, so the user program A transition is made to a predetermined interrupt handling routine (step 43).
).

According to the embodiment described above, the following effects can be obtained.

(1) Since the system program for debugging is incorporated into the user program to be debugged, and such a user program is executed by the user processor 6 installed in the target system 4, the emulator 1 It is not necessary to mount an evaluation chip on the emulator 1, thereby making it possible to make the emulator 1 smaller and lighter, and also to reduce the price.

(2) Due to the effect of (1) above, even when targeting ASICs that have a common CPU core and are developed in various types, there is no need to provide a dedicated emulator for each type, and the same Since it is possible to use an emulator with various configurations, the versatility of the emulator is achieved, and the development period of the emulator can be significantly shortened.Furthermore, by using such an inexpensive emulator in software debugging, the software of the target system can be improved. Debugging can be done more cheaply.

(3) As mentioned above, by using a real chip as a user processor in software debugging, there is no difference in operation timing etc. from the actual system, and therefore, compared to the case where an evaluation chip is used, Software debugging of the target system can be performed faithfully.

(4) A CPU that can be connected to the IC socket 22 of the target system 4 and that can detect the state of the bus 11 of the user processor 6 when the user processor 6 is connected to the target system 4. By using the probe 24, the state of the user processor bus 11 can be detected without making any special modifications to the user system 4.

(5) When the break interrupt is accepted by the user processor 6, the execution of the user program is interrupted and the transition is made to the interrupt handling routine of the system program (step 41). Based on the contents of the break register BFLG in the break control circuit 9, it is determined whether the interrupt request is related to an interrupt request from the control circuit 9 or a user interrupt. In such a determination, only if it is determined that the break register BFLG is set to "1" (Y), the transition is made to the predetermined break processing for the break interrupt. It is possible to distinguish between user interrupts and break interrupts without providing a dedicated terminal.

Although the invention made by the present inventor has been specifically explained based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. stomach.

For example, the peripheral devices included in the host system are not limited to those in the above embodiments, and an emulation system can be constructed using any appropriate host system. The host system may also be an engineering workstation.

[0035] The above explanation mainly describes the invention made by the present inventor, which is the field of application in which it is based.
Although software debugging targeting an IC has been described, the present invention is not limited thereto.
It can be applied to software debugging of various user systems equipped with microcomputers.

The present invention can be applied on the condition that at least a user system exists.

[0037]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, since the system program for debugging is incorporated into the user program to be debugged, and such a user program is executed by the user processor installed in the target system, the system program for evaluation by the emulator is It is not necessary to mount a chip, which makes it possible to lower the price of the emulator, simplify the configuration, and achieve versatility of the emulator. Further, by using such an emulator in software debugging, software debugging of a target system can be performed at a lower cost. By using the actual chip in software debugging as described above, software debugging of the target system can be performed faithfully.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of an emulation system according to an embodiment of the present invention.

FIG. 2 is a perspective view showing a CPU probe for coupling the emulator shown in FIG. 1 with a target system.

FIG. 3 is a flowchart of emulation operation.

[Explanation of symbols]

1 Emulator 2 Host system 3 User interface 4 Target system 5 System interface 6 User processor 7. Host computer 8 Target memory 9 Break control circuit 10 Trace circuit 11 User processor bus 12 Shared bus 14 Interface circuit 15 Shared memory 22 CPU socket 23 CPU socket 24 CPU probe 25 pin 26 Interface cable 30 Main memory 31 Input device 32 Display device 34 Auxiliary storage device

Claims (4)

[Claims] Claim 1: A system program for debugging and a user program are executed by a user processor as a real chip to be installed in a target system, and the state of the bus of the user processor at that time is monitored by an emulator. A debugging method that allows programs to be debugged. [Claim 2] The debugging system program includes:
a step of determining a break interrupt request made to the user processor when the execution state of the user program matches a predetermined break condition and an interrupt request on the user system during execution of the user program; and the determination in this step. 2. The debugging method according to claim 1, further comprising the step of transitioning to corresponding predetermined processing routines based on the respective predetermined processing routines. 3. A CPU probe that is connectable to an IC socket of a target system and that is capable of detecting information to be input/output by the user processor when the user processor is connected to the target system;
A user interface is connected to the CPU probe via an interface cable, and the bus state of the user processor is monitored through this user interface, and when the bus state matches a predetermined break condition, the user interface is connected to the CPU probe. An emulator that includes a break control circuit that requests a break interrupt. 4. The emulator according to claim 3, further comprising an information area that holds an interrupt factor for causing the user processor to transition from a user program execution state to a system program execution state in response to an interrupt request from the break control circuit.