JPH0427170Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention is a flat pack type IC chip package that includes an IC chip and is directly flattened onto a conductive pattern on a substrate on which passive elements are mounted or formed, especially for high-speed and high-frequency areas. The present invention relates to an IC chip package that realizes the application of this technology.

The structure of semiconductor packages can be roughly divided into four types: ceramic, metal, glass, and plastic. However, as active devices have progressed from transistors to ICs, LSIs, and even VLSIs, package structures have undergone rapid changes and cannot be classified simply into the four types mentioned above, and are made up of a variety of materials and structures. It's getting complicated. However, when classified based on shape, transistor external type packages (TO type), Single-In
-Line packages (SIP type), dual-in-line packages (DIP type), flat pack type packages, and tape carrier type packages.

The TO type package is a metal hermetic package that is the same as a transistor, with many leads attached, and has features such as strong metal cap welding strength and easy control of the enclosed atmosphere. However, these days, packages tend to be less used because they are expensive, and packages with a large number of leads are complicated to mount on a board.

A SIP type package has leads arranged on one side of the package, and a DIP type package has leads arranged on both sides of the package. SIP type and DIP type packages are suitable for mass production, as they enable continuous automation of chip mounting and bonding, as well as large batch processing, making it possible to obtain inexpensive packages, including in terms of materials.
Recently, not only ICs for consumer use but also ICs for communication industry,
It is also widely used in the LSI field. however,
Since SIP type and DIP type packages use lead frames, the internal leads are long, making them difficult to manufacture and handle, and they have drawbacks such as deterioration of electrical high frequency characteristics.

Tape carrier type packages are made by continuously incorporating chips into polyimide tape, coating them with resin and cutting them into individual chips, which are flattened onto the conductive surface of a circuit board.

A flat pack type package is a small package with terminals on both sides or in four directions.
This is a type that is directly flattened onto the conductor pattern without being inserted into a hole in the circuit board. Unlike SIP and DIP types, the package area is less than half that of conventional DIPs with the same number of pins. In addition, since the leads come out in four directions, the length of the internal leads is shortened, so it has the advantage of being able to reduce the effects of parasitic elements such as inductance and capacitance. Applied to circuits.

On the other hand, the operating range of electric circuits tends to become faster and wider every year, and for example, amplifiers with a GHz band, digital circuits that operate at several Gb/s, and the like are becoming necessary. Correspondingly, IC technology is progressing year by year, and high-speed digital ICs and high-frequency analog ICs using, for example, gallium arsenide field effect transistors are being realized. Therefore,
There is an increasing need for IC packages that are compatible with such high-speed ICs, but it has been extremely difficult to fully utilize the capabilities of such high-speed ICs with conventional IC packages.

Figure 1 is a plan view of a conventional flat pack type package suitable for relatively high-speed operation, and Figure 2 is a sectional view of the flat pack type package shown in Figure 1, showing an example in which an IC chip is mounted. There are, but
Here, we will explain the limitations of the conventional technology by taking as an example the case where such a package is equipped with a high-speed IC and used in a high-speed circuit.

In FIG. 1, 1101 is a lead, and the lead is usually gold-plated. 1102 is a package body, which is generally made of ceramic. A signal conductor pattern 1103 is electrically connected to the lead.
The width of this signal conductor pattern is usually about 400 μm, and it is formed using printed wiring technology, and the surface is gold-plated. The signal conductor pattern length is kept as short as possible. 1104
A gold land portion for mounting an IC chip is formed of a printed wiring pattern similar to the signal conductor pattern 1103, and the surface is plated with gold.

FIG. 2 is a cross-sectional view of the package shown in FIG. 1, in which 2101 is a lead, 2102 is a package body, 2103 is a signal conductor pattern,
2104 is a gold land portion for mounting an IC chip.
2105 is a heat dissipation stud, which includes a gold land portion 2104 for mounting an IC chip and a through hole 2110.
It is electrically conductive. This heat dissipation stud 21
05, the heat generated in the IC chip is dissipated through the circuit board on which it is mounted. 2106 is IC
A chip, for example a GaAs-IC chip.
A bonding wire 2107 connects the IC chip 2106 and the signal conductor pattern 2103. A package cap 2108 is sealed to the package body 2103 using metal solder or glass solder. In IC chip packages with this type of structure, the signal conductor pattern is made as short as possible to reduce the effects of parasitic elements, but as the operating speed (frequency) increases, the effects of these parasitic elements become negligible. It disappears.
In addition, when a signal conductor pattern is viewed as a distributed constant line, the characteristic impedance changes with frequency, so when used as a package for high-frequency, high-speed IC chips, impedance matching with other circuits at the input and output ends is required for signal transmission. It was impossible to do so. Therefore, even if an attempt is made to limit the operating speed of the IC and use it as an IC chip package for a high-speed IC with an operating speed of 1 Gb/s or higher, for example, good operation will not be obtained.

The present invention was developed in view of the above-mentioned drawbacks of conventional IC chip packages. Specifically, (1) the signal conductor pattern is made into a distributed constant line with a constant characteristic impedance by using a coplanar strip line structure in which the ground conductor pattern is placed on the same plane as the signal conductor pattern in the IC chip; 2) A ground conductor pattern and a heat dissipation stud are provided on the back side of the IC chip package, which are electrically connected to the ground conductor pattern on the front surface, and this heat dissipation stud is used for mounting on the circuit board and connecting to the ground conductor on the circuit board. (3) The signal conductor pattern at the signal input/output terminal with the outside can be made into a distributed constant line by using a microstrip that sandwiches the dielectric material between the signal conductor pattern and the ground conductor pattern. (4) By forming the signal conductor pattern continuously on the signal conductor pattern of the coplanar strip line structure, it is possible to further match the characteristic impedance with other circuits, and By creating a structure that allows direct connection to the signal line inside the package without leads, the parasitic element effect can be significantly reduced, and as described in (1) above,
The purpose is to provide an IC chip package that can improve IC operating speed through the effects of (2), (3), and (4), is easy to manufacture, is inexpensive, and does not increase the number of external connection points. There is.

According to the present invention, a flat pack type IC
In a chip package, the package main body is composed of a dielectric substrate stacked in two layers, a first layer and a second layer, and a plurality of signal conductor patterns are provided on the surface of the first layer dielectric substrate. By providing a continuous ground conductor pattern on the surface portion between the conductor patterns excluding the outer periphery of the package, each signal conductor pattern has a predetermined constant characteristic impedance Z ₀ in the portion excluding the outer periphery of the package. By using a coplanar strip line, and further providing a continuous ground conductor pattern immediately below the outer periphery of the package and between the first and second dielectric substrates, each of the signal conductors at the outer periphery of the package is The pattern is a microstrip line with a constant characteristic impedance Z ₀ , a continuous ground conductor pattern is provided on the back surface of the second dielectric layer, and a plurality of through holes are provided between each ground conductor pattern and on the back surface of the package for heat dissipation. The IC chip package is electrically connected by studs, and the signal conductor patterns and the heat dissipation studs on the outer periphery of the package are used as electrical connection parts when the IC chip package is mounted on a circuit board. A package for an IC chip is obtained.

FIG. 3 shows a plan view of the IC chip package according to the present invention.

In FIG. 3, 3101 is a ground conductor pattern, 3102 is a package body, 3103 is a signal conductor pattern, 3104 is a through hole for the ground conductor, and 3105 is a heat dissipation stud on the back side. Ground conductor pattern 3101 and signal conductor pattern 31
03 can be formed using either thin film or thick film techniques. A signal conductor pattern 3103 from point A to point B in the figure forms a coplanar distributed constant line by arranging ground conductor patterns 3101 on both sides. Its characteristic impedance is the signal conductor pattern 31
When the line width of 03 is W and the distance between the ground conductor pattern 3102 and the signal conductor pattern 3103 is S, it is determined as a value approximately proportional to S/W.
Signal conductor pattern 3103 from point B to point C
is directly below the signal conductor pattern 3103 across the dielectric substrate of the package (package body 310
A ground conductor pattern 4111 (the fourth intermediate layer)
A microstrip type distributed constant line is constructed by arranging the lines shown in the figure). Ground conductor pattern 3101 formed on the surface and package body 3102
The middle layer and the ground conductor patterns 4111, 4211 (FIG. 4) formed in the bottom layer are electrically connected through the ground conductor through hole 3104. FIG. 7 shows a plan view of the intermediate layer of the package body 3102. In the package body 3102,
The IC chip package of the present invention uses an ordinary ceramic substrate and has a multilayer structure in which two layers are stacked on top of each other. Since ground conductor patterns are also provided on the middle and bottom layers of the ceramic substrate, the thickness of the ceramic substrate affects the value of the characteristic impedance of the line. Therefore, this thickness must be set to an appropriate value in consideration of the required characteristic impedance value, mechanical strength, etc. of the line.

The IC chip is usually mounted on a heat dissipation stud 3105 attached to the central part of the back side of the package. This heat dissipation stud 3105 connects all the ground conductor patterns 3101, 4111, 421.
It is electrically connected to 1. Note that, although the signal conductor patterns are naturally separated from each other, the ground conductor pattern 3101 on the surface is integrated at the center. Further, the dotted line in the figure indicates the position when the package cap 4108 is mounted as shown in FIG.

FIG. 4 shows a cross section taken along line XX' in FIG. 3 in the IC chip package of the present invention. 4101, 4111, 4211 are ground conductor patterns, 4102 is the package body, 410
3 is a signal conductor pattern, 4104 is a through hole for a ground conductor, 4105 is a stud for heat dissipation, 410
6 is an IC chip, 4107 is a bonding wire,
4108 is a package cap. The ground conductor pattern 4101 is formed not only on the surface of the package body 4102 but also on the middle layer 4111, the bottom layer 4211, and the wall surface of the package body 4102 having a multilayer structure. IC chip 410
6 is mounted on a heat dissipation stud 4105 that is electrically connected to a ground conductor pattern 4101. This IC chip 4106 and signal conductor pattern 410
3 and the connection with the ground conductor pattern 4101 is as follows:
This is done by bonding wire 4107.

A signal conductor pattern 4103 between A and B in the figure is a coplanar distributed constant line. Signal conductor pattern 4 between A and B formed into a distributed constant line
As mentioned above, the characteristic impedance of the signal conductor pattern 4103 is determined by the distance S between the signal conductor pattern 4103 and the ground conductor pattern 4101 on the surface and the signal conductor pattern 4103.
It is determined by the ratio of the line width W to the line width W. Therefore, the fifth
As shown in the figure, the value of the distance S between the signal conductor pattern 5103 and the ground conductor pattern 5101 is set to S/
By continuously decreasing the value of W while keeping it constant, the line width W can be made as thin as possible while maintaining a constant characteristic impedance, allowing signals to reach the very near end of a small IC chip. A conductive pattern can be formed.

Signal conductor pattern 410 between B and C in FIG.
3 is a microstrip type distributed constant line. The characteristic impedance of the signal conductor pattern 4103 between B and C that has been made into a distributed constant line is:
It is determined by the ratio between the line width W of the signal conductor pattern 4103 and the thickness of the package dielectric substrate sandwiched between the signal conductor pattern 4103 and the ground conductor pattern 4111 formed in the intermediate layer of the package body 4102. Therefore, in order to keep the characteristic impedance constant, the line width W of the signal conductor pattern 4103 is also constant.

The signal conductor pattern 4103 between A and C is an IC
It is formed continuously from the proximal end of the chip to the end surface of the package body 4102. However, since the signal conductor pattern 4103 between A and B is a distributed constant line, the ground conductor pattern 4101 on the surface is formed from the center of the package to B in the figure, and this part is made into a coplanar stripline. A ground conductor pattern 4111 is formed from the end face of the package to B, and the signal conductor pattern 4103 between B and C has a microstripline structure. As a result, the ground conductor patterns 4101 and 41 on the package surface and the intermediate layer
11 do not overlap each other, and between A and B,
The characteristic impedance of the signal conductor pattern 4103 between B and C is kept constant and equal. In addition,
The ground conductor patterns of each layer are electrically connected to each other by a ground conductor through hole 4104.

With this configuration, it is possible to form a signal conductor pattern with a constant characteristic impedance up to the very near end of the IC chip, so that the bonding wire 410
The length of 7 is also shortened, and the signal conductor pattern at the signal connection part with the external circuit is formed with sufficient width, making it easy and sufficient to connect with the external circuit, and furthermore, it can be used with conventional IC packages. Comparatively, it is easier to downsize.

The heat dissipation stud 4105 is formed using a metal material with excellent thermal conductivity, such as oxygen-free copper. This heat dissipation stud 4105 has a structure in which its end face is exposed on the surface of the IC package, and has ground conductor patterns 4101, 4111,
It is electrically connected to 4211. This heat dissipation stud 4
An IC chip is mounted on the 105.

When mounting the package of the present invention on a circuit board, the signal conductor pattern on the circuit board and the signal conductor pattern 4103 may be directly connected by soldering or bonding wire. In addition,
At this time, the characteristic impedance of the signal conductor pattern on the circuit board is the same as the characteristic impedance of the signal conductor pattern in the package of the present invention.
It is assumed that the pattern on the circuit board has been designed. The connection between the ground conductor pattern of the IC package and the ground pattern of the circuit board is made using heat dissipation stud 4.
This is done by soldering 105 to the ground pattern of the circuit board, thereby providing sufficient grounding even at high frequencies. These allow the IC chip and the pattern on the circuit board to be connected with almost no parasitic element effects such as inductors and capacitances. Further, it can be easily mounted on a circuit board. The package cap 4108 is
For example, it is formed using a ceramic material, and the sealing to the package body 4102 is performed using a non-conductive material such as glass solder.

Such a configuration virtually eliminates the impedance mismatch that occurs in conventional IC chip packages, significantly reduces the effects of parasitic elements, and provides sufficient high-frequency grounding. Therefore, for example, an IC with an operating speed of 1 Gb/s or more
It becomes possible to easily mount and operate the chip. Furthermore, since the IC chip package of the present invention can be constructed from only a multilayered package body, a package cap, and a heat dissipation stud, it is easy to manufacture and relatively inexpensive. Furthermore, the size of the package can be easily reduced and high-density packaging can be achieved.

In the explanations so far, we have described an embodiment of the package that does not use leads for connection with external circuits, but the gist of the present invention is not limited to this. For this purpose, it may be provided with leads as shown in FIG. 6, for example. Further, although ceramic material is used as an example of the material of the package, the present invention is not limited to this, and for example, beryllium material or plastic material may be used.

[Brief explanation of the drawing]

Figure 1 is a plan view of a conventional IC chip package, and Figure 2 is a view of the conventional IC chip package shown in Figure 1.
FIG. 3 is a diagram showing a cross section of an IC chip package.
FIG. 3 is a diagram for explaining the structure of the IC chip package of the present invention, and FIG. 4 is a cross-sectional view taken along line X-X' in FIG. Figure 5 shows
It is a figure shown in order to explain the effect of this invention.
FIG. 6 shows a plan view of an embodiment in which the IC chip package of the present invention is provided with leads for connection to an external circuit. FIG. 7 is a plan view showing the middle layer of the package body. The symbols in the figure indicate the following, respectively. 1101,2101...Reed, 1102,2
102, 3102, 4102...Package body, 1103, 2106, 3103, 4103,
5103...Signal conductor pattern, 1104,2
104...Gold land part for mounting IC chip, 310
4,4104...Through hole for ground conductor, 21
05,3105,4105... Heat dissipation stud, 2
106,4106...IC chip, 2107,4
107... Bonding wire, 2108, 41
08...Package cap, 3101,410
1,4111,4211,5101...Ground conductor pattern.

Claims (1)

[Scope of utility model registration request] In a flat pack type IC chip package, the package body is composed of dielectric substrates stacked on a first layer and a second layer, and multiple signal conductor patterns are formed on the surface of the first layer dielectric substrate. By providing a continuous ground conductor pattern on the surface sandwiched between these signal conductor patterns except for the outer periphery of the package, each signal conductor pattern has a predetermined constant characteristic impedance in the part other than the outer periphery of the package. Z ₀
Each of the signal conductor patterns on the outer periphery of the package is formed by forming a coplanar strip line, and further providing a continuous ground conductor pattern immediately below the outer periphery of the package and between the first and second dielectric substrates. Let be a microstrip line with constant characteristic impedance Z ₀ ,
A continuous ground conductor pattern is provided on the back surface of the second dielectric layer, and each ground conductor pattern is electrically connected by a plurality of through holes and a heat dissipation stud provided on the back surface of the package. 1. A package for an IC chip, characterized in that the signal conductor patterns and the heat dissipation studs on the outer periphery of the package are used as electrical connection parts when the chip is mounted on a circuit board.