JPH04279033A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To provide for method for producing a TFT wherein fluctuation of characteristics, especially of ON current, is suppressed. CONSTITUTION:A semiconductor layer 2 is subjected to patterning on an insulation substrate 21 and then the semiconductor layer 2 is applied, thus forming a gate insulation film 3. A gate electrode 4 with a plurality of gate electrode portions 4a-c is formed on a gate insulation film 3 and then impurity ions are implanted to the semiconductor layer 2 with the gate electrode as a mask, thus forming low-impurity concentration regions 11a and 11b in self-aligned manner. Then, a resist 5 is formed among the gate electrode portions 4a-c and impurity ions are implanted into the semiconductor layer 2 with the gate electrode portion and the resist 5 as a mask, thus forming high-impurity concentration regions 10a and 10b at both outer sides of the gate electrode 4 in a self-aligned manner.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to thin film transistors (hereinafter referred to as "TFT") used as switching elements in liquid crystal display devices, loads in memory cells of static RAM, etc.
).

0002

2. Description of the Related Art TFTs are required to have low leakage current. For example, switching TFTs used in active matrix liquid crystal display devices are required to have low leakage current characteristics in order to sufficiently retain the charge accumulated in electrodes that sandwich a liquid crystal layer. Also, static RA
The TFT used for M is required to have low leakage current characteristics in order to reduce current consumption.

In order to obtain such low leakage current characteristics, a TFT as shown in FIG. 8 is used. This TF
T is NMOS type, LDD (Lightly
It has a Diffused Drain structure. A channel layer 9 and a high impurity concentration region (N+
region) 10a, 10b and low impurity concentration region (N- region)
11a and 11b are formed. A gate electrode 4 is provided above the channel layer 9 with a gate insulating film 3 in between. An interlayer insulating film 6 is formed on the gate electrode 4 and the gate insulating film 3, and contact holes 7a and 7b are formed through the gate insulating film 3 and the interlayer insulating film 6 on the high impurity concentration regions 10a and 10b, respectively. There is. Electrodes 8 made of Al-Si are provided in the high impurity concentration regions 10a and 10b.
a and 8b are electrically connected via contact holes 7a and 7b, respectively.

FIG. 3 shows the manufacturing process of the thin film transistor shown in FIG.
~ Shown in Figure 7. First, polycrystalline silicon is deposited on an insulating substrate 1 to a thickness of 50 to 100 nm. This polycrystalline silicon layer is patterned by photolithography and dry etching to form semiconductor layer 2 (FIG. 3).

Next, a gate insulating film 3 made of silicon oxide is formed to a thickness of 50 to 100 nm over the entire surface of the substrate 1 (FIG. 4). The gate insulating film 3 is formed by the CVD method or by oxidizing the upper surface of the semiconductor layer 2. Further, a gate electrode 4 is patterned on the insulating film 3 (FIG. 5). The width of the gate electrode 4 is approximately 6 μm. Gate electrode 4 is n
Made of + type polycrystalline silicon, its film thickness is approximately 300 nm.
It is. Using this gate electrode 4 as a mask, a 5×10 13 cm
The impurity is doped at a low concentration of m-2 (FIG. 6). Examples of impurities include P (phosphorus) and As (arsenic).

Next, a resist 5 is patterned to cover the gate electrode 4 and the sides of the gate electrode 4. Using this resist 5 as a mask, 1 to 5 x 101
Impurities are doped at a high concentration of 5 cm-2. Impurities that can be used include P (phosphorus), As (arsenic), etc., as described above. As a result, high impurity concentration regions 10a, 10b
, and low impurity concentration regions 11a and 11b are formed (
Figure 7). In this example, the low impurity concentration regions 11a and 11b are formed on both sides of the gate electrode 4, but as shown in FIG. 10, the low impurity concentration region 11 is formed only on one side of the gate electrode 4. TFTs of the configuration are also known.

Next, the resist 5 is removed, and an interlayer insulating film 6 made of silicon oxide is formed to a thickness of 600 nm over the entire surface of the substrate 1 by CVD. Next, in order to activate the doped impurities, this substrate is heat treated at 950° C. for 30 minutes in a nitrogen atmosphere, for example. Furthermore,
Contact holes 7a and 7b are formed in the interlayer insulating film 6 on the high impurity concentration regions 10a and 10b, respectively, and electrodes 8a and 7b are formed on the contact holes 7a and 7b, respectively.
, 8b are formed. (Figure 8).

[0008]

[Problems to be Solved by the Invention] When a TFT is manufactured by such a manufacturing method, one of the low impurity concentration regions 1 is misaligned due to the positional shift of the pattern of the resist 5, as shown in FIG.
0a length L1 and the other low impurity concentration region 11b
The length L2 is not constant. If the lengths of L1 and L2 are not constant, the lengths of high impurity concentration regions 10a and 10b are also not constant. In this way, high impurity concentration regions 10a and 10
Since b is formed in a non-self-aligned manner with respect to the gate electrode 4, there is a problem that variations in characteristics of the obtained TFTs, especially variations in on-current, become large.

The present invention solves these problems, and an object of the present invention is to provide a TF with small variation in characteristics.
An object of the present invention is to provide a method for manufacturing T.

0010

[Means for Solving the Problems] A method for manufacturing a thin film transistor of the present invention includes a step of patterning a semiconductor layer on a substrate having an insulating surface, a step of forming an insulating film covering the semiconductor layer, and a step of patterning a semiconductor layer on a substrate having an insulating surface. A process of forming a gate electrode having a plurality of gate electrode parts on the film, and implanting impurity ions into the semiconductor layer using the gate electrode as a mask, and forming a low impurity concentration region between the gate electrode parts in a self-aligned manner. a step of forming a resist between the gate electrode portion, and a step of implanting impurity ions into the semiconductor layer using the gate electrode portion and the resist as a mask to form a high impurity concentration region outside the gate electrode. The above-mentioned object is achieved.

[0011] Alternatively, the semiconductor layer may be made of polycrystalline silicon.

0012

According to the TFT manufacturing method of the present invention, the gate electrode is composed of a plurality of gate electrode parts. By implanting ions into the semiconductor layer using these gate electrode parts as a mask, a low impurity concentration region is formed between the gate electrode parts in a self-aligned manner. Furthermore, by forming a resist between the gate electrode parts and implanting impurity ions using the gate electrode part and the resist as a mask, a high impurity concentration region is formed in a self-aligned manner with respect to the gate electrode.

[0013]

[Examples] Examples of the present invention will be described below. FIGS. 1(a) to 1(c) show the manufacturing process of the TFT of the present invention. Further, a plan view of the TFT shown in FIG. 1(c) is shown in FIG. Figure 1
The TFT shown in (c) is an NMOS type. Figure 1(c)
), channel layers 9a, 9 are formed on a part of a semiconductor layer 2 such as a polycrystalline silicon layer formed on an insulating substrate 1.
b, 9c and low impurity concentration regions (N− regions) 11a, 11
b are formed alternately. Low impurity concentration region 11a
, 11b are high impurity concentration regions (N+ regions).
10a and 10b are formed. A gate electrode 4 is provided on the semiconductor layer 2 with a gate insulating film 3 in between. The gate electrode 4 has three gate electrode parts 4a arranged at equal intervals,
It is composed of 4b and 4c. The width of each gate electrode portion is about 2 μm, and the sum of these widths is equal to the width of the gate electrode 4 of the conventional TFT shown in FIG. 8 described above. The above-mentioned channel layers 9a, 9b, 9c are connected to each gate electrode portion 4.
A, 4b, and 4c are formed in a self-aligning manner as described later.

An interlayer insulating film 6 is formed on the gate electrode 4 and gate insulating film 3, and has high impurity concentration regions 10a, 10.
Contact holes 7a and 7b are formed through the gate insulating film 3 and the interlayer insulating film 6 on the upper surface of the contact hole 7a and the interlayer insulating film 6, respectively. Electrodes 8a and 8b made of Al-Si are electrically connected to the high impurity concentration regions 10a and 10b via contact holes 7a and 7b, respectively.

A method for manufacturing the TFT shown in FIG. 1(c) will be explained. First, polycrystalline silicon is deposited on an insulating substrate 1.
Deposited to a thickness of 0-100 nm. This polycrystalline silicon layer is patterned by photolithography and dry etching to form semiconductor layer 2.

Next, a gate insulating film 3 made of silicon oxide is formed over the entire surface of the substrate 1 to a thickness of 50 to 100 nm. The gate insulating film 3 is formed by the CVD method or by oxidizing the upper surface of the semiconductor layer 2. Furthermore, a gate electrode 4 is patterned on the insulating film 3. The gate electrode 4 consisting of three gate electrode parts 4a, 4b, and 4c is made of n+ type polycrystalline silicon and has a film thickness of about 300 nm. Using this gate electrode 4 as a mask, impurities are doped at a low concentration of 5×10 13 cm −2 by ion implantation. Examples of impurities include P (phosphorus) and As (arsenic). As a result, the channel layer 9
a, 9b, 9c, and low impurity concentration regions 11a, 11b
is formed in a self-aligned manner with respect to the gate electrode 4 (Fig. 1
(a)).

Next, a resist 5 is patterned between each gate electrode portion 4a, 4b, and 4c. This resist 5
Using the gate electrode portions 4a and 4c as masks, impurities are doped at a high concentration of 1 to 5×10 15 cm −2 into the portions that will become the high impurity concentration regions 10 a and 10 b by ion implantation. As the impurities that can be used, as mentioned above,
Examples include P (phosphorus) and As (arsenic). Thereby, the high impurity concentration regions 10a and 10b are formed in a self-aligned manner with respect to the gate electrode 4 (FIG. 1(b)). The resist 5 only needs to be formed to cover the portion between the gate electrode portions 4a and 4b and between the gate electrode portions 4b and 4c, and since the width of the gate electrode portions 4a and 4c is approximately 2 μm, the width is ±1 μm. Even if the pattern of the resist 5 is misaligned within the range, the high impurity concentration regions 10a and 10b can be formed in a self-aligned manner with respect to the gate electrode 4.

Next, the resist 5 is removed, and an interlayer insulating film 6 made of silicon oxide is formed to a thickness of 600 nm over the entire surface of the substrate 1 by CVD. Next, in order to activate the doped impurities, this substrate is heat treated at 950° C. for 30 minutes in a nitrogen atmosphere, for example. Furthermore,
Contact holes 7a and 7b are formed in the interlayer insulating film 6 on the high impurity concentration regions 10a and 10b, respectively, and electrodes 8a and 7b are formed on the contact holes 7a and 7b, respectively.
, 8b are formed. (Figure 1(c)).

According to the TFT manufacturing method of this embodiment, since the high impurity concentration regions 10a and 10b are formed in self-alignment with the gate electrode 4, a TFT with small variations in characteristics can be obtained.

In this embodiment, the gate electrode 4 is composed of three gate electrode parts, but it may be composed of more gate electrode parts.

[0021]

According to the method for manufacturing a thin film transistor of the present invention, the high impurity concentration region formed on the side of the channel layer below the gate electrode is formed in self-alignment with the gate electrode. A thin film transistor with small variation in characteristics can be obtained.

[Brief explanation of the drawing]

FIGS. 1A to 1C are process diagrams showing one embodiment of the method for manufacturing a thin film transistor of the present invention.

FIG. 2 is a plan view of the thin film transistor of FIG. 1(c).

FIG. 3 is a process diagram showing a conventional thin film transistor manufacturing method.

FIG. 4 is a process diagram showing a conventional method for manufacturing a thin film transistor.

FIG. 5 is a process diagram showing a conventional method for manufacturing a thin film transistor.

FIG. 6 is a process diagram showing a conventional thin film transistor manufacturing method.

FIG. 7 is a process diagram showing a conventional method for manufacturing a thin film transistor.

FIG. 8 is a process diagram showing a conventional thin film transistor manufacturing method.

FIG. 9 is a diagram for explaining variations in size of a low impurity concentration region and a high impurity concentration region of a conventional thin film transistor.

FIG. 10 is a cross-sectional view showing another conventional thin film transistor.

[Explanation of symbols]

1 Insulating substrate 2 Semiconductor layer 3 Gate insulating film 4 Gate electrode 4a, 4b, 4c Gate electrode part 5 Resist 6 Interlayer insulation film 7a, 7b Contact hole 8a, 8b electrode 9a, 9b, 9c Channel layer 10a, 10b High impurity concentration region 11a, 11b Low impurity concentration region

Claims (1)

[Claims] 1. A step of patterning a semiconductor layer on a substrate having an insulating surface, a step of forming an insulating film covering the semiconductor layer, and a gate electrode having a plurality of gate electrode parts on the insulating film. a step of implanting impurity ions into the semiconductor layer using the gate electrode as a mask and forming a low impurity concentration region between the gate electrode portions in a self-aligned manner; a step of forming a resist;
A method for manufacturing a thin film transistor, comprising the steps of implanting impurity ions into the semiconductor layer using the gate electrode portion and the resist as a mask, and forming a high impurity concentration region outside the gate electrode in a self-aligned manner.