JPH04278662A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To improve the availability of a shared memory in a multiprocessor system by enabling the collection of the fault information even if the subject microprocessor for collection of the fault information is disabled to operate by the bag of a software or the like. CONSTITUTION:A decoder 1 decodes the signals inputted via a control bus 101 and an address bus 102 and informs a device control circuit 10 of a reading operation, if detected, carried out into a free area 14 of a shared memory 13. Thus the circuit 10 grants an access to be applied to a fault information collecting memory 8 and at the same time controls the buffers 3 and 4 to connect the local address buses 117 and 118 to an address bus 102 and a data bus 103 respectively. Thus the circuit 10 can read the fault information out of the memory 8 via both buses 102 and 103.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a failure information collection method in a multiprocessor system comprising a plurality of microprocessors.

0002

2. Description of the Related Art Conventionally, in this type of multiprocessor system, failure information is collected by interprocessor communication via a shared bus connecting a plurality of microprocessors. Alternatively, failure information is collected by reading failure information from a failure information collection memory for each microprocessor allocated to a shared memory shared by a plurality of microprocessors.

In such conventional multiprocessor systems, when fault information is collected through inter-processor communication, if the microprocessor for which fault information is collected becomes inoperable due to a software bug or the like, the microprocessor's fault is detected. The disadvantage is that information cannot be collected. Furthermore, if the failure information collection memory is allocated to the shared memory for each microprocessor, there is a drawback that the memory usage efficiency of the shared memory decreases as the number of microprocessors increases.

0004

OBJECTS OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and it is possible to collect failure information even if the microprocessor that is the target of failure information collection becomes inoperable due to a software bug or the like. The present invention aims to provide a multiprocessor system that can improve memory usage efficiency of shared memory.

[0005]

SUMMARY OF THE INVENTION A multiprocessor system according to the present invention is a multiprocessor system in which a plurality of processors and a shared memory shared by each of the plurality of processors are connected via a shared bus. A failure information collection memory that stores failure information, and a failure information collection memory that determines whether the address information outputted onto the shared bus is an access from another processor other than the own processor to a specific area provided in advance in the shared memory. a detecting means for detecting; and when the detecting means detects an access from the other processor to the specific area, the shared bus is connected to the fault information collecting memory and the access from the fault information collecting memory is detected; The present invention is characterized in that each of the plurality of processors is provided with a control means for controlling the readout of failure information.

[0006]

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, decoder 1 is a shared bus 10
0 control bus 101 and address bus 102
is connected to the memory request signal line 11 for collecting fault information.
1 and an I/O port access request signal line 112 to the device control circuit 10.

The buffer 2 is connected to a shared bus 100, a control bus 101, and a local control bus 116.
and is connected to. Buffer 3 is connected to address bus 102 of shared bus 100 and local address bus 117.
and is connected to. Buffer 4 is connected to data bus 103 of shared bus 100 and local data bus 118. Buffer 5 is local address bus 1
17 and a CPU address bus 120. Buffer 6 connects local data bus 118 and CPU
It is connected to the data bus 121. These buffers 2-6 are connected to the device control circuit 10 via buffer control lines 115, respectively.

I/O port 7 connects to local data bus 11
8 and is connected to the device control circuit 10 via a fault information collection memory access permission signal line 123 and an I/O port permission signal line 122.

The fault information collection memory 8 and the dedicated memory 9 are connected to a local address bus 117 and a local data bus 118, respectively. Further, the fault information collection memory 8 is connected to a fault information collection memory access signal line 113.
The dedicated memory 9 is connected to the device control circuit 10 via a dedicated memory access signal line 114.

The device control circuit 10 is connected to a local control bus 116 and is connected to a local control bus 116 via a CPU control bus 119 and a CPU address bus 120.
It is connected to PU11. In addition, the device control circuit 1
0 controls each device inside the processor, and controls each buffer 2 to 6 via a buffer control line 115.

FIG. 2 is a block diagram showing the system configuration of an embodiment of the present invention. In the figure, each processor 12
A to 12c are shared buses 10 consisting of a control bus 101, an address bus 102, and a data bus 103.
0 and a shared bus 100
It is connected to the shared memory 13 via. Note that each of the processors 12a to 12c has the configuration shown in FIG.
Address bus 102 of shared bus 100 is a 20-bit wide bus.

FIG. 3 is a diagram for explaining address spaces of processors 12a to 12c and shared memory 13 in FIG. 2. In the figure, the processor 12a is at address “0”.
The address space from "0000" to "FFFFF" can be referenced. Of this address space, addresses "00000" to "4FFFF" are allocated to the dedicated memory 9a, and addresses "50000" to "4FFFF" are allocated to the dedicated memory 9a.
” to address “5FFFF” are assigned to the failure information collection memory 8a, and addresses “60000” to “FFFFFF” are assigned to the shared memory 13.

[0014] Furthermore, the processor 12b has an address "00".
The address space from ``000'' to address ``FFFFF'' can be referenced. Of this address space, addresses ``00000'' to ``3FFFF'' are allocated to the dedicated memory 9b, and address ``40000'' is allocated to the dedicated memory 9b.
” to address “5FFFF” are assigned to the fault information collection memory 8b, and addresses “60000” to “FFFFFF” are assigned to the shared memory 13.

Further, the processor 12c has the address "0".
You can refer to the address space from “0000” to address “FFFFF”. Among this address space,
Address “00000” to address “47FFF” are allocated to the dedicated memory 9c, and address “48000” is allocated to the dedicated memory 9c.
” to address “5FFFF” are assigned to the failure information collection memory 8c, and addresses “60000” to “FFFFFF” are assigned to the shared memory 13. Here, in the shared memory 13, each processor 12
The largest address space (address "E0000" to address "FFFFF") in the fault information collecting memories 8a to 8c of a to 12c is defined as a free area 14.

The operation of one embodiment of the present invention will be explained using FIGS. 1 to 3. When the processor 12a collects fault information of the processor 12b, the processor 12a first writes "1" to the I/O port 7 of the processor 12b. That is, inside the processor 12b, the decoder 1 is connected to the control bus 101 of the shared bus 100.
and decodes signals input from the processor 12a via the address bus 102. When the decoder 1 determines that the write operation is to the I/O port 7 based on the decoding result, the decoder 1 informs the device control circuit 10 that the write operation is to the I/O port 7 via the I/O port access request signal line 112. Notice.

The device control circuit 10 monitors each signal line, and if writing to the I/O port 7 is possible, the device control circuit 10 writes an I/O signal to the I/O port 7 via the I/O port permission signal line 122.
Allow O port access. At the same time, the device control circuit 10 controls the buffer 4 via the buffer control line 115 and connects the shared bus 100 via the buffer 4.
A local data bus 118 is connected to the data bus 103 of. As a result, "1" is written to the I/O port 7 from the processor 12a via the data bus 103 and the local data bus 118.

[0018] When writing to I/O port 7 is completed,
The device control circuit 10 controls the buffer 2 via a buffer control line 115 , and connects the local control bus 116 to the control bus 101 via the buffer 2 . As a result, the device control circuit 10 is connected to the local control bus 116 and the control bus 10.
1 to notify the processor 12a of the completion of writing. At the same time, the device control circuit 10 connects the buffer control line 11
5 to control the buffer 4 via the data bus 103.
and local data bus 118. Note that when the device control circuit 10 determines that writing to the I/O port 7 is not possible, the device control circuit 10 controls the I/O port 7 until writing becomes possible.
The write operation to port 7 is made to wait.

When “1” is written to I/O port 7,
Permission to access the fault information collection memory 8 is notified from the I/O port 7 to the device control circuit 10 via the fault information collection memory access permission signal line 123 .

Further, the processor 12a is the processor 12a.
When the completion of writing to I/O port 7 is notified from b,
A control bus 101 and an address bus 102 are used to read data from the free area 14 of the shared memory 13.
A request for access to the free area 14 of the shared memory 13 is output via the . At this time, inside the processor 12b, the decoder 1 decodes the signal from the processor 12a input via the control bus 101 and address bus 102 of the shared bus 100. When the decoder 1 determines from the decoding result that the operation is a read operation to the free area 14 of the shared memory 13, the device informs the device via the fault information collection memory request signal line 111 that the operation is a read operation to the free area 14 of the shared memory 13. Control circuit 1
Notify 0.

When the signal input from the decoder 1 via the fault information collection memory request signal line 111 becomes active, the device control circuit 10 monitors each signal line and can read from the fault information collection memory 8. If so, a signal output to the fault information collection memory 8 via the fault information collection memory access signal line 113 is activated. At the same time, the device control circuit 10 controls the buffers 3 and 4 via the buffer control line 115, and the address bus 102 of the shared bus 100 via the buffer 3.
Connect local address bus 117 to buffer 4
Local data bus 118 is connected to data bus 103 of shared bus 100 through. As a result, the fault information stored in the fault information collection memory 8 is transferred to the local data bus 118 and the data bus 1.
03 to the processor 12a.

When the processor 12a no longer needs to read the contents of the fault information collection memory 8b of the processor 12b, it writes "0" to the I/O port 7 of the processor 12b in the same manner as described above, and collects the fault information. Collection memory 8b
is separated from the free area 14 of the shared memory 13.

In this way, each processor 12a to 12c
By providing fault information collection memories 8a to 8c for each processor that can be read under control from other processors, fault information can be collected even if the processor targeted for fault information collection becomes inoperable due to a software bug or the like. becomes possible. Furthermore, by allocating the failure information collection memories 8a to 8c to the free space 14 of the shared memory 13,
Memory usage efficiency of the shared memory 13 can be improved.

[0024]

[Effects of the Invention] As explained above, according to the present invention, it is possible to prevent address information outputted onto a shared bus from being an access from another processor other than the own processor to a specific area provided in advance in the shared memory. When detected, fault information is collected by connecting the shared bus to the fault information collection memory that stores fault information in the own processor and making it possible to read the fault information from the fault information collection memory. Even if the target microprocessor becomes inoperable due to a software bug, it is possible to collect failure information, and this has the effect of improving the memory usage efficiency of shared memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing the system configuration of an embodiment of the present invention.

FIG. 3 is a diagram for explaining address spaces of the processor and shared memory in FIG. 2;

[Explanation of symbols]

1 Decoder 2-6 Buffer 7 I/O port 8 Memory for collecting fault information 10 Device control circuit 12a-12c Processor 13 Shared memory 14 Free space

Claims (1)

[Claims] 1. A multiprocessor system in which a plurality of processors and a shared memory shared by each of the plurality of processors are connected via a shared bus, the failure information collection storing failure information within the own processor. a detection means for detecting whether the address information outputted onto the shared bus is an access to a specific area provided in advance in the shared memory from a processor other than the own processor; When access to the specific area from the other processor is detected by means, the shared bus is connected to the fault information collection memory to enable reading of the fault information from the fault information collection memory. A multiprocessor system characterized in that each of the plurality of processors is provided with a control means for controlling the plurality of processors.