JPH04263198A - Memory device - Google Patents

Abstract

PURPOSE:To realize a memory device which is constituted of a nonvolatile memory and a volatile memory, which can examine whether a data has been written accurately or not in the nonvolatile memory by reading out the data and which can leave the data in the nonvolatile memory as soon as the data is generated while the data is being examined regarding the memory device which stores a hysteresis data. CONSTITUTION:A master CPU 1 and a slave CPU 2 are used. The master CPU 1 stores data generated instantaneously in large quantities and at high speed in a volatile memory 3 once and, after that, is used only for a write operation 'so as to be copied at each chip in a nonvolatile memory 4. The slave CPU 2 reads out the data at each chip of the nonvolatile memory 4, confirms the write life of each memory chip and rewrites them in another region in the memory chip when the life has expired. Hysteresis data which are generated instantaneously in large quantities and at high speed can be stored immediately without omission and, even when a power supply is dropped, the hysteresis at the point of time can be left.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly to a memory device for storing historical data.

[0002] Multiplex transmission equipment and the like need to keep a history of alarm data such as failures as well as normal operating conditions within the equipment, and since this history data is generated instantaneously in large quantities and at high speed, it is difficult for data to be leaked. In addition, these data must be stored even when the device is powered off.

0003

2. Description of the Related Art EEPROM (El
electrically Erasable and P
rogrammable Read Only Memo
ry) is used, but when writing byte data as one page, a maximum of about 10 ms is required for the data to be fixed in the EEPROM after writing one page. Therefore, when a large amount of data that is instantaneously generated at a high speed is to be stored in the EEPROM, a writing time of approximately 10 ms (number of pages of data) is required.

Furthermore, EEPROMs generally deteriorate in proportion to the number of electrical rewrites. This is because there are defects in the silicon dioxide insulating layer that makes up the EEPROM.
Electrons are injected into the silicon dioxide insulating layer in proportion to the number of times data is rewritten from "0" to "1" and from "1" to "0", and the number of rewrites reaches approximately 10,000 times. This is because the mobility of carriers decreases and eventually a state is reached in which current flows all the time, and the data always becomes "0".

On the other hand, as an element other than such EEPROM, SRAM (Static Random Acc
There is a known technology that allows volatile memory, such as ess Memory, to have the same functionality as non-volatile memory by supplying data retention current from a backup battery when the power is turned off, etc. In this case, the data retention current by the battery is limited and cannot be retained permanently, and the battery output voltage also needs to be constantly monitored. Furthermore, for completeness, a separate battery charging circuit must be added.

[0006] Therefore, both EEPROM and SRAM are used, and when the power is turned on, the data in the EEPROM is transferred to the SRAM.
and EEP the SRAM data before turning off the power.
A memory control method that saves data in ROM has come to be used, and in particular, in Japanese Patent Application Laid-Open No. 63-66797, it is possible to record whether or not the data in SRAM has been rewritten when the power is turned on. The page data in the SRAM is transferred to the EEPROM only when the power is turned off to reduce the number of times the EEPROM is rewritten.
The number of times the PROM has been rewritten is counted while being written to the EEPROM, and the lifespan of the number of times the EEPROM has been rewritten is notified.

[0007]

However, the accurate rewrite life of an EEPROM depends on usage conditions such as ambient temperature and the inherent life of the element, and cannot be determined simply by counting the number of rewrites. In order to accurately determine the rewriting lifespan, it is necessary to read and check whether data has been accurately written to the EEPROM.

[0008] However, in order to save data that is instantaneously generated in large quantities and at high speed without omission, the operation of reading and checking whether written data has been written accurately must occur immediately. There is a risk that the history of the data to be stored will be delayed, and even if the power is turned off, the history at that point will not remain.

Therefore, the present invention is constructed of a non-volatile memory and a volatile memory, and it is possible to read and check whether data has been accurately written to the non-volatile memory, and even during the checking. The object of the present invention is to realize a memory device that can leave data in a nonvolatile memory at the moment the data is generated.

0010

[Means for Solving the Problems] In order to achieve the above object, the memory device according to the present invention, as shown in principle in FIG. , a volatile memory 3 having dual ports connected to data buses 20, 22 and address buses 21, 23 of each CPU 1, 2 and storing input data under the control of the master CPU 1; A non-volatile memory array 4 having at least the same size as the area of the memory 3 and composed of a plurality of memory chips 41 to 4n, and connected to the data bus 20 and address bus 21 of the master CPU 1 to form a specific memory area unit. A write selection circuit 5 selects the memory chip and writes the data in the volatile memory 3 and writes the number of times of writing, and a write selection circuit 5 selects the memory chip to write the data in the volatile memory 3 and writes the number of times of writing, and determines which memory chip in the memory array 4 the data has been written to and read out. The corresponding data bus 22
A chip ready detection circuit 6 notifies the slave CPU 2 via a chip ready detection circuit 6, which is connected to the data bus 22 and address bus 23 of the slave CPU 2, and detects the memory chips detected by the chip ready detection circuit 6 in units of the specific memory area. Read/write selection circuit 7 that selects and reads the data
When the slave CPU 2 reads data from the readable memory chip and the number of writes in the data reaches the minimum guaranteed number of writes, the slave CPU 2 compares the data with the same data in the volatile memory and determines whether the data is different. When the data is read out, the data is newly rewritten via the read/write selection circuit 7 into an unused area in the memory chip from which it was read.

[0011]

[Operation] The operation of the memory device according to the present invention shown in FIG. 1 will be explained below with reference to the flowchart shown in FIG.

When a large amount of data is generated instantaneously (step S1 in FIG. 2), the master CPU 1 cannot write the input data to the non-volatile memory array 4 at once, so it is initially volatile. The data is stored in the memory 3 (S2). Thereafter, the master CPU 1 selects a number of bytes (usually 1 to 8 bytes) that can be written at once to the memory chips 41 to 4n constituting the memory array 4 using the write selection circuit 5 via the data bus 20 and address bus 21. The data is written in the form of a page and is copied to each memory chip in turn while updating the address (S3). Therefore, n pages equal to the number n of memory chips can be written to the nonvolatile memory array 4 at one time without waiting time. Then, since the master CPU1 has finished its own operation, the slave CPU
2 and activates it (S4).

[0013] I learned that activation was applied (S5)
The slave CPU 2 reads which memory chip has completed its write cycle from the chip ready detection circuit 6 via the data bus 22 (S6), and reads the data written to the memory chip that has just finished writing. - is read out by the read/write selection circuit 7 (S7).

[0014] The number of writes is simultaneously written to each memory chip from the master CPU 1 as write data, and in the slave CPU 2, if the number of writes in the read data of the memory chip exceeds the minimum guaranteed number of writes. It is determined whether the data exceeds the limit (S8), and only if it exceeds the same, the data is compared with data in the same area stored in the volatile memory 3 (S9). If the two are different, the slave CPU 2 uses the read/write selection circuit 7 to change the write area to an unused area of the memory chip from which the current data was read, and rewrites the data in the volatile memory 3 ( Same S
10).

In this way, even if the slave CPU 2 performs the above operations, it is independent of the data writing to the nonvolatile memory array 4 by the master CPU 1, so if a large amount of data is generated instantaneously, Even if the data is stored in the nonvolatile memory array 4, it is possible to immediately record the data in the nonvolatile memory array 4.

[0016]

[Embodiment] FIG. 3 shows an embodiment of the memory device according to the present invention. In this embodiment, an SRAM is used as the dual-port volatile memory 3 shown in FIG. EEPROM is used, and the nonvolatile memory 4 further includes n=3 memory chips 41 to 43.
It consists of Further, the write selection circuit 5 selects the master C
Each of the memory chips 41 to 43 is configured based on the address signal ADDR given from the PU1 via the address bus 21.
An address decoder 50 that generates a chip select signal CS for writing selection is connected to each memory chip 41 to 4.
3 in common, and further includes individual memory chips 41 to 4.
AND gates 51a, 51b, and 3 input the write enable signal WE from the master CPU 1 and the chip select signal CS from the address decoder 50, respectively.
51c and the output signals of the AND gates 51a, 51b, 51c, the data bus 20, chip select signal CS, and address signal A to each memory chip 41 to 43.
Arbiters 52a, 52b, and 52c that open gates for DDR and write enable signal WE are provided. Further, the read/write selection circuit 7 receives an address signal A applied from the slave CPU 2 via the address bus 23.
Each of the memory chips 41 to 43 has an address decoder 70 in common that generates a chip select signal CS for reading and selecting each memory chip 41 to 43 based on the DDR, and each of the memory chips 41 to 43 has Inverters 71a, 71b, 71c invert the output signals of AND gates 51a, 51b, 51c, and data buses 22, chip select signals CS, and addresses to each memory chip 41 to 43 by the output signals of these inverters 71a, 71b, 71c. Arbiter 7 that opens gates for signal ADDR and read enable signal RE
2a, 72b, and 72c, and further includes hardware for specifying an unused area for writing timing signals and address signals from the address decoder 70, and rewrite data received from the slave CPU 2 via the data bus 22. Each of the memory chips 41 to 43 has a register 73 in common. In addition, the chip ready detection circuit 6 receives toggle outputs (I/O) from each of the memory chips 41 to 43, timing signals and address signals from the address decoder 70, and slave the memory chips for which writing has been completed via the data bus 22. It consists of a hard register for notifying the CPU 2.

Next, to explain the operation of such an embodiment, when writing multi-page data to the EEPROM array 4, first a command (address ADD) from the master CPU 1 is sent.
R and chip select CS), the page data made up of several bytes as one page is once stored in the SRAM3 as a buffer.
Move to. After that, the chip select signal CS from the address decoder 50 and the write enable signal WE are ANDed.
Arbiter 52a~ received via gates 51a~51c
52c opens the gate. The first EEPROM memory chip 41 in the EEPROM array 4 is equipped with SRAM.
Write page data for one page in 3. Next, page data for the next page in the SRAM 3 is written into the second memory chip 42.

A detailed diagram of this part is shown in FIG.
Assuming that one page of data is, for example, 32 bytes, the data is written into the first EEPROM chip 41. 1 page
Address management within the 16-bit address bus 21 (
This is done using bits A0 to A4 of the address bus 23 (same).
Address management of memory chips used for chip selection is performed using bits A6 to A15. Thereafter, this EEPROM chip 41 is in a state where neither reading nor writing is possible for about 10 ms, so the two pages in the SRAM 3 are
The 32-byte page data of the second EEP
ROM chip 42 (first EEPROM chip 4
Write to the same area in the chip (as the memory area in the chip written to). In this case, the write time is only the chip-specific access time. Further, the chip select signal CS is output by the address decoder 50 every 32 bytes. Arbiter 52a~
52c and 72a to 72c use 3-state buffers. If the first EEPR is set by master CPU1,
Assume that OM chip 41 is selected as the write chip. Arbiter 52a opens and 72a closes. Arbiters 52b and 52c of memory chips that are not chip-selected by other master CPUs 1 are closed, and 72b and 72
c opens. From this, the master CPU 1 can access only the EEPROM chip 41 that has undergone chip selection. At this time, from the perspective of slave CPU2, the first EE for which chip selection was performed by master CPU1
Only the arbiter 72a of the PROM chip 41 is closed, and the arbiters 72b and 72c of memory chips that are not chip-selected by the other master CPUs are slave CPUs.
Open for 2. As a result of the above, the slave CPU
2 can read out internal data from memory chips not selected by the master CPU 1 at any time.

In this way, the master CPU 1
32 bytes of page data are written to each memory chip 41 to 43 of the OM array 4. Assuming that the number of EEPROM arrays 4 is 20, it is possible to write 20 page data, or in other words, 640 bytes of data without waiting time.

[0020] Note that the last EEPROM array 4
After reaching the EPROM chip 43 and writing one page of data, if one more page is to be written, the first EEPROM chip 41 to which one page of data has been written is
is selected again and data for the next page is written in section 10 of the second page. Thereafter, the same method as described in the section of the first page is repeated up to the third EEPROM chip 43.

Immediately after the master CPU 1 writes a large amount of data instantaneously into each memory chip of the EEPROM array 4, the slave CPU 2 writes the data to the memory chip of the EEPROM array 4 that has just been written by the master CPU 1. The data in the memory chip is read out and compared with the data in the same area in the SRAM 3 to determine whether or not it has reached its write life. However, if the number of times the EEPROM memory chip is written is the minimum guaranteed number of rewrites, for example 10,000.
The data comparison operation is not performed until the end of the data comparison period.

For this reason, the number of writes is written by the master CPU 1 to 2 bytes of 32 bytes of 1 page data in each EEPROM memory chip, and read out from the slave CPU 2 for each memory chip. Only when the number of writes shown in the data exceeds the minimum guaranteed number of rewrites of 10,000, the data is compared with the data stored in the SRAM3. The number of writes is determined by the master CPU1.
However, when the power is turned off, it can be known by reading the number of writes written in the memory chip by the master CPU 1 when the power is turned on.

When data is read from each memory chip by the slave CPU 2, an address signal ADDR and a read enable signal RE are applied to an address decoder 70, and a chip select signal CS generated is sent to each memory chip 4.
This is done for each page of data by selecting 1 to 43, but in order to prevent writing and reading from colliding in each memory chip, whether the internal write cycle of the memory chip is completed or not is determined by each EEPROM. The hard register 6 detects whether the toggle output (I/O) of the chip is busy. Then, the slave CPU 2 polls this hard register 6, and uses the code obtained from the hard register to write the E
The slave CPU 2 identifies the EPROM chip and writes 1 to the EEPROM chip for which the internal write cycle has been completed.
Go read the page data.

[0024] When it is found that the number of writes in the data read out by the slave CPU 2 from the memory chip immediately after the end of writing exceeds the above-mentioned 10,000 times, the data read from the memory chip and the SRA
The data in the same area stored in M3 is compared, and if the two are different, the data is written again. If the data still differs, it is determined that the writing life has been reached and the data may have been corrupted, and the writing area is changed to an unused area in the EEPROM memory chip and rewritten on the slave CPU 2 side. . In this case, the unused area refers to the 32-byte area 10 next to the area 9 written so far (see FIG. 4), and this area is changed on the slave CPU 2 side by the hard register 73 for specifying the unwritten area. The address bit A5 in each memory chip is changed from “0” to “1” by
Note that even without using the hard register 73, the slave CPU 2 can change the data write area by specifying its address signals A0 to A5.

[0025]

As described above, according to the memory device according to the present invention, a master CPU and a slave CPU are used, and the master CPU temporarily stores a large amount of data generated at high speed in a volatile memory, and , used exclusively for writing to copy each chip of non-volatile memory, slave C
The PU reads data from each chip of non-volatile memory, checks the write life of each memory chip, and when the life reaches the end of its life, it rewrites data to another area of the memory chip. History data that is generated at high speed can be instantly saved without omission, and even if the power goes out, the history at that point can be preserved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle configuration of a memory device according to the present invention.

[Fig. 2] Master CPU in the memory device according to the present invention
FIG. 2 is a flowchart showing the operation of a slave CPU.

FIG. 3 is a block diagram showing an embodiment of a memory device according to the present invention.

FIG. 4 is a detailed diagram of an EEPROM array portion of a memory device according to the present invention.

[Explanation of symbols] 1 Master CPU 2 Slave CPU 3 Dual port SRAM (volatile memory) 4
EEPROM array (nonvolatile memory) 41 to 4n
EEPROM chip 6 Chip ready detection circuit 7 Read selection circuit 20, 22 Data bus 21, 23 Address bus In the diagram, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] Claim 1: A master CPU (1) and the master C
Slave CPU (2) that is interrupt activated by PU (1)
and the data bus (20, 22) of each CPU (1, 2).
) and an address bus (21, 23) for storing input data under the control of the master CPU (1); a nonvolatile memory array (4) having at least the same size as the area of
U(1)'s data bus (20) and address bus (2
a write selection circuit (5) that is connected to the memory array (1) and selects the memory chip in units of a specific memory area, writes data in the volatile memory (3), and writes the number of times of writing; ) What memory chip data is inside?
a chip ready detection circuit (6) that notifies the slave CPU (2) via the data bus (22) whether the data has been written and is ready for reading;
(2) Data bus (22) and address bus (23)
) for selecting the memory chip detected by the chip ready detection circuit (6) in units of the specific memory area and reading data therefrom; When the CPU (2) reads data from the readable memory chip and the number of writes in the data has reached the minimum guaranteed number of writes, it compares it with the same data in the volatile memory, and if they are different, A memory device characterized in that the data is newly rewritten into an unused area in the read memory chip via the read/write selection circuit (7).