JPH0426280A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To automatically perform an appropriate video clamping operation by performing a clamping operation at a back porch when a composite video signal including a synchronizing signal is inputted, and switching a clamp pulse so as to perform the operation at a synchronizing signal part when the video signal other than that is inputted. CONSTITUTION:When the composite video signal V2 is inputted, a synchronizing separator circuit 9 separates a horizontal synchronizing signal SH2 from the composite video signal V2, and a back porch pulse circuit 10 generates the clamp pulse Cl2 based on the horizontal synchronizing signal SH2, and inputs it to a switching circuit 7. The switching circuit 7 selects a clamp pulse Cl1 when a voltage signal VS1 of high level is inputted from an integration circuit 6, and selects the clamp pulse Cl2 when a voltage signal VS2 of low level is inputted, and they are inputted to a pedestal clamping circuit 11, then, clamping is performed. Thereby, it is possible to automatically perform pedestal clamping corresponding to the mode of an inputted video signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal processing circuit, and more specifically, to a video signal processing circuit that selects and uses a clamp pulse with an appropriate timing according to the format of an input video signal. Related to signal processing circuits.

[Conventional technology]

Normally, the DC component of video No. 18 in the video processing circuit is pedestal clamped using a clamp pulse whose phase matches that of the horizontal synchronizing signal during the horizontal retrace period. There is.

In this case, the back porch section requires a sufficiently long time for the clamp pulse.

However, there are various forms of video signals output from personal computers and the like to display monitors, which are the display devices of personal computers, etc., and as the resolution has increased in recent years and the horizontal deflection frequency has become higher, back porch Class time is getting shorter and shorter.

On the other hand, the width of the clamp pulse cannot be made narrower than necessary due to the characteristics of the five circuits. For this reason, the signal is clamped at the back porch.

There is a problem that the clamp pulse gets stuck in the imaging part and the lamp cannot operate normally.

If pedestal clamping is performed at the part where the pulse is synchronized with the phase of the synchronization signal, if the input video signal is a composite video signal in which the synchronization signal is included in one of the R, G, and B video signals, clamping will not be performed. The problem arises that the level stands out from the other colors.

For this reason, conventional video signal processing circuits either switch the position of the clamp pulse using a manual switch depending on the format of the input video signal, or can only handle one of these unique input video signals. Ta.

[Problems to be Solved by the Invention] This invention was made to solve the above problems, and it automatically selects a clamp pulse with an appropriate phase depending on the format of the input video signal. An object of the present invention is to obtain a video signal processing circuit that performs pedestal clamping.

[Means to solve the problem]

The video signal processing circuit according to the present invention compares the level of a peak-clamped input video (No. 3 blanking period) with a reference voltage, generates a pulse signal corresponding to a period exceeding the reference voltage, and integrates this pulse signal. and a means for converting the input video signal into a voltage signal, and a method for determining whether or not an input video signal has a horizontal synchronization signal based on the level of the voltage signal, and in the case of a composite video signal containing a horizontal synchronization signal, determining whether or not the input video signal has a horizontal synchronization signal. Outputs a clamp pulse that matches the phase of the back porch of the horizontal sync signal, and in the case of a video signal that does not include a horizontal sync signal, selects a clamp pulse that matches the phase of the horizontal sync signal that is input separately to clamp the pedestal. The configuration is such that it is input to the circuit.

[Effect]

According to this invention, the level of a reference voltage and a peak-clamped input video signal are compared, a pulse signal with a pulse width corresponding to a period exceeding the reference voltage is output, and a voltage signal obtained by integrating this pulse signal is horizontally In the case of a video signal that does not include a synchronization signal, the pulse width is equivalent to the retrace period,
If a horizontal synchronization signal is included, it is the width of the horizontal synchronization signal.

Therefore, since the integrated voltage signal of this pulse signal is high level in the former case and low level in the latter case, using this voltage signal, in the former case, it is in phase with the horizontal synchronization signal input separately. In the latter case, a clamp pulse synchronized with the back porch portion of the horizontal sync signal is selected, so a clamp pulse with an appropriate phase is automatically selected according to the form of the input video signal. You can choose to do a pedestal clamp.

[Fu example]

An embodiment of this invention will be described below.

FIG. 11 is a block circuit diagram of this embodiment, in which (1) is an input terminal for a video signal, (2) is an input terminal for a horizontal synchronizing signal,
(3) is a peak clamp circuit, (4) is a comparator,
(5) is a reference voltage power supply, (6) is an integrating circuit, (month is a switching circuit, (8) is a synchronous separation circuit, (9) is a back porch pulse generation circuit, (10) is a clamp pulse buffer circuit, (11) ) is a pedestal clamp circuit, and (I2) is a synchronous circuit.

First, peak clamp circuit (3), comparator (4)
The operation of the integration circuit (6) will be explained using the waveform diagram shown in FIG.

Now, a video signal V without a synchronizing signal as shown in FIG. 2 (al) is input from the input terminal (1), and a horizontal synchronizing signal S, (FIG. 3 fa) is input from the input terminal (2). reference)
is input, the video No. 15 Vl peak-clamped by the peak crushing circuit (3) is input to the comparator (
4), it outputs a pulse 11ζ P (shown in FIG. 2 fb)) with a wide pulse width corresponding to the horizontal retrace period, which is at a level exceeding the reference voltage 7'fE.

This pulse signal P1 is integrated by an integrating circuit (6), and the second
A high level voltage signal VsI shown in Figure fc) is sent to the switching circuit (7).

On the other hand, when a composite video signal V2 having a synchronization signal as shown in the input terminal (from Rika, fd in Fig. 2) is input,
The peak clamp circuit (3) performs peak clamping using the horizontal synchronizing signal, so the comparator (4)
As shown in Fig. 2(f), a pulse signal 1) 2 with a narrow pulse width corresponding to the width of the horizontal synchronizing signal is output, and the level of the output voltage signal VS2 of the integrating circuit (6) is as shown in Fig. 2(f). The voltage is lower than VS+.

Therefore, it is possible to determine whether or not the input video signal has a horizontal synchronizing signal based on the level of the output voltage of the integrating circuit (6). Switch.

Next, the selection operation of the clamp pulse by the switching circuit (7) will be explained with reference to the waveform diagram of FIG.

The video signal V is input from the input terminal (11), and at the same time the horizontal synchronization signal SH shown from the input terminal (2) fa in Figure 3 is input.
, is input, the clamp pulse buffer circuit (8) shapes this input signal into a waveform and generates a clamp pulse C°C1 having the same phase as the horizontal synchronizing signal S Ml as shown in FIG. 3(b). Input to the switching circuit (7).

On the other hand, when the composite video signal ■2 is input from the input terminal (]), the synchronization separation circuit (9) inputs the composite video signal ■2
A horizontal synchronizing signal S82 is separated from the horizontal synchronizing signal S82 and inputted to the back porch pulse generating circuit (10). The back porch pulse circuit (10) generates a clamp pulse Cβ2 having a small timing as shown in FIG. 3(d) based on this horizontal synchronization signal No. 12 S N2. Input to the switching circuit (7).

The switching circuit (7) outputs a clamp pulse C when a high level voltage (G V31) is input from the integrating circuit (6).
℃, and when a low level voltage 1f "r V S 2" is input, clamp pulse Cρ2 is selected and input to the pedestal clamp circuit (11), and the pedestal level is changed at the timing of this clamp pulse. Therefore, if a video signal V that does not have synchronization number 45 is input, clamping is performed in the horizontal synchronization signal section, and if a composite video signal Clamping is performed at the

〔Effect of the invention〕

According to the present invention, as described in (2) above, when a composite video signal including a synchronization signal is input, the clamping operation is performed every step of the way.1. In the case of a video signal with -, the clamp pulse is automatically switched so that the clamp operation is performed in the synchronization signal section, so if a video signal with an extremely narrow backbone or a composite video signal is input, the clamp pulse will be automatically switched. This has the effect of providing a video signal processing circuit that can perform a video clamping operation that is generally appropriate.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a block circuit diagram of an embodiment of the present invention;
3 and 3 are timing diagrams for this embodiment. (4)...Comparator, (5)...Reference voltage power supply, (6)...Integrator circuit, (7)...Switching circuit, (8
)...clamp pulse buffer circuit, (9)...synchronization separation circuit, (10)...back porch pulse generation circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Means for comparing the level of the blanking period of the input video signal with a reference level and generating a pulse signal of a constant level corresponding to the period exceeding the reference level, and integrating this pulse signal to generate a voltage signal. means for converting the horizontal synchronizing signal from the input video signal to generate a back porch clamp pulse thereof; means for generating a clamp pulse synchronized with the input horizontal synchronizing signal; and the voltage signal and selecting means for outputting the back porch clamp pulse when the voltage signal is at a high level, and outputting the clamp pulse when the voltage signal is at a low level.