JPH04267553A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a power supply device for semiconductor integrated circuit which can efficiently supply electric power by utilizing part of the substrate of a large-scale integrated circuit, especially, the signal line wiring area of the substrate as power supply lines. CONSTITUTION:The power supply device of the cell of a semiconductor integrated circuit is constituted by expanding diffusion areas 14-1 and 15-1 in the direction 17 perpendicular to the conventional wiring direction of power supply lines and using the extended diffusion areas 14-2 and 15-2 as power supply lines for the original diffusion areas 14-1 and 15-2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device for a semiconductor integrated circuit that uses a part of a substrate constituting a semiconductor cell as a power supply line. When supplying power to conventional semiconductor integrated circuits, metal wires made of aluminum or other metal wires dedicated to the power supply have been used, which has resulted in a large amount of signal wiring and a reduction in the degree of integration. Therefore, even when forming large-scale integrated circuits, it has become necessary to take power supply into consideration and efficiently lay out the circuits.

0002

2. Description of the Related Art When an inverter as shown by the logic symbol in FIG. 9 is constructed using two FETs, the circuit diagram becomes as shown in FIG. It is formed. The range shown in FIG. 11 is commonly referred to as a "cell." 10 and 11, 1 is a P-channel FET, 2 is an N-channel FET, 3 is a signal input terminal, 4 is a signal output terminal, 5 is a power supply VDD terminal, 6 is a power supply VSS terminal, and 7 is a common gate of both FETs. The electrodes 8 are respective drain electrodes, and 9 are respective source electrodes. In FIG. 11 as an integrated circuit, two FETs 1 and 2 are connected in parallel and output to an output terminal 4 in response to a signal input to a terminal 3. For direct current, two F
It can be seen that the ETs are connected in series. Furthermore, Figure 11
A portion connecting the signal input terminal 3 and the gate electrode 7 in the
Since the supply lines 5 and 6 of the power supplies VDD and VSS are usually formed of aluminum metal wires, their resistance value is as low as about 0.05 Ω per unit area. In addition, the power supply line 5,
The connection between the drain electrode 6 and the drain electrode 8 is made through a contact hole indicated by a circle.

In the integrated circuit shown in FIG. 11, the source electrode 9 is formed by a so-called diffusion process. Diffusion process is the process of spreading from the surface of the silicon substrate after the mask exposure process.
This refers to the diffusion of a tertiary or quintiple valent element. The diffused region becomes P-type when a trivalent element such as boron is diffused, and becomes N-type when a pentavalent element such as phosphorus is diffused.

A large-scale integrated circuit has a configuration shown in FIG. 12. In FIG. 12, 10-1, 10-2 and 10-2 respectively indicate cells of the integrated circuit. 11 is a range called a "stage" in a large-scale integrated circuit, and 12-1, 12-2 to 12-2 are intervals between "stages". 13 is signal wiring, 5
, 6 indicate power supply wiring. As shown in FIG. 12, a large number of cells are connected to each stage of the large-scale integrated circuit, and power supply wirings 5 and 6 are commonly connected. Step interval part 12-1, 1
Since the signal wiring 13 is wired to 2-2, naturally there is no FET, and a plurality of wires are present at predetermined intervals.

[0005]

[Problems to be Solved by the Invention] In the configuration shown in FIG. 11, it is not possible to wire a signal line in the part of the cell through which the power supply line runs, and the signal line must avoid the power supply line. Ta. Therefore, when the number of cells increases and the power supply lines inside the cells alone are not sufficient, it is necessary to cut out the signal line wiring area in the wiring area outside the cells and route the auxiliary power line. Therefore, since the signal wiring area is provided outside the area of the auxiliary power supply line, the degree of integration is further reduced. In other words, even if microtechnology improves and a large number of microcells are used to form stages as shown in FIG. 12, it is necessary to increase the number of power supply lines, and large-scale This resulted in the drawback that it was not possible to reduce the area of the integrated circuit as desired.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and to provide an apparatus for efficiently supplying power by using a part of a substrate in a large-scale integrated circuit, especially a signal wiring area, as a power supply line. It is about providing.

[0007]

[Means for Solving the Problems] FIG. 1 is a diagram showing the basic configuration of the present invention. In Figure 1, 1 is a P-channel FET
, 2 is an N-channel FET, 5 is a power supply VDD terminal, 6 is a power supply VSS terminal, 7 is a common gate electrode of both FETs, 14-
1, 15-1 are electrodes formed by the diffusion regions of both FETs, such as drains, 14-2, 15-2 are diffusion regions expanded according to the present invention, 16 is the entire frame of the cell, 17
is an arrow indicating the direction of expansion of the diffusion region. First diffusion regions 14-1, 15-1 in which electrodes are formed on the substrate, and a second diffusion region 14 formed in a region different from the first diffusion regions 14-1, 15-1. -2,15-2
The second diffusion regions 14-2 and 15-2 are provided on two opposing sides of the cell and form a power supply line.

[0008]

[Operation] As shown in FIG. 1, the region formed by the diffusion process among the electrodes of FETs 1 and 2 is
It is expanded in the direction of , and that part serves as the power supply section for the cell. That is, in the conventional substrate, the region diffused in the diffusion process has a high resistance value, so it was difficult to use it as a wiring for flowing current, but it has become possible to use it by selecting the material. In the present invention, the area of the cell itself increases by providing upper and lower power supply diffusion regions, but this frees up the area that was previously used for power supply wiring within the cell, so the wiring area between cells can be reduced as in the past. There is no need to provide one, just lay out the cells, and the degree of integration itself will improve.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a cross-sectional view showing a method of manufacturing a diffusion region according to the present invention. In FIG. 2, 18 is a substrate diffusion layer, 19
Reference numeral 20 indicates a portion of the substrate other than the diffusion layer, and 20 indicates a metal that can react with silicon, such as tungsten, on the diffusion layer of the Si (silicon) substrate, resulting in tungsten silicide as a result of the reaction. Diffusion layers have conventionally had a resistance value of about 50 ohms per unit area. As mentioned above, the product obtained by reacting with silicon is generally called metal silicide.
Its resistance value is 2 to 5 Ω per unit area. Since its resistance value is extremely high compared to conventional aluminum wiring, it is used to supply power by applying treatments such as making the silicide portion thicker to lower its resistance.

FIG. 3 is a top view showing the configuration of an inverter as a specific circuit to which the present invention is applied, FIG. 4 is a sectional view taken along the dashed line IV--IV in FIG. 3, and FIG. A sectional view taken along the dashed line V-V is shown. Figure 3,
In FIGS. 4 and 5, 16 is the entire frame of the cell, 14-1,
15-1 is a diffusion region of conventional configuration, 14-2, 15-2
indicates an expanded diffusion region, and all of 14-1 to 15-2 are formed of metal silicide material. 21-1, 21
-2 and 21-3 indicate the range of the first layer of wiring, and 22 indicates the range of the second layer of wiring. In FIG. 3, the first wiring layer 21-3 is used as an input terminal, and the applied data is inverted and output from the second wiring layer 22. At this time, the diffusion region 14-
2 and 15-2 are the parts that supply the power necessary for operation. In addition, in FIG. 5, 25 indicates a contact window,
The first wiring layer 21-1, 21-3 is connected to the diffusion region 14-1 which acts as a drain electrode.

The configuration shown in FIG. 3 is equivalent to connecting the parts constituting the logic cell in the horizontal direction along the dashed line IV--IV. Therefore, when adopting a configuration in which other circuits are connected in cascade, including the case of the inverter shown in FIG. 3, it is natural that the diffusion regions 14-2 and 15-2 as power supply sections are extended in the horizontal direction of the figure. be.

Next, FIG. 6 is a diagram showing the configuration of another application example of the present invention. In FIG. 6, 23-1 and 23-2 respectively indicate a set of conventional cells as a whole. In FIG. 6, the diffusion region 1 for power supply shown as VSS in the cell 23-2
5-2 is shared with the region 15-2 of the VSS diffusion region in the cell 23-1, and shares the extended region 15-2 of the diffusion region. Therefore, the length of the integrated circuit in the vertical direction in the figure can be reduced. Although this configuration has been described for sharing the supply path of the voltage source VSS, it may also happen that the voltage source VDD is shared.

FIG. 7 is a diagram specifically showing the configuration of FIG. 6 as two sets of ring oscillators, and FIG. 8 is a diagram showing its equivalent circuit. In FIGS. 7 and 8, 24-1 and 24-2 are signal input terminals (also used as output terminals for the oscillator), 2
5-1 and 25-2 are signal output terminals (not used as external terminals because they are oscillators), and 26-1 and 26-2 are feedback circuits. 27-1, 27-1 are signal lines necessary for other cells, and 28 is an auxiliary power line made of aluminum, for example, which supplies power to the ring oscillator or other cells when necessary. Reference numeral 29 denotes a contact portion with the substrate, which can be placed anywhere below the auxiliary power supply line 28. Reference numeral 30 indicates a contact portion between the auxiliary power supply line 28 and a necessary location. The power contact portion 30 can be opened in a long and narrow manner all the way under the auxiliary power line 28 . The contact portion 30 with the substrate does not need to be placed under the auxiliary power supply line 28, but can be placed anywhere above the diffusion region 15-2. In FIG. 7, the input and output terminals of the three inverters are connected to the feedback circuit 26.
Two sets of ring oscillators are formed by combining the ring oscillators, and the power supply VSS necessary for operation is commonly supplied to each oscillator through the diffusion layer 15-2. In this case, there is no space between stages as shown in the conventional example shown in FIG. 12, and the size of the integrated circuit can be reduced.

In the above description, the terms "power supply" and "power supply line" are used to include "ground" and "ground line." Further, the specific configuration of the circuit can of course be applied to a NAND gate, a NOR gate, etc. in addition to an inverter ring oscillator.

[0015]

As described above, according to the present invention, the extended diffusion region is used as the power supply line instead of the conventional wiring provided independently as the power supply line. It is possible to reduce the size of the integrated circuit without having to provide an integrated circuit. Conventionally, power supply lines were arranged, making it difficult to arrange signal lines between the stages of an integrated circuit, but according to the present invention, signal lines can be easily passed through, making design easier. Integrated circuits can be further miniaturized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 shows a method of manufacturing a diffusion region according to the invention.

FIG. 3 is a top view showing a specific circuit to which the present invention is applied.

FIG. 4 is a cross-sectional view of FIG. 3;

FIG. 5 is a cross-sectional view of FIG. 3;

FIG. 6 is a diagram showing another application example of the present invention.

FIG. 7 is a configuration diagram specifically showing the configuration of FIG. 6;

8 is an equivalent circuit diagram of FIG. 7. FIG.

FIG. 9 is a logical symbol diagram of an inverter.

FIG. 10 is a circuit configuration diagram regarding FIG. 9;

FIG. 11 is a configuration diagram of the C-MOS circuit in FIG. 9;

FIG. 12 is a configuration diagram of a large-scale integrated circuit corresponding to FIG. 11;

[Explanation of symbols]

1 P-channel FET 2 N-channel FET 5 Power supply VDD terminal 6 Power supply VSS terminal 7 Common gate electrodes of both FETs 14-1, 15-1 Electrodes 14-2, 15-2 formed by diffusion regions of both FETs According to the present invention Expanded diffusion area 16 Entire frame of cell

Claims (3)

[Claims] 1. A first diffusion region (14-1) (15-1) in which an electrode is formed on a substrate, and a first diffusion region (14-1) (15-1) having an electrode formed on a substrate;
14-1) a second diffusion region (142) (15-2) formed in a different region from the second diffusion region (15-1); (14
-2) A semiconductor integrated circuit characterized in that (15-2) is provided on two opposing sides of the cell (16) and forms a power supply line. 2. A semiconductor integrated circuit according to claim 1, wherein the second diffusion region is made of silicide obtained by reacting a metal with a silicon substrate. 3. The power supply line according to claim 1 is of two types, a high potential side power supply and a low potential side power supply for the integrated circuit, and the same type of power supply line is shared to serve two cells. A semiconductor integrated circuit characterized by being formed in contact with each other.