JPH04258162A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce power consumption of a MISFET to which a high operating power source voltage is supplied and to improve driving capacity of a MISFET to which a low operating power source voltage is supplied in a semiconductor integrated circuit device in which different operating power source voltages are supplied to a plurality of MISFETs. CONSTITUTION:In a semiconductor integrated circuit device in which different operating power source voltages are supplied to a plurality of MISFETs, an impurity concentration of a source region or a drain region of a MISFET Qn2 to which a high operating power source voltage is supplied, at the side of a channel forming region (LDD 38) is reduced as compared with that of a source region of a drain region of a MISFET Qn1 to which a low operating power source voltage is supplied, at the side of a channel forming region side (LDD 37).

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a MISFET.

0002

[Prior Art] SRAM (Static Random
A memory cell that stores 1 bit of information (Access Memory) is arranged at the intersection of the complementary data line and the word line. A memory cell basically includes a flip-flop circuit (differential amplifier circuit) as an information storage section and a transfer MOSFET. The transfer MOSFET is arranged between the input/output terminal of the flip-flop circuit and the complementary data line, and its operation is controlled by the word line. The flip-flop circuit includes, for example, two driving MOSs.
It consists of a FET and two load elements.

When the SRAM receives an address signal from an external device, it selects a memory cell at a predetermined address through an address buffer circuit, a predecoder circuit, and a decoder circuit. In an information write operation, information 1 or information 0 is input from an external device, and the information is written into a selected memory cell through an input buffer circuit and a write driver circuit, respectively. The respective operations of the input buffer circuit and the write driver circuit are controlled by control system signals output from the control buffer circuit. Control system signals such as a column address strobe signal, a write enable signal, and an output enable signal are input to the control buffer circuit from an external device.

On the other hand, in an information read operation, information in a memory cell selected by an address signal is determined and amplified by a sense amplifier circuit, and this amplified information is output to an external device via an output buffer circuit. do. The operation of the output buffer circuit is controlled by control system signals output from the control buffer circuit described above.

Circuits such as the address buffer circuit, input buffer circuit, write driver circuit, and sense amplifier circuit are arranged around the memory cell array of the SRAM as peripheral circuits of the SRAM. These peripheral circuits are constructed using complementary MOSFEs for the purpose of high integration and low power consumption.
Mainly composed of T (CMOS).

This type of SRAM is generally driven with a single operating power supply voltage, for example, 5 [V], but in the future, it will be driven with multiple operating power supply voltages with the main purpose of reducing power consumption. There is a tendency. SRAM input buffer circuit,
The output buffer circuit, control buffer circuit, write driver circuit, sense amplifier circuit, memory cell, etc. are required to operate stably and at high speed, so they are driven by an operating power supply voltage of 5 [V]. Each of the address buffer circuit and predecoder circuit of the SRAM performs one write operation or one read operation, that is, one operation cycle.
Since the number of circuits (number of elements) operating at a time is large, low power consumption is required during circuit operation, and the device is driven with a step-down operating power supply voltage. The step-down operating power supply voltage is obtained by installing a step-down circuit in the SRAM and stepping down the 5 [V] operating power supply voltage supplied to the SRAM to, for example, 4 [V] using the above-mentioned step-down circuit.

[0007] Regarding general SRAM, for example, Science Forum Co., Ltd., VLSI Device Handbook, published November 28, 1980, Vol.
It is described from page 05 onwards.

[0008]

[Problems to be Solved by the Invention] (1) All or some complementary MOs forming the peripheral circuit of the SRAM
At least one of the SFET, the memory cell transfer MOSFET, or the drive MOSFET is L.
A DD (Lightly Doped Drain) structure is adopted. In a MOSFET employing an LDD structure, the impurity concentration on the channel forming region side of the drain region is set lower than in the other region. In other words, MOSFETs that adopt the LDD structure can reduce the impurity concentration gradient in the pn junction formed between the drain region and the channel formation region, and the electric field strength, thereby reducing the amount of hot carriers generated. Deterioration of threshold voltage can be prevented. The adoption of an LDD structure in a MOSFET becomes a necessary requirement as channel lengths are reduced and gate insulating films are made thinner due to miniaturization due to higher integration.

[0009] When a multiple operating power supply voltage system (step-down operating power supply voltage) is adopted for SRAM, in circuits driven by a 4 [V] step-down operating power supply voltage, such as address buffer circuits and predecoder circuits, the source region and drain of MOSFET are The amount of current flowing between the regions decreases, and the driving ability of the MOSFET decreases.

[0010] In particular, MOSFETs employing an LDD structure
In this case, the impurity concentration on the channel forming region side of the drain region is set low, and the parasitic resistance value in this region increases.
Driving ability is significantly reduced.

(2) Furthermore, in order to improve the driving ability of the MOSFET, if the impurity concentration on the channel forming region side of the drain region of the MOSFET is set high, 5[
V] Power consumption of circuits driven by the operating power supply voltage, specifically, input buffer circuits, write driver circuits, etc., increases. In other words, in a MOSFET that adopts the LDD structure, the impurity concentration on the channel forming region side of the drain region is high,
Since the parasitic resistance value in this region is reduced, the source region
The amount of current flowing between the drain regions increases.

[0012] Moreover, MOS adopting this LDD structure
In FETs, the impurity concentration gradient in the pn junction formed between the drain region and the channel forming region is steep;
As the electric field strength increases, the amount of hot carriers generated increases and the threshold voltage deteriorates.

(3) Furthermore, in an SRAM incorporated in a microcomputer system, TTL (Transistor Transistor) is used as an information input signal.
Logic) is developed in a manner that allows for various operational levels. Currently, the TTL operation level is 0.8[V on the low level side.
], the high level side is standardized to 2.2 [V]. The first stage circuit of the information input signal of the input buffer circuit is NOT
When composed of a circuit (CMOS inverter circuit), p
Each of the channel MOSFET and the n-channel MOSFET is set to a threshold voltage of approximately 0.5 to 0.6 [V].

Therefore, when the NOT circuit, which is the first stage circuit of the input buffer circuit, receives the high level of the TTL operation level, the p-channel MOSFET and the n-channel MOSFET
All of the SFETs conduct (become ON state), and 5[
V] A DC through current flows between the operating power supply voltage and the ground voltage (0 [V]). This through current is a wasteful current that does not directly contribute to circuit operation, leading to an increase in power consumption. In addition, the through current is caused by the source region of the MOSFET.
Since the current flowing between the drain regions increases, the amount of hot carriers generated increases, resulting in deterioration of the threshold voltage of the MOSFET. In the case of an SRAM to which a single operating power supply voltage is supplied, this kind of problem similarly occurs in the first stage circuit of the address buffer circuit.

(4) Furthermore, in order to increase the operating speed, SRAM has an address transition (ATD) located near the address buffer circuit and directly connected to the address buffer circuit.
on Detection) circuits. The ATD circuit detects, for example, switching of the address signal input to the address buffer circuit, and based on this detection, outputs a control signal that equalizes the input signal level of the differential amplifier circuit of the sense amplifier circuit to an intermediate level. When the input signal level of the sense amplifier circuit is equalized to an intermediate level, the speed at which the minute potential, which is the information stored in the memory cell, is amplified from the intermediate input signal level to either the high level side or the low level side is increased. Therefore, the operating speed of the sense amplifier circuit can be increased.

Equalization of the input signal level of the sense amplifier circuit to an intermediate level is performed by a transmission circuit that short-circuits a pair of input/output signal terminals of the sense amplifier circuit. The transmission circuit is an n-channel MOSFE
The structure is such that the source regions of the T and p-channel MOSFETs are shorted together, and the drain regions are shorted together, so that current flows in both directions.

The above-mentioned ATD circuit operates more often (has a higher frequency) than other peripheral circuits such as the address buffer circuit during an information write or read operation, that is, one operation cycle. Frequently. Further, since the ATD circuit operates in any operation cycle such as an information write operation or a read operation, the ATD circuit operates frequently. In other words, the number of times that current flows between the source region and the drain region of the MISFET is large. Therefore, in the case of an SRAM driven by a single operating power supply voltage, the power consumption increases in the ATD circuit, or the threshold voltage of the MOSFET deteriorates due to an increase in the amount of hot carriers generated.

Similarly, in the case of an SRAM driven by a single operating power supply voltage, current flows in both directions in the transmission circuit incorporated in the sense amplifier circuit, and when this alternating current stress is applied, the direct current The threshold voltage deteriorates significantly due to the generation of hot carriers, compared to when stress is applied.

An object of the present invention is to provide a semiconductor integrated circuit device in which a plurality of MISFETs are supplied with mutually different operating power supply voltages.
It is an object of the present invention to provide a technology that can reduce the power consumption of T and improve the driving ability of a MISFET that is supplied with a low operating power supply voltage.

Another object of the present invention is to provide a plurality of MISFETs.
In semiconductor integrated circuit devices to which mutually different operating power supply voltages are supplied, MIS to which a high operating power supply voltage is supplied
It is an object of the present invention to provide a technology that can improve the hot carrier withstand voltage of each FET and MISFET to which a low operating power supply voltage is supplied.

Another object of the present invention is to provide a technique capable of reducing power consumption during operation of a MISFET in a semiconductor integrated circuit device having a MISFET with a large amount of through current during operation. .

Another object of the present invention is to provide a technique capable of improving the hot carrier breakdown voltage of the MISFET in a semiconductor integrated circuit device having a MISFET with a large amount of through current during operation.

Another object of the present invention is to provide a technique capable of reducing power consumption during operation of a MISFET in a semiconductor integrated circuit device having a MISFET that operates many times (operates frequently). It is in.

Another object of the present invention is to
In a semiconductor integrated circuit device having an SFET, the M
The object of the present invention is to provide a technology that can improve the hot carrier withstand voltage of an ISFET.

Another object of the present invention is to provide a semiconductor integrated circuit device having a MISFET in which current flows bidirectionally.
It is an object of the present invention to provide a technique capable of reducing power consumption during operation of the MISFET.

Another object of the present invention is to provide a semiconductor integrated circuit device having a MISFET in which current flows bidirectionally.
The object of the present invention is to provide a technique that can improve the hot carrier breakdown voltage of the MISFET.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0028]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

(1) In a semiconductor integrated circuit device having a MISFET, a first MI supplying a first operating power supply voltage
SFET, and a second operating power supply voltage lower than the first operating power supply voltage.
A second MISFET that supplies an operating power supply voltage and has the same channel conductivity type as the first MISFET is configured;
Compared to the impurity concentration on the channel forming region side of the source region or drain region of the MISFET, the second MISFE
The impurity concentration on the channel forming region side of the source region or drain region of T is configured to be high. the first MISFET;
Each of the second MISFETs has an LDD structure.

(2) First MISFET and this first M
It is constructed of the same channel conductivity type as the ISFET and
The second M has a larger amount of through current during operation than the ISFET.
In a semiconductor integrated circuit device having an ISFET, the second MISFET has a higher impurity concentration than a channel forming region side of the source region or drain region of the first MISFET.
The impurity concentration on the channel forming region side of the source region or drain region of the FET is configured to be low.

(3) First MISFET and this first M
It is constructed of the same channel conductivity type as the ISFET and
In a semiconductor integrated circuit device having a second MISFET that operates more frequently than the ISFET, the first MISFET
The impurity concentration on the channel forming region side of the source region or drain region of the second MISFET is configured to be lower than the impurity concentration on the channel forming region side of the source region or drain region of the second MISFET.

(4) A first MISFET in which current flows in one direction between the source region and the drain region, and this first MISFET
A second MIS configured with the same channel conductivity type as the SFET and in which current flows bidirectionally between the source region and the drain region.
In the semiconductor integrated circuit device having an FET, the first
Compared to the impurity concentration on the channel forming region side of the source region or drain region of the MISFET, the second MISFE
The impurity concentration on the channel forming region side of the source region or drain region of T is configured to be low.

[0033]

[Operation] According to the above-mentioned means (1), the first MIS
It is possible to supply the first operating power supply voltage, which is a high power supply voltage, to the FET, increase the amount of current flowing between the source region and the drain region, and increase the operating speed of the first MISFET. The impurity concentration on the channel forming region side of the channel forming region is set low (increasing the parasitic resistance value on the channel forming region side of the source or drain region), reducing the amount of current flowing between the source region and the drain region, and reducing power consumption. Yes, the second MISF
By supplying the second operating power supply voltage (step-down power supply), which is a low power supply voltage, to the ET, the amount of current flowing between the source region and the drain region can be reduced, and power consumption can be reduced.
The impurity concentration on the channel forming region side of the source region or drain region of the SFET is set high (to reduce the parasitic resistance value on the channel forming region side of the source region or drain region).
, the amount of current flowing between the source region and the drain region of the second MISFET can be increased, and the driving capacity of the second MISFET can be increased, so that the operating speed of the semiconductor integrated circuit device can be increased, the power consumption can be reduced, and the driving capacity can be increased. .

Furthermore, the impurity concentration gradient of the pn junction formed between the drain region and the channel forming region of the first MISFET to which the first operating power supply voltage, which is the high power supply voltage, is supplied is relaxed, and the impurity concentration gradient of the drain region is reduced. Since the electric field strength in the vicinity can be relaxed, the amount of hot carriers generated can be reduced.
In addition to preventing deterioration of the threshold voltage of the first MISFET, the amount of current flowing between the source region and the drain region of the second MISFET to which the second operating power supply voltage, which is the low power supply voltage, is supplied is reduced. It is possible to reduce the amount of generation and prevent the threshold voltage from deteriorating.

According to the above-mentioned means (2), the second M
By setting the impurity concentration on the channel forming region side of the source region or drain region of the ISFET to be low (increasing the parasitic resistance value), the amount of current flowing between the source region and the drain region can be reduced, so power consumption can be reduced.

Furthermore, since the impurity concentration gradient in the pn junction formed between the drain region and the channel forming region of the second MISFET can be relaxed, and the electric field strength near the drain region can be relaxed, the amount of hot carriers generated can be reduced. can be reduced, and deterioration of the threshold voltage of the second MISFET can be prevented.

According to the above-mentioned means (3), the second M
Since the impurity concentration on the channel forming region side of the source region or drain region of the ISFET is set low and the amount of current flowing between the source region and the drain region can be reduced, power consumption can be reduced.

Furthermore, since the impurity concentration gradient in the pn junction formed between the drain region and the channel forming region of the second MISFET can be relaxed, and the electric field strength near the drain region can be relaxed, the amount of hot carriers generated can be reduced. can be reduced, and deterioration of the threshold voltage of the second MISFET can be prevented.

According to the above-mentioned means (4), the second M
The impurity concentration gradient in the pn junction formed between the drain region and the channel forming region of the ISFET can be relaxed, and the electric field strength near the drain region can be relaxed, which reduces the amount of hot carriers generated and improves the efficiency of the second MISFET. Deterioration of threshold voltage can be prevented.

Furthermore, since the impurity concentration on the channel forming region side of the source region or drain region of the second MISFET is set low, the amount of current flowing between the source region and the drain region can be reduced, so that power consumption can be reduced.

The configuration of the present invention will be described below along with an embodiment in which the present invention is applied to an SRAM equipped with an ATD circuit.

In all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[0043]

[Example] (Example 1) This example 1 is an SRAM having a step-down circuit (adopting a multiple operation power supply voltage system).
This is a first embodiment of the present invention in which the present invention is applied to.

FIG. 1 (block circuit diagram) shows the configuration of an SRAM which is a first embodiment of the present invention.

As shown in FIG. 1, in the SRAM, direct peripheral circuits such as a decoder circuit 2, a write driver circuit 12, and a sense amplifier circuit 12 are arranged around a memory cell array 1. The direct peripheral circuit directly controls each of the information write operation and information read operation of the memory cells (24) arranged in the memory cell array 1.

Although the decoder circuit 2 is schematically shown in FIG. 1, it actually consists of an X-system decoder circuit that selects a word line (WL) and a Y-system decoder circuit that selects a complementary data line (DL). configured. This decoder circuit 2 is supplied with address signals A0 to An supplied from an external device to external terminals (bonding pads) 7 through an address buffer circuit 3 and a predecoder circuit 5 in sequence. Similar to the decoder circuit 2 described above, the address signal A
, the address buffer circuit 3, and the pre-decoder circuit 5 are each shown in a simplified manner in FIG. Consists of.

The address buffer circuit 3 receives the address signal A as shown in FIG. 2 (detailed circuit diagram of the address related circuit).
It is comprised of a plurality of address buffer circuits 3A, 3B, . . . connected to each external terminal 7 to which is applied. Each of the plurality of address buffer circuits 3A, 3B, . . . is constructed by connecting a plurality of stages of NOT circuits (inverter circuits) in series. In this embodiment, although not limited to this number of stages, a plurality of address buffer circuits 3A, 3B,
Each of... is constructed by connecting four stages of NOT circuits in series.

[0048] The NOT circuit is a p-channel MISFET.
and n-channel MISFET or complementary MISFE
It is composed of T (CMOS). This complementary MISFET
The gate electrodes of each of the p-channel MISFET and n-channel MISFET are connected to the external terminal 7 in the first stage circuit 3A1, and to the output terminal of the previous stage circuit in the next stage circuit and thereafter. The drain regions of the p-channel MISFET and n-channel MISFET are connected to each other and constitute an output terminal to the next stage circuit. p-channel MIS
A step-down operation power supply voltage VccL is supplied to the source region of the FET. A ground voltage (GND) Vss is supplied to the source region of the n-channel MISFET.

The step-down operation power supply voltage VccL basically has a large number of operating circuits or a large number of circuit operations in one operation cycle (high operating frequency or high frequency).
Used for the purpose of reducing power consumption in circuits. As shown in FIG. 1, this step-down operation power supply voltage VccL is formed by the operation power supply voltage VccH supplied to the external terminal 7 being supplied to the step-down circuit 9 through the operation power supply wiring 10. The step-down operation power supply voltage VccL formed by the step-down circuit 9 is supplied to the address buffer circuit 3 through the step-down power supply wiring 11. This address buffer circuit 3
is a circuit with a large number of operating circuits during one operation cycle. The operating power supply voltage VccH is, for example, 5 [V] (for example, a common operating power supply voltage used in microcomputer systems). The step-down operation power supply voltage VccL
For example, 4 [V] is used. The ground voltage Vss is, for example, 0 [V] (common ground voltage used in the system). Therefore, the SRAM of this embodiment has an operating power supply voltage VccH and a step-down operating power supply voltage VccL.
Adopts multiple operating power supply voltage method using different power supplies.

As shown in FIG. 2, the predecoder circuit 5 is constructed by arranging a plurality of circuits in which NAND circuits and NOT circuits are connected in series. Each of the NAND circuit and NOT circuit of the predecoder circuit 5 is basically composed of complementary MISFETs. Like the address buffer circuit 3, the predecoder circuit 5 has a large number of operating circuits in one operation cycle, so the source region of the p-channel MISFET of the complementary MISFET constituting the predecoder circuit 5 is connected to the step-down operating power supply. A voltage VccL is supplied.

The input signal terminal of the NAND circuit of the predecoder circuit 5 is connected to the address signal line 18. This address signal line 18 is connected to the output signal terminal of the address buffer circuit 3 described above.

The output signal terminal of the predecoder circuit 5 is connected to the input signal terminal of the first stage circuit 2A of the decoder circuit 2, for example, a NOT circuit. The first stage circuit 2A of the decoder circuit 2, the next stage circuit, and the subsequent circuits are basically designed for the purpose of stability of circuit operation and high speed of circuit operation.
An operating power supply voltage VccH is supplied to the source region of the p-channel MISFET of the complementary MISFET.

As shown in FIGS. 1 and 2, an ATD connected to the address buffer circuit 3 is located near the address buffer circuit 3.
A circuit 4 is configured. The ATD circuit 4 detects switching of the address signal A input to the address buffer circuit 3, and based on this detection, sets the input signal level of the differential amplifier circuit (12A, 12B, 12C) of the sense amplifier circuit 12 to an intermediate level. Outputs an equalizing control signal φATD. Based on this control signal φATD, the sense amplifier circuit 12
When the input signal level is equalized to an intermediate level, it is possible to increase the speed at which the minute potential, which is the information stored in the memory cell (24), is amplified from the aforementioned intermediate level to either the high level side or the low level side. In other words, the ATD circuit 4 can increase the operating speed of the sense amplifier circuit 12, that is, the information read operation speed.

As shown in FIG. 2, the ATD circuit 4 is composed of a plurality of ATD circuits 4A, 4B, . . . arranged for each of a plurality of address buffer circuits 3A, 3B, . Each of the plurality of ATD circuits 4A, 4B,...
It is constructed by combining an R circuit and a plurality of NOT circuits, and each of the NOR circuit and NOT circuit is basically a complementary M
Consists of ISFET. The ATD circuit 4 performs multiple operations during an information write operation or an information read operation, that is, one operation cycle. In other words, for one switching of the address signal A input to the address buffer circuit 3 from high level to low level or from low level to high level, the ATD circuit 4 switches twice from low level to high level and from high level to low level. Performs switching (outputs pulse-like control signal φATD). Further, the ATD circuit 4 operates if the address signal A is switched in any operation cycle such as an information write operation or an information read operation. In other words, in the SRAM, the ATD circuit 4 is the circuit that operates the most times and is the circuit that operates most frequently. therefore,
Basically, the step-down operation power supply voltage VccL is supplied to the source regions of the p-channel MISFETs of the complementary MISFETs of the NOR circuit and NOT circuit of the ATD circuit 4.

The input signal terminal of the ATD circuit 4 is connected to the output signal terminal of the first stage circuit (for example, 3A1) of the address buffer circuit 3 or the input signal terminal of the next stage circuit. A.T.
The output signal terminal of the D circuit 4 is connected to the input signal terminal of the ATD decoder circuit 6. ATD decoder circuit 6 is NOR
It is constructed by connecting each of a circuit and a NOT circuit in series. The ATD decoder circuit 6 performs AT every time the ATD circuit 4 operates.
Input the control signal φATD output from the D circuit 4,
Moreover, this control signal φATD is transmitted to the sense amplifier circuit 12.
The number of circuit operations increases. Therefore, the step-down operation power supply voltage VccL is supplied to the source regions of the p-channel MISFETs of the complementary MISFETs of the NOR circuit and NOT circuit of the ATD decoder circuit 6, respectively.

Each of the address buffer circuit 3, predecoder circuit 5, ATD circuit 4, and ATD decoder circuit 6 described above constitutes an indirect peripheral circuit that controls the decoder circuit 2, which is a direct peripheral circuit.

The write driver circuit 12, as shown in FIG.
Information input signals I0 to In supplied from 5 are input. Further, the write driver circuit 12 receives a control system signal that controls the write operation of information output from the control buffer circuit 16 . The control buffer circuit 16 receives a column address strobe signal CS* (* represents an inverted signal, the same applies hereinafter), a write enable signal WE*, and an output enable signal OE* from an external device via an external terminal 17. control system signals are input. Each of the input buffer circuit 14 and the control buffer circuit 16 is mainly composed of complementary MISFETs, similarly to the address buffer circuit 3 and the like described above. These complementary MISFETs are connected to the input buffer circuit 14.
, p
The operating power supply voltage Vc is applied to the source region of the channel MISFET.
cH is supplied.

As shown in FIG. 1, the sense amplifier circuit 12 is connected to an external terminal 15 with an output buffer circuit 13 interposed therebetween.
The information output signals O0 to On are output to the terminals. A control system signal for controlling the read operation of information output from the control buffer circuit 16 is input to each of the sense amplifier circuit 12 and the output buffer circuit 13.

As shown in FIG. 3 (detailed circuit diagram of the sense amplifier circuit), the sense amplifier circuit 12 includes differential amplifier circuits 12A, 12B, and 12C, and a transmission circuit 1.
It is mainly composed of 2D and 12E. In each of the differential amplifier circuits 12A and 12B, the gate electrode of the driving MISFET is connected to the common data line CDL. The differential amplifier circuit 12A determines and amplifies the information stored in the memory cell (24), and outputs only one of the pieces of information to the differential amplifier circuit 12C. The differential amplifier circuit 12B determines and amplifies the information stored in the memory cells, and outputs only the other information to the differential amplifier circuit 12C. The differential amplifier circuit 12C further determines and amplifies the information output signals of the differential amplifier circuits 12A and 12B, and outputs the signals to the output buffer circuit 13 via the transfer circuit 22 and the data bus signal line DBL. .

The aforementioned differential amplifier circuits 12A, 12B, 12
Each of C is an n-channel MISFET as a driving MISFET.
p-channel MISFET as SFET and load element
It is composed of complementary MISFETs. An operating power supply voltage VccH is supplied to the source region of the p-channel MISFET of this complementary MISFET for the purpose of improving the stability of circuit operation and increasing the speed of circuit operation. n
The source region of the channel MISFET is connected to the ground voltage Vss.
is supplied.

The transmission circuit 12D of the sense amplifier circuit 12 equalizes the input signal level of each of the differential amplifier circuits 12A and 12B to an intermediate level. The transmission circuit 12E equalizes the levels of the pair of input signals of the differential amplifier circuit 12C to an intermediate level. Each of the transmission circuits 12D and 12E is composed of a p-channel MISFET and an n-channel MISFET whose source regions are connected to each other and whose drain regions are connected to each other, and whose gate electrodes are connected to the output from the ATD circuit 4 described above. It is controlled by a control signal φATD. Current flows in both directions in each of the transmission circuits 12D and 12E.

As shown in FIG. 3, the common data line CDL consists of two signal lines to which complementary information signals are applied, and between these two signal lines there is a A transmission circuit 21 is configured which is controlled by a control signal φATD.

The transfer circuit 22 includes transmission circuits 22A, 22B and N, as shown in FIG.
Mainly composed of OT circuits.

As shown in FIG. 3, the data bus signal line DBL is composed of two signal lines to which complementary information output signals are transmitted, and a control signal φA is connected between these two signal lines.
A transmission circuit 23 controlled by TD is configured.

The memory cell array 1 shown in FIG. 1, as shown in FIGS. 3 and 4 (memory cell circuit diagrams),
A plurality of memory cells 24 for storing information of bit] are arranged in a matrix. Memory cell 24 is connected to complementary data line D
It is arranged at each intersection between L and word line WL. As shown in FIG. 4, the memory cell 24 includes a flip-flop circuit (differential amplifier circuit) as an information storage section and two transfer M
It is composed of ISFETQt. The flip-flop circuit is composed of two driving MISFETs Qd and two high resistance load elements R. MISFETQt for transfer, M for drive
Each of ISFETQd is an n-channel MISFE
Consists of T. The high resistance load element R is basically composed of a polycrystalline silicon film (or an amorphous silicon film).

The flip-flop circuit of the memory cell 24 is designed to stabilize information retention characteristics, ensure an operating margin,
For the purpose of increasing the operating speed, etc., the operating power supply voltage Vcc
H is supplied. Further, the ground voltage Vss is supplied to the flip-flop circuit.

Note that in the memory cell 24, the high resistance load element R is replaced with a p-channel MISFET, and a so-called fully complementary type M
It may be configured with ISFET (full CMOS). The p-channel MISFET is basically a driving MISFETQ.
It is constructed on the main surface of the semiconductor substrate like d and transfer MISFET Qt, but it is constructed with an SOI structure in which the source region, drain region, and channel formation region are formed in a polycrystalline silicon film laminated on the main surface of the semiconductor substrate. You may.

The word line WL is connected to the X-system decoder circuit of the decoder circuit 2 shown in FIG. 1, and the X-system decoder circuit selects the word line WL connected to the memory cell 24 at a predetermined address.

The complementary data line DL is connected at one end to the load circuit 19, as shown in FIG. This load circuit 19 connects the operating power supply voltage VccH to the complementary data line DL via an n-channel MISFET as a load element.
supply to. The other end of the complementary data line DL is connected to the sense amplifier circuit 12 via the aforementioned common data line CDL, and is also connected to the Y-system decoder circuit of the decoder circuit 2 via the Y-system switch circuit 20. be done. The Y-system switch circuit 20 is mainly composed of a transmission circuit, and the operation of this transmission circuit is controlled by a Y-system decoder circuit. In other words, the decoder circuit 2 can select the complementary data line DL connected to the memory cell 24 at a predetermined address.

Each of the input buffer circuit 14, output buffer circuit 13, and control buffer circuit 16 described above is
An indirect peripheral circuit that controls the write driver circuit 12 or sense amplifier circuit 12, which is a direct peripheral circuit, is configured.

Next, the information writing operation and information reading operation of the SRAM described above will be briefly explained using FIGS. 1 and 2 described above.

First, the writing operation of information in the SRAM will be explained.

In the SRAM, when an address signal A from an external device is input to an external terminal 7, the address signal A is inputted to the external terminal 7, and the address signal A is inputted to the external terminal 7, and then the address signal A is inputted to the external terminal 7. Select memory cell 24. This selection of memory cell 24 is performed by selecting the word line WL and complementary data line DL that connect it.

On the other hand, an information input signal I of information 1 or information 0 is input from an external device to the external terminal 15, and the information is input to the selected memory cell 24 through the input buffer circuit 14 and write driver circuit 12. written. The operations of the input buffer circuit 14 and the write driver circuit 12 are controlled by control system signals output from the control buffer circuit 16.

Next, the operation of reading information from the SRAM will be explained.

In the SRAM, when an address signal A from an external device is input to an external terminal 7, the address signal A is inputted to the external terminal 7, and the address signal A is inputted to the external terminal 7, and the address signal A is inputted to the external terminal 7. Select memory cell 24. The information stored in the memory cell 24 selected by this address signal A is determined and amplified by the sense amplifier circuit 12. This amplified information output signal passes through each of the transfer circuit 22 and the output buffer circuit 13 in sequence, and is output as an information output signal O from the external terminal 15 to an external device. Each of the sense amplifier circuit 12, transfer circuit 22, and output buffer circuit 13 is controlled by a control system signal output from the control buffer circuit 16 described above.

Next, the aforementioned SRAM memory cell 24,
Complementary type M that constitutes each of the direct peripheral circuit and indirect peripheral circuit
The specific structure of the ISFET will be briefly explained using FIG. 5 (a sectional view of the main part of the SRAM).

As shown in FIG. 5, the SRAM is mainly composed of an n- type semiconductor substrate 30 made of single crystal silicon. The p-channel MISFET of this n-type semiconductor substrate 30
An n-type well region 31 is formed on the main surface of the region where Qp is formed. n-channel MI of n-type semiconductor substrate 30
A p-type well region 3 is provided on the main surface of the SFET formation region.
2 is configured.

The SRAM of this embodiment is a complementary MISFE
T n-channel MISFET
It consists of two types, Qn1 and Qn2. One n-channel MISFET Qn1 has a p- type well region 32 in a region defined by an element isolation insulating film (field insulating film) 33 and a p-type channel stopper region 34.
consists of the main surface of In other words, n-channel MISFET
Qn1 is a channel forming region (p-type well region 32
), a gate insulating film 35, a gate electrode 36, a source region, and a drain region.

The gate electrode 36 is composed of, for example, a composite film consisting of a polycrystalline silicon film and a WSi film laminated on top of the polycrystalline silicon film. In addition to this, the gate electrode 36 may be composed of a single layer of a polycrystalline silicon film, a high melting point metal film, a high melting point metal silicide film, or a composite film of these (except in the case described above).

Each of the source region and drain region is composed of an n + -type semiconductor region 41 with a high impurity concentration and an n-type semiconductor region 37 with a low impurity concentration. n with low impurity concentration
The semiconductor region 37 is electrically connected to the n+ type semiconductor region 41 and is formed between the n+ type semiconductor region 41 and the channel formation region (on the channel formation region side of the n+ type semiconductor region 41). In other words, this n-type semiconductor region 37 is configured as a so-called LDD section, and is an n-type semiconductor region 37 of the LDD structure.
Configure channel MISFETQn1. Basically, the LDD structure can reduce the impurity concentration gradient at the pn junction formed between the drain region and the channel formation region, and the electric field strength in this region, thereby reducing the amount of hot carriers generated. This can prevent the threshold voltage of n-channel MISFET Qn1 from deteriorating. Although the n-channel MISFET Qn1 of this embodiment is not limited to this value,
The threshold voltage is set to 0.4 to 0.6 [V].

Among the source and drain regions, the n-type semiconductor region 37 with a low impurity concentration is formed by using the ion implantation method using the gate electrode 36 as an impurity introduction mask. The n+ type semiconductor region 41 with a high impurity concentration is formed by using an ion implantation method using the sidewall spacer 40 as an impurity introduction mask.

A wiring 46 is electrically connected to each of the n+ type semiconductor regions 41 of the source region and drain region of the n-channel MISFET Qn1. The wiring 46 is formed on the interlayer insulating film 45 and is connected to the n+ type semiconductor region 41 through connection holes formed in the interlayer insulating films 43 and 45. The wiring 46 is formed of, for example, an aluminum alloy film.

The other n-channel MISFETQn2 is
Similarly, it is formed on the main surface of the p- type well region 32 in a region surrounded by the element isolation insulating film 33 and the p-type channel stopper region 34. In other words, the n-channel MISFET Qn2 includes a channel forming region (p-type well region 32), a gate insulating film 35, and a gate electrode 36.
, is mainly composed of a source region and a drain region.

Each of the source region and drain region is composed of an n+ type semiconductor region 41 with a high impurity concentration and an n type semiconductor region 38 with a low impurity concentration. n with low impurity concentration
type semiconductor region 38 is the aforementioned n-channel MISFETQ.
Similarly to the low impurity concentration n-type semiconductor region 37 of n1, the LD
A D structure is formed, but the impurity concentration is set lower than that of this n-type semiconductor region 37. That is, n-channel MI
The n-type semiconductor region 38 of SFETQn2 is an n-channel M
The resistance value is set higher than that of the n-type semiconductor region 38 of ISFETQn1. n-channel MISFET of this embodiment
Similarly to the aforementioned n-channel MISFET Qn1, Qn2 is set to have a threshold voltage of, for example, 0.4 to 0.6 [V].

A wiring 46 is electrically connected to each of the n+ type semiconductor regions 41 of the source region and drain region of the n-channel MISFET Qn2.

p channel MI of the complementary MISFET
SFETQp is formed on the main surface of the n- type well region 31 within a region defined by the element isolation insulating film 33. That is, the p-channel MISFET Qp is mainly composed of a channel forming region (n- type well region 31), a gate insulating film 35, a gate electrode 36, a source region, and a drain region.

Each of the source region and drain region is composed of a p + -type semiconductor region 42 with a high impurity concentration and a p-type semiconductor region 39 with a low impurity concentration. p of low impurity concentration
type semiconductor region 39 is the aforementioned n-channel MISFETQn.
Similar to the low impurity concentration n-type semiconductor region 37 of No. 1, the LDD
Configure the structure. p-channel MISFETQ of this embodiment
p is set to a threshold voltage of 0.4 to 0.6 [V], for example, similarly to the above-mentioned n-channel MISFET Qn1.

A wiring 46 is electrically connected to each p + -type semiconductor region 42 of the source region and drain region of the p-channel MISFET Qp.

When an SRAM adopts a multiple operation power supply voltage system, as shown in FIG. circuits with a large number of elements)
Specifically, the address buffer circuit 3 and the predecoder circuit 5
A step-down operating power supply voltage VccL is supplied to each of the two. In other words, each of the address buffer circuit 3 and the predecoder circuit 5 reduces the amount of current used during operation, thereby reducing power consumption. Similarly, in one operation cycle, a large number of circuits operate at once, and the number of circuit operations is the highest (highest operation frequency) in SRAM, specifically, A.
A step-down operation power supply voltage VccL is supplied to each of the TD circuit 4 and the ATD decoder circuit 6. Similarly, the ATD circuit 4,
Each of the ATD decoder circuits 6 can achieve low power consumption. In other words, the step-down operation power supply voltage usage area 8 including each of the address buffer circuit 3, pre-decoder circuit 5, ATD circuit 4, and ATD decoder circuit 6 shown in FIG. A voltage VccL is supplied.

The complementary MISFETs constituting each circuit in the step-down operation power supply voltage use region 8 to which this step-down operation power supply voltage VccL is supplied are basically n-type semiconductors that are LDD sections with a high impurity concentration. n with area 37
It consists of a channel MISFETQn1. In other words, n
The channel MISFET Qn1 has a step-down operation power supply voltage Vc.
Low power consumption can be ensured by supplying cL, and LD
Since the resistance value of the n-type semiconductor region 37, which is the D portion, can be lowered and the amount of current flowing between the source region and the drain region can be increased, the driving ability can be improved. Also, n-channel MISF
ETQn1 can reduce the amount of current flowing between the source region and the drain region based on the supply of the step-down operating power supply voltage VccL, or reduce the electric field strength near the drain region, thereby reducing the amount of hot carriers generated. , deterioration of threshold voltage can be prevented.

On the other hand, the SRAM includes circuits arranged in areas other than the step-down operation power supply voltage usage area 8, specifically, the memory cell array 1, the decoder circuit 2, and the write driver circuit 1.
2. Supplying the operating power supply voltage VccH to the sense amplifier circuit 12, input buffer circuit 14, output buffer circuit 13, control buffer circuit 16, etc. In other words, these circuits are basically configured for the purpose of increasing the stability of circuit operation and increasing the speed of circuit operation. This operating power supply voltage V
Complementary MIS that constitutes each circuit to which ccH is supplied
The FET is an n-channel MISFETQ having an n-type semiconductor region 38 which is an LDD portion with a low impurity concentration.
Consists of n2. In other words, n-channel MISFETQ
n2 can ensure the stability of circuit operation and increase the speed of circuit operation, and can also increase the resistance value of the n-type semiconductor region 38, which is the LDD portion, and reduce the amount of current flowing between the source region and the drain region. Therefore, it is possible to reduce power consumption. Furthermore, based on the fact that the impurity concentration of the n-type semiconductor region 38, which is the LDD portion, is set low, the n-channel MISFET Qn2 alleviates the impurity concentration gradient of the pn junction formed between the drain region and the channel formation region. Since the electric field strength can be relaxed, the amount of hot carriers generated can be reduced, and deterioration of the threshold voltage can be prevented.

Next, the above-mentioned SRAM manufacturing method will be briefly explained using FIGS. 6 to 9 (cross-sectional views of main parts shown for each manufacturing process).

First, an n- type semiconductor substrate 30 is prepared,
An n- type well region 31 and a p- type well region 32 are formed on the main surface of this n- type semiconductor substrate 30, respectively.

Next, the n- type well region 31, the p-
An element isolation insulating film 33 is formed on the main surface of each non-active region of the mold well region 32 . The element isolation insulating film 33 is formed of a silicon oxide film formed by selectively oxidizing the main surface of the substrate using a thermal oxidation method. In substantially the same manufacturing process as that for forming element isolation insulating film 33, p-type channel stopper region 34 is formed on the main surface of p- type well region 32 below element isolation insulating film 33.

Next, the n- type well region 31, the p-
A gate insulating film 35 and a gate electrode 36 are sequentially formed on the main surface of each active region of the type well region 32 . The gate insulating film 35 is formed of a silicon oxide film obtained by oxidizing the substrate surface using a thermal oxidation method. The gate electrode 36 is formed of a composite film in which a polycrystalline silicon film deposited by a CVD method and a WSi film deposited by a sputtering method or a CVD method are sequentially laminated.

Next, among the complementary MISFETs, an n-channel MISFETQ whose LDD portion is set to a high impurity concentration
In the formation region n1, as shown in FIG. 6, an n-type semiconductor region 37 with a low impurity concentration is formed on the main surface of the p--type well region 32. The n-type semiconductor region 37 is, for example, 2×1
It is formed by introducing P at an impurity concentration of 0.013 [atoms/cm2] by ion implantation. When introducing this P, the gate electrode 36 and the photoresist film 48 shown by broken lines in FIG. 6 are used as impurity introduction masks.

Next, among the complementary MISFETs, an n-channel MISFETQ whose LDD portion is set to a low impurity concentration
In the formation region n2, as shown in FIG. 7, an n-type semiconductor region 38 with a low impurity concentration is formed on the main surface of the p--type well region 32. For example, the n-type semiconductor region 38 is 1×1
It is formed by introducing P at an impurity concentration of 0.013 [atoms/cm2] by ion implantation. When introducing this P, the gate electrode 36 and the photoresist film 49 shown by broken lines in FIG. 7 are used as impurity introduction masks.

[0099] The n-type semiconductor region 37 which is the LDD section described above
, 38 may be formed by basically changing the order of the manufacturing steps. That is, after forming the n-type semiconductor region 38 which is set to have a low impurity concentration in advance, the n-type semiconductor region 37 which is set to have a high impurity concentration may be formed. Further, after forming an n-type semiconductor region 38 whose impurity concentration is set to be low in advance in the formation region of each of the n-channel MISFETQn1 and Qn2, the n-channel MISFETQ
An n-type impurity may be further introduced into the formation region of n1, and the n-type semiconductor region 38 in this formation region may be formed into the n-type semiconductor region 37 having a high impurity concentration.

Next, in the formation region of the p-channel MISFET Qp among the complementary MISFETs, as shown in FIG. Form. This p
The type semiconductor region 39 has, for example, 2×10 13 [atoms/
It is formed by introducing BF2 with an impurity concentration of [cm2] by ion implantation. When introducing this BF2, the gate electrode 36 and the photoresist film 50 shown by broken lines in FIG. 8 are used as impurity introduction masks.

In the SRAM of this embodiment, complementary type M
Although only one type of p-channel MISFETQp of the ISFET, that is, only one type of p-type semiconductor region 39 serving as the LDD section, the present invention is applicable to the above-mentioned n-channel MISFET
Two types of p with different impurity concentrations are available for the same purpose as TQn.
A type semiconductor region 39 may also be formed.

Next, the n-channel MISFETQn1
, Qn2, and p-channel MISFET Qp, a sidewall spacer 40 is formed on the sidewall of the gate electrode 36. The sidewall spacer 40 is formed by depositing a silicon oxide film by, for example, the CVD method, and then subjecting the silicon oxide film to anisotropic etching such as RIE to an amount corresponding to the thickness of the deposited film.

Next, the n-channel MISFETQn1
, Qn2, an n + -type semiconductor region 41 with a high impurity concentration is formed on the main surface of the active region of the p - -type well region 32 . The n+ type semiconductor region 41 is formed, for example, by introducing As with an impurity concentration of 5×10 15 [atoms/cm 2 ] by ion implantation. When introducing this As, the sidewall spacer 40 and a photoresist film (not shown) are used as an impurity introduction mask. By forming the n+ type semiconductor region 41, n-channel MISFETs Qn1, Q
Each of n2 is completed.

Next, in the formation region of the p-channel MISFET Qp, as shown in FIG. 9, a p+ type semiconductor region 42 with a high impurity concentration is formed on the main surface of the active region of the n- type well region 31. The p+ type semiconductor region 42 is formed, for example, by introducing BF2 at an impurity concentration of 2×10 15 [atoms/cm 2 ] by ion implantation. When introducing this BF2, the sidewall spacer 40 and a photoresist film (not shown) are used as an impurity introduction mask. By forming the p+ type semiconductor region 42, a p-channel MISFET
Qp is completed.

Next, the n-channel MISFETQn1
, Qn2, and p-channel MISFET Qp, an interlayer insulating film 43 is formed over the entire surface of the substrate. After this, gate wiring (for example, polycrystalline silicon film. This polycrystalline silicon film is used as high resistance load element R and operating power supply voltage wiring)
44, an interlayer insulating film 45, and a wiring 46 are formed in sequence. By performing these series of manufacturing steps, the above-mentioned figure 1
The SRAM shown in is completed.

In this way, n-channel MISFETQn
In the SRAM having the operating power supply voltage VccH (5
[V]), and an n-channel MISFET Qn1 of the same channel conductivity type as the n-channel MISFET Qn2, which supplies a step-down operating power supply voltage VccL (4 [V]) lower than the operating power supply voltage VccH. Configure the n-channel MISF
Compared to the impurity concentration on the channel formation region side (n-type semiconductor region 38) of the source region or drain region of the n-channel MISFETQn1, the impurity concentration on the channel formation region side (n-type semiconductor region 38) of the source region or drain region of the n-channel MISFETQn1 is
7) with a high impurity concentration. With this configuration, the operating power supply voltage VccH, which is a high power supply voltage, is supplied to the n-channel MISFET Qn2, increasing the amount of current flowing between the source region and the drain region, and increasing the amount of current flowing between the source region and the drain region.
In addition to increasing the operating speed of TQn2, the impurity concentration on the channel forming region side of the source region or drain region of n-channel MISFET Qn2 is set low (LD
increasing the parasitic resistance value of the D section), reducing the amount of current flowing between the source region and the drain region, reducing power consumption, and supplying the n-channel MISFET Qn1 with a step-down operation power supply voltage VccL, which is a low power supply voltage, The amount of current flowing between the source region and the drain region can be reduced to reduce power consumption, and the impurity concentration on the channel forming region side of the source region or drain region of n-channel MISFET Qn1 can be set high (the parasitic resistance value of the LDD section can be reduced). ), n
The amount of current flowing between the source region and the drain region of channel MISFET Qn1 is increased, and the n-channel MISFET
Since the driving capability of Qn1 can be increased, the operating speed of the SRAM can be increased, power consumption can be reduced, and driving capability can be increased.

Furthermore, the n-channel MISFETQn2 is supplied with the operating power supply voltage VccH, which is the high power supply voltage.
The impurity concentration gradient in the pn junction formed between the drain region (n-type semiconductor region 38) and the channel formation region can be relaxed, and the electric field strength near the drain region can be relaxed, so the amount of hot carriers generated can be reduced. reduce, n-channel M
It is possible to prevent the threshold voltage of ISFETQn2 from deteriorating, and to reduce the step-down operation power supply voltage Vc, which is the low power supply voltage.
In the n-channel MISFET Qn1 driven by cL, the amount of current flowing between the source region and the drain region is reduced, so the amount of hot carriers generated can be reduced and deterioration of the threshold voltage can be prevented.

(Example 2) In this example 2, SRA
This is a second embodiment of the present invention in which the power consumption of a specific circuit in which a through current flows between power supplies during operation is reduced or the hot carrier withstand voltage is improved.

When the SRAM according to the second embodiment of the present invention adopts the single operating power supply voltage system driven by the operating power supply voltage VccH without the step-down circuit 9, the address shown in each of FIGS. 1 and 2 is Complementary MISFETs in the first stage circuits (for example, 3A1) of each of the plurality of address buffer circuits 3A, 3B, .
It consists of TQn2. Similarly, the complementary MISFETs in the first stage circuits of the input buffer circuit 14 and control buffer circuit 16 shown in FIG. 1 are n-channel MISFETs.
It is composed of SFETQn2. Complementary MISFETs in circuits other than these first-stage circuits are n-channel MISFETQ having an n-type semiconductor region 37 set to a high impurity concentration.
Consists of n1.

[0110] SRAM operates at TTL operation level (0.8 to 2
．． 2 [V]), the complementary MISFETs in the first stage circuit are n-channel MISFETQn and p-channel MISFETQn when the input signal is at high level.
Both ISFETQp are conductive and the operating power supply voltage Vc
A through current flows between cH and ground voltage Vss. This through current flows through the n-channel M
By configuring the ISFETQn2, the impurity concentration can be reduced in the n-type semiconductor region (LDD section) 38 set to a low impurity concentration. As a result, the complementary MISFET of the first stage circuit
It is possible to reduce power consumption or improve hot carrier withstand voltage.

[0111] Furthermore, when a multiple operating power supply voltage system is adopted for the SRAM, the address buffer circuit 3 is supplied with the step-down operating power supply voltage VccL, and this address buffer circuit 3
The complementary MISF of the first stage circuits of the input buffer circuit 14 and the control buffer circuit 16 can reduce power consumption and improve hot carrier withstand voltage in the first stage circuit.
ET is composed of an n-channel MISFETQn2.

[0112] Furthermore, when adopting a multiple operating power supply voltage system for SRAM, the operating power supply voltage V shown in FIGS. 1 and 2 above is
A boundary portion between the circuit to which ccH is supplied and the step-down operation power supply voltage use region 8 to which the step-down operation power supply voltage VccL is supplied;
Specifically, the complementary MIS of the first stage circuit 2A of the decoder circuit 2
FET is an n-type semiconductor region (
It is composed of an n-channel MISFETQn2 having an LDD section) 38. The complementary MISFET of this first stage circuit 2A is:
Since the output stage circuit of the predecoder circuit 5, which is the preceding stage circuit, is driven by the step-down operation power supply voltage VccL, when the output signal level of the output stage circuit is at a high level (for example, 4 [V] - threshold voltage), A through current flows. This through current flows through the n-channel M
By configuring the ISFETQn2, the impurity concentration can be reduced in the n-type semiconductor region (LDD section) 38 set to a low impurity concentration. As a result, the complementary MISF of the first stage circuit 2A
It is possible to reduce power consumption of ET or improve hot carrier withstand voltage.

Complementary MI of circuits other than the first stage circuit 2A
SFET is basically an n-channel MISFE with an n-type semiconductor region (LDD section) 37 set to a high impurity concentration.
Consists of TQn1.

In this way, the first stage circuit 3A1 of the address buffer circuit 3, the first stage circuit of the input buffer circuit 14, etc., have n-channel MISFETQn with a large amount of through current during operation.
In the SRAM, the impurity concentration on the channel forming region side (LDD part) of the source or drain region of the n-channel MISFET Qn, which has a large amount of through current during the operation, is configured to be low (configured with the n-channel MISFET Qn2). With this configuration, the n-channel MISF
By setting the impurity concentration on the channel forming region side of the source region or drain region of ETQn2 low (increasing the parasitic resistance value), the amount of current flowing between the source region and the drain region can be reduced, so power consumption can be reduced. Also, a pn formed between the drain region (n-type semiconductor region 38) of the n-channel MISFET Qn2 and the channel formation region
Since the impurity concentration gradient at the junction can be relaxed and the electric field strength near the drain region can be relaxed, the amount of hot carriers generated can be reduced and the threshold voltage of n-channel MISFET Qn2 can be prevented from deteriorating.

(Embodiment 3) In the present embodiment 3, in an SRAM that adopts a single operating power supply voltage system, the power consumption of a circuit that operates many times (circuit operation frequency is high) can be reduced or the hot carrier withstand voltage can be increased. This is a third embodiment of the present invention in which improvements have been made.

When the SRAM according to the third embodiment of the present invention adopts the single operation power supply voltage method, the SRAM of the complementary type that constitutes each of the ATD circuit 4 and the ATD decoder circuit 6 shown in FIGS. 1 and 2, respectively, is used. The MISFET is constituted by an n-channel MISFETQn2 having an n-type semiconductor region (LDD section) 38 set to a low impurity concentration. ATD circuit 4, ATD
As explained in the first embodiment, each of the decoder circuits 6 operates many times, so each decoder circuit 6 is an n-channel MISFE.
Adoption of TQn2 can reduce power consumption or improve hot carrier withstand voltage.

In this way, n-channel MISFE circuits that operate many times, such as the ATD circuit 4 and the ATD decoder circuit 6,
In the SRAM having TQn, the impurity concentration on the channel forming region side (LDD part) of the source or drain region of the n-channel MISFETQn, which undergoes many circuit operations, is configured to be low (configured with the n-channel MISFETQn2). With this configuration, the n-channel MISFE
The impurity concentration on the channel formation region side (n-type semiconductor region 38) of the source or drain region of TQn2 is set low, and the amount of current flowing between the source region and the drain region can be reduced, so power consumption can be reduced. In addition, the impurity concentration gradient in the pn junction formed between the drain region and the channel forming region of the n-channel MISFET Qn2 can be relaxed, and the electric field strength near the drain region can be relaxed, thereby reducing the amount of hot carriers generated. and n channel M
Deterioration of the threshold voltage of ISFETQn2 can be prevented.

(Embodiment 4) Embodiment 4 is an SRAM that employs a single operating power supply voltage method, and is an example of the present invention, which aims to reduce the power consumption of a circuit in which current flows bidirectionally or to improve the hot carrier withstand voltage. This is a fourth embodiment of the invention.

In the SRAM according to the fourth embodiment of the present invention, when a single operating power supply voltage system is adopted, the transmission circuits 12D and 1 of the sense amplifier circuit 12 shown in FIG.
2E, transmission circuit of Y system switch circuit 20, transmission circuit 22 of transfer circuit 22
The complementary MISFETs of A, 22B, and transmission circuits 21 and 23 are set to low impurity concentrations.
n-channel MISFETQn2 with type semiconductor region 38
Consists of. In the n-channel MISFET Qn2 of these transmission circuits, current flows bidirectionally, that is, in an alternating current manner, but since the n-type semiconductor region 38, which is the LDD portion, is set to have a low impurity concentration, the hot carrier breakdown voltage can be improved.

[0120] In this way, transmission circuits etc.
Current flows bidirectionally between the source region and the drain region n
In an SRAM with channel MISFETQn,
The impurity concentration on the channel forming region side (LDD portion) of the source region or drain region of the n-channel MISFETQn is configured to be low (configured by the n-channel MISFETQn2). With this configuration, the n-channel MISFE
The impurity concentration on the channel formation region side (n-type semiconductor region 38) of the source or drain region of TQn2 is set low, and the amount of current flowing between the source region and the drain region can be reduced, so power consumption can be reduced. In addition, the impurity concentration gradient in the pn junction formed between the drain region and the channel forming region of the n-channel MISFET Qn2 can be relaxed, and the electric field strength near the drain region can be relaxed, thereby reducing the amount of hot carriers generated. and n channel M
Deterioration of the threshold voltage of ISFETQn2 can be prevented.

In addition to the transmission circuit described above, the present invention also provides an n-channel MISF in which current flows bidirectionally.
ET, for example, MISFETQt for transfer of memory cell 24
is composed of n-channel MISFETQn2, and other than that,
For example, the driving MISFETQd of the memory cell 24 may be configured with an n-channel MISFETQn1.

[0122] As described above, the invention made by the present inventor is as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, it goes without saying that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof.

For example, the present invention is not limited to SRAM, but can be applied to DRAM (Dynamic Random Access
Semiconductor storage devices such as ss Memory), logic LSI
It can be widely applied to semiconductor integrated circuit devices such as.

Further, the present invention is not limited to semiconductor integrated circuit devices having complementary MISFETs, but also includes complementary MISFETs.
It can be applied to semiconductor integrated circuit devices that include both ET and bipolar transistors.

[0125] The present invention also provides an M
Instead of an ISFET, the present invention can be applied to a MISFET that employs a so-called double drain structure, which has an n-type semiconductor region with a high impurity concentration on the main surface of an n-type semiconductor region with a low impurity concentration.

[0126]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device in which different operating power supply voltages are supplied to a plurality of MISFETs, it is possible to reduce the power consumption of the MISFETs to which a high operating power supply voltage is supplied, and to reduce the power consumption of the MISFETs to which a low operating power supply voltage is supplied.
The driving ability of SFET can be improved.

In the semiconductor integrated circuit device, the hot carrier withstand voltage of each of the MISFET to which a high operating power supply voltage is supplied and the MISFET to which a low operating power supply voltage is supplied can be improved.

MISFET with large amount of through current during operation
In the semiconductor integrated circuit device having the MISFE
Power consumption during operation of T can be reduced.

[0130] In the semiconductor integrated circuit device, the M
The hot carrier withstand voltage of ISFET can be improved.

In a semiconductor integrated circuit device having a MISFET that operates many times, power consumption during operation of the MISFET can be reduced.

[0132] In the semiconductor integrated circuit device, the M
The hot carrier withstand voltage of ISFET can be improved.

In a semiconductor integrated circuit device having a MISFET through which current flows in both directions, power consumption during operation of the MISFET can be reduced.

[0134] In the semiconductor integrated circuit device, the M
The hot carrier withstand voltage of ISFET can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the configuration of an SRAM that is a first embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of an address related circuit of the SRAM.

FIG. 3 is a detailed circuit diagram of the sense amplifier circuit of the SRAM.

FIG. 4 is a circuit diagram of a memory cell of the SRAM.

FIG. 5 is a sectional view of a main part of a complementary MISFET of the SRAM.

FIG. 6 is a sectional view of a main part of a complementary MISFET in a first step in the SRAM manufacturing method.

FIG. 7 is a sectional view of main parts in a second step.

FIG. 8 is a sectional view of main parts in the third step.

FIG. 9 is a sectional view of main parts in the fourth step.

[Explanation of symbols]

2...Decoder circuit, 3...Address buffer circuit, 4...A
TD circuit, 5... Predecoder circuit, 6... ATD decoder circuit, 8... Step-down operation power supply voltage usage area, 9... Step-down circuit,
10... Operating power supply voltage wiring, 11... Step-down operating power supply voltage wiring, 12... Sense amplifier circuit, 2A, 3A1... First stage circuit,
24...Memory cell, 12D, 12E, 21, 22A, 2
2B, 23... Transmission circuit, 30... Semiconductor substrate, 31, 32... Well region, 37, 38, 39... Semiconductor region (LDD section), 41, 42... Semiconductor region, Q...M
ISFET.

Claims (5)

[Claims] Claim 1: In a semiconductor integrated circuit device having a MISFET, a first MIS supplies a first operating power supply voltage.
FET, and a second MISFET having the same channel conductivity type as the first MISFET, which supplies a second operating power supply voltage lower than the first operating power supply voltage;
Compared to the impurity concentration on the channel forming region side of the source region or drain region of the ISFET, the second MISFET
1. A semiconductor integrated circuit device characterized in that the impurity concentration on the channel forming region side of the source region or drain region is configured to be high. Claim 2: A first MISFET and this first MISFET.
The first MI is configured with the same channel conductivity type as the SFET.
The second MI has a larger amount of through current during operation than the SFET.
In a semiconductor integrated circuit device having an SFET, the impurity concentration of the second MISFET is higher than that of the source region or the drain region of the first MISFET on the channel forming region side.
A semiconductor integrated circuit device characterized in that the impurity concentration on the channel forming region side of the source region or drain region of an ET is configured to be low. Claim 3: A first MISFET and this first MISFET.
The first MI is configured with the same channel conductivity type as the SFET.
In a semiconductor integrated circuit device having a second MISFET that operates more often than the SFET, the first MISFET
A semiconductor integrated circuit device characterized in that the impurity concentration on the channel forming region side of the source region or drain region of the second MISFET is lower than the impurity concentration on the channel forming region side of the source region or drain region of the second MISFET. 4. A first MISFET in which a current flows in one direction between a source region and a drain region, and the first MISFET.
A second MISF configured with the same channel conductivity type as the FET and in which current flows bidirectionally between the source region and the drain region.
In the semiconductor integrated circuit device having an ET, the first M
Compared to the impurity concentration on the channel forming region side of the source region or drain region of the ISFET, the second MISFET
1. A semiconductor integrated circuit device characterized in that the impurity concentration on the channel forming region side of the source region or drain region is configured to be low. [Claim 5] The first MISFET and the second MISF
Each of the ETs has a source region or a drain region formed of a semiconductor region with a high impurity concentration and a semiconductor region with a low impurity concentration formed between the semiconductor region and the channel formation region.
5. The semiconductor integrated circuit device according to claim 1, wherein an LDD structure is adopted.