JPH04192885A - Horizontal synchronizing circuit of television receiver - Google Patents

Abstract

PURPOSE:To eliminate the image distortion and the image irregularities at the time of moving reception, etc.,by switching and using a synchronizing signal formed by a horizontal AFC circuit and a synchronizing signal formed by a timingcircuit in accordance with a receiving state. CONSTITUTION:A loop consisting of a horizontal AFC circuit 3, a horizontal oscillating circuit 4, a horizontal drive circuit 5 and an integrator 6, and a loop consisting of a pulse formig circuit 8, a comparator 9, a low-pass filter 10, a VCO 11 and a timing pulse generating circuit 12 form a high gain PLL and a low gain PLL, respectively. In such a state, by utilizing a fact that amplitude of a control voltage of the VCO becomes small at the time when the whole screen is scarcely fluctuated in the horizontal direction and stable, the low gain PLL is selected,when the amplitude of the control voltage of the VCO is small, and the high gainPLL is selected, when the control voltage of the VCO is above a certain level. In such a way, image distortion and irregularities can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television receiver, and more particularly to a horizontal synchronization circuit improved to obtain stable and less distorted images.

[Prior Art] FIG. 3 shows a horizontal synchronization circuit of a conventional general television receiver. In the figure, l is an input terminal for a received video detection signal, 2 is a synchronization separation circuit, 3 is a horizontal AFC circuit, 4 is a horizontal oscillation circuit, 5 is a horizontal drive circuit, 6 is an integrator, and 7
is the horizontal deflection coil.

A received video detection signal a (hereinafter referred to as VIP) output from a video detector (not shown) is applied to a synchronization separation circuit 2. The horizontal AFC circuit 3 receives the horizontal synchronization signal separated by the synchronization separation circuit 2 and the wave suppression output from the integrator 6, and detects the phase difference between the output C of the horizontal oscillation circuit 4 and the horizontal synchronization signal. horizontal oscillation circuit 4 according to this phase difference.
A control voltage with an oscillation frequency of is output. Horizontal oscillation circuit 4
creates a pulse C with a period of fH (ratio to fH = 15.75) at the timing of dividing the frequency according to this control voltage,
Output to horizontal drive circuit 5.

Horizontal drive circuit 5f) Part of the output is from the horizontal deflection coil 7
In addition, the other part is connected to an integrator 6, which integrates the horizontal drive pulse d output from the horizontal drive circuit 5 to obtain wave suppression.

[Problems to be Solved by the Invention] In the circuit shown in FIG.
) to (d) are the waveforms shown in Fig. 3 (a) to (d), but V
If the IP contains noise such as a ghost that exceeds the threshold level of synchronization separation, each of the above sections (a) to
The waveform and phase of (d) are as shown in FIGS. 4(a) to (d).

In the state shown in FIG. 4, the phase of the horizontal drive pulse (d) matches the horizontal synchronizing signal (b) separated from the received video signal (8). Therefore, at this time, the television receiver can provide a stable screen without image distortion or disturbance, but the fifth
If the received video signal contains noise such as a ghost as shown in the figure, the horizontal drive pulse (d) causes an error with respect to the phase of the original synchronization signal. This phase error causes image distortion.

In addition, when in-vehicle television receivers receive mobile signals while driving, the location and frequency of noise such as ghosts change drastically over time, resulting in significant image distortion, especially when the D/U ratio drops significantly. There is a drawback.

The present applicant previously filed Japanese Patent Application No. 2-199705 as a method for reducing image distortion caused by such phase errors. This method has the effect of reducing image distortion in fixed reception such as when the vehicle is stopped, but even if the image distortion can be reduced while the vehicle is running, the horizontal fluctuation of the entire screen as shown in Figure 6 (a) ( There is still room for improvement in that flutter occurs.

An object of the present invention is to add a PLL circuit with a low loop gain and a clock pulse formed by this PLL circuit to a horizontal separation circuit of a conventional television receiver consisting of a synchronization separation circuit, a horizontal AFC circuit, etc. By adding a timing circuit to create various pulses based on the reference, mobile reception is possible by switching between the synchronization signal formed by the horizontal AFC circuit and the synchronization signal formed by the above timing circuit depending on the reception situation. The objective is to correct image distortion and image disturbance in etc. and obtain a stable playback screen. [Means for Solving the Problems] In order to achieve the above object, the present invention provides a synchronization separation circuit that extracts a horizontal synchronization signal from a received video detection signal, and a phase difference between the horizontal synchronization signal and a pulse signal of a predetermined period. In the horizontal synchronization circuit of a television receiver, the horizontal synchronization circuit of a television receiver includes a horizontal AFC circuit that outputs a control signal according to the horizontal synchronization signal, and a horizontal output deflection circuit that displays an image based on the pulse signal of the predetermined period according to the control signal. a timing pulse generation circuit that outputs a timing pulse signal as a reference for generating a signal, and detecting a phase difference by comparing the phases of the timing pulse signal and the pulse signal of the predetermined period;
a phase comparator circuit that outputs a phase difference control signal according to the phase difference, and a phase and period of a timing pulse signal outputted by the timing pulse generation circuit in response to the phase control signal, and a phase and period of the horizontal synchronization signal. a control circuit that controls the timing pulse generation circuit so as to match the timing pulse generation circuit; and a control circuit that selectively controls the output signal of the timing pulse generation circuit and the pulse signal of a predetermined period output from the horizontal oscillation circuit according to the phase control signal. A selection circuit for outputting to the horizontal output deflection circuit is provided.

[Function] In the horizontal synchronization circuit of the present invention, the phase control signal corresponds to the reception state, and in response to this signal, the timing pulse signal or the pulse signal of the predetermined period is output to the horizontal deflection circuit. Ru.

When the control circuit is a PLL circuit with a low loop gain, the phase control signal is the ■C○ control voltage.

[Example] The present invention will be described in detail below as shown in the drawings.

FIG. 1 shows an embodiment of a horizontal synchronization circuit for a television receiver according to the present invention. In the same figure, the same reference numerals as in FIG. 3 indicate the same or similar circuits, 5° is a horizontal drive circuit, 8 is a pulse generation circuit, 9.9' is a comparator, 1O is a low-pass filter, and 11 is a voltage A controlled oscillation circuit (VC○), 12 a timing pulse generation circuit, ]3 a flip-flop, and 14 an electronic switch.

Parts (a) to (e) and (C)' to (e) of the above embodiments
The waveform of '' is shown in FIG.

The fH period pulse C output from the horizontal oscillation circuit 4 passes through the pulse shaping circuit 8 and has a waveform as shown in FIG. 5(e), for example.

On the other hand, the timing pulse generation circuit 12 generates a timing pulse signal e' that serves as a reference for generating a horizontal synchronization signal.

The signals e' and e are input to a comparator 9, and their phase difference is detected. The output representing the detected phase difference is converted into a DC component by a low-pass filter 10, and this DC component becomes a control voltage of a phase difference control signal, for example, vC○11. The output signal of the VCOII is a reference clock for the timing pulse generation circuit 12, and its oscillation frequency is generally 4 fsc (14,31818 MHz), for example.

The timing pulse generation circuit 12 generates a timing pulse signal e' and a pulse C' having a period of fH for phase comparison with the signal e corresponding to the pulse C. As described above, this circuit 12 generates the The phase and period of the timing pulse signal e' outputted by the circuit 12 in response to the control voltage (phase difference control signal) are controlled so as to match the phase and period of the signal e, and thus the horizontal synchronization signal. .

The pulse C'' is input to the horizontal drive circuit 5', but one of the two types of drive pulses d and d' output from the respective horizontal drive circuits 5 and 5' is selected by the switch 14. applied to the horizontal deflection coil 7.

The switch 14 is connected to the input terminal 14a by the output of the flip-flop 13 which is triggered by the output of the comparator 9'.
, 14b, the control voltage of VCOII is input to the (+) input terminal of the comparator 9', and the variable setting voltage E is input to the (-) input terminal. Therefore, the control voltage of VCOII is set by comparator 9'
When there is a change in the control voltage, the switch 14 is switched by the output of the flip-flop 13.

Since the vertical synchronization signal vD is applied to the clock terminal CK of the flip-flop 13 from the synchronization separation circuit 2, switching of the switch 13 is performed within the vertical blanking period and is not performed in the middle of the screen.

As can be seen from the above description, in the embodiment shown in FIG. <Later 9, low-pass filter 10, VCO II and timing pulse generation circuit 1
The two loops each form a low gain PLL.

In general, a PLL with a high loop gain has a fast pull-in time but has a large negative effect due to noise, while a PLL with a low loop gain has a slow pull-in time but good stability during locking.

That is, when switching channels, it is better to have a high loop gain, and conversely, when the channel is fixed and reception conditions are poor, it is better to have a low loop gain.

In addition, when the loop gain is low in mobile reception during high-speed driving, horizontal shaking becomes noticeable on the entire screen, so it may be better to set the loop gain high.

According to the configuration of the embodiment described above, the amplitude of the control voltage of ■CO is reduced by utilizing the fact that the amplitude of the control voltage of VC○ is small when the entire screen is in a stable state with little horizontal shaking. Horizontal drive that reduces image distortion and disturbance by selecting the PLL with a smaller loop gain when the control voltage of C0 is small, and selecting the PLL with a larger loop gain when the control voltage of C0 is above a certain level. You can get a pulse.

FIG. 2 shows another embodiment of the horizontal synchronization circuit according to the present invention, in which the same reference numerals as in FIG. 1 indicate the same or similar circuits;
The configuration different from the embodiment shown in the figure is the pulse shaping circuit 8.8'
, comparator 9.9", 9", low pass filter 10
．． 10', VCOII, 11' and a timing pulse generation circuit 13.12, each including first and second low gain PLLs each having two types of loop gains, and a timing pulse generation circuit 12.12 including a synchronization signal generation circuit. '', and is provided with an adder 15 that adds the video signal a and the horizontal synchronizing signal selected by the switch 14.

゛The method of the embodiment shown in Fig. 2 is the same in principle as the method shown in Fig. 1, but the method shown in Fig. 1 requires a change in the circuit inside the receiver, and is not suitable for a type that is built into the receiver. On the other hand, the method shown in FIG. 2 is suitable as a type that is added as an adapter to the outside of the receiver.

In addition, if the receiver is equipped with an external synchronization input terminal,
Adder 15 is not necessary. Furthermore, when it is desired to switch the loop gain to three or more stages depending on the reception situation, the number of input systems of the switch 14 may be increased to utilize horizontal drive pulses, or the number of PLL stages may be increased.

Adder 15 includes a circuit that adjusts the level of the synchronizing signal to the level of the video signal, and output terminal 16 is connected to the video input terminal of the receiver when used as an adapter.

[Effects of the Invention] As explained above, according to the present invention, for example, it is possible to reduce image distortion and image part blurring when an in-vehicle television receiver is moving, and horizontal synchronization after synchronization separation can be achieved. Even if the pulses contain noise, pulses are dropped, or bits are dropped, almost no image distortion occurs by replacing this with a stable synchronization signal. Furthermore, as shown in FIG. 6(b), it is possible to suppress horizontal screen fluctuation when the vehicle is traveling at high speed.

Furthermore, the present invention is not limited to in-vehicle applications, but is also highly effective when applied to fixed reception systems such as general home receivers. In fixed reception, there is almost no horizontal screen wobbling, but switching the loop gain of the PLL exhibits its effect when switching channels.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a horizontal synchronization circuit according to the present invention, FIG. 2 is a block diagram showing another embodiment of the invention, and FIG. 3 is a block diagram showing an example of a conventional horizontal synchronization circuit. , Figure 4 is a waveform diagram of each part (a) to (d) of Figures 1 and 3 under stable conditions, and Figure 5 is a waveform diagram of each part of Figures 1 and 2 when reception conditions are poor. (a) ~ (d), (C)' ~
6(d) is an explanatory diagram showing an example of a distorted image by the conventional method, and FIG. 6(b) is an explanatory diagram showing an example of an image with distortion corrected by the method of the present invention. Yes. 1......Video detection signal input terminal, 2...
......Synchronization separation circuit, 3......Horizontal AFC circuit, 4......Horizontal oscillation circuit, 5,5
′ ......Horizontal drive circuit, 7...
・・・・・・Horizontal deflection coil, 8・・・・・・Pulse shaping circuit, 9・・・・・・Comparator, 10
......Low pass filter, 11...
・・・・vCO112・・・・・・・Timing pulse generation circuit, 14・・・・・・・Electronic switch. Patent applicant Glarion Co., Ltd. Agent Patent attorney Nagai 1) Takeshi Part 2 Figure 15; Addition device 1s:8*Image signal output 3
Figure 4N (d)' Figure 5 (b); (c)'
. ; Figure 6 (a) (b)

Claims (3)

[Claims] (1) A synchronization separation circuit that extracts a horizontal synchronization signal from a received video detection signal; A horizontal AFC circuit that outputs a control signal according to the phase difference between the horizontal synchronization signal and a pulse signal of a predetermined period; A horizontal synchronization circuit for a television receiver, comprising: a horizontal oscillation circuit that outputs the pulse signal of the predetermined period; and a horizontal output deflection circuit that displays an image based on the pulse signal of the predetermined period; a timing pulse generation circuit that outputs a timing pulse signal that is a reference for the timing pulse signal; and a timing pulse generation circuit that compares the phases of the timing pulse signal and the pulse signal of the predetermined period to detect a phase difference, and detects a phase difference according to the phase difference. a phase comparator circuit that outputs a control signal; and a timing pulse that outputs a timing pulse signal such that the phase and period of the timing pulse signal outputted by the timing pulse generation circuit in response to the phase control signal match the phase and period of the horizontal synchronization signal. a control circuit for controlling a generation circuit; and selectively outputting an output signal of the timing pulse generation circuit and a pulse signal of a predetermined period output from the horizontal oscillation circuit to the horizontal output deflection circuit according to the phase control signal. A horizontal synchronization circuit for a television receiver, comprising a selection circuit; (2) The control circuit is a voltage-controlled oscillation circuit, and the voltage-controlled oscillation circuit, the timing pulse generation circuit, and the phase comparison circuit constitute a PLL circuit with a low loop gain. ) horizontal synchronization circuit for a television receiver. (3) The PLL circuit is composed of a plurality of PLL circuits set to different loop gains, and the selection circuit is
3. The horizontal synchronization circuit for a television receiver according to claim 2, wherein one of the timing pulses from the L circuit is selected depending on reception conditions.