JPH04192178A - Refresh device for memory - Google Patents

Abstract

PURPOSE:To improve an operation efficiency for a processing device by controlling the interval of refresh variably against a memory in accordance with the change of atmospheric temperature. CONSTITUTION:A thermistor 12 has the characteristic such that the resistance value becomes low when the measured temperature rises. So, the oscillation pulse width of a pulse signal S1 is short when the temperature is high and becomes long as the temperature is lowered. Then, the pulse signal S1 outputted from an RC oscillator 11 is inputted to the clock terminal CK of a DFF 10 and converted to a square wave pulse signal S2 having the twice pulse width by the DFF 10 then supplied to a refresh counter 9 as a refresh timing signal. Consequently, a refresh interval control means making the supply interval of refresh timing signal variable with the temperature measured by the thermistor 12 is constituted of the RC oscillator 11 and the DFF 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory refresh device applied to dynamic random access memory (hereinafter abbreviated as D-RAM) and the like.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional memory refresh device. In the figure, l is the central processing unit (hereinafter CP
(abbreviated as U), 2 requires refreshing - RAM
The two are connected by path lines of an address bus 3a, a data bus 3b, and a control bus 3c.

An address multiplexer 4 is interposed in the address bus 3a for dividing addresses into row addresses and column addresses and supplying them to the D-RAM 2 in a time-division manner. Also, from the address multiplexer 4 of the address bus 3a, C
An address decoder 5 that decodes addresses and outputs control signals to the control bus 3c is connected to the PUI side.

A data buffer 6 for latching data is interposed in the data bus 3b.

A timing controller 7 is interposed in the control bus 3c for supplying control signals such as RA, S signal (negative logic) RASO1CAS signal (negative logic) CASO, and write signal (negative logic) WEO to the D-RAM2. There is. In addition, a refresh request for the D-RAM 2 is generated from the timing controller 7 of the control bus 3C to the CPUI side, and the refresh request and the CPU
A refresh controller 8 is connected which arbitrates with access requests from I to the D-RAM 2 and controls the data buffer 5 based on the result.

9 in the figure inputs a clock signal CK of a constant frequency from the CPU as a refresh timing signal, regularly creates refresh addresses, and sends a refresh signal containing the refresh address to the multi-address multiplexer 4.
This is a refresh counter that supplies data to

When the refresh request becomes valid as a result of arbitration in the refresh controller 8, a switching signal SX is output from the timing controller 6 to the multi-address multiplexer 4. Accordingly, in the multi-address plexer 4, the refresh address supplied from the refresh counter 9 is divided into a row address and a column address and supplied to the D-RAM 2 in a time division manner, and at the same time, the timing controller 7 sends the RAS signal RASO to the D-RAM 2. and C
The AS signal CASO is applied in a time-division manner to the D-RAM.
2 refresh is performed.

In this way, conventionally, the frequency of the clock signal CK of a constant frequency is divided by the refresh counter 9 to generate refresh addresses at a constant cycle, and when a refresh request becomes valid as a result of arbitration by the refresh controller 8, the address multiplexer 4 is switched. Since the above refresh address was configured to be supplied to D-RAM2, D
~RAM2 was refreshed at regular intervals.

By the way, it is already known that the maximum permissible refresh interval in the D-RAM 2 depends on the surrounding atmospheric temperature. Figure 5 shows the maximum allowable refresh interval t.
(is) and the ambient temperature T (''C).

As is clear from the figure, when the ambient temperature is 0 (℃), the data in D-RAM2 is held stably even if the refresh interval is approximately 800 (ms), but if the ambient temperature is If the temperature rises, data may be lost. For this reason, in the past, the refresh interval was controlled to be constant, so it was set to a relatively short interval so as to be able to handle even high ambient temperatures.

[Problems to be Solved by the Invention] As described above, in the conventional memory refresh device, the refresh interval for the memory is controlled at relatively short constant intervals. For this reason, the processing device cannot access the memory while the refresh is being executed, so there is a problem that the operating efficiency of the processing device deteriorates when a memory that requires refreshing is used as the main storage device.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a memory refresh device that can variably control the refresh interval of the memory according to changes in ambient temperature and improve the operating efficiency of the processing device.

Means for Solving the Problem] The present invention provides an arbitration unit that arbitrates between a refresh request to a memory and an access request from a processing device, and a refresh unit that generates a refresh signal based on a refresh timing signal that is intermittently supplied. A memory refresh device comprising a signal generating means and a refresh control means for supplying a refresh signal generated by the generating means to the memory when a refresh request is validated by the arbitration means, comprising a temperature measuring means for measuring an ambient temperature; A refresh interval adjusting means is provided for varying the supply interval of the refresh timing signal depending on the level of the ambient temperature measured by the measuring means.

[Function] According to the present invention configured as described above, when the ambient temperature measured by the temperature side means decreases, the refresh timing signal supply interval increases accordingly. As a result, the interval between refresh signals generated by the refresh signal generating means becomes longer, and the interval between refreshes for the memory becomes longer.

Conversely, when the ambient temperature rises, the refresh timing signal supply interval becomes correspondingly shorter. This shortens the generation interval of the refresh signal generated by the refresh signal generating means, which in turn shortens the refresh interval for the memory.

When the refresh interval becomes longer, the access requests and refresh requests of the processing device are less likely to overlap.
The operating efficiency of the processing device is increased.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the apparatus of this embodiment.

First, a brief explanation will be provided by assigning the same reference numerals to the same parts as in FIG. 4. That is, the CPUI, which is a processing device, and the D-RAM 2, which is a memory that needs to be refreshed, are connected through each path line of an address bus 3a, a data bus 3b, and a control bus 3c. and address bus 3a
An address multiplexer 4 is interposed between the address bus 3a and the address multiplexer 4 of the address bus 3a.
An address decoder 5 is connected to the PUI side. A data buffer 6 is interposed on the data bus 3b. A timing controller 7 is interposed in the control bus 3C, and the timing controller 7 of the control bus 3c
A refresh controller 8 is connected to the CPUI side.

The refresh counter 9 inputs the signal S2 outputted from the output terminal Q of the D-type flip-flop (hereinafter abbreviated as DFF) 10 as a refresh timing signal, regularly creates a refresh address, and includes the refresh address. A refresh signal S3 is supplied to the multi-address plexer 4.

Here, the refresh counter 9 constitutes a refresh signal generating means that generates a refresh signal S3 based on a refresh timing signal S2 that is intermittently supplied. The refresh controller 8 is a D-RAM2
An arbitration means is configured to arbitrate between a refresh request for the CPU and an access request from the CPUI. When the refresh request becomes valid as a result of arbitration, the address multiplexer 4 and the timing controller 7 send a refresh signal s.
3 to the D-RAM 2.

On the other hand, the DC power supply VCC is connected to the input terminal of the above DFFIO.
is applied. RC oscillator 1 is connected to clock terminal CK.
1 inverting output terminal QO is connected.

The RC oscillator 11 generates an oscillation pulse that is expressed by the following equation (1), where the total resistance value of a thermistor 12 and a resistor 13 as a temperature measuring means for measuring the ambient atmospheric temperature is set to C as the capacitance of an R1 capacitor 14. A pulse signal S1 having a width T is generated from an inverting output terminal QO.

T-0, 46CR-(1) Here, the resistance value of the thermistor 12 generally decreases as the measured temperature increases. Therefore, the oscillation pulse width T of the pulse signal S1 is short when the ambient temperature is high, and becomes gradually longer as the ambient temperature becomes lower.

Therefore, the pulse signal S1 output from the RC oscillator 11 is input to the clock terminal CK of DFFIO, and
Square wave pulse signal S2 with double pulse width due to FFIO
The signal is converted into a refresh timing signal and supplied to the refresh counter 9 as a refresh timing signal.

Here, the RC oscillator 11 and DFFIO constitute a refresh interval adjusting means that varies the supply interval of the refresh timing signal depending on the level of the ambient temperature measured by the thermistor 12.

In this embodiment configured in this way, the resistor 13 is now
Let the resistance value of the capacitor l4 be 5 (KΩ), and the capacitance of the capacitor l4 be 2200 (pF). In addition, the resistance value of the thermistor 12 is 2 (KΩ) when the ambient temperature is 70 ("C).
When the ambient temperature is 0 (℃), the resistance value is 40 (K
Ω) shall be used.

Then, when the ambient temperature is 70 ("C), R
The oscillation pulse width T of the pulse signal S1 output from the C oscillator 11 is approximately 7 (μS) according to the above equation (1). In this case, the output of DFF unit 0 has a pulse width T' of approximately 14 (μ
S) becomes a square wave pulse signal S2, and this signal S2 is supplied to the refresh counter 9 as a refresh timing signal. As a result, refresh counter 9
, the rising edge of the pulse signal S2 is counted, a refresh address is regularly created based on it, and a refresh signal S3 containing the refresh address is output to the address multiplexer 3.

On the other hand, when the ambient temperature is 0 (℃), the RC oscillator 1
The oscillation pulse width T of the pulse signal S1 output from 1 is
According to the above equation (1), it is approximately 45 (μS). in this case,
The output of DFFIO becomes a square wave pulse signal S2 with a pulse width T' of approximately 90 (μS), and this signal S2 is supplied to the refresh counter 9 as a refresh timing signal.

As a result, the refresh counter 9 counts the rise of the pulse signal S2, based on which a refresh address is regularly created, and a refresh signal S3 containing the refresh address is output to the address multiplexer 3.

Fig. 2 shows an example of the timing waveforms of the oscillation pulse signal S1, square wave pulse signal S2, and refresh signal S3 when the ambient temperature is 70 ('IC'), and Fig. 3 shows an example of the timing waveforms of the oscillation pulse signal S1, square wave pulse signal S2, and refresh signal S3 when the ambient temperature is O ('C'). Examples of the timing waveforms of the oscillation pulse signal S1, the square wave pulse signal S2, and the refresh signal S3 are shown below.As is clear from both figures, the interval t (ms) of the refresh signal S3 is shorter when the ambient temperature is lower than when it is higher. ) becomes longer.

As described above, in this embodiment, the ambient atmospheric temperature is measured using the thermistor 12, and the refresh interval is adjusted so that when the measured temperature is low, the refresh interval is longer than when the measured temperature is high. Generally, as shown in FIG. 5, when the ambient temperature is low, the data in the D-RAM 2 is stably held even if the refresh interval is longer than when the ambient temperature is high.

Therefore, when the ambient temperature is low, the refresh interval becomes longer, so the CPUI access requests and the refresh requests are less likely to overlap, and the operating efficiency of the CPUI is improved.

In the above embodiment, an example was shown in which the supply interval of the refresh timing signal was varied by varying the oscillation pulse width T of the RC oscillator 1 depending on the temperature measured by the thermistor 12. The data is stored as a table in a ROM, etc., and the CPU detects the temperature measured by the thermistor, selects a frequency interval corresponding to the measured temperature from the table data, and based on that selects the frequency of the clock signal CK to the refresh counter 9. It may be made variable.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a memory paste/french device that can variably control the refresh interval for the memory according to changes in ambient temperature and improve the operating efficiency of the processing device.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of an embodiment of the present invention, Figure 2 is a timing waveform diagram of main signals when the ambient temperature is low in the same embodiment, and Figure 3 is a diagram of the timing waveforms of the main signals in the same embodiment when the ambient temperature is high. Timing waveform diagram of main signals when
The figure is a block diagram showing a conventional configuration, and FIG. 5 is a characteristic diagram showing the relationship between ambient temperature and maximum allowable refresh interval. 1...CPU. 2...D-RAM. 4... Address multiplexer, 7... Timing controller, 8... Refresh controller, 9... Refresh counter, 10... DFF. 11...RC oscillator, 12...Thermistor. Applicant's representative Patent attorney Takehiko Suzue Figure 1:::.醗 t(ms) , t(ms
), t(ms) i second
Figure 3 Figure 4

Claims (1)

[Scope of Claims] Arbitration means that arbitrates between a refresh request to a memory and an access request from a processing device, a refresh signal generation means that generates a refresh signal based on a refresh timing signal that is intermittently supplied, and said arbitration means. A memory refresh device comprising a refresh control means for supplying a refresh signal generated by the generating means to the memory when a refresh request is enabled by the means, comprising a temperature measuring means for measuring an ambient temperature; 1. A memory refresh device comprising: refresh interval adjusting means for varying the supply interval of the refresh timing signal depending on the level of ambient temperature.