JPH0419798Y2 - - Google Patents
Info
- Publication number
- JPH0419798Y2 JPH0419798Y2 JP1986043982U JP4398286U JPH0419798Y2 JP H0419798 Y2 JPH0419798 Y2 JP H0419798Y2 JP 1986043982 U JP1986043982 U JP 1986043982U JP 4398286 U JP4398286 U JP 4398286U JP H0419798 Y2 JPH0419798 Y2 JP H0419798Y2
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- resin part
- semiconductor device
- board
- main body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011347 resin Substances 0.000 claims description 19
- 229920005989 resin Polymers 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000005476 soldering Methods 0.000 claims description 8
- 230000017525 heat dissipation Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 description 13
- 238000004140 cleaning Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000004907 flux Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 2
- 238000011179 visual inspection Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【考案の詳細な説明】
（産業上の利用分野）
本考案は基板への取付けが面実装型の半導体装
置に関するものである。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a surface-mounted semiconductor device that is attached to a substrate.
（従来の技術）
第２図ａは従来の面実装型半導体装置の基板実
装の一例を示す側面図である。第２図ｂは実装前
の半導体装置の底面図である。図において１はリ
ード、２は本体樹脂部、３は放熱板、４は基板の
配線導体部、５は基板である。(Prior Art) FIG. 2a is a side view showing an example of a conventional surface mount type semiconductor device mounted on a board. FIG. 2b is a bottom view of the semiconductor device before mounting. In the figure, 1 is a lead, 2 is a main body resin part, 3 is a heat sink, 4 is a wiring conductor part of a board, and 5 is a board.
第２図ａ，ｂに示すように従来の面実装型半導
体装置は、リード１がフオーミングされ、本体樹
脂部２の底面と放熱板３の露出面の底面が同一平
面になるように成形されていた。このため、面実
装型半導体装置を、配線導体部４が形成されてい
る基板５にはんだ付けする場合、配線導体部４の
厚みは10μm程度なので、配線導体部４が配設さ
れていない基板５面と本体樹脂部２底面との間隔
も10μm程度と隙間がほとんどない状態になつて
いる。また隙間がないことより、放熱板３下のは
んだペーストが溶融時に本体樹脂部２底面部より
押し出され、放熱板３下のはんだ量が不足して、
放熱板３と配線導体部４のはんだ付けが不十分に
なるという問題もあつた。 As shown in FIGS. 2a and 2b, in a conventional surface-mount semiconductor device, the leads 1 are formed so that the bottom surface of the main body resin part 2 and the bottom surface of the exposed surface of the heat sink 3 are on the same plane. Ta. For this reason, when soldering a surface-mounted semiconductor device to the substrate 5 on which the wiring conductor portion 4 is formed, the thickness of the wiring conductor portion 4 is approximately 10 μm, so the substrate 5 on which the wiring conductor portion 4 is not provided is soldered. The distance between the surface and the bottom surface of the main body resin part 2 is approximately 10 μm, so there is almost no gap. In addition, since there is no gap, the solder paste under the heat sink 3 is pushed out from the bottom of the main body resin part 2 when melted, resulting in an insufficient amount of solder under the heat sink 3.
There was also the problem that the soldering between the heat sink 3 and the wiring conductor portion 4 was insufficient.
（考案が解決しようとする問題点）
従来の面実装型半導体装置は、上記のように本
体樹脂部２底面および放熱板３底面が同一平面に
あり、基板実装時には本体樹脂部２底面と基板５
面との隙間がほとんどない状態になるので、はん
だ付け検査における良否判定が目視では難しいと
いう問題がある。またはんだ付け後のフラツクス
洗浄においては、洗浄液が本体樹脂部２底面と基
板５面との隙間に浸入してゆかず、洗浄が不十分
になり、フラツクス残りのリークにより特性不良
が発生するという問題もある。(Problems to be solved by the invention) In the conventional surface-mounted semiconductor device, the bottom surface of the main body resin part 2 and the bottom surface of the heat sink 3 are on the same plane as described above, and when mounted on a board, the bottom surface of the main body resin part 2 and the bottom surface of the board 5 are on the same plane.
Since there is almost no gap with the surface, there is a problem in that it is difficult to judge the quality of soldering by visual inspection. In addition, when cleaning flux after soldering, the cleaning liquid does not penetrate into the gap between the bottom surface of the main body resin part 2 and the surface of the board 5, resulting in insufficient cleaning and resulting in poor characteristics due to leakage of remaining flux. There is also.
本考案は、上記の問題点に鑑みてなされたもの
で、放熱板と基板の配線導体部のはんだ付け性を
向上させるとともに、フラツクス洗浄が十分に行
われ、放熱板と基板の配線導体部とのはんだ付け
の目視検査が可能となる半導体装置を提供するこ
とを目的とする。 The present invention was developed in view of the above-mentioned problems, and it not only improves the solderability of the wiring conductor part of the heat sink and the board, but also improves the solderability of the wiring conductor part of the heat sink and the board. An object of the present invention is to provide a semiconductor device that enables visual inspection of soldering.
（問題点を解決するための手段）
この考案に係る半導体装置は、はんだ付け用放
熱板３底面を本体樹脂部底面より突出させ、同時
にリード１の基板接着面も同一方向にリードフオ
ーミングを行ない、放熱板３底面とリード１の基
板接着面が同一平面になるように構成されたもの
である。(Means for Solving the Problems) The semiconductor device according to this invention has the bottom surface of the soldering heat sink 3 protruding from the bottom surface of the main body resin part, and at the same time, the board bonding surface of the lead 1 is also lead-formed in the same direction. , the bottom surface of the heat sink 3 and the substrate bonding surface of the lead 1 are configured to be on the same plane.
（考案の実施例）
第１図にこの考案の一実施例を示す。図におい
て第２図と同一符号は同一または相当する部分を
示している。図において放熱板３は本体樹脂部２
をモールドする時に、リード側の側面３１が本体
樹脂部２底面より0.2mm程度突出するように成形
する。本体樹脂部２底面と放熱板３底面とは平行
度が保たれるようにしてある。またリード１は基
板との接着面が放熱板３底面と同一平面内になる
ようにリードフオーミングを行なう。(Embodiment of the invention) FIG. 1 shows an embodiment of the invention. In the figure, the same reference numerals as in FIG. 2 indicate the same or corresponding parts. In the figure, the heat sink 3 is the resin part 2 of the main body.
When molding, the lead side side surface 31 is molded so that it protrudes from the bottom surface of the main body resin part 2 by about 0.2 mm. The bottom surface of the main body resin portion 2 and the bottom surface of the heat sink 3 are kept parallel. Further, the lead 1 is formed so that the adhesive surface to the substrate is in the same plane as the bottom surface of the heat sink 3.
本考案の半導体装置は上記のような構造になつ
ているので、第１図のように基板５の配線導体部
４１，４２にそれぞれ放熱板３とリード１をはん
だ付けすると、本体樹脂部底面と基板５との間に
0.2mm程度の隙間６が形成される。このために、
放熱板３底面と配線導体部４１との間のはんだペ
ーストが溶融接着時に押し出されても、押し出さ
れたはんだは放熱板側面３１と配線導体部４１の
接点部分に集まり、そこで固まつて接着部３２を
成形する。ここでフラツクス洗浄を行なうと、洗
浄液は隙間６を通して放熱板側面３１付近のフラ
ツクス残渣を十分除去することができるようにな
る。その後のはんだ付け検査も目視できるように
なる。また隙間６の空間を利用して本体樹脂部底
面下に配線導体部７を設けることも可能になつて
くる。 Since the semiconductor device of the present invention has the above-described structure, when the heat sink 3 and the leads 1 are soldered to the wiring conductor parts 41 and 42 of the board 5, respectively, as shown in FIG. Between the board 5
A gap 6 of about 0.2 mm is formed. For this,
Even if the solder paste between the bottom surface of the heat sink 3 and the wiring conductor section 41 is extruded during melt bonding, the extruded solder collects at the contact area between the heat sink side surface 31 and the wiring conductor section 41, where it hardens and forms the adhesive part. 32 is molded. If flux cleaning is performed here, the cleaning liquid passes through the gap 6 and can sufficiently remove the flux residue near the side surface 31 of the heat sink. Subsequent soldering inspections can also be visually observed. Furthermore, it becomes possible to provide the wiring conductor portion 7 under the bottom surface of the main body resin portion by utilizing the space of the gap 6.
（考案の効果）
以上のように、本考案の半導体装置によれば、
基板実装後の、本体樹脂部２で側面を囲まれた放
熱板側面３１と配線導体部４１の接着も接着部３
２により、強度が増すと共に、はんだ接合面積が
増し、半導体装置の放熱板３よりの放熱性が向上
する。隙間６により基板５面の有効利用ができ、
フラツクス洗浄も十分に行なえるので、実装基板
の信頼性を大きく向上させることができる。(Effects of the invention) As described above, according to the semiconductor device of the invention,
After mounting on the board, the adhesive portion 3 is also used to bond the wiring conductor portion 41 to the heat sink side surface 31 whose side surface is surrounded by the main body resin portion 2.
2 increases the strength, increases the solder joint area, and improves heat dissipation from the heat sink 3 of the semiconductor device. The gap 6 allows effective use of the 5 sides of the board,
Since flux cleaning can also be carried out sufficiently, the reliability of the mounted board can be greatly improved.
第１図は本考案の一実施例を示す基板実装をし
た半導体装置の側面図、第２図ａ，ｂはそれぞれ
従来の半導体装置の側面図、底面図である。
１……リード、２……本体樹脂部、３……放熱
板、４，７，４１，４２……配線導体部、５……
基板、６……隙間。
FIG. 1 is a side view of a semiconductor device mounted on a substrate, showing an embodiment of the present invention, and FIGS. 2a and 2b are a side view and a bottom view, respectively, of a conventional semiconductor device. 1... Lead, 2... Main body resin part, 3... Heat sink, 4, 7, 41, 42... Wiring conductor part, 5...
Board, 6... gap.
Claims (1)
樹脂部で囲んだ状態で部分的に露出させるととも
に、上記放熱板の残りの一側面側を該モールド樹
脂部の底面の一方向へ延出させた、はんだ付け用
放熱板を設けると共に、上記放熱板の放熱面と上
記モールド樹脂部の側面より延出したフオーミン
グリードの底面とが、同一平面となるように構成
した半導体装置に於て、 該放熱板の放熱面をモールド樹脂部の底面より
突出させたことを特徴とする半導体装置。[Claims for Utility Model Registration] The three sides of the heat sink are partially exposed on the bottom of the molded resin part with the resin part surrounding them, and the remaining one side of the heat sink is covered with the molded resin part. A heat sink for soldering is provided extending in one direction of the bottom surface, and the heat sink surface of the heat sink and the bottom surface of the forming lead extending from the side surface of the molded resin part are on the same plane. What is claimed is: 1. A semiconductor device comprising: a heat dissipation surface of the heat dissipation plate protruding from a bottom surface of a molded resin portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986043982U JPH0419798Y2 (en) | 1986-03-27 | 1986-03-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986043982U JPH0419798Y2 (en) | 1986-03-27 | 1986-03-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62157155U JPS62157155U (en) | 1987-10-06 |
| JPH0419798Y2 true JPH0419798Y2 (en) | 1992-05-06 |
Family
ID=30861359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986043982U Expired JPH0419798Y2 (en) | 1986-03-27 | 1986-03-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0419798Y2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6083249U (en) * | 1983-11-15 | 1985-06-08 | 松下電器産業株式会社 | integrated circuit components |
-
1986
- 1986-03-27 JP JP1986043982U patent/JPH0419798Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62157155U (en) | 1987-10-06 |
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