JPH0417578B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a phase modulation method used for various data transmissions. [Prior Art] In modulators and demodulators for data transmission, data is used to perform phase modulation on a carrier wave of a specific frequency before transmission. ) bits as continuous data, feed it to the adder, and hold the addition output in a register, and feed the output held in the register again to the adder, and in the adder convert the continuous data and the output held in the register into binary and add
An addition output called modulo 2 ⁿ addition is obtained, ignoring carries exceeding n bits, and this is held in the register again. While repeating this operation, 2 ^n- phase carrier waves are generated for each, and the register is It has become common practice to select and transmit each carrier wave using a holding output. [Problems to be solved by the invention] However, in the case of the conventional method, it is necessary to generate carrier waves with different phases depending on the number of modulation phases, and as the number of phases increases, the configuration of the generation circuit changes. Along with this, carrier wave selection circuits, registers, etc. have also become more complex, resulting in lower reliability and higher costs. [Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention is constituted by the following means. In other words, in a method that performs 2 ^n- phase phase modulation on a carrier wave using n bits of continuous data,
A clock pulse having a frequency ²ⁿ times the carrier wave frequency is divided by an n-stage frequency divider, each stage consisting of a binary counter, to generate a carrier wave, and n-bit continuous data and each stage of the frequency divider are divided. A modulo 2 ⁿ summation output is obtained from the output from the summation output, and each stage of the frequency divider is controlled in accordance with the order of each bit of this summation output, and the state of each stage is set. [Operation] Therefore, the carrier wave of the original phase is obtained from the output of the final stage of the frequency divider, and the bit order of this can be changed by the modulo 2 ⁿ addition output of the continuous data and the output from each stage of the frequency divider. Each stage of the frequency divider corresponding to is controlled, and these states are forcibly set. Accordingly, the phase of the frequency divider output is determined, and ^2n- phase modulation is performed. [Example] Hereinafter, details of the present invention will be explained with reference to figures showing examples. Figure 1 is a circuit diagram, and Figure 2 is a timing chart showing the waveforms of each part in Figure 1. In this case, n = 2, and 2 ⁿ = 4-phase differential phase modulation is performed. , the frequency divider 1 divides the clock pulse (hereinafter referred to as CLK) P _c1 (a) having a frequency of 7.2 KHz, which is four times the carrier frequency of 1.8 KHz, and sends out the phase modulation signal S _PM . Each stage of the frequency divider 1 is controlled by the addition outputs i and j from the adder 2 which performs addition. In addition, the transmission data SD is given to the holding circuit 3 that performs sampling and holding using CLK _Pc3 with a frequency of 1.2 KHz synchronized with this, where it becomes 2-bit continuous data e and f, and is given to the adder 2. It has become a thing. Here, the frequency divider 1 has a two-stage configuration mainly consisting of a binary counter formed by D-type flip-flop circuits (hereinafter referred to as FFC) 101 and 102, and each FFC 101 and 102 is connected to an OR gate 10.
3,104, and NAND gate 105,10
6, the outputs Q are individually fed back to the data inputs D, and the NAND gates 105 and 106
The addition outputs (i) and (j) are respectively given through OR gates 107 and 108, while the FFC1
The clock input CK of 01 has a NOR gate 111.
CLK·P _c1 (a) is applied to the clock input CK of the FFC·102 through an AND gate 112 and a NOR gate ₁₁₃ , respectively. There is. In addition, the OR gates 103 _and 104 are provided with a timing pulse (hereinafter referred to as
TMP) P _t (b) is given, and an inverted TMP obtained by inverting this by the inverter 4 is given to OR gates 107 and 108. Note that the NOR gates 111 and 113 have
CLK with a frequency of 1.2KHz synchronized with TMP・P _t (b)
P _c2 (c) is given, and when TMP P _t (b), which changes from logical value “0” to “1”, becomes “1”, CLK P _c2 (c) becomes a NOR gate. Clock input CK of FFC/101, 102 via 111, 113
It has become a driving force. Therefore, while TMP・P _t (b) is “0”, it is “1”
When CLK・P _c1 (a) changes from “0” to “0”, the output of NOR gate 111 changes to “1” and drives FFC・101, while FFC・102
is only when the output g of FFC101 is “1”
Since the AND gate 112 is turned on, it is similarly driven under this condition. Also, when TMP・P _t (b) is “0”, FFC・
Outputs g and h of 101 and 102 are OR gate 10
3 and 104, and since the output of the inverter 4 is "1", the outputs of the OR gates 107 and 108 are "1", and if the FFCs 101 and 102 are in the reset state, the outputs g and h are "1". 0", the outputs of the NAND gates 105 and 106 become "1", and CLK・P _c1 (a) becomes "0".
As the clock input CK is driven in response to
Turn to On the other hand, if the FFCs 101 and 102 are in the set state, the outputs of the NAND gates 105 and 106 become "0" and are reset in response to the clock input CK being driven, setting the outputs g and h to "0". ”. Therefore, the FFC 101 repeats setting and resetting according to CLK P _c1 (a), and the output g becomes
Each cycle of CLK・P _c1 (a) indicates “0” and “1”, and when this is further divided,
Since the output h of the FFC 102 repeats "0" and "1", the output h indicates the original phase of the frequency obtained by dividing CLK P _c1 (a) into 1/4. However, if TMP・P _t (b) occurs as “1”, then
Regardless of the states of FFCs 101 and 102, the outputs of OR gates 103 and 104 become "1", and the outputs of OR gates 107 and 108 are determined by the corresponding order of addition outputs i and j. When the addition outputs i and j are “1”,
While the outputs of the NAND gates 105 and 106 are "0", if the addition outputs i and j are "0", the outputs of the NAND gates 105 and 106 are "1", and at the same time, CLK・P _c2 ( Since the clock input CK is driven by c), a forced reset is performed by adding outputs i and j of "1", and a forced setting is performed by a similar "0", and the states of FFCs 101 and 102 are set. Therefore, according to TMP・P _t (b) and according to the addition outputs i and j, FFC・101, 102
The outputs g and h of the output h change, and if we pay attention to the output h, the phase of this changes based on the previous state, so that a phase modulation signal S _PM is obtained. In this example, the amount of phase change θ corresponding to the values of continuous data e and f is shown in Table 1.

[Table] On the other hand, the holding circuit 3 repeats the operation of holding every other bit of the transmission data SD given to the data input D of the FFC 301 according to the CLK _Pc3 , and the output Q of the FFC 301 At the same time, the first bit f is taken out from the data input D, and the data given to the data input D is taken out as the second bit e, and these are given to the adder 2 as continuous data e and f. The adder 2 includes an AND gate 201 that inputs the rear bit e and the output g of the FFC 101, and an exclusive OR (hereinafter referred to as EXOR) gate 20 of the same inputs.
2, and an EXOR gate 204 whose inputs are the first bit f and the output h of the FFC 102, and
Each output of each gate 201, 204 is input
It is composed of EXOR gate 205,
Based on the outputs g, h and continuous data e, f from each stage of the frequency divider 1, the addition outputs i, j according to the logical conditions in Table 2 are sent out, and the lower addition output i
In addition to controlling the FFC 101, the FFC 102 is also controlled by the addition output j of the higher order.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, phase modulation is performed with a simple configuration, and reliability is improved and costs are reduced.
Remarkable effects can be obtained in polyphase modulation for various applications.

[Brief explanation of drawings]

The figure shows an embodiment of the present invention, and FIG. 1 is a circuit diagram;
FIG. 2 is a timing chart showing waveforms at various parts in FIG. 1. 1... Frequency divider, 2... Adder, 101, 102
...FFC (flip-flop circuit: binary counter), P _c1 ...CLK (clock pulse), P _t ...
TMP (timing pulse), SD...transmission data,
S _PM ...Phase modulation signal, e, f...Continuous data,
i, j...addition output.

Claims (1)

[Claims] 1 ⁿ bits of continuous data
In a method for performing phase modulation, a clock pulse having a frequency 2 ⁿ times the carrier wave frequency is divided by an n-stage frequency divider, each stage consisting of a binary counter, to generate the carrier wave; A modulo 2 ⁿ addition output is obtained from the continuous bit data and the output from each stage of the frequency divider, and each stage of the frequency divider is changed to the state before the modulation timing according to the addition output at each modulation timing. A phase modulation system characterized in that the phase of the carrier wave is determined by setting the opposite state, and the final stage output of the frequency divider is used as a modulation output.