JPH04167611A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To easily test an IC by enabling the input signal of a flip-flop circuit to be observed as its output by providing an exclusive OR circuit, and controlling the clock signal of the flip-flop circuit arbitrarily. CONSTITUTION:The exclusive OR circuit 12 is provided. The clock signal 22 and a scan clock signal 23 are connected to the input terminal of the exclusive OR circuit 12, and when the scan clock signal 23 is set at a low level, the clock signal 22 is handled preferentially, and the circuit is operated as an ordinary flip-flop circuit 11. When a positive clock waveform is inputted to the scan clock signal 23, an edge from the low level to a high level, or the one from the high level to the low level is inputted to the clock terminal C of the flip-flop circuit 11 without depending on the clock signal, and the flip-flop circuit 11 reads in an input signal 21, and outputs it to the output terminal 24 of the flip-flop circuit 11. Thereby, the IC can be easily tested.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flip-flop circuit for facilitating LSI testing.

[Prior Art] As ICs become more highly integrated, their circuit scale increases and their functions become more complex. As a result, testing of ICs has become a very difficult problem.

Generally, IC circuits are divided into combinational circuits and sequential circuits, and the latter sequential circuits, such as flip-flop circuits and latch circuits, are a factor that hinders IC testing. Therefore, the flip-flop circuit
In order to improve the controllability and observability of latch circuits, techniques such as shift register methods and access methods, as well as flip-flop circuits and latch circuits with their respective characteristics, have been considered. There were required circuit constraints. Some of the typical constraints are shown below.

1) The clock signal of the flip-flop circuit is controlled by a path from the external clock input terminal through only the gate.

2) The flip-flop circuit should not operate if the external clock input terminal is turned off.

3) When transferring data between latch circuits, do not use the same clock signal for both clock signals.

4) AND of clock signals is prohibited.

5) Prohibition of loops consisting only of gates.

[Problems to be Solved by the Invention] The present invention provides a flip-flop circuit that facilitates IC testing, has excellent controllability and observability, and has no circuit restrictions required of the original circuit. .

[Means for Solving the Problem] A flip-flop circuit is provided with a scan clock terminal that receives a scan clock signal that can be directly controlled from the outside, and an exclusive OR circuit, and the output terminal of the exclusive OR circuit is connected to the flip-flop circuit. A clock signal and a scan clock signal are connected to the input terminal of the flip-flop circuit, and a control signal is optionally sent to the clock terminal of the flip-flop circuit using the scan clock signal. It is characterized by having the function of providing

[Function] With the above configuration and function, the clock signal of the flip-flop circuit can be arbitrarily controlled, and the human input signal of the flip-flop circuit can be easily observed as its output, which facilitates testing.

[Embodiment] FIG. 1 shows an embodiment of a flip-flop circuit according to the present invention. In FIG. 1, 11 is a flip-flop circuit, and the clock terminal is an exclusive OR circuit 12.
connected to the output terminal of

A clock signal 22 and a scan clock signal 23 are connected to an input terminal of the exclusive OR circuit 12.

When the scan clock signal 23 is at a low level, the clock signal is given priority and the circuit operates as a normal flip-flop circuit. When a positive lock waveform is input to the scan clock signal, an edge from a low level to a high level or from a high level to a low level is input to the clock terminal of the flip-flop circuit 11 without depending on the clock signal, and the flip-flop circuit 11 The input signal 21 is read and outputted to the output terminal 25 of the flip-flop circuit according to the present invention.

From the above, it can be seen that the present invention is a flip-flop circuit with excellent controllability and observability, which does not require any circuit restrictions on the basic circuit due to the above configuration and functions, facilitates IC testing, and has excellent controllability and observability. Although the embodiment described here is based on a D-type flip-flop circuit, it is not limited to the flip-flop circuit type, and can also be applied to a latch circuit.

[Effects of the Invention] As ICs become more highly integrated, circuit scales increase and functions become more complex, creating test patterns with high failure coverage requires a huge amount of time and effort. According to the circuit of the present invention, a highly reliable test pattern with a high failure coverage rate can be easily created, which contributes to reducing the number of man-hours, shortening the test pattern length, and reducing the CPU load of the tester.

Moreover, it can be realized without any circuit restrictions on the basic circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a flip-flop circuit of the present invention. 11- Flip-flop circuit 12- Exclusive OR circuit 21- Human input signal 22- Clock signal 23- Scan clock signal 24- Output terminal and above Applicant: Seiko Epson Corporation

Claims (1)

[Claims] In the flip-flop circuit, a scan clock terminal that receives a scan clock signal that can be directly controlled from the outside and an exclusive OR circuit are provided, and an output terminal of the exclusive OR circuit is connected to a clock terminal of the flip-flop circuit, A clock signal and a scan clock signal are connected to the input terminal of the exclusive OR circuit, and a control signal can be arbitrarily applied to the clock terminal of the flip-flop circuit using the scan clock signal. flip-flop circuit.