JPH04165529A - Fifo memory control circuit - Google Patents

Abstract

PURPOSE:To control the FIFO memory by an arbitrary data quantity by comparing the data of a counting circuit for counting the data quantity stored in the FIFO memory and the data of a request register set on the system and executing the read-out and write control of the FIFO memory. CONSTITUTION:The data quantity stored in an FIFO memory 431 is counted and stored in a register 433. Subsequently, data of the register 433 and data of a read-out number request register 120 are compared by a comparator circuit 130, and when the data of the register 433 is above the data of the read-out number request register 120, OUTPUT READY becomes active. Accordingly, when a receiving equipment 420 sets an arbitrary number of data for requesting read-out to the read-out number request register 120, thereafter, it will suffice that said equipment controls only whether an OUTPUT READY signal being an output signal of the comparator circuit 130 becomes active or not. In such a way, the read-out control of the FIFO memory can be executed by an arbitrary data quantity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to control of a FIFO memory that stores data in a first-in, first-out manner.

[Prior Art] As a prior art, there is Japanese Patent Application Laid-Open No. 62-225050.

In the figure, (410) is a transmitting device, (420) is a receiving device, (430) is a FIFO control circuit, <440)
is the data bus on the transmitting side, (45G) is the data bus on the receiving side, and (431) is the FI that sends data first in first out.
F○ memory, (432) is F○ memory (431)
A counter (433) is a register that stores the value of the counter (432). Also,
n represents the number of bits of data; 9m represents the number of bits of the counter.

Next, the operation will be explained. First of all, the transmitter (4
1G) The data from the file is FIFO Memo IJ (431
)l,: At the same time as writing, the counter (432) counts up by l in response to the write signal WR.

Conversely, when data is read from the FIFO memory (431) by the receiving device (420), the counter (432) counts by 1 due to the H output signal RD.
Go down. On the other hand, the contents of the counter (432) are stored in the register (433), and the received bag ft (420
) can be read out. As a result, the receiving device (
420) is the FTPO according to the contents of the register (433).
Reading from the memo IJ (431) can be controlled.

However, when this method is adopted, the receiving device (420')
It is necessary to constantly monitor the contents of the register (433).

Furthermore, since it was necessary to read and control the contents of the register (433) one by one, the load on the receiving device was heavy and high-speed processing was difficult. Therefore, JP-A-1-121926 and JP-A-1-126722 have been devised as a system for controlling reading and writing of the FIFO memory (431) while reducing the load on the transmitter/receiver. All of these inventions count the amount of data in the FIF'O memory (431) to reduce the load on the transmitter/receiver, and
FLAG (flag indicating that the amount of data in the FIFO memory is O) and FULLFLAG (FIFO
This flag outputs a flag indicating that the amount of data in the memory is full.

[Problems to be solved by the invention] Among the conventional techniques, JP-A-62-225050 uses FIFO
Although it was possible to control the memory with an arbitrary amount of data, there was a problem in that the load on the transmitter/receiver was heavy. On the other hand, JP-A-1-+21926 and JP-A-1-12672
2 was able to reduce the load on the transmitter/receiver, but the FIF
In order to perform control based on the flag output from O memory,
There is a problem in that reading and writing cannot be controlled with an arbitrary amount of data.

The object of the present invention is to obtain a circuit that is capable of high-speed processing by reducing the load on a transmitting/receiving device.

[Means to solve the problem] A FIFO memory control circuit according to the present invention is as follows.

FIFO memory stores data first in, first out.

A counting circuit that counts the amount of data stored in this FIF○ memory, a read count request register that sets the number of reads necessary for the system, or a write count request register that sets the number of writes, or both. A comparison circuit was provided to compare the data of the circuit and the data of these registers.

"Operation" In this invention, the data of a counting circuit that counts the amount of data stored in the FIFO memory is compared with the data of a request register set on the system, and based on the comparison result, reading and writing of the FIFO memory is performed. Take control.

One example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows one embodiment of this invention, in which 1 FIFO
Read control of the memory control circuit will be explained in detail. In V, (+10) is a counting circuit that counts the amount of data stored in the FIFO memory (431), (+20) is a read number request register that stores the number of read requests requested by the receiving side, (130)
is a comparison circuit that compares the data of the counting circuit (110) and the data of the readout number request register (120), and 0UTPUT REAI)Y is the comparison circuit (
130). Also, (43+
) to (433) are equivalent to those shown in FIG.

The operation will be explained. As in the case of the third part 1, at the same time that the transmitting device (410) writes data to the F+F○ memory (431), the counter (432) counts up by l, and conversely, the receiving device (432) counts up by l. When the data is read from the F' TFO memory (4:'II) by the counter (420), the counter (432) counts down by l.As a result, the counter (432) reads out the data stored in the FIFO memory (430) The amount of data stored can be counted.

This value is also stored in a register (433). On the other hand, the number of readings requested by the receiving device (420) is stored in the number of readings request register (120). The data in the register (433) and the data in the readout number request register (+20) are compared by a comparison circuit (+30), and the data in the register (433) is greater than or equal to the data in the readout number request register (120). If there is 0U
Activate TPUT READY.

Therefore, the receiving device (420) sets the arbitrary number of data requested to be read into the readout number request register (+20), and then the 0UTPtJT READY signal, which is the output signal of the comparison circuit (13fl), becomes active. You only need to control whether it is. As a result,
It becomes possible to control reading of an arbitrary amount of data from the FIF○ memory, and the load on the receiving device can be reduced.

There are various ways to use the 0UTPLIT READY signal, such as sensing the flag when the receiving device (420) reads data, or sending an interrupt signal when the amount of data in FIF○ becomes less than the number of read requests. As,
It may also be transmitted to a receiving device.

FIFO memory which is another embodiment of this invention
! The same applies to the integrated control circuit. Provide a write number request register, compare, and create INPUT READY. Therefore, as in the above explanation, the transmitting device (410) only needs to set the arbitrary number of data requested to be written in the write request number register, and the rest is the output signal of the comparison circuit.
It is only necessary to control whether the INPIJT READY signal is active.

There are various ways to use the INPUT READY signal, and as above, it may be used as a flag sense, or it may be used as a flag sense.
It may also be used as an interrupt signal. Also, FIFO
A subtraction circuit may be used to determine the amount of data free space in the memory (431), or the initial value of the counter (432) may be set to K, which is the maximum amount of data that can be stored, instead of 0, and then transmitted. When the device (410) writes data to the FIFO memory (431), the counter (432)
When counting down by 1 and reading it out, the counter (4
32) may be incremented by one.

Further, other embodiments will be described. FIG. 2 explains in detail the read and write control of the FIFO memory control circuit.

In the figure, (121) is a write number request register.

(131) is a comparison circuit that compares the data of the write number request register and the data amount of the counter, and (201) is a subtraction circuit that calculates the free space of the FIFO memory from the difference between the maximum capacity @ and the data of the counter. Everything else is the same as already explained.

At the same time that data is written from the transmitting device (410) to the FIF○ memory (431), the counter (432) counts up by 1, and conversely, data is written from the FIF○ memory (431) to the receiving device (420). At the same time as is read out, the counter (432) counts down by one. As a result, the transmitting device (4]0) and the receiving device (
420) independently accesses the FIFO memory (43]), the counter (432) always
The amount of data stored in the FO memory (431) is accurately counted, and this value is stored in the register (433).

On the other hand, if the receiving device (420) sets the number of data read requests in the read number request register (120), and the transmitting device (410) sets the number of data write requests in the write number request register (+21), The rest is the output of the comparison circuit (+30) and (+31) ○UTPUT
Reading and writing may be controlled based on the READY and INPLIT READY signals.

At this time, it may be used as a flag sense as above, or I
It may also be used as an I entry. Also, in Figure 2, FIF
One counter (432) is used to count the amount of data stored in the O memory (431), and the FIFO memory (4
3]), a subtraction circuit (20+) is used to count the amount of free data in A method may also be used in which a counter is prepared, this initial value is set as K, which is the maximum capacity of 6J that can be stored in the FIFO memory (431), and the counter is counted down by 1 at the time of writing.

;Effects of the Invention] As described below, according to the present invention, the counting circuit counts the storage data of the FIFO memory V or F.
Compare the free space in IFO memory and the amount of data in the request register in which the required number of systems 1- is set, and based on the comparison result,
Since the IFO memory is controlled, reading or writing of arbitrary data qt to the FIFO memory can be controlled, and the load on the transmitting and receiving sides can be reduced.

[Brief explanation of drawings]

FIG. 1 is a FIFO memory read control circuit diagram which is one embodiment of the present invention, and FIG. 2 is a FIFO memory read control circuit diagram which is another embodiment of the present invention.
FIG. 3 is a conventional FIFO memory control circuit diagram. In the figure, (110) is a counting circuit, (120) is a read number request register, (121) is a write number request register (1ao) (fat) + i comparison circuit, (431)
liF I FO, +lmo! There is J Te. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] FIFO memory that stores data first-in, first-out, and this F
A counting circuit that counts the amount of data written to the IFO memory and the amount of data read from this FIFO memory, and a read count request register that sets the number of reads required for the system or sets the required number of writes. A FIFO comprising one or both of the write number request registers and a comparison circuit that compares the data of the counting circuit with the data of the read number request register or the write number request register.
Memory control circuit.