JPH041434B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a sense amplifier system for a semiconductor memory device.

[Technical Background of the Invention] FIG. 4 shows a part of a typical configuration example of a conventional dynamic RAM (random access memory). That is, 1 is an input address buffer into which an address signal is input, 2 is a refresh address generator that generates a refresh address signal, 3 is an address multiplexer, LR is a row decoder line,
RD ₁ , RD ₂ , RD ₃ , RD ₄ ...... are row decoders,
WL ₁ , WL ₂ , WL ₃ , WL ₄ ...... are word lines,
MC ₁ , MC ₂ , MC ₃ , MC ₄ ...... are memory cells,
BL, is a bit line, DMC ₁ , DMC ₂ are dummy memory cells, DWL ₁ , DWL ₂ are dummy word lines,
SA is a sense amplifier, LS is a sense latch control signal line, SE is a sense signal, Q _{B B} is a bit line selection transistor controlled by the column decoder (CD) output, DL is a data line, 4 is an output circuit,
C _B is the capacitance of the bit line, and C _R is the capacitance of the row decoder line.

Each of the memory cells _MC1 ...... consists of one capacitor C _S and one transfer gate Q, and has information "0" or "1" depending on whether charge is stored in the capacitor C _S or not. It is something to remember. However, the charge accumulated in the capacitor C _S usually decreases over time due to leakage or the like. Therefore, before the accumulated charge is completely lost, it is necessary to read it once and then write it again to accumulate the charge again. This operation is called refresh, and in general, dynamic RAM requires the above-mentioned refresh operation. For example, in a 256K bit dynamic RAM, there is a restriction that all memory cells must be refreshed at least once every 4ms.

FIG. 5 shows the sequence of operations in a memory configured to perform the above-mentioned refresh periodically, and normal read/write operations cannot be performed during the refresh period. This is because, for example, when refreshing a certain memory cell _MC1 , this
This is because it is not possible to read data from other memory cells connected to the bit line BL used for the operation of _MC1 . Therefore,
In computer systems using RAM,
During the period when RAM is being refreshed
Even when you want to access RAM, the RAM cannot be used, so you have to wait before accessing the RAM during the refresh period, which equivalently increases the time it takes to access the RAM, which is a hindrance to speeding up the process. That's a problem.

Here, the operation of the dynamic RAM will be briefly described with reference to the timing waveforms shown in FIG. A cycle of memory operation begins when an address signal input changes or a chip enable signal (not shown) is input. First, bit line BL,
When BL is precharged and then, for example, word line WL ₁ is selected by the above address signal input, this word line WL ₁ and the dummy word line
DWL ₁ becomes high level, and the memory cell MC ₁ and dummy cell connected to them
Each transfer gate Q of DMC ₁ opens, and the respective accumulated information appears on the bit line BL, and a minute potential difference is generated between the bit lines BL and BL. Next, when the sense signal SE is activated, the sense amplifier
SA operates and senses and amplifies the potential difference between bit lines BL and BL. At this point the memory cell
Since MC ₁ remains selected by word line WL ₁ , bit line BL remains selected after the above sense operation.
The information stored in memory cell _MC1 is refreshed by the potential. At the same time, the information on bit line BL is transmitted to data line DL via bit line selection transistors _QB and _B. This data line DL,
The information read out to DL undergoes waveform shaping etc. in the output circuit 4, and output data _Dput is obtained with a considerable delay from the sensing operation.

Dynamic RAM that involves a refresh operation as described above has the disadvantage that it is difficult to use because it burdens the user to always keep the refresh timing in mind when designing system products. . On the other hand, dynamic RAM has the advantage that it is suitable for high-density storage and can be realized at low cost because the area of the memory cell is usually 1/4 of that of static RAM that does not involve a refresh operation.

Therefore, although the above-mentioned refresh operation is involved, so that the user does not need to be aware of it, that is, the user can use it as if it were a static RAM, the normal operation and the refresh operation are performed in a time-sharing manner. simulated statistics
RAM is proposed. This pseudo static
An overview of the operation in the RAM will be explained with reference to FIG. This operation differs from the operation described above with reference to FIG. 6 in that (1) the selected word line (for example, WL ₁ ) and a predetermined dummy word line (for example, DWL ₁ ) are driven in a pulsed manner; (2) The sense amplifier SA is driven in a pulsed manner by the sense signal SE to sense the potential difference generated between the bit lines BL and (3) The data sensed by the sense amplifier SA is sent to the output circuit 4. The bit line BL, is precharged once to its original state during the period from 1 to 1 until it is completely output, and after a short delay, a word line other than the selected word line WL ₁ (for example,
WL ₃ ) and a given word line (e.g. WL ₂ )
is selectively driven in a pulsed manner and the word line WL ₃
The data in the memory cell _ML3 connected to the memory cell MC3 is read out, and the sense amplifier SA is pulse-driven again by the SE signal to sense the bit line potential difference, thereby rewriting the memory cell _MC3 ( Refreshment) is carried out.
Note that the memory cell where this refresh is performed
Since the data of MC ₃ does not need to be output from the output circuit 4, this refresh operation is performed relatively quickly. That is, in the operation shown in FIG. 7, the refresh operation of another memory cell is completed temporally in parallel with the normal access operation. Note that in the above operation example, cell selection for refresh operation is performed after cell selection for normal access operation, but conversely, even if it were performed earlier in time, it would not have too much of a negative impact on normal operation. does not occur. In addition, in the above operation example, the refresh operation is completely completed before the read data from the normal access operation is output from the output circuit 4, but if the refresh operation takes a little longer, the normal access This method can be adopted if it is determined that the pseudo-static method, in which the user does not see (or does not need to worry about, the refresh operation) the refresh operation, has a great advantage even if it increases the time required.
Further, the time it takes for the word line selected for the refresh operation to return to the unselected state may be longer than the time it takes for the word line selected in the normal access operation to return to the unselected state. . Further, in the above operation example, word line selection is performed twice within one memory cycle to perform refresh, but refresh does not necessarily have to be performed for each cycle. This is because refreshing only needs to be performed once for each memory cell within a fairly long period, and in the above operation example, the memory cell _MC3 to be refreshed, the bit line BL,
Since this is a case where the memory cell _MC1 which happens to be shared is accessed, the word line is selected twice within one cycle. If not, i.e. when trying to refresh
If the RAM is not being accessed, just refresh it.

[Problems with background technology]

By the way, since there is a delay associated with the large stray capacitance _CD in the data line DL, it takes quite a long time to drive it by the sense amplifier SA, and the data line DL is driven. During this time, the sense amplifier SA cannot move on to the next job (refresh operation in the above example). If the sense amplifier SA operates slowly as described above, the cycle time will become slow if the sense amplifier SA is operated more than once in one cycle as described above.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and
The present invention provides a sense amplifier system for a semiconductor memory device that speeds up the bit line potential sensing operation by the sense amplifier and enables the sense amplifier to be driven more than once in one cycle even if the cycle time is short. be.

[Summary of the invention]

That is, the sense amplifier system of the semiconductor memory device of the present invention is provided with a latch circuit that latches the output of the sense amplifier, and a plurality of the latch circuits are connected to the data line through a switch circuit, respectively. This is characterized in that a switch circuit on the sense amplifier output side is provided between the sense amplifier output side and the sense amplifier output side. Therefore, after the first information sensed by the sense amplifier is latched by the latch circuit, it is possible to control the switch circuit on the output side of the sense amplifier to an OFF state and cause the sense amplifier to sense the second information. Become.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 schematically shows a part of a semiconductor memory integrated circuit, with SA ₁₁ to SA ₁₄ ,...
and SA ₂₁ to _{SA 24} , . . . are sense amplifiers, and the first bit line pairs (BL ₁₁ , ₁₁ ) to (BL ₁₂
~ ₁₂ ), ...... and (BL ₂₁ , ₂₁ ) ~
(BL ₂₄ , ₂₄ ), ......, and each of these bit lines is connected to the bit lines BL, BL, shown in Fig. 4.
Similar to BL, a plurality of memory cells of a memory cell block and one dummy cell are connected.
LA ₁₁ is a latch circuit that connects the sense amplifier.
Switch circuits S ₁₁ and S ₁₂ are arranged between SA ₁₁ and SA ₁₂ to control the connection between the latch input terminal and each output terminal of the sense amplifiers SA ₁₁ and SA ₁₂ . It is provided. In the same manner as above, latch circuit LA ₁₂ and switch circuits S 12 and S ₁₄ are connected to sense amplifiers _{SA 12} and SA ₁₄ .
A latch circuit LA 21 and switch circuits S ₂₁ and S ₂₂ are provided corresponding to _the sense amplifiers SA ₂₁ and SA _22.
A latch circuit LA 22 and switch circuits S ₂₂ and S ₂₄ are provided corresponding to _the sense amplifiers SA ₂₃ and SA _24.
is provided.

On the other hand, 2BL ₁ and 2 ₁ are the bit lines (BL ₁₁ ,
BL ₁₁ ) to (BL _{14 to 14} ) _{, .} , ₂₁ ) to (BL ₂₄ , ₂₄ ), . . . are second bit line pairs provided in parallel on both sides. The connections between the bit line pairs 2BL ₁ , 2 ₁ and the latch output terminals of the latch circuits LA ₁₁ , LA ₁₂ , . Switch circuits 2S ₁₁ , 2S ₁₂ , . . . are provided for the bit line pairs 2BL ₂ , 2 ₂ and the latch outputs of the latch circuits LA ₂₁ , LA ₂₂ , . Switch circuits _2S21 , _2S22 , .

2SA ₁ is the second bit line pair 2BL ₁ , 2 ₁
A second sense amplifier is connected to the data line pair DL via a switch circuit _2S1 . Similarly, _2SA2 is a second sense amplifier connected to the second bit line pair _2BL2 , ₂₂ , and is connected to the data line pair DL via a switch circuit _2S2 . 4 is an output circuit connected to the data line pair DL, C _B , C _2B ,
C _D is the wiring capacitance.

Next, an example of the operation of the above memory will be explained. During a normal read operation, for example, the bit line pair
When sensing the information of BL ₁ , ₁ , first the above information is sensed and amplified by the sense amplifier SA ₁₁ . At this time, the above sense amplifier SA ₁₁ and the latch circuit
The switch circuit S 11 between the latch circuit LA ₁₁ and the switch circuit S ₁₁ may be closed or open, but the other switch circuits S ₁₂ and 2S ₁₁ connected to the latch circuit LA ₁₁ are open, and at the latest the sense amplifier SA ₁₁ When the sensing operation is completed, the switch circuit _S11 is closed and the data of the sense amplifier _SA11 is transferred to the latch circuit _LA11 and latched. After this, even if the switch circuit SA ₁₁ is opened, the latch circuit LA ₁₁ latches the data. Then, the switch circuits 2S ₁₁ and 2S ₁ close, and the latch circuit LA ₁₁ connects the second bit line pair 2BL ₁ , 2 ₁ and the data lines DL,
is driven, and the information on the bit lines 2BL ₁ , 2 ₁ is sensed and amplified by the second sense amplifier 2SA ₁ . The output of the sense amplifier _2SA1 is read out to the output circuit 4 via the switch circuit _2S1 and the data line pair DL.

In the above operation, in order for the latch circuit CA ₁₁ to drive the second bit lines 2BL ₁ and 2 ₁ , the large wiring capacitances C _B and _CD must be charged and discharged, which increases the required time. However, even when this latch circuit LA ₁₁ is driving the second bit lines 2BL ₁ and 2 ₁ and the data line DL, the switch circuit S ₁₁ between this latch circuit LA ₁₁ and the sense amplifier SA ₁₁ is If left open, the sense amplifier _SA11 can be operated freely without adversely affecting the data line DL. Therefore, first, normal read data is sensed by the sense amplifier SA ₁₁ and then latched to the latch circuit CA _11. When the latch circuit LA ₁₁ is disconnected from the sense amplifier SA ₁₁ by the switch circuit S ₁₁ , the sense amplifier
SA ₁₁ can operate for the next refresh on bit line BL ₁₁ or the memory cell connected to BL ₁₁ . That is, the latch circuit
The second bit line 2BL ₁ , where LA ₁₁ is heavily loaded,
The above refresh operation can be fully incorporated while driving the data line _2BL1 and the data line DL.

By the above-described operation, the sense amplifier SA ₁₁ can be used once for a normal read operation and once for a refresh operation during one cycle. in this case,
During reflex operation, the sense amplifier SA ₁₁
Since there is no need to read out the data read out to the output circuit 4, there is no need to transfer the data of the sense amplifier _SA11 to the latch circuit _CA11 . Further, the output circuit 4 normally has a latch function and latches only the read data for the normal operation.

FIG. 2 shows a representative example of a part of the bit line group, sense amplifier group, latch circuit group, and switch circuit group. Here, the sense amplifier SA ₁₁ consists of a CMOS type sense amplifier including a drive transistor controlled by a pair of sense signals SE, and similarly a latch circuit LA _11.
The switch circuit S11 is composed of a CMOS type latch circuit including a drive transistor controlled by a pair of latch signals LE, the switch circuit _S11 is composed of an N-channel transistor controlled by a switch signal _φ1 , and the switch circuit _2S11 is a CMOS type latch circuit including a drive transistor controlled by a pair of latch signals _LE , It consists of an N-channel transistor controlled by.

The above embodiment shows a memory with a folded bit line type configuration, but FIG. 3 shows a part of the case where the present invention is applied to a memory with an open bit line type configuration. Here, the latch circuit _LA11 ' has a latch input terminal connected to the output terminal of the sense amplifier _SA11 via the switch circuit _S11 , and a latch output terminal connected to the switch circuit 2.
It is connected to one second bit line _2BL1 via _S11 '. Similarly, the latch circuit CA ₁₂ ′ is connected to the sense amplifier SA ₁₂ via the switch circuit S ₁₂ and to the second bit line 2BL 1 via the switch circuit 2S ₁₂ ′, and is connected to the second bit line 2BL ₁ via the switch circuit 2S 12 ′. Similarly to the above, switch circuits S ₂₁ , S ₂₂ , ...... are connected between the circuits LA ₂₁ ′, LA ₂₂ ′, and the corresponding sense amplifiers SA ₂₁ , SA ₂₁ , and so on. 2S ₂₁ ′, 2S ₂₂ ′ . . . are connected to the second bit line 2BL ₂ .

In the above memory, for example, the sense amplifier
After the sense operation of SA ₁₁ , the sense data is latched to the latch circuit LA ₁₁ ′ and the switch circuit S ₁₁ is opened, so that the latch circuit CA ₁₁ ′ is connected to the second bit line 2.
While driving _BL1 and the data line DL connected thereto via the switch circuit _2S1 , the sense amplifier _SA11 can freely perform the next refresh operation. In addition, the above latch circuit
The data latched by CA ₁₁ ' is “1” or “0”
Therefore, the second bit line and the data line do not have to be a pair, but only one can be used as in the above example.

Note that the present invention is not limited to a memory that performs a normal read operation and a refresh operation during one cycle as described above, but can also be applied to a general memory for the purpose of increasing the speed of a sense amplifier. That is, in this case, the first sense operation in one cycle is used to read data by accessing the first address, and after latching this first read data, it is transferred from the data line to the output circuit. During the transmission, the sense amplifier may be disconnected from the latch circuit and left free, and may be used for data reading by the next second address access. In this way, sensing of the subsequent data is completed during the signal delay on the data line, so pipeline-like or parallel control is possible, and for the second read data, It appears as if the sense time is zero. In other words, high-speed operation is possible when reading several consecutive pieces of data.

〔Effect of the invention〕

As described above, the sense amplifier system of the semiconductor memory device of the present invention includes a latch circuit between the sense amplifier and the data line, and determines the timing relationship between the latch circuit and the sense amplifier and the connection between the latch circuit and the data line. By appropriately setting the sense amplifier, the speed of the sense amplifier can be increased, and even if the cycle time is short, sensing operations can be performed more than once in one cycle. Therefore, it is particularly suitable for a pseudo-static memory in which a normal operation and a refresh operation are performed in a time-division manner within one cycle.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a part of a semiconductor memory according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of a part of the circuit in FIG. FIG. 4 is a block diagram showing a part of a conventional semiconductor memory, and FIG. 5 shows the difference between normal operation and refresh operation in the memory shown in FIG. 4. 6 is a diagram showing an example of the operation of the memory shown in FIG. 4, and FIG. 7 is a timing diagram showing an example of the operation of the memory in which normal operation and refresh operation are performed in one cycle in a time-sharing manner. be. BL ₁₁ ~ BL ₁₄ , ₁₁ ~ ₁₄ , BL ₂₁ ~ _{BL 24} ,
BL ₂₁ to ₂₄ ...Bit line, 2BL ₁ , 2 ₁ , 2
BL ₂ , 2 ₂ ... second bit line (data line),
DL, ...data line, SA ₁₁ , SA ₁₂ , SA ₂₁ ,
SA ₂₂ ...Sense amplifier, LA ₁₁ , LA ₁₂ , LA ₂₁ ,
LA ₂₂ , LA ₁₁ ′, LA ₁₂ ′, LA ₂₁ ′, LA ₂₂ ′...Latch circuit, S ₁₁ ~ S ₁₄ , S ₂₁ ~ S ₂₄ , 2S ₁₁ , 2S ₁₂ , 2
S ₂₁ , 2S ₂₂ , 2S ₁ , 2S ₂ , 2S ₁₁ ′, 2S ₁₂ ′, 2
S ₂₁ ′, 2S ₂₂ ′...Switch circuit.

Claims (1)

[Claims] 1. A sense amplifier that senses and amplifies information on the bit line of the memory cell array, a latch circuit that latches the output of this sense amplifier, and a column decoder output connected between the latch circuit and the data line. a switch circuit to be controlled; and a sense amplifier output side switch circuit connected between the sense amplifier and the latch circuit; . A sense amplifier system for a semiconductor memory device, wherein a switch circuit on the output side of the sense amplifier is controlled to be in an off state so that the sense amplifier can sense second information. 2. The sense amplifier system for a semiconductor memory device according to claim 1, wherein the first information is generated by a normal read operation, and the second information is generated by a refresh operation. 3. A sense amplifier system for a semiconductor memory device according to claim 1, wherein the bit line is divided into a large number of parts.