JPH04133438A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture the title semiconductor capable of enhancing the hot carrier resistance using the conventional processing technology by a method wherein sidewalls are formed on the sidewall thick parts of a gate electrode having thick central part and then low concentration diffused layers using the thick region as a mask and high concentration diffused layers using thin region as masks are formed. CONSTITUTION:A gate oxide film 2a is formed on one conductivity type semiconductor substrate 1; a gate electrode 3 having thick central part is formed on the gate oxide film 2a; and sidewalls 7a are formed on the sidewalls in the thick region of the gate electrode 3; while said semiconductor substrate 1 is provided with the other conductivity type low concentration diffused layers 8 formed using the thick region of the gate electrode 3 as a mask and the high concentration diffused layers 9 formed using the sidewalls 7a as masks. For example, a partly thick polycrystal silicon film is formed on the gate oxide film 2a and after the formation of the concentration diffused layers 8 using the thick region as a mask, the sidewalls 7a are formed. Finally, after the formation of the high concentration diffused layers 9, the polycrystal silicon film in the needless part is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device with high hot carrier resistance and a method for manufacturing the same.

Conventional Technology In order to prevent transistor deterioration due to hot carriers, which has become a major problem as LSIs become smaller, transistors with various structures have been developed.4 Conventional semiconductor devices are explained below. is a sectional view of a conventional N-channel MO3) transistor (see Japanese Patent Laid-Open No. 54-44482). As shown in the figure, even though a gate electrode 10 made of a polycrystalline silicon film is formed on a P-type silicon substrate 1 via an oxide film 2a, a diffusion layer 9 serving as a source and a drain is formed outside the sidewall 7a. A low concentration diffusion layer 8 extends from the diffusion layer 9 to below the gate electrode 10 to form a transistor. Such an N-channel MOS transistor is formed as follows. First, P-type silicon substrate 1
A polycrystalline silicon film is deposited on top of the oxide film 2a.
The polycrystalline silicon film is etched using a photoresist as a mask to form the gate electrode 10. Next, phosphorus ions or arsenic ions are implanted into the surface of the P-type silicon substrate 1 to form a low concentration diffusion layer 8. Next! q An oxide film is deposited on the surface of the P-type silicon substrate 1, and the oxide film is etched using an etch-back method to form the sidewall 7a.
Next, arsenic ions are implanted into the surface of the P-type silicon substrate 1 to form a diffusion layer 9 that will serve as a source or drain to complete the transistor. Since the electric field near the source or drain of the transistor is relaxed, the injection of holes or electrons into the oxide film 2 is controlled, and deterioration of transistor characteristics due to hot carriers is prevented. 1 is a sectional view of an N-channel MO3) transistor (see Japanese Patent Laid-Open No. 63-95669). As shown in the figure, a gate electrode lO made of a polycrystalline silicon film is formed on a P-type silicon substrate 1 with an oxide film 2a interposed therebetween.

A diffusion layer 9 serving as a source and a drain is formed outside the gate electrode 10, and a low concentration diffusion layer 8 extends from the diffusion layer 9 to below the gate electrode 10 to form a transistor. A channel MOS transistor is formed as follows: First, a polycrystalline silicon film is deposited on a P-type silicon substrate 1 via an oxide film 2a, and a gate electrode 10 is formed by depositing the polycrystalline silicon film using a photoresist as a mask. Sumo gate electrode 1
A protective film 11 is formed on the P-type silicon substrate 1. Next, phosphorus ions or arsenic ions are implanted under the gate using a large angle ion implantation method to form a low concentration diffusion layer 8. A transistor is completed by implanting arsenic ions to form a source or drain diffusion layer 9. In this semiconductor device (the low concentration diffusion layer 8 is connected to the gate electrode 10)
As a result of the overlap, the electric field near the source or drain is further relaxed compared to the conventional example shown in FIG. 3, and hot carriers are suppressed, further improving reliability. In addition, since the low concentration diffusion layer 8 is formed under the gate electrode IO, the actual gate length is shortened.
However, in the conventional configuration described above, in order to increase the penetration of the low concentration diffusion layer 8 under the gate electrode 10 and improve hot carrier resistance (ion implantation), the driving force of the transistor increases. The former method requires a larger angle and higher implantation energy.The former method is difficult in highly integrated LSIs, and the latter method has the problem of increasing damage to the gate oxide film 2a. SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and aims to provide a semiconductor device and a manufacturing method thereof that can improve hot carrier resistance using conventional process technology.

Means for Solving the Problems In order to achieve this object, a semiconductor device of the present invention (in which a gate electrode having a thick center portion is formed on a semiconductor substrate of one conductivity type with a gate oxide film interposed therebetween), A sidewall is formed on the sidewall of the thick part of the semiconductor substrate, and a low concentration diffusion layer of the other conductivity type is formed using the thick region of the gate electrode as a mask, and a high concentration diffusion layer of the other conductivity type is formed using the thin region of the gate electrode as a mask. With this configuration, an overlap between the gate and the diffusion layer (hereinafter referred to as gate overlap structure) can be easily realized using conventional process technology. The amount of the low-concentration diffusion layer penetrating under the gate can be easily controlled by changing the width of the sidewall, and the reliability of the transistor against hot carriers can be easily improved. 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention. 2a is formed. Even if a partially thick polycrystalline silicon film 3 is formed on this gate oxide film 2a, a silicon nitride film used for selective oxidation is formed on this polycrystalline silicon film 3. (hereinafter referred to as nitride film) 4 remains, a sidewall 7a is formed on the thin region of the polycrystalline silicon film 3, that is, on the sidewall of the thick region of the polycrystalline silicon film 3. 1, an N-type low concentration diffusion layer 8 is formed using the thick region of the polycrystalline silicon film 3 as a mask, and an N-type high concentration diffusion layer 9 is further formed using the sidewall 7a as a mask. Even if the concentration diffusion layer 8 forms the drain, the second
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be explained along the process cross-sectional views shown in FIGS. 2(a) to 2(j). First, as shown in FIG. niL
An OGO3 oxide film 2a of about 600 nm and a gate oxide film 2a of about 20 nm are formed in predetermined regions. Next, as shown in FIG. 3B, a polycrystalline silicon film 3 of about 300 nm is deposited by low pressure CVD. Next, as shown in the same figure (C), a nitride film 4 of approximately 20 Or+m
accumulate. Next, as shown in FIG. 2D, a resist pattern 5 is formed using photolithography. Next, as shown in FIG. 4(e), the nitride film 4 is processed into the same shape as the resist pattern 5 using dry etching technology, and then the resist pattern 5 is removed. Next, the same figure (f)
As shown in FIG. 3, polycrystalline silicon film 3 is oxidized by about 250 ron in the thickness direction using nitride film 4 as a mask to form oxide film 6. Next, the oxide film 6 is removed by wet etching.

Next, as shown in the same figure (g), using the thick region of the polycrystalline silicon film 3 as a mask, phosphorus ions are applied at about 2X at about 60 KeV.
A low concentration diffusion layer 8 for constituting a drain is formed by implanting 10"atoms/cm, and then a silicon oxide film 7 of about 300 nm is deposited by low pressure CVD as shown in FIG. 2(h). Next, as shown in Figure (i), the silicon oxide film 7 is etched by anisotropic dry etching
Then, using the side wall 7a as a mask, arsenic ions are etched to form the side wall 7a.
Approximately 5 x 10"atoms/Cm's at 0KeV are implanted into the drain region to form a high concentration diffusion layer 9.
Next, as shown in FIG. 2(j), the polycrystalline silicon film 3 other than the region that will become the gate electrode is etched and removed. Also, the polycrystalline silicon film 3 having regions with different thicknesses as shown in FIG. The pattern of the film 3 can be effectively used not only as a gate electrode but also as a part of a crossover in a multilayer wiring. In other words, the polycrystalline silicon film in most areas except for a portion of the crossover is made thick, ions are implanted into this polycrystalline silicon film to lower its electrical resistance, and then an insulating film is formed over the entire surface of the polycrystalline silicon film. By forming conductive wiring made of aluminum or the like on the thin region of the film, it is possible to make the surface flat as a whole.4 Effects of the Invention As described above, the present invention has the following advantages: A transistor having a gate overlap structure can be easily formed, and the amount of the low concentration diffusion layer penetrating under the gate can be easily controlled by controlling the sidewall width. As a result, the reliability of transistors against hot carriers can be improved, and the practical effect is significant (°C

[Brief explanation of the drawing]

Figure 1 is a cross-section of a main part of a semiconductor device according to an embodiment of the present invention @ Figures 2 (a) to (j) are process cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention Cross section of conventional N-channel MOS transistor FIG. 4 is a cross-sectional view of another conventional N-channel MOS transistor. 1...P-type silicon substrate (semiconductor substrate), 2a.
... Gate oxidation [3... Polycrystalline silicon film (gate electrode), 7a... Side wall, 8...
・Low-concentration diffusion seed 9... Name of high-concentration diffusion agent Patent attorney Akira Okaji and 2 people Figure P-type silico) Motoki (1000 II Fuden) Shima I Arrogance Several layers

Claims (3)

[Claims] (1) A gate oxide film is formed on a semiconductor substrate of one conductivity type, a gate electrode with a thick center portion is formed on the gate oxide film, and the side walls of the thick region of the gate electrode are A sidewall is formed, and the semiconductor substrate includes a low concentration diffusion layer of the other conductivity type formed using the thick region of the gate electrode as a mask, and a high concentration diffusion layer formed using the sidewall as a mask. semiconductor device. (2) forming a gate oxide film on a semiconductor substrate of one conductivity type; forming a partially thick polycrystalline silicon film on the gate oxide film; a step of forming a low concentration diffusion layer of the other conductivity type using the thick region as a mask; a step of forming a sidewall on the sidewall of the thick region of the polycrystalline silicon film; and a step of forming a high concentration diffusion layer of the other conductivity type using the sidewall as a mask. A method for manufacturing a semiconductor device, comprising: forming a diffusion layer; and removing unnecessary portions of the polycrystalline silicon film, leaving a thick region of the polycrystalline silicon film and a region under the sidewall. (3) A step of selectively forming an oxidation-preventing film on the polycrystalline silicon film formed on the insulating film on the semiconductor substrate, and using the oxidation-preventing film as a mask in one direction in the thickness direction of the polycrystalline silicon film. and a step of etching away the oxidized region of the polycrystalline silicon film, forming a polycrystalline silicon film pattern having a partially thick region. .