JPH04111669A - Picture reader - Google Patents

Abstract

PURPOSE:To prevent deformation of a black level of a picture and fog of a highlight part by providing a light shield part on part of a light receiving section and using an output signal of the light shield section so as to correct level fluctuation of other effective picture element section. CONSTITUTION:A signal converted into a digital video signal at an A/D converter section of a video processing circuit is inputted to latch circuits 401, 402 in a dark state output voltage correction circuit. The latch circuit 401 samples a level of a light shield picture element section in a timing of a clamp pulse phiCLP and the latch circuit 402 samples a level of an idle transfer section in a timing of a clamp pulse phiSAMP. The level of the light shield picture element section and the idle transfer section latched by the latch circuits 401, 402 is inputted to an address input of a correction ROM 404. The correction ROM 404 acts like a lookup table, from which a value of B/A is outputted as a correction value. Let ambient temperature at level adjustment be 30 deg.C, then B is a dark state output voltage level of the effective picture element section and A is a level at a dark state output voltage of the light shield picture element section.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image reading device, and more particularly to an image reading device using a CCD image sensor or the like, which has a light shielding part in a part of a light receiving part. The present invention relates to an image reading device that corrects signals of other effective pixels using the output signals of the pixels.

[Conventional technology] FIG. 13 shows a conventional image reading device.

In the figure, 1601 is a 3-line color CCD image sensor, which is composed of three dual-channel CCD image sensors 1602 to 1604, and is configured to transfer the charges of odd and even pixels separately, and on the sensor element, R, G, and B organic color separation filters are arranged.

102a and 102b are buffer amplifiers, each with an R-C
It receives the odd pixel signal 101a and the even pixel signal 1otb of the CD image sensor 1602 and performs impedance conversion. 103a and 103b are sample and hold circuits (S/H), which are output in time series (R
- Odd pixel signal 101 of CCD image sensor 1602
a. Reset noise contained in the even-numbered pixel signal 101b is removed. 104a and 104b are clamp amplifiers as correction means, and each amplifier 104a-1
, 104b-1 and clamp circuits 104a-2, 104b
-2, the clamp amplifier 104a clamps the DC offset level of the odd pixel signal from which reset noise has been removed by the sample and hold circuit 103a to 0■, and the clamp amplifier 104b from which reset noise has been removed by the sample and hold circuit 103b. This is to clamp the DC offset level of the even-numbered pixel signal to the same level (Ov) as the clamp amplifier 104a. 105
is a multiplexer as a combining means, which inputs the odd pixel signal and the even pixel signal from the clamp amplifiers 104a and 104b, and sequentially combines the odd pixel (ODD) signal and the even pixel (EVEN) signal at the timing shown in FIG. 14 (10). ) signals to obtain serial pixel signals in the order of pixel arrangement of the light receiving section of the R-CCD image sensor 1602 as shown in FIG.

Reference numeral 106 denotes a variable amplifier as variable amplification means, which amplifies the output level of the serial pixel signal output in time series by the multiplexer 105 up to the dynamic range of the A/D converter 108.

107 is a clamp amplifier, and the variable amplifier 106
The DC offset level of the serial pixel signal amplified to the dynamic range of the A/D converter 108 is clamped to the lowest reference level of the A/D converter 108, that is, 0.

The A/D converter 108 converts an analog pixel signal, which is a serial pixel signal whose DC offset has been corrected by the clamp amplifier 107, into a digital pixel signal.

FIG. 16 shows the configuration of the 3-line color CCD image sensor 1601 shown in FIG. 13.

In the figure, 161 is a light receiving section that performs photoelectric conversion according to the amount of incident light (only R is given a reference numeral; the same applies to G and B). R, G, and B color separation filters are arranged directly on the CCD sensor element of this light receiving section 161. Further, at the top of the light receiving section 161, there is a light shield pixel section for always obtaining an output in a dark state by placing an aluminum mask on the light receiving section 161 to block incident light. Transfer gates 162 and 163 transfer the charges accumulated in the light receiving section 161 to the CCD shift registers 164 and 165 in response to a shift gate pulse φTO. Light receiving section 16
The charges accumulated in one even-numbered pixel are transferred to each CCD shift register 16 for even-numbered pixels by a transfer gate 163.
On the other hand, the charges accumulated in odd-numbered pixels of the light receiving section 161 are transferred to each CCD shift register 164 for odd-numbered pixels by a transfer gate 162.

The CCD shift registers 164 and 165 CCD transfer (complete transfer) the charge sent from the light receiving section 161 side to the output section, and drive clocks φ, (φlF++ φl□).

φIQ+ φIFG, φI11. φIF
ll) and φ2(φ21+, φ2rFl+φ2Q,
It is driven in two phases by φ2WQ + φ2B, φ2□).

166 is an output gate, which transfers the charge to each CCD register 1.
64 and 165 to the output capacitor sections 167a and 167b. Reference numerals 167a and 167b are output capacitance sections that convert transferred charges into voltage. 168a and 168b are two-stage source follower amplifiers that lower the output impedance and prevent noise from being added to the output signal.

FDA (Floatin
g Diffusion Amplifier) and tail.

03AR, 03BR, 03AG, 03BG, 03A
B, 03BB are signal output terminals, φRAR, φRBR,
φRAG, φRBG, φRAB, and φRBB are reset pulse terminals, φIR, φIG, φIB, and φ2R.

φ2G and φ2B are COD shift register clock terminals, φTGR, φTGG, and φTGB are transfer gate clock terminals, and ODR, ODG, and ODB are source follower amplifier drain terminals.

In the color image sensor 1601 configured in this way, the light incident on the light receiving section 161 is converted into an electric charge proportional to the amount of light, and this electric charge is converted into a shift gate pulse φ.

The driving clock φ1. φ
2, one bit at a time is output to the FDA via the output gate 166 at the timing shown in FIG. 14, and the output capacitor section 167a of the FDA.

The charge output is converted to voltage at 167b, and then
It is outputted via two stage source follower amplifiers 168a, 168b and respective output terminals O3A, O3B.

When no light is applied to the light receiving section 161, the output voltage level of the light shield pixel section and the effective pixel section should be essentially the same, but the light shield pixel section is provided with an aluminum mask on the same light receiving section as the effective pixel section. Because of the structure in which the aluminum mask is formed, stress different from that in the effective pixel part, which is another light receiving part, is applied thereto, and the generated dark current may be greater than that in the effective pixel part.

Then, in a state where no light is applied to the light receiving section 161, a difference in output voltage level occurs between the light shield pixel section and the effective pixel.

[Problem to be solved by the invention]

Incidentally, the temperature coefficient of dark current of the silicon (Si) semiconductor forming the C, CD image sensor is as shown in FIG. That is, it is known that the dark current increases approximately twice every time the temperature rises by 8°C.

Therefore, as mentioned above, if there is a step in the dark output voltage level between the light shield pixel part and the effective pixel when no light is applied to the light receiving part 161, the light shield pixel part will be damaged due to temperature rise due to ambient temperature, self-heating, etc. The difference in the dark output voltage level between the effective pixel and the effective pixel increases.

Furthermore, in the conventional example shown in FIG. 13, the voltage level of the light shield pixel part is adjusted by clamping the dark output voltage level from the light shield pixel part to a reference level (for example, O[■]) using a clamp circuit. The output voltage of the effective pixel portion is obtained as a reference. Therefore, in such a case, the DC level of the output voltage of the effective pixel portion fluctuates due to the temperature increase, causing collapse of the black portion of the image, fogging of the highlight portion, etc., resulting in image deterioration.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image reading device that can solve the above-mentioned problems and prevent image deterioration.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a light shield pixel section in which a light shielding layer is provided in a part of the light receiving section to block the incidence of light, and an output signal corresponding to the level of the incident light is provided. an image sensor having an effective pixel section to be obtained, and an empty transfer section having a predetermined number of pixels provided at a position where signals from the light shield pixel section and the effective pixel section are transferred; and the light shield pixel section. a first correction means for correcting the output signal of the image sensor to a reference level based on the output level of the transfer section; and a second correction means for correcting the reference level of the first correction means based on the output level of the idle transfer section. According to the present invention, the above structure corrects level fluctuations in the effective pixel portion, thereby eliminating the collapse of black portions and fogging of highlight portions of the image. Prevented.

[Examples] Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an image reading device to which the present invention is applied;
FIG. 2 is a diagram showing an example of a schematic internal configuration of the device.

In FIG. 1, the same parts as in FIG. 13 are indicated by the same reference numerals.

In FIG. 2, 100 is a document pressing plate, and 102 is a document 14.
110 is a mirror unit composed of a halogen lamp 1501 for exposing an original and a first reflective mirror 105, and 111 is composed of a second reflective mirror 106 and a third reflective mirror 107. It is a mirror unit.

A 3-line color CCD sensor 108 receives a reflected light image from the original 102 exposed and scanned by a halogen lamp 1501.
A lens unit for forming a reduced image on 601,
Mirror units 110 and 111 are moved by a stepping motor 109 at a scanning speed of 2:1 in the direction of arrow A (sub-scanning direction).

When reading an original, the halogen lamp 1501 is turned on, and the stepping motor 109 is used to expose and scan the width of the original 102 placed on the platen glass 1402 in the direction of arrow A. When the exposure scanning of the original 102 is completed, the halogen lamp 1501 is turned on. The light goes out, and the mirror unit 110 is returned to the home position in the opposite direction of arrow A.

3 line color CCD sensor 1601 while scanning exposure
The color separated image signals read line by line are input to a video processing circuit 100 shown in FIG. 1 and subjected to signal processing.

Furthermore, in this embodiment, the signal processing systems for the output signals of the R, G, B CCD image sensors 1602, 1603, and 1604 have the same circuit configuration;
The image sensor 1602 will be mainly explained, and the G and B signal processing systems will be omitted from illustration.

102a and 102b are buffer amplifiers, each of which receives the odd pixel signal 10 of the R-CCD image sensor 1602.
1a and even-numbered pixel signals 1i11b to perform impedance conversion. Reference numerals 103a and 103b are sample and hold circuits (S/H) that remove reset noise contained in the odd pixel signals of the R-CCD image sensor 1602 outputted in time series]01a and the even pixel signals 101b. It is.

104a and 104b are clamp amplifiers as correction means, and are amplifiers 104a-1 and 104b-1, respectively.
and clamp circuits 104a-2 and 104b-2, and the clamp amplifier 104a sets the DC offset level of the odd pixel signal from which reset noise has been removed by the sample-and-hold circuit 103a to a reference level V, . . . =O
The clamp amplifier 104b clamps the DC offset level of the even pixel signal from which reset noise has been removed by the sample hold circuit 103b to the reference level Vrllf2 output from the voltage control circuit 109.

105 is a multiplexer as a combining means, which inputs the odd pixel signal and the even pixel signal from the clamp amplifiers 104a and 104b, and sequentially combines the odd pixel (ODD) signal and the even pixel signal at the timing shown in FIG. 3 (10). Pixel (E
VEN) signal as shown in Figure 16.
- Serial pixel signals are obtained in the order of pixel arrangement of the light receiving section of the CCD image sensor 1602.

Reference numeral 106 denotes a variable amplifier as variable amplification means, which amplifies the output level of the serial pixel signal output in time series by the multiplexer 105 up to the dynamic range of the A/D converter 108. Control voltage VCO output from
Voltage controlled amplifier (Vo
ltage Control Amplifier：V
CA).

Reference numeral 107 denotes a clamp amplifier, which converts the DC offset level of the serial pixel signal amplified to the dynamic range of the A/D converter 108 by the variable amplifier 106 to the control voltage ■coNT of the voltage control circuit 111.
3, the lowest reference level VBOT of the A/D converter 108
a. M (in this embodiment, V80T, = OV). The A/D converter 108 converts an analog pixel signal, which is a serial pixel signal whose DC offset has been corrected by the clamp amplifier 107, into a digital pixel signal.

Reference numeral 112 denotes a dark output voltage correction circuit, which samples the output level of the idle transfer section (described later) shown in FIG.
11 setting data is corrected to always keep the level of the effective pixel portion of the digital image signal constant.

FIG. 3 is a timing chart of the image reading device in this embodiment.

In FIG. 3, (1) φTG is a transfer gate pulse for transferring the charge accumulated under the light receiving portion to the CCD shift register, (2) φl, φIF and (3) φ2. φ2F is CCD
Two-phase drive pulse that drives the shift register, (4) φRA is a set pulse that resets the residual charge remaining in the output capacitance section of the CCD shift register for odd pixel transfer, (5) φRB is a CCD shift register for even pixel transfer. (6) O3A and (7) O3B are odd pixel output and even pixel output, respectively. (8) S/HODD and (9) S/HEVEN are odd number pixel outputs. A sample-and-hold pulse of a sample-and-hold circuit 103a that samples and holds pixel outputs and a sample-and-hold circuit 10 that samples and holds even-numbered pixel outputs.
3b sample and hold pulse, (10) SELECT is the multiplexer 105 in FIG.
CC is added to the CC
This is a multiplex pulse that makes the pixel arrangement the same as that of D.

Note that D7 to D+a are light shield pixel parts, 1 to 5
006 is an effective pixel section, and Dzs~040 is an empty transfer section.What differs from the conventional example is that the CCD is driven so as to obtain this empty transfer section of Dza~040.

FIG. 4 is a diagram showing the configuration of the dark output voltage correction circuit 112.

401 is a latch circuit for sampling the data of the light shield pixel section of ~D+8 shown in FIG. 3 among the digital video signals output from the A/D converter 108 of the video processing circuit 100 of FIG. 1; 402 is a latch circuit for sampling the data of the empty transfer part of D2s to D4° shown in FIG. 3 in the digital video signal, and 403 is a latch circuit for sampling the data from the CPU that controls the voltage control circuit 111 from the data bus of the CPU. A setting register 404 is a correction ROM for outputting a correction value based on the data of the light shield pixel section and the empty transfer section latched by the latch circuits 401 and 402, and has a look-up table configuration. Reference numeral 405 denotes an adder circuit for calculating the sum of the data from the CPU that controls the voltage control circuit 109 set in the register 403 and the correction data of the correction ROM 404, and its output is output to the voltage control circuit 111.

Here, the voltage control circuit 111 will be explained.

According to FIG. 5, the voltage control circuit 111 is composed of an 8-bit multiplication type D/A converter 111a, operational amplifiers 1llb and 1llc, and resistors R and 2R (resistance values), and is a multiplication type D/A converter. Reference human power of the vessel 111a■1. ．． The value of is multiplied by four quadrants according to the set data value of the CPU (not shown), and an output voltage, for example, is output.

Since voltage control circuits 109 and 110 have the same configuration, voltage control circuit 110 will be representatively described.

Voltage control circuit 110 is voltage control circuit 1
11, an 8-bit multiplication type D/A converter 110a,
Consists of an operational amplifier 110b (Fig. 6)
, reference human power of the multiplication type D/A converter 110a ■1
．． ．． The value is multiplied by two quadrants according to the CPU setting data value, and the voltage becomes, for example, VcoN□2. I will do my best as VCON engineer 8.

Here, the difference between the voltage control circuits 110 and 111 is that the voltage control circuit 110 is a voltage control amplifier (VC
A) While the voltage control circuit 111 generates the control voltage VCOHT□ of 106
This clamp level is the lowest reference level vB0a of the A/D converter 108. It is almost the same as 2. Therefore, the reference power Vr s f of the multiplier A/D converters of the voltage control circuits 110 and 111 differs depending on the voltage to be controlled.

Next, the operation will be explained using the R-CCD image sensor 1602 as an example.

The structure of the CCD of the sensor 1601 is a dual channel type, and the odd and even charges of the sensor pixel 161 are transferred by separate CCD shift registers 164 and 165.
．． 165 causes a difference in the output DC offset level of odd-numbered pixels and even-numbered pixels.

Output signal 10 of R-CCD image sensor 1602 having a difference in output DC offset level between odd and even pixels
1a and 101b are buffer amplifiers 102a and 10
After the impedance is converted by 2b, the signal is input to sample and hold circuits 103a and 103b. This input signal is sent to sample and hold circuits 103a and 103.
b, the reset noise contained in the input signal is sampled and held according to the timing shown in FIG. 3 (8) and (9), and then each clamp amplifier 1
04a and 104b.

Then, the DC output level of the dark output section from the R-CCD image sensor 1602 is determined by the clamp amplifier 104a,
A predetermined reference level V, .

The other 8-power signal of the R-CCD image sensor 602 is sent to the clamp amplifier 10 by the clamp amplifier 104b.
Similar to 4a, the reference level Vr*f! At this time, the reference level Vr@f2 is the difference between the ODD/EVEN output data of the CCD output signal that is finally converted into a digital pixel signal by the A/D converter 108. It is detected by a CPU (not shown), and in this example, O
Reference level Vrll of crank amplifier 104a on DD side
Since fl is fixed at 0, a CPU (not shown) sends data to the multiplication type D/A converter of the voltage control circuit 109 according to the detected value so that the difference between ODD/EVEN disappears in the digital pixel signal. By setting the reference level Vr@f2, the DC offset level difference between the odd pixel signal and the even pixel signal is removed.

The odd pixel signal from which the DC offset level difference between the odd and even pixels has been removed is sent to the multiplexer 105 as shown in FIG.
) The odd-numbered pixel signals and the even-numbered pixel signals are sequentially switched and selected based on the timing shown in ), and are combined into the serial pixel signal of the line (■).

The arrangement of the serial pixel signals synthesized by the multiplexer 105 is the same as the pixel arrangement order of the light receiving section.

The serial pixel signals synthesized by the multiplexer 105 are amplified by the variable amplifier 106, and when the reference white plate is read and scanned by the R-CCD image sensor 1602, the output level reaches the maximum value of the dynamic range of the A/D converter 108. Almost approximated.

Here, the amplification degree of the variable amplifier 106 is set by a clamp amplifier 107, which will be described later, for the R-CCD image sensor 160.
After adjusting the dark output level of No. 2 to be the lowest level of the dynamic range of the A/D converter 108, the reference white board is read and the output data of the A/D converter 108 is sent to a CPU (not shown). The output data is A
/D converter 108 maximum dynamic range value FF,
The voltage control circuit 11
This is done by setting data to 0 from the CPU.

The R signal, which is regulated by the variable amplifier 106 to the maximum value of the dynamic range of the white level A/D converter 10g, is controlled by the clamp amplifier 07 to have an output level in the dark that is within the dynamic range of the A/D converter 108. Clamped to the lowest level.

Here, the clamp level of the clamp amplifier 107 is set by the clamp amplifiers 104a and 104b.
After the level difference of EVEN is removed, the output level during the dark period is read by a CPU (not shown) and fed back to the voltage control circuit 111 to adjust the control voltage V.
By raising and lowering the level of CONT2, the lowest level V of the dynamic range of the A/D converter 108 is set. Engineering T
. The level is adjusted to approximate 11.

In this way, the R signal whose maximum value and minimum value are regulated with respect to the dynamic range of the A/D converter 108 is
The D converter 108 converts it into a digital image signal.

The R-CCD image sensor 1602 has been described above, but the levels are similarly adjusted for the G-CCD image sensor 1603 and the B-CCD image sensor 1604, and the actual image reading operation is performed in this setting state. .

By the way, as explained in the conventional example, if the dark output voltage of the CCD differs between the light shield pixel portion and the effective pixel portion due to self-heating due to the operation of the CCD and temperature rise inside the device due to the reading operation, the seventh As shown in the figure, the effective pixel level at the time of level adjustment (3) is set to V of the A/D converter 108.
Adjust to about (1g) 1 above BOTTOM (OQH). In this case, when the dark output voltage increases due to temperature rise, the level increases in both the light shield pixel part and the effective pixel part, but since the light shield pixel part is always clamped at a constant level by the clamp circuit, the DC level increases. Although there is no change, the level difference between the dark output voltage of the light shield pixel part and the effective pixel part and the empty transfer part increases due to temperature rise, and as shown in (4), the level difference between the output voltage of the A/D converter 108 and the dark output voltage increases. As a result, the output of the A/D converter becomes OOH unless there is an input level of 67 or higher, resulting in blurred black areas in the image.

Note that (1) φTG in Figure 7 is the same as (1) φTG in Figure 3.
is the same transfer gate pulse as (2) φC
Similarly, LP is the same clamp pulse as φcLP in FIG. 3 (11).

Therefore, in the present invention, the above-mentioned problem is corrected using a dark time output correction circuit 112 as shown in FIG.

The correction method shown in FIG. 4 will be described in detail below in conjunction with FIG. 3. A/D converter 1 of video processing circuit 100 in FIG.
The signals converted into digital video signals in step 08 are input to latch circuits 401 and 402 in the dark output voltage correction circuit 112.

The latch circuit 401 samples the level of the light shield pixel portion at the timing of φCLP in FIG. 3 (11),
The latch circuit 402 samples the level of the idle transfer section at the timing of φ3□2 in FIG. 3 (12). The levels of the light shield pixel section and the empty transfer section latched by the latch circuits 401 and 402 are input to the address input of the correction ROM 404. The correction ROM 404 is a look-up table, and a value such as B/A shown in the graph of FIG. 8 is output as a correction value.

That is, in FIG. 8, the solid line shows how the dark output voltage increases with respect to the ambient temperature of the effective pixel part, and the broken line is a similar graph of the light shield pixel part. These values are all determined based on the level of the empty transfer section.

Therefore, assuming that the ambient temperature at the time of level adjustment is 30°C, the dark output voltage level of the effective pixel portion at that time is B
If the level of the dark output voltage of the light shield pixel section is A, the value of (B/A) at that time is determined at the time of initial setting, and based on that value, the latch level of the light shield pixel section and the idle transfer section are determined. The latch level of is used as the address input, and the correction value of the level of the effective pixel portion is made into a look-up table and written to the correction ROM 404 (the correction data of the correction ROM 404 is stored in the voltage control circuit 111 at the time of initial setting).
register 40 from the CPU data bus to set
After the addition circuit 405 calculates the sum with the data set to 3, the sum is output to the voltage control circuit 111.

Here, when the level difference between the empty transfer section and the light shield pixel section increases due to temperature rise, the correction ROM 404 provides a correction value that can be considered as the level of the effective pixel section by multiplying the level difference by (B/A). is output, added to the initial setting value, and output to the voltage control circuit 111.
1 output, the clamp level of the clamp amplifier 107 is finally raised, and the level of the effective pixel portion is corrected to the same level as the initial setting.

[Other Examples]

FIG. 9 shows another embodiment of the invention.

The embodiment shown in FIG. 1 and the embodiment shown in FIG. 9 differ in the correction means, but have the same structure in other respects.

That is, in the embodiment shown in FIG. 1, in order to correct the dark output voltage, as shown in FIG. 4, digital data at two locations, the light shield pixel section and the idle transfer section, are sampled as the dark output voltage. A correction value is obtained from that value using a correction ROM, and the value is added to the setting data of the D/A 109a that determines the clamp level of the clamp amplifier 107.
D/A is set to 109a.

On the other hand, in FIG. 9, first, the dark pressure voltage value to the dark output voltage correction circuit 901 is not the output digital data of the A/D converter 108 but the input analog signal of the A/D converter 108. The configuration of the correction circuit is different from the embodiment shown in FIG. That is, a voltage control circuit 902 having a different configuration from the voltage control circuit in FIG. 5, and a dark output voltage correction circuit 90 having a different configuration from the dark output voltage correction circuit in FIG.
1, and the output ■ of the dark output voltage correction circuit 901. 0NT
4 and the output VCON 3 of the voltage control circuit 902 are added together to obtain a voltage (■) that controls the clamp level of the clamp amplifier 107. Addition circuit 903 to obtain 0NTS
is used.

FIG. 10 shows the configuration of voltage control circuit 902.

Although the configuration is the same as the voltage control circuit in Figure 4,
The difference is that the data setting to the D/A 1lla is not done from the dark output voltage correction circuit (directly from the CPU), but the output voltage VCON□ is input to the adder circuit 903.

FIG. 11 is a configuration diagram of the dark output voltage correction circuit 901, which is a sample hold circuit that samples and holds the voltage level of the light shield pixel portion of the output signal of the clamp amplifier 107 at the timing of ψCLP in FIG. 3 (11). 110
Sample and hold circuit 1102 samples and holds the voltage level of 1 and the empty transfer section at the timing of φ□1 in FIG. , a D/A converter 1104 that outputs a voltage level corresponding to the coefficient (B/A) shown in FIG. 8 according to setting data from the CPU, and a subtraction circuit 1103
The analog multiplier 1 performs a multiplication operation based on the output voltage of the D/A converter 1104 to obtain the amount of change in the voltage level of the effective pixel portion, and outputs it to the addition circuit 903 as T4.
It is composed of 105. In other words, the amount of change X in the dark output voltage of the light shield pixel section is determined from the sample-held voltage levels of the empty transfer section and the light shield pixel section, and
As mentioned in the example of FIG. 1, the A converter 1104 obtains an output voltage Y corresponding to the output ratio CB/A of the light shield pixel part and the effective pixel part obtained at the time of initial setting, and outputs it to the analog multiplier 1105. VcoN as the output voltage VCONT4
The multiplication result y-=(Y/10)X is output, and the amount of change in the dark output voltage of the effective pixel portion is isometrically determined.

FIG. 12 shows an adder circuit 903, which is a non-inverting adder circuit composed of an operational amplifier 1201 and a resistor R (resistance value), and outputs the voltage control circuit 902. . 1. and dark output voltage correction circuit 901
is added to the output VCONT4 of VCONT@, and the clamp level of the clamp amplifier 107 is corrected.

Note that the timing of the correction is the same as in FIG. 3.

[Effects of the Invention] As described above, according to the present invention, it is possible to correct level fluctuations of effective pixels, and it is possible to prevent image deterioration such as blurring of black parts of an image and fogging of highlight parts.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an image reading device of the present invention, FIG. 2 is a diagram showing a schematic internal configuration of the image reading device of the present invention, FIG. 3 is a timing diagram of the image reading device of the present invention, and FIG. A block diagram of the dark output voltage correction circuit, FIG. 5 is a block diagram of the voltage control circuit 111, FIG. 6 is a block diagram of the voltage control circuit 110, and FIG. 7 is a block diagram of the light shield pixel section, effective pixel section, and idle transfer section. FIG. 8 is a diagram showing the dark output voltage temperature characteristics of the CCD, FIG. 9 is a block diagram of another embodiment of the image reading device of the present invention, and FIG. Example voltage control circuit 902
The configuration diagram of FIG. 11 is the dark output voltage correction circuit 901 of the embodiment in the same place.
, FIG. 12 is a configuration diagram of an adder circuit according to an embodiment of the same location, FIG. 13 is a configuration diagram of a conventional image reading device, FIG. 14 is a timing diagram of a conventional image reading device, and FIG. 15 is a diagram of a conventional image reading device. Figure 16 is a diagram showing the dark output voltage temperature characteristics of the light-receiving section of the CCD. 1601...3 line color CCD image sensor,
1602...R-CCD image sensor, 1603...
...G-CCD image sensor, 1604...B-C
CD image sensor, 101a... Odd pixel signal of R-CCD image sensor, 101b... Even pixel signal of R-CCD image sensor, 102a, 102b... Buffer amplifier, 103a
, 103b---3/H circuit, 104a 104b...
- Clamp amplifier, 105... Multiplexer, 106... Variable amplifier, 107... Clamp amplifier, 108... A/D converter, 109, 110.111... Voltage control circuit,
112... Dark output voltage correction circuit. Figure 4 Complementary circuit Figure CPU Figure 10 Figure

Claims (1)

[Scope of Claims] 1) A light shield pixel section in which a light shielding layer that blocks the incidence of light is provided in a part of the light receiving section, an effective pixel section that provides an output signal corresponding to the level of incident light, and the light shield. an image sensor having an empty transfer section with a predetermined number of pixels provided at a position where signals from the pixel section and the effective pixel section are transferred; A first correction means for correcting the output signal of the above to a reference level; and a second correction means for correcting the reference level of the first correction means based on the output level of the idle transfer section. image reading device. 2) The image reading device according to claim 1, wherein the first correction means is a clamp circuit.