JPH04119034A - Dual loop control system in information processing system - Google Patents

Abstract

PURPOSE:To select a loop by providing a start bit detection section connecting to each of duplicate loops to each terminal equipment so as to detect a start bit of a signal on a loop thereby using its detection signal to connect a transmission reception section of a terminal equipment and the loop causing the start bit. CONSTITUTION:When a loop check request is caused, an FF5 is reset by a clock t1, an FF6 is reset and the detection is started. When a reception signal falls down, a Q output of an FF1 falls down and an output Q of an FF2 falls down. An H output from an AND1 sets an FF5 and its output Q generates an H signal. An FF6 receives an H signal at the output Q of an FF5 and is set and its output generates an H signal. When the reception signal falls down once due to noise and rises again in a short time, even when the FF1 latches once the signal and the output Q goes to H. Although an H level is generated from the output Q of the FF5, the FF6 is not triggered yet by a clock t2. When the output Q of the FF1 goes to H, an input signal to an AND2 goes to H and its output goes to H, then the FF5 is reset and a start bit detection output is blocked.

Description

[Detailed Description of the Invention] [Summary] A duplex loop control method in an information processing system that connects a control device and a large number of terminal devices with a duplex loop and uses an asynchronous interface, which does not require identifying the loop to be used at startup and is simple. The purpose of this paper is to provide a duplex loop control method for an asynchronous ink face that can be controlled by a circuit.

Each terminal device is provided with a start bit detection section at the signal input terminal of each loop of the duplex loop.When starting up the system or recovering from a failure, each terminal device detects the start bit detection section in the two start bit detection sections. The detection output is used to select three usage loops.

[Industrial Application Field] The present invention relates to a duplex loop control method in an information processing system that connects a control device and a large number of terminal devices with a duplex loop and uses an asynchronous interface. Information processing systems are used in a wide range of fields, in which a large number of terminals are arranged for a control device, data input from each terminal is processed by the control device, and the processing results are output to each terminal. Then, the control device and a large number of terminal devices are connected in a loop (Imosuru-style transfer path).
A system that transfers data using a step-synchronized ink face is used, for example, in a voting system (horse racing ticket, etc.).

In such a system, the reliability of the system is ensured by duplicating the loop connecting the control device and the terminal device. However, it may not be possible to determine which of the duplex loops is currently in use from the terminal device's perspective, such as at the time of initial startup.

[Prior art] Figure 5 shows a system configuration using an asynchronous interface.
FIG. 6 shows the signal configuration of the start-stop synchronization interface.

The system shown in FIG. 5 processes data input via a loop from a plurality of terminal devices 51 in a control device 50, sends the processing results to each terminal device, and
A system is constructed in which a large number of terminal devices, such as a voting system, are installed in a certain area by performing processing such as aggregating and managing data from 1.

Data transfer is performed between the control device 50 and a plurality of terminal devices 51 using serial signals through an asynchronous interface via one of the duplicated loops.

The signal configuration of the start-stop synchronization interface is shown in Fig. 2.
It has a configuration in which data bits are arranged between a start bit and a stop bit with a waveform as shown in the figure.

Each loop 52, 53 is connected to each terminal device 51 as shown in FIG.
It is made up of sequentially adjacent transfer paths,
The terminal device 51 is provided with a receiver/driver (R/D), and data sent from the control device 50 to each terminal device 51 is taken in by the corresponding destination terminal device 51 and transmitted from the terminal device 51 to the control device 50. The addressed data is sent to the control bag w50 through the return route via the ImoTsuru connections in sequence.

The system of FIG. 5 typically has one loop (e.g.
52), data transfer is performed between the control device 50 and each terminal device 51, and if a failure occurs in the current loop (transfer path disconnection or transmission/reception circuit failure) and data cannot be transferred, the other side By switching to the loop 53, reliability is improved.

In such a duplex loop connection, it is necessary to determine which loop the control device is currently operating on, especially when initially starting up the system and when restarting the use of a terminal device that has recovered from a fault. I can't decide whether to send it or not.

Therefore, conventional methods have been used to fix the loop used at startup on the terminal device side (for example, fix it to loop 52 in Figure 5), or to always make it possible to receive data from both loops. Measures such as these are being taken.

[Problems to be Solved by the Invention] Among the methods for receiving data from the used loop in the duplex loop connection described above, the method of fixing the used loop is a method that prevents the use of the backup loop from being used at startup due to an abnormality on the control device side. , there was a problem that it became difficult to detect on the terminal device side. Also.

If it were possible to receive data from both loops, there would be a problem in that the receiving circuits for receiving signals from each loop would be duplicated, which would increase the size of the circuit and increase costs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a duplex loop control method for an asynchronous interface that does not require fixing the loop used at startup and can be controlled by a simple circuit.

[Failure to solve the problem] FIG. 1 is a diagram showing the principle configuration of the present invention.

In FIG. 1, IO is the first loop, 11 is the second loop, 12 is the terminal device, and 120 and 121 are the first loop, respectively.
a receiver and a driver (indicated by R/D) connected to the loop and the second loop, 122 is a first start hint detection section, 123 is a second start bit detection section, 124
125 represents a connection switching unit for connecting either the first loop or the second loop to the data transmitting/receiving unit 125, and 125 represents a data transmitting/receiving unit.

In the present invention, each terminal device is provided with a start bit detection section connected to each loop of the duplex loop, and when a start bit appearing on the loop is detected, the detection signal is used to connect the transmitting/receiving section of the terminal device to the start bit detection section.

This switch is used to connect the loop where the error occurred.

[Operation] The terminal device 12 has a first loop 10 and a second loop 11.
and R/D 120 and R,/D 121, respectively. One of these two loops 1011 is currently used by a control device (not shown), and the control device generates a signal having a signal configuration of an asynchronous interface.

Each terminal device 12 receives the signal on each loop from R/D 120 .
It is received on the R (receiver) side of 121. The first and second start bit detection units 122 and 123 each have a function of detecting the first start bit of the asynchronous signal configuration (see FIG. 6).

It is activated when a terminal device is initially started up or when a failure is recovered.

When either the first start bit detection section 122 or the second start bit detection section 123 detects a start bit, its detection output is supplied to the connection switching section 124 . The connection switching unit 124 selects the loop in which the detection signal has been generated and switches it to connect to the data transmitting/receiving unit 125, thereby connecting the currently used loop to the data transmitting/receiving unit 125.

In this way, the terminal device side can detect the loop currently being used by the control device and connect it to the data transmitting/receiving section without being aware of which loop the control device side will use during initial startup.

[Embodiment] FIG. 2 is a block diagram of the embodiment, FIG. 3 is a detailed circuit diagram, and FIG. 4 is a timing chart thereof.

In FIG. 2, 20 represents a control device, 21 represents a terminal device, and the transfer paths connecting the control device 20 and the plurality of terminal devices f21 are duplicated as shown in loop A and loop B. In the terminal device 21, corresponding to loop A and loop B, R/D 22a, 22b, falling detection circuits 23a, 23b, 2 time check circuits 24a, 24b,
Timing correction circuits 25a and 25b are provided, fall detection circuits 23a and 23b, and time check circuit 2.
4a and 24b are used to detect the start bit detection section (1 in Fig. 1).
22, 123).

To explain the operation, R/Ds 22a, 22 of the terminal device 21 are connected from loop A or loop B connected to the control device 20.
When the receiver R receives the start-stop synchronization signal on one side of the start/stop synchronization signal, the falling edge of the first start bit is detected by one of the falling edge detection circuits 23a and 23b. The time check circuit 24a checks that the falling edge continues for a predetermined period of time to prevent malfunctions caused by falling edge due to noise or the like. Time check circuit 24a or 2
A start bit detection output is generated from 4b.

The timing correction circuits 25a and 25b correct the timing of the signal from the receiver R using the clock signal of the terminal device, and input the signal to the connection switching circuit 26.

The connection switching circuit 26 performs a switching operation based on the start bit detection output, and switches to supply the output of the timing correction circuit 25a or 25b on the loop side where the start bit is detected to the data transmission/reception control circuit 27.

The data transmission/reception control circuit 27 is controlled by a central processing unit (
CPtJ)28. It is connected to a main memory (MM) 29 and an operation unit 30 that includes a keyboard and a display. The data sent from the control device 20 to the terminal device is stored in the MM 29 from the data transmission/reception control circuit 27.
The data transmitted from the terminal device 21 to the control device 20 (including data input from the operation unit 30) is MM
29 to the data transmission/reception control circuit 27, and from there, via the connection switching circuit 26, to the driver D connected to the loop in use.

FIG. 3 shows a specific circuit configuration of the falling edge detection circuit, the two-hour check circuit, and the timing correction circuit in the configuration of FIG. 2.

In FIG. 3, FFI to FF6 represent flip-flop circuits, and ANDI and AND2 represent AND circuits. tl, u
2 is a clock supplied to the clock terminal of the flip-flop circuit, tl has a cycle shorter than l bit length of asynchronous synchronization, and clock L2 has a cycle longer than tl.

To explain the timing correction operation shown in Fig. 3, R in Fig. 2 is explained.
The signals output from Lenoha R in /D, 22a, and 22b are input to the FFI. 20FFI is the clock signal t
1 (■ in Figure 4) to hold the input signal, its output is supplied to FF2, and is held in FF2 by the next clock signal t1, and its output is sent to FF3, which constitutes the timing correction circuit. ．． The input data, which is sequentially held by the clock signal tl and whose timing has been corrected, is outputted to the FF4. This output is input as a data signal to the connection switching circuit 26 shown in FIG.

On the other hand, in Fig. 3, the output Q of FFI and the output Q of FF2
A fall detection circuit is configured by the ANDI which inputs , and a time check circuit is configured by the FF5 which holds the output of the ANDI at the clock t1, the FF6 which operates at the primary clock t2 (t2>tl), and the AND2.

The output Q of FFI, the output Q of FF2, and the output Q of FF6 are input to AND2, and the output thereof is supplied as a reset input of FF5.

The start bit detection operation shown in FIG. 3 will be explained with reference to the timing chart shown in FIG. 4.

In this example, clock L1, clock L1, and clock t2 are each
As shown in FIG. 4 (■) and (■), it is assumed that the relationship t2=2xt1 exists.

When a loop detection request occurs, FF5 starts clock tl(
4), the FF6 is also reset by the clock t2 that arrives thereafter, and the detection operation is started.

When the received signal falls to a low level (indicated by "L") due to the appearance of the start bit as shown in ■ in Figure 4, the Q output of the FFI falls ('L'') in synchronization with clock t1 as shown in ■. ”) at the primary clock t1
The output Q of F2 similarly falls as shown in ■ (L”
become).

In this way, a high-level (indicated by "H") output is generated from ANDI for a certain period of time as shown in ■, FF5 is sent at the next clock L1, and the output Q is as shown in ■.
” signal is generated. After that, when clock L2 is generated,
The FF6 receives the "H" signal from the output Q of the FF5 and is set, and the output Q generates a ``H'' signal (start bit detection output) as shown in (3).

If the received signal (■) once falls due to noise and then rises in a short time as shown by the dotted line in (■) in Figure 4, even if the FFI holds the signal once, the output Q will go "H" at the primary clock t1. become. At this point, from the output Q of FF5 to 'H
” is generated, but FF6 is not yet triggered by clock t2.

During this time, if the FFI output Q becomes “H”, AND
Since all input signals of 2 become “H”, the output becomes ■
As shown by the dotted line, the signal becomes H'', so FF5 is reset and generation of the start bit detection output from FF6 is prevented.

In this way, when a rising edge is detected within a certain period of time, the previous falling edge is invalidated and the process waits for another falling edge.

Further, the gate switching signal outputted from the FF 6 is reset by the occurrence of a loop detection request at the time of initial startup of the terminal device or when an error is detected, and then a new check of the used loop is performed. If this reset is executed every time a stop focus is detected, loop switching can be performed in units of hides.

[Advantageous Effects of the Invention 1] According to the present invention, in a system that requires high reliability, a control device and a terminal device connected in a duplex loop can operate without being particularly aware of the loop in use. Moreover, it is possible to realize control of the multiplexed loop at a lower cost than with a simple configuration.

[Brief explanation of drawings]

Figure 1 is the principle configuration of the present invention, Figure 2 is a block diagram of the embodiment, Figure 3 is a concrete circuit diagram, Figure 4 is the timing chart of the third circuit, and Figure 5 is start-stop synchronization. System configuration by interface, Part 6 is the signal configuration of the asynchronous interface. 10 in Figure 1: First loop 11: Second loop 121: Receiver driver (R/D) 122: First start bit detection section 123: Second start bit detection section 124: Connection switching section 125: Data Transmitter/receiver

Claims (2)

[Claims] (1) A duplex loop control method in an information processing system using a start-stop synchronization interface, in which a control device and a large number of terminal devices are connected by a duplex loop, and each terminal device has a signal input terminal for each loop of the duplex loop. A start bit detection unit is provided in each of the two start bit detection units, and each terminal device selects the loop to be used using the start bit detection output of the two start bit detection units at the time of system startup or recovery from a failure. Duplex loop control method for information processing systems. (2) In claim (1), each start bit detection section provided corresponding to each loop includes a falling detection circuit that detects a falling edge of an input signal and generates a detection output, and a falling detection circuit that generates a detection output by detecting a falling edge of an input signal, and a falling detection circuit that generates a detection output by detecting a falling edge of an input signal, and a falling detection circuit that detects a falling edge of an input signal and generates a detection output. Duplication in an information processing system characterized by comprising: a falling duration check circuit that checks whether the time continues and generates an output when the duration continues; and a start bit holding circuit that holds the output from the duration check circuit. Loop control method.