JP7520177B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7520177B2 JP7520177B2 JP2023060114A JP2023060114A JP7520177B2 JP 7520177 B2 JP7520177 B2 JP 7520177B2 JP 2023060114 A JP2023060114 A JP 2023060114A JP 2023060114 A JP2023060114 A JP 2023060114A JP 7520177 B2 JP7520177 B2 JP 7520177B2
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- lead
- electrode
- semiconductor device
- back surface
- wire bonding
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- 239000004065 semiconductor Substances 0.000 title claims description 237
- 229920005989 resin Polymers 0.000 claims description 76
- 239000011347 resin Substances 0.000 claims description 76
- 150000004767 nitrides Chemical class 0.000 claims description 55
- 238000007789 sealing Methods 0.000 claims description 46
- 239000000758 substrate Substances 0.000 description 18
- 238000005530 etching Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 7
- 230000007774 longterm Effects 0.000 description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
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- 238000005452 bending Methods 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
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- WABPQHHGFIMREM-AKLPVKDBSA-N lead-210 Chemical compound [210Pb] WABPQHHGFIMREM-AKLPVKDBSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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Description
図1~図7に基づき、本開示の第1実施形態にかかる半導体装置A1について説明する。半導体装置A1は、複数のリード1~5、半導体素子6、ボンディングワイヤ71~74、および封止樹脂8を備えている。
図11および図12に基づき、本開示の第2実施形態にかかる半導体装置A2について説明する。これらの図において、先述した半導体装置A1と同一または類似の要素には同一の符号を付して、重複する説明を省略する。
図13および図14に基づき、本開示の第3実施形態にかかる半導体装置A3について説明する。これらの図において、先述した半導体装置A1と同一または類似の要素には同一の符号を付して、重複する説明を省略する。
図15に基づき、本開示の第4実施形態にかかる半導体装置A4について説明する。図 15において、先述した半導体装置A1と同一または類似の要素には同一の符号を付して、重複する説明を省略する。図15は、半導体装置A4を示す平面図である。図15においては、理解の便宜上、封止樹脂8を透過して、封止樹脂8の外形を想像線(二点鎖線)で示している。
図16に基づき、本開示の第5実施形態にかかる半導体装置A5について説明する。図16において、先述した半導体装置A1と同一または類似の要素には同一の符号を付して、重複する説明を省略する。図16は、半導体装置A5の半導体素子6を示す模式的な断面図である。
図17に基づき、本開示の第6実施形態にかかる半導体装置A7について説明する。図17において、先述した半導体装置A1と同一または類似の要素には同一の符号を付して、重複する説明を省略する。図17は、半導体装置A6の半導体素子6を示す模式的な断面図である。
窒化物半導体からなる電子走行層と、厚さ方向において互いに反対側を向く素子主面および素子裏面と、前記素子主面に配置された第1電極と、前記素子裏面に配置され、かつ、前記第1電極に導通する第2電極とを有する半導体素子と、
前記半導体素子が搭載され、前記第2電極が接合された第1リードと、
前記第1電極に電気的に接続された第2リードと、
を備え、
前記半導体素子はトランジスタであって、
前記第2リードは、前記第1リードから離間して配置され、かつ、スイッチングの対象である主電流が流れる、
ことを特徴とする半導体装置。
〔付記2〕
前記半導体素子を覆う封止樹脂をさらに備え、
前記第1リードの、前記厚さ方向において前記素子裏面と同じ方向を向く面は、前記封止樹脂から露出している、
付記1に記載の半導体装置。
〔付記3〕
前記半導体素子は、前記素子主面に配置された第3電極および第4電極をさらに備え
前記第3電極に電気的に接続された第3リードと、
前記第4電極に電気的に接続された第4リードと、
をさらに備える、
付記1または2に記載の半導体装置。
〔付記4〕
前記第2リードおよび前記第3リードは、前記厚さ方向視において、前記第1リードを挟んで互いに反対側に配置される、
付記3に記載の半導体装置。
〔付記5〕
前記厚さ方向視において、前記第1リードと前記第3リードとの離間距離は、前記第1リードと前記第2リードとの離間距離より大きい、
付記4に記載の半導体装置。
〔付記6〕
前記第3リードおよび前記第4リードは、前記厚さ方向視において、前記第1リードを挟んで互いに反対側に配置される、
付記3ないし5のいずれかに記載の半導体装置。
〔付記7〕 前記第1電極に電気的に接続され、前記第1電極の電位を出力する第5リードをさらに備える、
付記3ないし6のいずれかに記載の半導体装置。
〔付記8〕
前記第1電極と前記第2リードとを接続する第1ボンディングワイヤと、
前記第1電極と前記第5リードとを接続する第2ボンディングワイヤと、
をさらに備え、
前記第1ボンディングワイヤの本数は、前記第2ボンディングワイヤの本数より多い、付記7に記載の半導体装置。
〔付記9〕
厚さ方向視において、前記第5リードは、前記第2リードと前記第4リードとの間に配置されている、
付記7または8に記載の半導体装置。
〔付記10〕
前記第3電極と前記第3リードとを接続する第3ボンディングワイヤと、
前記第4電極と前記第4リードとを接続する第4ボンディングワイヤと、
をさらに備える、
付記3ないし9のいずれかに記載の半導体装置。
〔付記11〕
前記第1リードおよび前記第2リードが並ぶ方向と前記厚さ方向とに直交する第1方向において、前記第2リードの寸法は、前記第3リードの寸法より小さく、前記第4リードの寸法より大きい、
付記3ないし10のいずれかに記載の半導体装置。
〔付記12〕
前記第1電極はソース電極であり、
前記第3電極はドレイン電極であり、
前記第4電極はゲート電極である、
付記3に記載の半導体装置。
〔付記13〕
前記半導体素子は、
前記電子走行層に対して前記素子裏面側に配置された基板と、
前記電子走行層に対して前記素子主面側に配置され、かつ、窒化物半導体からなる電子供給層と、
前記電子走行層および前記電子供給層を貫通し、前記第1電極と前記第2電極とを導通させる導電部と、
をさらに備える、
付記1ないし12のいずれかに記載の半導体装置。
〔付記14〕
前記第1電極と前記第1リードとを接続する第5ボンディングワイヤをさらに備える、付記1ないし12のいずれかに記載の半導体装置。
〔付記15〕
前記電子走行層はGaNからなる、
付記1ないし14のいずれかに記載の半導体装置。
1 :第1リード
110 :搭載部
111 :搭載部主面
112 :搭載部裏面
113 :搭載部裏面側凹部
120 :連結部
121 :連結部主面
122 :連結部裏面
123 :連結部端面
130 :端子部
131 :端子部主面
132 :端子部裏面
133 :端子部端面
2 :第2リード
210 :ワイヤボンディング部
211 :ワイヤボンディング部主面
212 :ワイヤボンディング部裏面
213 :ワイヤボンディング部裏面側凹部
220 :端子部
221 :端子部主面
222 :端子部裏面
223 :端子部端面
230 :連結部
231 :連結部主面
232 :連結部裏面
233 :連結部端面
3 :第3リード
310 :ワイヤボンディング部
311 :ワイヤボンディング部主面
312 :ワイヤボンディング部裏面
313 :ワイヤボンディング部裏面側凹部
320 :端子部
321 :端子部主面
322 :端子部裏面
323 :端子部端面
330 :連結部
331 :連結部主面
332 :連結部裏面
333 :連結部端面
4 :第4リード
410 :ワイヤボンディング部
411 :ワイヤボンディング部主面
412 :ワイヤボンディング部裏面
413 :ワイヤボンディング部裏面側凹部
420 :端子部
421 :端子部主面
422 :端子部裏面
423 :端子部端面
430 :連結部
431 :連結部主面
432 :連結部裏面
433 :連結部端面
5 :第5リード
510 :ワイヤボンディング部
511 :ワイヤボンディング部主面
512 :ワイヤボンディング部裏面
513 :ワイヤボンディング部裏面側凹部
520 :端子部
521 :端子部主面
522 :端子部裏面
523 :端子部端面
6 :半導体素子
6a :素子主面
6b :素子裏面
60 :素子本体
601 :基板
602 :バッファ層
603 :第1窒化物半導体層
604 :第2窒化物半導体層
605 :第3窒化物半導体層
606 :保護膜
607 :導電部
61 :第1電極
62 :第2電極
63 :第3電極
64 :第4電極
71~75:ボンディングワイヤ
8 :封止樹脂
81 :樹脂主面
82 :樹脂裏面
83 :樹脂側面
10 :リードフレーム
1010 :主面
1020 :切断線
Claims (9)
- 第1リードと、
第2リードと、
前記第1リードに搭載された半導体素子と、
前記半導体素子と前記第1リードとを接続する接続部材と、
前記半導体素子を覆う封止樹脂と、
を備え、
前記半導体素子は、
厚さ方向において互いに反対側を向く素子主面および素子裏面と、
前記素子裏面よりも前記素子主面に近い位置に配置され、第1窒化物半導体で形成された電子走行層と、
前記電子走行層と前記素子裏面との間に配置され、かつ、前記第1窒化物半導体とは異なる第2窒化物半導体で形成された電子供給層と、
制御信号を入力されるゲート電極と、
前記素子主面に配置され、かつ、断面視において前記ゲート電極を間に介在させて互いに離間する第1電極および第3電極と、
前記素子裏面に配置されて前記第1リードに接合された第2電極と、
を備え、
前記第1電極は、前記電子走行層と電気的に接続される第1接続部を含み、
前記第3電極は、前記電子走行層と電気的に接続される第3接続部を含み、
前記第2リードは、前記第1電極と電気的に接続され、前記ゲート電極による制御に基づいて流れる状態と流れない状態とで切り替えられる電流を流すように構成され、
前記接続部材は、前記第1電極と前記第2電極とを電気的に接続し、前記第1電極に接合された第1端部および前記第1リードに接合された第2端部を含み、
前記第2端部は、前記第1リードの前記半導体素子の搭載位置の近傍に配置され、
前記封止樹脂は、第1樹脂側面と第2樹脂側面とを有し、
前記第2リードは、前記第2樹脂側面よりも前記第1樹脂側面の近くに配置され、
前記第1リードは、前記第2樹脂側面から露出する端面を有する連結部を備えている、半導体装置。 - 前記接続部材は、ボンディングワイヤである、
請求項1に記載の半導体装置。 - 前記第1リードの、前記厚さ方向において前記素子裏面と同じ方向を向く面の少なくとも一部は、前記封止樹脂から露出している、
請求項1または2に記載の半導体装置。 - 前記連結部は、前記厚さ方向において前記素子裏面と同じ方向を向く裏面を有し、
前記連結部の裏面の全体が前記封止樹脂で覆われている、
請求項1に記載の半導体装置。 - 前記第2リードは、前記封止樹脂から露出し、かつ、前記封止樹脂内で互いに電気的に接続された複数の端子を含んでいる、
請求項1ないし4のいずれかに記載の半導体装置。 - 前記半導体素子は、前記素子主面に配置された第4電極をさらに備え、
前記第3電極に電気的に接続された第3リードと、
前記第4電極に電気的に接続された第4リードと、
をさらに備える、
請求項1ないし5のいずれかに記載の半導体装置。 - 前記第2リードおよび前記第3リードは、前記厚さ方向視において、前記第1リードを挟んで互いに反対側に配置される、
請求項6に記載の半導体装置。 - 前記厚さ方向視において、前記第1リードと前記第3リードとの離間距離は、前記第1リードと前記第2リードとの離間距離より大きい、
請求項6または7に記載の半導体装置。 - 前記第3リードおよび前記第4リードは、前記厚さ方向視において、前記第1リードを挟んで互いに反対側に配置される、
請求項6ないし8のいずれかに記載の半導体装置。
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