JP7589574B2 - Multilayer wiring board - Google Patents

Description

The present invention relates to a multilayer wiring board.

In recent years, as semiconductor devices have become faster and more highly integrated, there is a demand for wiring boards for flip chip ball grid arrays (FC-BGA boards) on which semiconductor chips are mounted, with narrower pitches for the bonding terminals used to bond with the semiconductor chips and finer wiring within the board. On the other hand, bonding between FC-BGA boards and motherboards requires bonding with bonding terminals arranged at roughly the same pitch as before. In response to these demands, technology has been adopted to provide a multilayer wiring board containing fine wiring, also known as an interposer, between the FC-BGA board and the semiconductor chip.

One of these is silicon interposer technology. This technology manufactures interposers by forming a multi-layer wiring structure, each layer of which contains fine wiring, on a silicon wafer using semiconductor circuit manufacturing technology.

A method has also been developed in which the above multi-layer wiring structure is directly built into the FC-BGA substrate, rather than being formed on a silicon wafer. This method involves forming the above multi-layer wiring structure using chemical mechanical polishing (CMP) or the like in the manufacture of an FC-BGA substrate whose core layer is made of, for example, a glass epoxy substrate. This is disclosed in Patent Document 1.

There is also a method (hereinafter referred to as the transfer method) in which an interposer is formed on a support such as a glass substrate, the interposer is bonded to an FC-BGA substrate, and then the support is peeled off from the interposer, thereby providing the above-mentioned multilayer wiring structure on the FC-BGA substrate. This method is disclosed in Patent Document 2.

JP 2014-225671 A International Publication No. 2018/047861

The present invention aims to provide a multilayer wiring board that is less susceptible to delamination when heated.

According to one aspect of the present invention, a multilayer wiring board is provided that includes two or more layers stacked on top of each other, each of the two or more layers having a first surface and a second surface that is the back surface of the first insulating layer, a first and second recessed portion that penetrates from the first surface to the second surface, a third surface that contacts the second surface and a fourth surface that is the back surface of the second insulating layer, the first recessed portion being embedded in the second insulating layer, the third ...

According to another aspect of the present invention, there is provided a multilayer wiring board according to the above aspect, in which the conductor layer includes a via portion located in the second recess, a land portion located in the third recess that is connected to the second recess, and a wiring portion located in the third recess that is not connected to the second recess.

According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, in which each of the two or more layers further includes an adhesion layer including a portion interposed between the conductor layer and the first insulating layer, a portion interposed between the conductor layer and the second insulating layer, and a portion covering the surface of the conductor layer on the first side, and a seed layer interposed between the adhesion layer and the conductor layer.

According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, in which, in at least a portion of the first insulating layer, the opening diameter of the first recess on the second surface is within a range of 0.5 to 5 μm, and the opening diameter of the second recess on the second surface is within a range of 5 to 50 μm.

According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, in which, in at least a portion of the first insulating layer, the ratio N1/N2 of the number N1 of the first recesses to the number N2 of the second recesses is in the range of 1 to 5.

According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, in which the first and second insulating layers are made of a material containing an organic insulator.

According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, the thickness of which is in the range of 10 μm or more and 300 μm or less.

According to yet another aspect of the present invention, there is provided a multilayer wiring board according to any of the above aspects, in which the surface of the conductor layer on the fourth surface side is flush with the fourth surface.

According to yet another aspect of the present invention, there is provided a composite wiring board comprising a first wiring board and a second wiring board joined to the first wiring board, the first and second wiring boards being electrically connected to each other via a joining electrode interposed between them, and the second wiring board being a multilayer wiring board according to any of the above aspects.

According to yet another aspect of the present invention, there is provided a composite wiring board according to the above aspect, in which the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer.

According to yet another aspect of the present invention, there is provided a packaged device comprising a composite wiring board according to any of the above aspects and a functional device mounted on a surface of the first wiring board opposite the second wiring board.

Here, a "functional device" is a device that operates when supplied with at least one of power and an electrical signal, a device that outputs at least one of power and an electrical signal in response to an external stimulus, or a device that operates when supplied with at least one of power and an electrical signal and outputs at least one of power and an electrical signal in response to an external stimulus. The functional device is in the form of a chip, such as a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. The functional device may include, for example, one or more of a large scale integrated circuit (LSI), a memory, an imaging element, a light-emitting element, and a MEMS (Micro Electro Mechanical Systems). The MEMS is, for example, one or more of a pressure sensor, an acceleration sensor, a gyro sensor, a tilt sensor, a microphone, and an acoustic sensor. According to one example, the functional device is a semiconductor chip including an LSI.

According to yet another aspect of the present invention, a method for manufacturing a multilayer wiring board is provided, which includes forming two or more layers stacked on a support, and each of the two or more layers includes forming a first insulating layer having a first surface and a second surface that is the back surface of the first insulating layer and having first and second recesses that each penetrate from the first surface to the second surface, forming a second insulating layer having a third surface in contact with the second surface and a fourth surface that is the back surface of the second insulating layer and having the first recesses embedded therein, the second insulating layer having a third recess that penetrates from the third surface to the fourth surface and at least one third recess that communicates with the second recesses, forming a conductor layer that covers the fourth surface and has the second and third recesses embedded therein, and polishing the conductor layer to remove the portion of the conductor layer that is outside the second or third recess.

1 is a schematic cross-sectional view of a packaged device according to an embodiment of the present invention; 2 is a cross-sectional view illustrating a multilayer wiring substrate included in the packaged device illustrated in FIG. 1 . 3 is an enlarged cross-sectional view showing a portion of the multilayer wiring board shown in FIG. 2 . 3 is an enlarged cross-sectional view showing another part of the multilayer wiring board shown in FIG. 2 . 1 is a cross-sectional view illustrating a process of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention. 6 is a cross-sectional view illustrating another step in the method for manufacturing a multilayer wiring board according to an embodiment of the present invention. 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a process for producing a multilayer wiring board according to an embodiment of the present invention. FIG. FIG. 11 is a cross-sectional view illustrating a multilayer wiring board according to a comparative example. 17 is an enlarged cross-sectional view showing a portion of the multilayer wiring board shown in FIG. 16 . 17 is an enlarged cross-sectional view showing another part of the multilayer wiring board shown in FIG. 16 .

Below, an embodiment of the present invention will be described with reference to the drawings. The embodiment described below is a more concrete embodiment of any of the above aspects. The embodiment described below shows an example of a concrete embodiment of the technical idea of the present invention, and does not limit the technical idea of the present invention to the materials, shapes, structures, arrangements, etc. of the components described below. Various modifications can be made to the technical idea of the present invention within the technical scope defined by the claims.

In the drawings referred to in the following description, components having the same or similar functions are given the same reference numerals. It should be noted that the drawings are schematic, and the relationship between the dimension in the thickness direction and the dimension perpendicular to the thickness direction, i.e., the in-plane direction, and the relationship between the dimensions in the thickness direction of multiple layers, etc., may differ from the actual ones. Therefore, the specific dimensions should be determined with reference to the following description. It should also be noted that the dimensional relationship between two or more components may differ between multiple drawings. Furthermore, it should be noted that the same structure is drawn upside down in some drawings compared to other drawings.

In this disclosure, the terms "upper surface" and "lower surface" refer to the two main surfaces of a plate-like member or a layer contained therein, i.e., the surface perpendicular to the thickness direction and having the widest area, and the back surface thereof, respectively, the surface shown at the top and the surface shown at the bottom in the drawings. Additionally, "side surface" refers to a surface that is perpendicular or inclined to an in-plane direction.

In addition, in this disclosure, the phrase "AA on BB" is used regardless of the direction of gravity. The state specified by the phrase "AA on BB" includes a state in which AA is in contact with BB. The phrase "AA on BB" does not exclude the presence of one or more other components between AA and BB.

<Structure>
FIG. 1 is a schematic cross-sectional view of a packaged device according to one embodiment of the present invention.

The packaged device 1 shown in FIG. 1 includes a composite wiring substrate 10, a functional device 20, a sealing resin layer 30, and a bonding electrode 40.

The functional device 20 is, for example, a semiconductor chip, or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. Here, as an example, the functional device 20 is a semiconductor chip. That is, here, the packaged device 1 is a semiconductor package.

The packaged device 1 includes multiple functional devices 20. The packaged device 1 may include only one functional device 20.

The functional device 20 is bonded to the composite wiring board 10 via the bonding electrodes 40. Here, the functional device 20 is bonded to the composite wiring board 10 by flip-chip bonding. One or more of the functional devices 20 may be bonded to the composite wiring board 10 by other bonding methods such as wire bonding.

The bonding electrodes 40 are arranged at a narrow pitch between the functional device 20 and the composite wiring board 10. The bonding electrodes 40 are made of, for example, solder. When the functional device 20 is bonded to the composite wiring board 10 by wire bonding, for example, a gold wire can be used to electrically connect the functional device 20 and the composite wiring board.

The sealing resin layer 30 includes a portion interposed between the functional device 20 and the composite wiring board 10 and a portion that at least partially covers the side surface of the functional device 20. The sealing resin layer 30 fixes the functional device 20 to the composite wiring board 10.

The composite wiring board 10 includes an FC-BGA substrate 11, a multilayer wiring board 12, a sealing resin layer 13, and a bonding electrode 14.

The FC-BGA substrate 11 is an example of a first wiring substrate. The FC-BGA substrate 11 is joined to, for example, a motherboard (not shown).

The FC-BGA substrate 11 includes a core layer 111, an insulating layer 112, a conductor layer 113, an insulating layer 114, and a joining conductor 115.

The core layer 111 is an insulating layer. The core layer 111 is, for example, a fiber-reinforced substrate in which a woven or nonwoven fabric is impregnated with a thermosetting insulating resin. For example, glass fiber, carbon fiber, or aramid fiber can be used as the woven or nonwoven fabric. For example, epoxy resin can be used as the insulating resin.

Through holes are provided in the core layer 111. Part of the conductor layer 113 covers the side walls of the through holes. Here, part of the conductor layer 113 covers the side walls of the through holes provided in the core layer 111 so as to produce through holes whose side walls are made of a conductor. These through holes whose side walls are made of a conductor may be filled with an insulator.

The remaining conductor layers 113 and the insulating layers 112 form a multilayer wiring structure on both major surfaces of the core layer 111. Each multilayer wiring structure includes alternating stacks of conductor layers 113 and insulating layers 112.

Each insulating layer 112 included in the multilayer wiring structure is, for example, an insulating resin layer. The insulating layer 112 has a through hole.

The conductor layer 113 is made of a metal such as copper or an alloy. The conductor layer 113 may have a single-layer structure or a multi-layer structure.

Each conductor layer 113 included in the multilayer wiring structure includes a wiring portion and a land portion. The conductor layer 113 facing the core layer 111 with the insulating layer 112 sandwiched therebetween further includes a via portion that covers the sidewall of a through hole provided in the insulating layer 112.

The insulating layer 114 is provided on the multi-layer wiring structure. The insulating layer 114 is, for example, an insulating resin layer such as a solder resist. The insulating layer 114 has a through hole that communicates with the conductor layer 113 located on the outermost surface of the multi-layer wiring structure.

The joining conductor 115 is a metal bump provided on the portion of the conductor layer 113 that is exposed at the position of the through hole of the insulating layer 114. The joining conductor is also called a joining terminal. The joining conductor 115 is made of, for example, solder.

The multilayer wiring board 12 is a second wiring board. The multilayer wiring board 12 is bonded to the functional device 20 via bonding electrodes 40, and is bonded to the FC-BGA board 11 via bonding electrodes 14. In other words, the multilayer wiring board 12 is an interposer that mediates the bonding between the functional device 20 and the FC-BGA board 11. The thickness of the multilayer wiring board 12 is, for example, in the range of 10 μm to 300 μm. The multilayer wiring board 12 will be described in detail later.

The bonding electrodes 14 are arranged between the multilayer wiring substrate 12 and the functional device 20. The pitch of the bonding electrodes 14 is wider than the pitch of the bonding electrodes 40 and narrower than the pitch of the bonding conductors 115 located on the underside of the FC-BGA substrate 11. The bonding electrodes 14 are made of, for example, solder.

The sealing resin layer 13 includes a portion interposed between the FC-BGA substrate 11 and the multilayer wiring substrate 12. The sealing resin layer is also called an underfill layer. The sealing resin layer 13 fixes the second wiring substrate 11 to the FC-BGA substrate 11.

The multilayer wiring board 12 will be described in more detail with reference to FIGS.
Fig. 2 is a cross-sectional view showing a schematic diagram of a multilayer wiring board included in the packaged device shown in Fig. 1. Fig. 3 is a cross-sectional view showing an enlarged view of a part of the multilayer wiring board shown in Fig. 2. Fig. 4 is a cross-sectional view showing an enlarged view of another part of the multilayer wiring board shown in Fig. 2.

The multilayer wiring board 12 shown in Figures 2 to 4 includes two or more layers 120, an insulating layer 121, an adhesion layer 122a, a seed layer 122b, a conductor layer 123, an insulating layer 124, an adhesion layer 125a, a seed layer 125b, a conductor layer 126, a surface treatment layer 127, and an insulating layer 128, as shown in Figure 2.

Two or more layers 120 are stacked on top of each other. Each of these layers 120 includes a first insulating layer 1201, a second insulating layer 1202, a conductor layer 1203, an adhesion layer 1204a, and a seed layer 1204b.

As shown in Figures 3 and 4, the first insulating layer 1201 has a first surface S1 and a second surface S2, which is the back surface of the first surface S1. The first insulating layer 1201 has first and second recesses that each extend from the first surface S1 to the second surface S2.

The bottom surface of the first recess in the first insulating layer 1201 adjacent to the insulating layer 121 is part of the surface of the insulating layer 121, as shown in FIG. 2. The bottom surface of the first recess in the first insulating layer 1201 not adjacent to the insulating layer 121 is part of the surface of the second insulating layer 1202 included in the layer 120 adjacent to the layer 120 including the first insulating layer 1201, as shown in FIG. 2 and FIG. 3.

The bottom surface of the second recess in the first insulating layer 1201 adjacent to the conductor layer 123 is part of the surface of the conductor layer 123, as shown in FIG. 2. The bottom surface of the second recess in the first insulating layer 1201 not adjacent to the conductor layer 123 is part of the surface of the conductor layer 1203 included in the layer 120 adjacent to the layer 120 including the first insulating layer 1201, as shown in FIG. 2 and FIG. 4.

As shown in Figs. 3 and 4, the second insulating layer 1202 has a third surface S3 in contact with the second surface S2, and a fourth surface S4 which is the reverse surface of the third surface S3. The second insulating layer 1202 fills the first recess of the first insulating layer 1201. The second insulating layer 1202 has a third recess which penetrates from the third surface S3 to the fourth surface S4 and at least one of which is connected to the second recess of the first insulating layer 1201. The bottom surface of the third recess of the second insulating layer 1202 included in each layer 120 is part of the surface of the first insulating layer 1201 included in that layer 120, as shown in Figs. 2 to 4.

The first insulating layer 1201 and the second insulating layer 1202 are made of a material containing an organic insulator, for example. The material of the first insulating layer 1201 and the second insulating layer 1202 may be an inorganic material, but preferably contains an organic material. According to one example, the first insulating layer 1201 and the second insulating layer 1202 are insulating resin layers. These insulating resin layers preferably do not contain a filler. The material of the first insulating layer 1201 and the material of the second insulating layer 1202 may be the same or different. Even if the material of the first insulating layer 1201 and the material of the second insulating layer 1202 are the same, the interface between the first insulating layer 1201 and the second insulating layer 1202 can be confirmed by observing a cross section parallel to the thickness direction, for example, with a scanning electron microscope. The first to third recesses will be described in more detail later.

The conductor layer 1203 fills the second and third recesses. The surface of the conductor layer 1203 on the fourth surface S4 side is flush with the fourth surface S4.

The portion of the conductor layer 1203 in which the second recess is embedded is the via portion 1203V shown in Figures 2 and 4. The portion of the conductor layer 1203 in which one or more of the third recesses are embedded, specifically, the portion in which the third recess that is connected to the second recess is embedded, is the land portion 1203L shown in Figures 2 and 4. And the portion of the conductor layer 1203 in which the rest of the third recesses are embedded, specifically, the portion in which the third recess that is not connected to the second recess is embedded, is the wiring portion 1203W shown in Figures 2 and 3.

The conductor layer 1203 is made of a metal such as copper or an alloy. The conductor layer 1203 may have a single-layer structure or a multi-layer structure.

As shown in Figures 2 to 4, the adhesion layer 1204a includes a portion interposed between the conductor layer 1203 and the first insulating layer 1201, a portion interposed between the conductor layer 1203 and the second insulating layer 1202, and a portion covering the surface on the first surface side of the conductor layer 1203. That is, the adhesion layer 1204a is provided on the bottom surface and sidewalls of the first to third recesses. The adhesion layer 1204a is a layer that improves the adhesion of the seed layer 1204b to the first insulating layer 1201 and the second insulating layer 1202, making it difficult for the seed layer 1204b to peel off.

The seed layer 1204b is provided on the adhesion layer 1204a. The seed layer 1204b is interposed between the adhesion layer 1204a and the conductor layer 1203. The seed layer 1204b serves as a power supply layer in the formation of the conductor layer 1203 by electrolytic plating.

As shown in FIG. 2, the insulating layer 121 is provided on one main surface of the multilayer wiring structure made up of the layer 120. The insulating layer 121 is, for example, an insulating resin layer. A through hole is provided in the insulating layer 121 at the position of the second recess of the first insulating layer 1201 included in the layer 120 adjacent thereto.

The conductor layer 123 fills the through hole provided in the insulating layer 121. The conductor layer 123 is made of a metal such as copper or an alloy. The conductor layer 123 is electrically connected to the via portion 1203V located on the outermost surface of the multilayer wiring structure.

The adhesion layer 122a includes a portion that covers the sidewalls of the through holes provided in the insulating layer 121 and a portion that spreads to close the openings of the through holes that are spaced apart from the multilayer wiring structure. The adhesion layer 122a is a layer that improves the adhesion of the seed layer 122b to the insulating layer 121, making it difficult for the seed layer 122b to peel off.

The seed layer 122b is provided on the adhesion layer 122a. The seed layer 122b serves as a power supply layer in the formation of the conductor layer 123 by electrolytic plating.

The insulating layer 124 is provided on the other main surface of the multilayer wiring structure made up of the layer 120. The insulating layer 124 is, for example, an insulating resin layer. A through hole is provided in the insulating layer 124 at the position of a third recess that communicates with the second recess of the second insulating layer 1202 included in the layer 120 adjacent thereto.

The conductor layer 126 fills the through-hole provided in the insulating layer 121 and covers the area of the main surface of the insulating layer 121 surrounding the through-hole. The conductor layer 126 is made of a metal such as copper or an alloy. The conductor layer 126 is electrically connected to the land portion 1203L located on the outermost surface of the multilayer wiring structure.

The adhesion layer 125a includes a portion that covers the sidewalls of the through holes provided in the insulating layer 124, a portion that covers the areas of the land portion 1203L that are exposed at the positions of the through holes, and a portion that covers the areas of the main surface of the insulating layer 121 surrounding the through holes. The adhesion layer 125a is a layer that improves the adhesion of the seed layer 125b to the insulating layer 124, making it difficult for the seed layer 125b to peel off.

The seed layer 125b is provided on the adhesion layer 125a. The seed layer 125b serves as a power supply layer in the formation of the conductor layer 126 by electrolytic plating.

The insulating layer 128 is provided on the insulating layer 124. The insulating layer 128 is, for example, an insulating resin layer. A through hole is provided in the insulating layer 128 at the position of the conductor layer 126.

The surface treatment layer 127 is provided on the conductor layer 126. The surface treatment layer 127 is provided to prevent oxidation of the surface of the conductor layer 126 and to improve wettability to solder.

<Production Method>
The multilayer wiring substrate 12 included in this packaged device 1 can be manufactured, for example, by the following method.

Figures 5 to 15 are cross-sectional views that show a schematic diagram of a method for manufacturing a multilayer wiring board according to one embodiment of the present invention.

In this method, the structure shown in Figure 5 is first obtained. Below, the steps for obtaining the structure shown in Figure 5 are explained in order.

(1) Formation of Release Layer 3 on Support 2 First, the release layer 3 is formed on one surface of the support 2 .
Since light may be irradiated to the peeling layer 3 through the support 2, it is advantageous for the support 2 to have light transmissivity. For example, a rectangular glass plate can be used as the support 2. The rectangular glass plate is suitable for large size. In addition, the glass plate can achieve excellent flatness and high rigidity. Therefore, the rectangular glass plate as the support 2 is suitable for forming a fine pattern thereon.

In addition, glass plates have a small CTE (coefficient of thermal expansion) and are less likely to distort, making them excellent for ensuring pattern placement accuracy and flatness. When using a glass plate as the support 2, it is desirable for the glass plate to have a large thickness in order to suppress the occurrence of warping during the manufacturing process, and the thickness is, for example, 0.7 mm or more, preferably 1.1 mm or more.

The CTE of the glass plate is preferably 3 ppm or more and 15 ppm or less, and is more preferably around 9 ppm from the viewpoint of compatibility with the CTE of the FC-BGA substrate 11 and the functional device 20.

On the other hand, if the support 2 does not require optical transparency when peeling it off, such as when the peeling layer 3 is made of a resin that foams when heated, the support 2 can be made of a material with less distortion, such as metal or ceramics.

In the following, as an example, the material of the peelable layer 3 is a resin that absorbs ultraviolet light (UV light) and becomes peelable, and the support 2 is a glass plate.

The peeling layer 3 may be, for example, a resin that absorbs light such as UV light, generates heat or changes in quality to become peelable, or may be a resin that foams when heated, making it peelable.

The peeling layer 3 may further contain additives such as a photodecomposition promoter, a light absorber, a sensitizer, and a filler.

The peeling layer 3 may have a single-layer structure or a multilayer structure. For example, a protective layer may be provided on the peeling layer 3 for the purpose of protecting the multilayer wiring structure formed on the support 2, and a layer for improving the adhesion between the support 2 and the peeling layer 3 may be further provided. A laser light reflecting layer or a metal layer may be further provided between the peeling layer 3 and the multilayer wiring structure.

When the material of the peeling layer 3 is a resin that can be peeled off by light such as UV light, for example laser light, if the support 2 is translucent, the peeling layer 3 may be irradiated with light through the support 2.

(2) Formation of insulating layer 121 on release layer 3 After forming the release layer 3 on the upper surface of the support 2, the insulating layer 121 is formed on the upper surface of the release layer 3. Here, as an example, a photosensitive epoxy resin is applied onto the release layer 3 by a spin coating method. Photosensitive epoxy resin can be cured at a relatively low temperature and shrinks little when cured, which is advantageous for the subsequent formation of fine patterns.

(3) Patterning of the insulating layer 121 Next, through holes are provided in the insulating layer 121 by photolithography. These through holes may be subjected to plasma treatment in order to remove residues from development. The thickness of the insulating layer 121 is set according to the thickness of the conductor layer to be formed in the through holes. Here, as an example, the thickness of the insulating layer 121 is set to 7 μm.

The shape of the through holes in plan view, i.e., the shape of the orthogonal projection of the through holes onto a plane perpendicular to the thickness direction, is appropriately set according to the pitch and shape of the bonding electrodes 40 that bond the functional device 20 to the composite wiring board 10. Here, as an example, the shape of the through holes in plan view is a circle with a diameter of 25 μm, and the pitch of the through holes is 55 μm.

(4) Formation of Adhesion Layer 122a and Seed Layer 122b Next, the adhesion layer 122a and the seed layer 122b are formed in a vacuum. As described above, the adhesion layer 122a is a layer that improves the adhesion of the seed layer 122b to the insulating layer 121 and prevents peeling of the seed layer 122b. In addition, as described above, the seed layer 122b serves as a power supply layer in electrolytic plating for forming the conductor layer 123.

The adhesion layer 122a and the seed layer 122b can be formed by, for example, a sputtering method or a vapor deposition method. The materials for the adhesion layer 122a and the seed layer 122b can be, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped zinc oxide), ZnO, PZT (lead zirconate titanate), TiN, Cu ₃ N ₄ , Cu alloy, or a combination of a plurality of these. Here, as an example, a titanium layer and a copper layer are adopted for the adhesion layer 122a and the seed layer 122b, respectively, in consideration of electrical characteristics, ease of manufacture, and cost, and they are formed by a sputtering method.

The total thickness of the adhesion layer 122a and the seed layer 122b is preferably 1 μm or less. In this example, a titanium layer with a thickness of 50 nm is formed as the adhesion layer 122a, and a copper layer with a thickness of 300 nm is formed as the seed layer 122b.

Next, a conductor layer 123' is formed on the seed layer 122b by electrolytic plating. The portion of the conductor layer 123' located within the through-hole of the insulating layer 121 becomes an electrode for bonding to the functional device 20. Examples of electrolytic plating include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating. Electrolytic copper plating is preferable because it is simple and inexpensive, and can produce a conductor layer 123 with good electrical conductivity.

The thickness of the conductor layer 123' is preferably 1 μm or more from the viewpoint of completely filling the through-holes of the insulating layer 121, and is preferably 30 μm or less from the viewpoint of productivity. Here, as an example, a copper layer having a thickness of 9 μm at the position of the through-holes of the insulating layer 121 and a thickness of 2 μm on the upper surface of the insulating layer 121 is formed as the conductor layer 123'.

Next, the following steps are performed to obtain the structure shown in Figure 6.

(6) Polishing of Conductive Layer 123' The structure shown in Fig. 5 is polished by chemical mechanical polishing (CMP) or the like to remove the conductor layer 123' and the seed layer 122b that are located outside the through-holes provided in the insulating layer 121. That is, polishing is performed so that the surface of the adhesion layer 122a becomes the outermost surface at the position of the upper surface of the insulating layer 121, and the surface of the conductor layer 123' becomes the outermost surface at the position of the through-holes provided in the insulating layer 121. Here, as an example, a portion of the conductor layer 123' that is 2 µm or less away from the surface and a portion (300 nm thick) of the seed layer 122b that is located on the upper surface of the insulating layer 121 are removed by polishing.

(7) Polishing of Adhesion Layer 122a and Insulation Layer 121 Next, polishing such as CMP is performed again to remove the portion of adhesion layer 122a located on the upper surface of insulation layer 121 and a part of insulation layer 121. Note that since adhesion layer 122a and insulation layer 121 are made of different materials, chemical polishing for removing the part of adhesion layer 122a has little effect on the removal of the part of insulation layer 121. Physical polishing with an abrasive mainly contributes to the removal of the part of insulation layer 121.

In order to simplify the process, the adhesion layer 122a and the insulating layer 121 may be polished using a method similar to that used for polishing the conductor layer 123' and the seed layer 122b described above. Alternatively, in order to improve the efficiency of polishing, the adhesion layer 122a and the insulating layer 121 may be polished using a polishing method that is suitable for the materials of the adhesion layer 122a and the insulating layer 121 and that is different from that used for polishing the conductor layer 123' and the seed layer 122b.

The portion of the conductor layer 123' shown in FIG. 5 that remains after the above-mentioned polishing is the conductor layer 123 shown in FIG. 6. As described above, the conductor layer 123 is used as an electrode for bonding to the functional device 20.

(8) Formation of the first insulating layer 1201 Next, the first insulating layer 1201 shown in FIG. 6 is formed on the polished surface. The first insulating layer 1201 has a first surface S1 in contact with the insulating layer 121 and the like, and a second surface S2 which is the back surface of the first insulating layer 1201. The first insulating layer 1201 is provided with a first recess R1 and a second recess R2 each penetrating from the first surface S1 to the second surface S2. The first recess R1 is located on the upper surface of the insulating layer 121. The second recess R2 is located on the conductor layer 123. Here, each of the first recess R1 and the second recess R2 is a through hole. These recesses are distributed approximately uniformly throughout the first insulating layer 1201.

The first insulating layer 1201 can be formed using, for example, a photosensitive resin. For example, the photosensitive resin is applied to the polished surface by spin coating, and the first insulating layer 1201 having the first recess R1 and the second recess R2 is obtained by photolithography. As described below, a via portion 1203V is formed in the second recess R2.

The depth of each of the first recess R1 and the second recess R2, i.e., the thickness of the first insulating layer 1201, is set according to the thickness of the via portion 1203V to be formed in the second recess R2. The thickness of the first insulating layer 1201 is preferably in the range of 1 to 5 μm, and more preferably in the range of 1 to 3 μm. Here, as an example, the first insulating layer 1201 is formed to a thickness of 2 μm.

The opening diameter of the first recess R1 on the second surface S2 is preferably in the range of 0.5 to 5 μm, more preferably in the range of 1 to 2 μm, in at least a part of the first insulating layer 1201, for example, in the part where the wiring portion 1203W is most densely arranged. The opening diameter of the second recess R2 on the second surface S2 is preferably in the range of 5 to 50 μm, more preferably in the range of 10 to 20 μm, in at least a part of the first insulating layer 1201, for example, in the part where the wiring portion 1203W is most densely arranged. If the opening diameter of the first recess R1 on the second surface S2 is reduced, the reliability of the interlayer connection of the conductor layer 1203 decreases. If the opening diameter of the first recess R1 or the second recess R2 on the second surface S2 is increased, it becomes difficult to arrange the land portion 1203L and the wiring portion 1203W at a high density.

Here, the opening diameter of the first recess R1 on the second surface S2 is the average circle equivalent diameter of the opening of the first recess R1 on the second surface S2. Also, the opening diameter of the second recess R2 on the second surface S2 is the average circle equivalent diameter of the opening of the second recess R2 on the second surface S2. The average circle equivalent diameter of the recess openings is a value obtained by arithmetically averaging the diameters of circles having the same area as the areas of those openings.

The shape of the second recess R2 in a plan view, i.e., the shape of the orthogonal projection of the opening of the second recess R2 on the second surface S2 onto a plane perpendicular to the thickness direction, is set from the perspective of connection with the conductor layer 123. Here, as an example, the orthogonal projection shape is a circle with a diameter of 10 μm.

The ratio N1/N2 of the number N1 of first recesses R1 to the number N2 of second recesses R2 is preferably in the range of 1 to 5 in at least a part of the first insulating layer 1201, for example in the part where the wiring portions 1203W are most densely arranged. Increasing the ratio N1/N2 increases the contact area between the first insulating layer 1201 and the second insulating layer 1202. However, if the ratio N1/N2 is excessively large, it may become difficult to form the wiring portions 1203W with a sufficient line width.

(9) Formation of the second insulating layer 1202 Next, as shown in FIG. 7, the second insulating layer 1202 is formed on the first insulating layer 1201. The second insulating layer 1202 has a third surface S3 in contact with the second surface S2 and a fourth surface S4 which is the back surface of the third surface S2. The second insulating layer 1202 fills the first recess R1 of the first insulating layer 1201. The second insulating layer 1202 is provided with a third recess R3 which penetrates from the third surface S3 to the fourth surface S4 and at least one of which is connected to the second recess R2 of the first insulating layer 1201. The bottom surface of the third recess R3 is a part of the surface of the first insulating layer 1201.

Here, a part of the third recess R3 communicates with the second recess R2, and the rest of the third recess R3 does not communicate with the second recess R2. Specifically, the third recess R3 that is provided above the conductor layer 123 communicates with the second recess R2. The third recess R3 that is provided above the insulating layer 121 does not communicate with the second recess R2. The third recess R3 that communicates with the second recess R2 is a through hole, and the third recess R3 that does not communicate with the second recess R2 is a groove. As described later, a land portion 1203L is formed in the third recess R3 that communicates with the second recess R2, and a wiring portion 1203W is formed in the third recess that does not communicate with the second recess R2.

The second insulating layer 1202 can be formed, for example, using a photosensitive resin. For example, a photosensitive resin is applied by spin coating to the surface on which the first insulating layer 1201 having the structure shown in FIG. 6 is provided, and the second insulating layer 1202 having the third recess R3 is obtained by photolithography.

The thickness of the second insulating layer 1202 is set according to the thickness of the land portion 1203L and the wiring portion 1203W formed in the third recess R3. Here, as an example, the second insulating layer 1202 is formed to a thickness of 2 μm.

The shape in plan view of the third recess R3 in which the land portion 1203L is formed, i.e., the shape of the orthogonal projection of the opening of the third recess R3 on the fourth surface onto a plane perpendicular to the thickness direction, is set from the perspective of the interlayer connection of the conductor layer 1203. Here, as an example, the shape of the orthogonal projection is a circle with a diameter of 25 μm that is concentric with the orthogonal projection of the second recess R2 onto the previous plane.

(10) Formation of Adhesion Layer 1204a and Seed Layer 1204b Next, on the surface on which the first insulating layer 1201 and the second insulating layer 1202 of the structure shown in FIG. 7 are formed, the adhesion layer 1204a and the seed layer 1204b shown in FIG. 8 and FIG. 9 are sequentially formed. The adhesion layer 1204a and the seed layer 1204b can be made of the same materials as those described above for the adhesion layer 122a and the seed layer 122b. The adhesion layer 1204a and the seed layer 1204b can be formed by the same method as those described above for the adhesion layer 122a and the seed layer 122b. Here, as an example, a titanium layer having a thickness of 50 nm is formed as the adhesion layer 1204a, and a copper layer having a thickness of 300 nm is formed as the seed layer 1204b.

(11) Formation of Conductive Layer 1203' Next, as shown in Fig. 10, a conductor layer 1203' is formed on the seed layer 1204b. As described below, of the conductor layer 1203', a portion located in the second recess R2 becomes a via portion 1203V, and a portion located in the third recess R3 becomes a land portion 1203L or a wiring portion 1203W. The conductor layer 1203' can be formed by the same method as described above for the conductor layer 123'.

The thickness of the conductor layer 1203' is preferably 0.5 μm or more from the viewpoint of the electrical resistance of the wiring portion 1203W, and is preferably 30 μm or less from the viewpoint of productivity. Here, as an example, the conductor layer 1203' is formed as a copper layer having a thickness of 6 μm at the position of the second recess R2, a thickness of 4 μm at the position of the third recess R3 that is not connected to the second recess R2, and a thickness of 2 μm on the fourth surface S4.

(12) Polishing of Conductive Layer 1203' Next, as shown in Fig. 11, the portion of the conductor layer 1203' that is located outside the second recess R2 or the third recess R3 is removed by polishing. This polishing can be performed by the same method as that for polishing the conductor layer 123'. Here, as an example, the portion of the conductor layer 1203' that is 2 µm or less away from the surface and the portion (thickness 300 nm) of the seed layer 1204b that is located on the upper surface of the fourth surface S4 are removed by polishing.

(13) Polishing of Adhesion Layer 1204a and Second Insulation Layer 1202 Next, polishing such as CMP is performed again to remove the portion of the adhesion layer 1204a located on the fourth surface S4 and a part of the second insulation layer 1202. This polishing can be performed by the same method as that used for polishing the adhesion layer 122a and the insulation layer 121.

The portion of the conductor layer 1203' shown in FIG. 10 that remains after the above-mentioned polishing is the conductor layer 1203 shown in FIG. 11. The conductor layer 1203 includes a via portion 1203V, a land portion 1203L, and a wiring portion 1203W.

In this manner, a layer 120 is obtained that includes a first insulating layer 1201, a second insulating layer 1202, a conductor layer 1203, an adhesion layer 1204a, and a seed layer 1204b.

(14) Formation of a multilayer wiring structure by repeating steps Thereafter, the sequence consisting of steps (8) to (13) described with reference to Figures 6 to 11 is repeated. This results in the multilayer wiring structure shown in Figure 12. In Figure 12, the multilayer wiring structure includes two layers 120. The number of layers 120 included in the multilayer wiring structure may be three or more.

(15) Formation of Insulating Layer 124 Next, an insulating layer 124 as shown in Fig. 13 is formed on the multilayer wiring structure. A through hole is provided in the insulating layer 124 at the position of a land portion 1203L included in the layer 120 located on the outermost surface of the multilayer wiring structure.

The insulating layer 124 can be formed, for example, using a photosensitive resin. For example, the photosensitive resin is applied onto the multilayer wiring structure by a spin coating method, and the insulating layer 124 having through holes is obtained by photolithography.

(16) Formation of Adhesion Layer 125a and Seed Layer 125b Next, the adhesion layer 125a and the seed layer 125b are sequentially formed on the multilayer wiring structure and the insulating layer 124 thereon. The adhesion layer 125a and the seed layer 125b can be made of the same materials as those described above for the adhesion layer 122a and the seed layer 122b, respectively. The adhesion layer 125a and the seed layer 125b can be formed by the same methods as those described above for the adhesion layer 122a and the seed layer 122b, respectively.

(17) Formation of Conductive Layer 126 Next, a resist pattern 228 is formed on the seed layer 125b. The resist pattern 228 has through holes at the positions of the through holes provided in the insulating layer 124. The conductive layer 126 can be formed by the same method as described above for the conductive layer 123′.

From the viewpoint of solder bonding, it is desirable for the thickness of the conductor layer 126 to be 1 μm or more, and from the viewpoint of productivity, it is desirable for the thickness to be 30 μm or less. Here, as an example, the conductor layer 126 is formed as a copper layer having a thickness of 9 μm at the position of the through hole of the insulating layer 124 and a thickness of 7 μm at other positions.

(18) Removal of the resist pattern 228 After obtaining the structure shown in FIG. 13, the resist pattern 228 is removed. Then, the exposed portions of the adhesion layer 122a and the seed layer 122b are removed by etching using the conductor layer 126 as an etching mask. The conductor layer 126 remaining in this state becomes an electrode used for bonding to the FC-BGA substrate 11.

(19) Formation of Insulating Layer 128 Next, as shown in Fig. 14, insulating layer 128 is formed on insulating layer 124 and conductor layer 126. Insulating layer 128 has a through hole at the position of conductor layer 126. The insulating layer can be formed, for example, by providing a solder resist on insulating layer 124 and conductor layer 126, and subjecting the solder resist to exposure and development. Note that an insulating layer obtained from a solder resist is also called a solder resist layer.

As a material for the solder resist, for example, insulating resins such as epoxy resins and acrylic resins can be used. Here, as an example, a photosensitive epoxy resin containing filler is used as the solder resist.

(20) Formation of Surface Treatment Layer 127 Next, the surface treatment layer 127 is provided on the conductor layer 126. The surface treatment layer 127 is provided for the purpose of preventing oxidation of the surface of the conductor layer 126 and improving wettability to solder. Here, as an example, an electroless Ni/Pd/Au plating layer is formed as the surface treatment layer 127.

The surface treatment layer 127 may be an OSP (Organic Solderability Preservative) film, i.e., a surface treatment layer made of a water-soluble preflux. Alternatively, the surface treatment layer 127 may be an electroless tin plating or electroless Ni/Au plating layer.

(21) Formation of the bonding conductor 129 Next, the bonding conductor 129 is formed on the surface treatment layer 127. The bonding conductor 129 is, for example, a metal bump such as a solder bump. The bonding conductor 129 can be formed, for example, by placing a solder material such as a solder ball on the surface treatment layer 127, melting it, and then cooling it to adhere to the surface treatment layer 127.

In this manner, a multilayer wiring board 12 supported by the support 2, i.e., a multilayer wiring board with a support, is obtained.

By using the multilayer wiring board with support obtained in this manner, the packaged device 1 shown in Figure 1 can be manufactured, for example, by the following method.

First, the multilayer wiring board 12 supported by the support 2 is joined to the FC-BGA board 11. Next, the joint is sealed with the sealing resin layer 13 shown in FIG. 1.

As a material for the sealing resin layer 13, for example, a mixture of resin and filler can be used. As the resin, for example, one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins can be used. As the filler, for example, one of silica, titanium oxide, aluminum oxide, magnesium oxide, and zinc oxide, or two or more of these can be used. The sealing resin layer 13 can be formed, for example, by filling a liquid material between the FC-BGA substrate 11 and the multilayer wiring substrate 12.

In this manner, a composite wiring board 10 is obtained that includes the FC-BGA board 11 and the multilayer wiring board 12. At this point, the support 2 remains on the multilayer wiring board 12.

Then, the release layer 3 shown in FIG. 15 is irradiated with laser light to peel the support 2 and the composite wiring board 10 from each other. If the release layer 3 remains on the composite wiring board 10, it is removed by, for example, etching. In addition, the portion of the adhesion layer 122a that was in contact with the release layer 3 is also removed by, for example, etching. The portion of the seed layer 122b that faced the release layer 3 with the adhesion layer 122a sandwiched therebetween may also be removed by, for example, etching.

Thereafter, the functional device 20 shown in FIG.
Prior to bonding of the functional device 20, a surface treatment layer such as an electroless Ni/Pd/Au plating layer, an OSP film, an electroless tin plating layer, or an electroless Ni/Au plating layer may be provided on the conductor layer 123 exposed on the surface for the purpose of preventing oxidation and improving wettability to solder.

Next, the joints are sealed with a sealing resin layer 30 .
As the material of the sealing resin layer 30, for example, the materials exemplified as the materials of the sealing resin layer 13 can be used. The sealing resin layer 30 can be formed, for example, by the same method as that described above for the sealing resin layer 13.
In this manner, the packaged device 1 shown in FIG. 1 is completed.

In the above method, the multilayer wiring board 12 is bonded to the FC-BGA board 11, and then the functional device 20 is bonded to the multilayer wiring board 12. Alternatively, the functional device 20 may be bonded to the multilayer wiring board 12, and then the multilayer wiring board 12 may be bonded to the FC-BGA board 11.

＜Effects＞
Interposers obtained by silicon interposer technology, so-called silicon interposers, are manufactured using silicon wafers and equipment for semiconductor front-end processing. Silicon wafers are limited in shape and size, and the number of interposers that can be manufactured from one wafer is not necessarily large. In addition, the manufacturing equipment is expensive. Therefore, silicon interposers are expensive. In addition, since silicon wafers are semiconductors, there is also the problem that the transmission characteristics deteriorate when silicon interposers are used.

No silicon wafer is required to manufacture the multilayer wiring board 12. In addition, in the multilayer wiring board 12, for example, most or all of the insulating layers can be insulating resin layers. Therefore, the multilayer wiring board 12 can be manufactured using inexpensive materials and equipment, making it possible to reduce costs and also achieving excellent transmission characteristics.

The method of directly fabricating a multi-layer wiring structure including a conductor layer with a fine wiring pattern on an FC-BGA substrate results in little degradation of the transmission characteristics seen in silicon interposers. However, this method has issues with the manufacturing yield of the FC-BGA substrate itself, and the difficulty of forming a multi-layer wiring structure including a conductor layer with a fine wiring pattern on a core layer such as a glass epoxy substrate, resulting in a low overall manufacturing yield. Furthermore, it is difficult to achieve a high degree of symmetry with this FC-BGA substrate with respect to a plane that bisects its thickness. Therefore, such FC-BGA substrates are prone to warping and distortion when heated.

In manufacturing the above-mentioned composite wiring board 10 and packaged device 1, a multilayer wiring board 12 is manufactured separately from the FC-BGA board 11, and they are then bonded together. The multilayer wiring structure including the conductor layer 1203 having a fine wiring pattern is not built into the FC-BGA board 11, but is built into the multilayer wiring board 12. Therefore, the above-mentioned composite wiring board 10 and packaged device 1 can be manufactured with a high yield.

In addition, in the manufacture of the composite wiring board 10, the multilayer wiring structure including the conductor layer 1203 having a fine wiring pattern is formed on the support 2, rather than on a core layer such as a glass epoxy board. Since a support 2 having excellent smoothness can be used, the fine patterns formed thereon can be formed with high shape precision. For these reasons, the above-mentioned composite wiring board 10 and packaged device 1 can be manufactured with a high yield.

Furthermore, in the above-mentioned composite wiring board 10 and packaged device 1, it is easy to achieve a high degree of symmetry with respect to a plane that bisects the thickness of the FC-BGA substrate 11, and it is also easy to achieve a high degree of symmetry with respect to a plane that bisects the thickness of the multilayer wiring substrate 12. Therefore, the above-mentioned composite wiring board 10 and packaged device 1 are less likely to warp or distort when heated.

In addition, the multilayer wiring board 12 is less likely to delaminate when heated. This is explained below.

Figure 16 is a cross-sectional view that shows a schematic diagram of a multilayer wiring board according to a comparative example. Figure 17 is a cross-sectional view that shows an enlarged view of a portion of the multilayer wiring board shown in Figure 16. Figure 18 is a cross-sectional view that shows an enlarged view of another portion of the multilayer wiring board shown in Figure 16.

The multilayer wiring board 12' shown in Figures 16 to 18 is similar to the multilayer wiring board 12 described with reference to Figures 2 to 4, except for the following points.

That is, the multilayer wiring board 12' includes a layer 120' instead of the layer 120. Each layer 120' includes an insulating layer 1201', an insulating layer 1202', an adhesion layer 1204a, and a seed layer 1204b. The insulating layer 1201' is similar to the first insulating layer 1201 except that the first recess R1 is not provided. Since the insulating layer 1201' does not have the first recess R1, the insulating layer 1202' does not fill the first recess R1. Except for this, the insulating layer 1202' is similar to the second insulating layer 1202.

When the insulating layers 1201' and 1202' are insulating resin layers, the material used is an insulating resin that does not contain a filler. On the other hand, the underfill layer as the sealing resin layer 13 and the solder resist layers as the insulating layers 114 and 128 contain a filler in addition to the insulating resin. An insulating resin layer that does not contain a filler tends to have a lower elastic modulus and a higher CTE than an insulating resin layer that contains a filler.

Therefore, even if a high degree of symmetry can be achieved with respect to a plane that bisects the thickness of each of the multilayer wiring board 12' and the FC-BGA board 11, when a composite wiring board or packaged device including them is heated, the insulating resin layer that does not contain filler may expand significantly compared to other layers such as the insulating resin layer that contains filler, causing warping. Even if warping does not occur, large stress may occur within the multilayer wiring structure. Therefore, the composite wiring board or packaged device including the multilayer wiring board 12' shown in Figures 16 to 18 has a problem that delamination is likely to occur at the interface between the insulating layers 1201' and 1202' in each layer 120', making it difficult to ensure connection reliability.

In contrast, in the multilayer wiring board 12 shown in Figures 2 to 4, the first insulating layer 1201 is provided with a first recess R1 and a second recess R2 in each layer 120, and the second recess R2 is used to form the via portion 1203V, while the first recess R1 is filled with the second insulating layer 1202. Therefore, the contact area between the first insulating layer 1201 and the second insulating layer 1202 in each layer 120 is larger than the contact area between the insulating layer 1201' and the insulating layer 1202' in each layer 120' of the multilayer wiring board 12' shown in Figures 16 to 18. Therefore, the multilayer wiring board 12 is less likely to cause interlayer peeling compared to the multilayer wiring board 12', and can achieve high connection reliability.

<Verification of effectiveness>
The effects of the multilayer wiring board 12 described above were verified by the method described below.

(Example)
The multilayer wiring board 12 described with reference to Figures 2 to 4 was manufactured by the method described with reference to Figures 5 to 15. Here, the opening diameters of the first recess R1 and the second recess R2 on the second surface S2 were set to 10 μm, and the opening diameter of the third recess R3, in which the land portion 1203L was provided, on the fourth surface S4 was set to 20 μm.

Comparative Example
A multilayer wiring board 12' was manufactured in the same manner as in the above embodiment, except that the structure described with reference to FIGS. 16 to 18 was employed.

(test)
A via connection reliability test was performed on the multilayer wiring board 12 according to the example and the multilayer wiring board 12' according to the comparative example in accordance with JESD22-A106B (Condition D). Specifically, the board was first cooled at -65°C for 5 minutes, then heated and kept at room temperature for 1 minute, and then heated and kept at 150°C for 5 minutes. This cycle was repeated, and the number of cycles was counted until cracks or delamination occurred or the rate of change in resistance value exceeded the range of ±3%.

As a result, for the multilayer wiring board 12 according to the embodiment, the number of cycles was within the range of 800 to 1000. In contrast, for the multilayer wiring board 12' according to the comparative example, the number of cycles was within the range of 300 to 500. While the multilayer wiring board 12' according to the comparative example was prone to interlayer delamination, the multilayer wiring board 12 according to the embodiment was less prone to interlayer delamination.

1 ... packaged device, 2 ... support, 3 ... peeling layer, 10 ... composite wiring board, 11 ... FC-BGA board, 12 ... multilayer wiring board, 12' ... multilayer wiring board, 13 ... sealing resin layer, 14 ... bonding electrode, 20 ... functional device, 30 ... sealing resin layer, 40 ... bonding electrode, 111 ... core layer, 112 ... insulating layer, 113 ... conductor layer, 114 ... insulating layer, 115 ... bonding conductor, 120 ... layer, 120' ... layer, 121 ... insulating layer, 122a ... adhesion layer, 122b ... seed layer, 123 ... conductor layer, 123' ... conductor layer, 124 ... insulating layer, 125a ... adhesion layer, 125b...seed layer, 126...conductor layer, 127...surface treatment layer, 128...insulating layer, 129...joint conductor, 228...resist pattern, 1201...first insulating layer, 1201'...insulating layer, 1202...second insulating layer, 1202'...insulating layer, 1203...conductor layer, 1203'...conductor layer, 1203L...land portion, 1203V...via portion, 1203W...wiring portion, 1204a...adhesion layer, 1204b...seed layer, R1...first recess, R2...second recess, R3...third recess, S1...first surface, S2...second surface, S3...third surface, S4...fourth surface.

Claims (12)

The laminated laminate includes two or more layers laminated together, each of the two or more layers comprising:
a first insulating layer having a first surface and a second surface which is a back surface of the first surface, and having first and second recesses each penetrating from the first surface to the second surface;
a second insulating layer having a third surface in contact with the second surface and a fourth surface which is the back surface of the third surface, the second insulating layer having the first recess filled therein, the second insulating layer being provided with third recesses which penetrate from the third surface to the fourth surface and at least one of which is connected to the second recess;
a conductor layer filling the second and third recesses. The multilayer wiring board according to claim 1, wherein the conductor layer includes a via portion located in the second recess, a land portion located in the third recess that is connected to the second recess, and a wiring portion located in the third recess that is not connected to the second recess. Each of the two or more layers comprises:
an adhesive layer including a portion interposed between the conductor layer and the first insulating layer, a portion interposed between the conductor layer and the second insulating layer, and a portion covering the surface of the conductor layer on the first surface side;
3. The multilayer wiring board according to claim 1, further comprising a seed layer interposed between the adhesion layer and the conductor layer. The multilayer wiring board according to any one of claims 1 to 3, wherein in at least a portion of the first insulating layer, the opening diameter of the first recess on the second surface is within a range of 0.5 to 5 μm, and the opening diameter of the second recess on the second surface is within a range of 5 to 50 μm. The multilayer wiring board according to any one of claims 1 to 4, wherein in at least a portion of the first insulating layer, the ratio N1/N2 of the number N1 of the first recesses to the number N2 of the second recesses is in the range of 1 to 5. The multilayer wiring board according to any one of claims 1 to 5, wherein the first and second insulating layers are made of a material containing an organic insulator. The multilayer wiring board according to any one of claims 1 to 6, having a thickness in the range of 10 μm to 300 μm. The multilayer wiring board according to any one of claims 1 to 7, wherein the surface of the conductor layer on the fourth surface side is flush with the fourth surface. A composite wiring board comprising a first wiring board and a second wiring board joined to the first wiring board, the first and second wiring boards being electrically connected to each other via a joining electrode interposed between them, the second wiring board being a multilayer wiring board according to any one of claims 1 to 8. The composite wiring board according to claim 9, wherein the first wiring board is a wiring board for a flip chip ball grid array, and the second wiring board is an interposer. The composite wiring board according to claim 9 or 10,
a functional device mounted on a surface of the first wiring substrate opposite to the second wiring substrate. forming two or more layers on a support, the layers being laminated together, the forming of each of the two or more layers comprising:
forming a first insulating layer having a first surface and a second surface that is a back surface of the first insulating layer, the first surface having first and second recesses that respectively extend from the first surface to the second surface;
forming a second insulating layer having a third surface in contact with the second surface and a fourth surface which is the back surface of the third surface, the second insulating layer having the first recesses filled therein, the second insulating layer being provided with third recesses which penetrate from the third surface to the fourth surface and at least one of which is connected to the second recesses;
forming a conductor layer covering the fourth surface and filling the second and third recesses;
and polishing the conductor layer to remove a portion of the conductor layer located outside the second or third recess.