JP7581797B2 - Vibration Device - Google Patents

Description

The present invention relates to vibration devices, etc.

Conventionally, vibration devices such as oscillators have been known as devices using vibration elements. For example, Patent Document 1 discloses an oscillator in which a piezoelectric vibrating piece is mounted as a vibration element on a semiconductor substrate such as a silicon substrate on which a circuit pattern of an integrated circuit is formed, and the piezoelectric vibrating piece is sealed between the semiconductor substrate and a lid. In this oscillator, the vibration element and the circuit pattern are electrically connected via a through electrode of a through hole, which is a through hole.

JP 2004-214787 A

In the oscillator of Patent Document 1, the vibration element is directly mounted on the semiconductor substrate on which the integrated circuit is formed, so it was found that heat generated in the output buffer circuit of the integrated circuit is easily transferred to the vibration element, causing problems such as deterioration of the oscillation characteristics.

One aspect of the present disclosure relates to a vibration device including a semiconductor substrate having a first surface and a second surface that is opposite to the first surface, a base including a through electrode that penetrates between the first surface and the second surface, a vibration element fixed to the first surface via a conductive bonding member, and a first external connection terminal provided on the second surface side via an insulating layer, in which an oscillation circuit that is electrically connected to the vibration element via the through electrode and that oscillates the vibration element to generate an oscillation signal, an output buffer circuit that outputs a clock signal based on the oscillation signal, and a first contact pad that is electrically connected to the first external connection terminal are arranged on the second surface, and when the distance between the output buffer circuit and the through electrode is Dbx and the distance between the output buffer circuit and the first contact pad is Dbc, Dbc<Dbx.

FIG. 1 is a cross-sectional view showing an example of the configuration of a vibration device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a specific configuration example of the vibration device according to the embodiment. FIG. 2 is a plan view showing an example of a vibration element of the vibration device. FIG. 1 is a diagram showing a configuration example of an integrated circuit. FIG. 2 is a diagram showing a detailed configuration example of an integrated circuit. FIG. 2 is a diagram showing a configuration example of an oscillator circuit. FIG. 4 is a diagram showing a configuration example of an output buffer circuit. 5A to 5C are manufacturing process diagrams showing an example of a method for manufacturing a vibration device. FIG. 2 is a plan view showing the arrangement relationship of an output buffer circuit, contact pads, and through electrodes. FIG. 4 is a plan view showing an example of an arrangement of external connection terminals. FIG. 2 is a plan view showing the arrangement relationship of an output buffer circuit, contact pads, and through electrodes. FIG. 2 is a plan view showing the arrangement relationship of an output buffer circuit, contact pads, and through electrodes. 13 is a plan view showing another example of the arrangement relationship between the output buffer circuit, the contact pads, and the through electrodes. FIG. FIG. 11 is a cross-sectional view showing another example of the through electrode. FIG. 13 is a diagram showing another example of the configuration of an output driver of the output buffer circuit. FIG. 13 is a diagram showing another example of the configuration of an output driver of the output buffer circuit. FIG. 11 is a plan view showing another example of the arrangement of the external connection terminals.

The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the contents of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential components. Furthermore, in the drawings below, some components may be omitted for the sake of convenience. Furthermore, in the drawings, the dimensional ratios of each component are different from the actual ones for ease of understanding.

1. Vibration device FIG. 1 is a cross-sectional view showing an example of the configuration of a vibration device 1 of this embodiment. As shown in FIG. 1, the vibration device 1 of this embodiment includes a base 2, a vibration element 5, and external connection terminals 91 and 92. The vibration device 1 may also include a lid 7 and a relocation wiring layer 8. The base 2 includes a semiconductor substrate 20 and a through electrode 40. The semiconductor substrate 20 has a first surface 21 and a second surface 22 that is in a front-back relationship with the first surface 21. The first surface 21 is, for example, the upper surface of the semiconductor substrate 20, and the second surface 22 is, for example, the lower surface of the semiconductor substrate 20. The through electrode 40 is an electrode that penetrates the first surface 21 and the second surface 22 of the semiconductor substrate 20. The vibration element 5 is disposed on the first surface 21 side of the semiconductor substrate 20. For example, the vibration element 5 is disposed at a position spaced apart from the first surface 21 of the semiconductor substrate 20 by a given distance. Specifically, the vibration element 5 is fixed to the first surface 21 of the semiconductor substrate 20 via, for example, a conductive bonding member 60. The external connection terminals 91, 92 are provided on the second surface 22 side of the semiconductor substrate 20 via an insulating layer 80 or the like. The insulating layer 80 is an insulating layer that constitutes the rearrangement wiring layer 8, for example.

In each figure described in this embodiment, the X-axis, Y-axis, and Z-axis are illustrated as three mutually orthogonal axes. The direction along the X-axis is called the "X-axis direction", the direction along the Y-axis is called the "Y-axis direction", and the direction along the Z-axis is called the "Z-axis direction". The tip side of the arrow in each axis direction is also called the "plus side", the base side is called the "minus side", the plus side of the Z-axis is called the "upper", and the minus side of the Z-axis is called the "lower". For example, the Z-axis direction is along the vertical direction, and the XY plane is along the horizontal plane. Figure 1 is a cross-sectional view of the vibration device 1 as viewed from the Y-axis direction. The first surface 21 and the second surface 22 of the semiconductor substrate 20 are surfaces along the XY plane and are perpendicular to the Z-axis. Note that "perpendicular" includes cases where the surfaces intersect at an angle slightly inclined from 90°, in addition to cases where the surfaces intersect at 90°.

The vibration device 1 is, for example, an oscillator. Specifically, the vibration device 1 is an oscillator such as a simple package crystal oscillator (SPXO), a voltage-controlled crystal oscillator (VCXO), a temperature-compensated crystal oscillator (TCXO), an oven-controlled crystal oscillator (OCXO), a SAW (Surface Acoustic Wave) oscillator, a voltage-controlled SAW oscillator, or a MEMS (Micro Electro Mechanical Systems) oscillator. A MEMS oscillator can be realized by a MEMS vibration element in which a piezoelectric film and electrodes are arranged on a substrate such as a silicon substrate. However, the vibration device 1 may also be an inertial sensor such as an acceleration sensor or an angular velocity sensor, or a force sensor such as an inclination sensor.

The base 2 is composed of a semiconductor substrate 20. The semiconductor substrate 20 is, for example, a silicon substrate. However, the semiconductor substrate 20 is not limited to a silicon substrate, and may be a semiconductor substrate such as Ge, GaP, GaAs, or InP.

The base 2 also includes an integrated circuit 10. The integrated circuit 10, which is a semiconductor circuit, is formed on the second surface 22 of the semiconductor substrate 20. The integrated circuit 10 is composed of a plurality of circuit elements. The circuit elements are, for example, active elements such as transistors, or passive elements such as capacitors and resistors. Specifically, the integrated circuit 10 is composed of a plurality of circuit blocks, each of which includes a plurality of circuit elements. The integrated circuit 10 is also formed of a diffusion region, which is an impurity region formed by doping impurities into the semiconductor substrate 20, and a wiring layer in which a metal layer and an insulating layer are laminated. The diffusion region forms the source region and drain region of the transistor, which is a circuit element of the integrated circuit 10, and the wiring region forms wiring that connects the circuit elements.

The base 2 also includes a through electrode 40. The through electrode 40 is made of a conductive material that penetrates the first surface 21 and the second surface 22 of the semiconductor substrate 20. For example, a through hole is formed in the semiconductor substrate 20, and the through hole is filled with a conductive material to form the through electrode 40. The conductive material may be a metal such as copper, or may be conductive polysilicon. Conductive polysilicon refers to polysilicon that has been doped with impurities such as phosphorus (P), boron (B), and arsenic (As) to give it conductivity. By using polysilicon as the conductive material, it is possible to realize a through electrode 40 that has sufficient resistance to heat applied during the formation process of the integrated circuit 10.

One end of the through electrode 40 is electrically connected to the vibration element 5 via a conductive bonding member 60. In FIG. 1, the conductive bonding member 60 is realized by a bump 62 or the like, one end of which is electrically connected to the vibration element 5 and the other end of which is electrically connected to the through electrode 40. Specifically, the other end of the bump 62 is connected to the through electrode 40 via a terminal 64. The bump 62 is a conductive bump, specifically a metal bump. The conductive bonding member 60 may be realized by a conductive adhesive or the like.

The other end of the through electrode 40 is electrically connected to the integrated circuit 10. Specifically, the other end of the through electrode 40 is connected to a circuit element of the integrated circuit 10 via a contact pad 36 formed on the integrated circuit 10. In this manner, the vibration element 5 and the integrated circuit 10 can be electrically connected via the through electrode 40.

The lid 7 is joined to the base 2 via joining members 71 and 72. The base 2 and the lid 7, which is a cover body, form an airtight storage space SP, and the vibration element 5 is housed in this storage space SP. The storage space SP is hermetically sealed, and the inside of the storage space SP is, for example, in a reduced pressure state. This allows the vibration element 5 to be driven stably. Note that the state inside the storage space SP is not limited to a reduced pressure state, and the inside of the storage space SP may be, for example, an inert gas atmosphere.

The relocation wiring layer 8 is provided on the second surface 22 side of the semiconductor substrate 20, and includes an insulating layer 80 and wiring 82 for relocation wiring. The insulating layer 80 is realized by a resin layer such as polyimide, and the wiring 82 is realized by a metal wiring such as copper foil. The insulating layer 80 needs to have heat resistance that can withstand soldering when mounting the vibration device 1, and it is preferable to use polyimide. The material of the wiring 82 may be a metal material such as silver other than copper. The thickness of the wiring layer and terminals in the relocation wiring layer 8 is, for example, about 50 μm. By providing the relocation wiring layer 8, it becomes possible to electrically connect the contact pads 38, 39 formed on the integrated circuit 10 to the external connection terminals 91, 92. Then, by mounting the external connection terminals 91, 92 of the vibration device 1 to terminals and wiring of a circuit board or the like on which the vibration device 1 is mounted, it becomes possible to incorporate the vibration device 1 into an electronic device. Furthermore, by providing such a relocation wiring layer 8, it is possible to mechanically protect the integrated circuit 10 and thermally protect the integrated circuit 10 from heat generated during the soldering process when mounting the vibration device 1.

Figure 2 is a cross-sectional view showing a specific configuration example of the vibration device 1, and Figure 3 is a plan view showing an example of the vibration element 5 of the vibration device 1. First, the details of the vibration element 5 will be described with reference to Figure 3.

The vibration element 5 is an element that generates mechanical vibration by an electrical signal. For example, as shown in FIG. 3, the vibration element 5 has a vibration substrate 50 and an electrode arranged on the surface of the vibration substrate 50. The vibration substrate 50 has a thickness shear vibration mode, and is formed from an AT-cut quartz substrate in this embodiment. The AT-cut quartz substrate has a third-order frequency-temperature characteristic, so the vibration element 5 has excellent temperature characteristics. The electrodes include an excitation electrode 52 arranged on the upper surface of the vibration substrate 50 and an excitation electrode 53 arranged on the lower surface opposite the excitation electrode 52. The upper surface is the surface on the positive side in the Z-axis direction, and the lower surface is the surface on the negative side in the Z-axis direction. One of the excitation electrodes 52 and 53 is a first excitation electrode, and the other of the excitation electrodes 52 and 53 is a second excitation electrode. The electrode also has a pair of terminals 56, 57 arranged on the lower surface of the vibration substrate 50, a wiring 54 that electrically connects the terminal 56 to the excitation electrode 52, and a wiring 55 that electrically connects the terminal 57 to the excitation electrode 53.

The configuration of the vibration element 5 is not limited to the above configuration. For example, the vibration element 5 may be a mesa type in which the vibration area sandwiched between the excitation electrodes 52 and 53 protrudes from its surroundings, or conversely, may be an inverted mesa type in which the vibration area is recessed from its surroundings. In addition, bevel processing for grinding the periphery of the vibration substrate 50, or convex processing for making the upper and lower surfaces convex curved surfaces may be performed. In addition, the vibration element 5 is not limited to one that vibrates in a thickness-shear vibration mode. For example, the vibration element 5 may be a tuning fork type vibration element in which multiple vibrating arms vibrate in an in-plane direction, a tuning fork type vibration element in which multiple vibrating arms vibrate in an out-of-plane direction, a gyro sensor element that has a driving arm that vibrates and a detection arm that vibrates, and detects angular velocity, or an acceleration sensor element that has a detection unit that detects acceleration. The vibration substrate 50 is not limited to being formed from an AT-cut quartz substrate, and may be formed from a quartz substrate other than an AT-cut quartz substrate, for example, an X-cut quartz substrate, a Y-cut quartz substrate, a Z-cut quartz substrate, a BT-cut quartz substrate, an SC-cut quartz substrate, an ST-cut quartz substrate, etc. In the present embodiment, the vibration substrate 50 is made of quartz, but is not limited to this, and may be made of a piezoelectric single crystal such as lithium niobate, lithium tantalate, lithium tetraborate, potassium niobate, gallium phosphate, or other piezoelectric single crystal. The vibration element 5 is not limited to a piezoelectric drive type vibration element, and may be an electrostatic drive type vibration element using electrostatic force.

2 and 3, the vibration element 5 is fixed to the first surface 21, which is the upper surface of the semiconductor substrate 20, via conductive bonding members 60 and 61. Although not shown in FIG. 2, as shown in FIG. 3, for example, two bonding members 60 and 61 are provided along the Y-axis direction. Also, as shown in FIG. 9 described later, two through electrodes 40 and 41 are provided on the semiconductor substrate 20, for example, along the Y-axis direction, and these through electrodes 40 and 41 are electrically connected to the vibration element 5 via conductive bonding members 60 and 61. One of the through electrodes 40 and 41 is a first through electrode, and the other of the through electrodes 40 and 41 is a second through electrode. Specifically, one end of the through electrode 40 is electrically connected to the excitation electrode 52 of the vibration element 5 via the bonding member 60, the terminal 56 of the vibration element 5, and the wiring 54. Also, one end of the through electrode 41 is electrically connected to the excitation electrode 53 of the vibration element 5 via the bonding member 61, the terminal 57 of the vibration element 5, and the wiring 55. The other ends of the through electrodes 40 and 41 are electrically connected to the integrated circuit 10. This allows the vibration element 5 and the integrated circuit 10 to be electrically connected via the through electrodes 40 and 41. Specifically, the other ends of the through electrodes 40 and 41 are electrically connected to the oscillation circuit 11 of the integrated circuit 10 via the contact pads 36 and 37 shown in Figures 2 and 9. This allows the vibration element 5 and the oscillation circuit 11 to be electrically connected via the through electrodes 40 and 41.

The bonding members 60 and 61 are not particularly limited as long as they have both electrical conductivity and bonding properties, and can be realized by various conductive bumps 62 such as gold bumps, silver bumps, copper bumps, solder bumps, and resin core bumps. Alternatively, the bonding members 60 and 61 may be conductive adhesives in which conductive fillers such as silver fillers are dispersed in various adhesives such as polyimide, epoxy, silicone, and acrylic adhesives. If conductive bumps 62 are used as the bonding members 60 and 61, gas generation from the bonding members 60 and 61 can be suppressed, and environmental changes in the storage space SP, particularly pressure increases, can be effectively suppressed. On the other hand, if a conductive adhesive is used as the bonding members 60 and 61, the bonding members 60 and 61 become softer than when the bonding members 60 and 61 are conductive bumps 62, and there is an advantage that stress is less likely to be transmitted to the vibration element 5.

In addition, the semiconductor substrate 20 is thermally oxidized after the through-hole is formed, so that an insulating layer 44, which is an insulating film made of, for example, silicon oxide (SiO ₂ ), is formed on the first surface 21 of the semiconductor substrate 20 and the inner surface of the through-hole. By forming the insulating layer 44 by thermal oxidation, a dense and homogeneous insulating layer 44 can be formed on the surface of the semiconductor substrate 20. In addition, the difference in linear expansion coefficient between the insulating layer 44 and the semiconductor substrate 20 can also be reduced. Therefore, thermal stress is less likely to occur, and a vibration device 1 having excellent oscillation characteristics can be realized. The constituent material of the insulating layer 44 is not particularly limited, and may be made of, for example, silicon nitride (SiN) or resin. In addition, the method of forming the insulating layer 44 is not limited to thermal oxidation, and may be formed by, for example, CVD (Chemical Vapor Deposition).

Then, the through-hole insulating layer 44 is filled with a conductive material such as copper or conductive polysilicon to form the through-hole electrodes 40, 41. That is, the through-holes are filled with a conductive material to form the through-hole electrodes 40, 41. One end of the through-hole electrodes 40, 41 is electrically connected to the vibration element 5. Specifically, one end of the through-hole electrodes 40, 41 is electrically connected to the excitation electrodes 52, 53 of the vibration element 5. Meanwhile, the other end of the through-hole electrodes 40, 41 is electrically connected to the integrated circuit 10. Specifically, the other end of the through-hole electrodes 40, 41 is electrically connected to the oscillation circuit 11 of the integrated circuit 10 via the contact pads 36, 37.

2, the integrated circuit 10 is composed of, for example, an N-type transistor 23 and a P-type transistor 24. These transistors 23 and 24 are composed of a source region and a drain region, which are diffusion regions formed in a semiconductor substrate 20, a gate electrode, and a gate oxide film. The transistors 23 and 24 are also isolated by an element isolation film 25 called LOCOS (LOCal Oxidation of Silicon). The integrated circuit 10 also includes a wiring layer 30 that realizes connection wiring between multiple circuit elements such as the transistors 23 and 24. For example, the wiring layer 30 in FIG. 2 includes metal layers 31 and 32 and insulating layers 33, 34, and 35. The metal layers 31 and 32 are the first metal layer and the second metal layer, respectively, and the insulating layers 33, 34, and 35 are the first insulating layer, the second insulating layer, and the third insulating layer, respectively. The metal layer 31 is formed between the insulating layer 33 and the insulating layer 34, and the metal layer 32 is formed between the insulating layer 34 and the insulating layer 35. These metal layers 31 and 32 are realized by a metal such as aluminum. A passivation film is formed by the insulating layer 35 of the top layer. The metal layer 31 and the metal layer 32 are electrically connected by a contact called a via contact, and the metal layer 31 and the source region and the drain region of the transistors 23 and 24 are electrically connected by the contact. As shown in FIG. 2, the contact pad 36 electrically connected to the other end of the through electrodes 40 and 41 is formed by the lower metal layer 31. The contact pads 38 and 39 electrically connected to the external connection terminals 91 and 92 are formed by the upper metal layer 32. In the wiring layer 30, the layer closer to the transistors 23 and 24 in the integrated circuit 10 is the lower layer, and the layer farther from the transistors 23 and 24 is the upper layer. Also, while FIG. 2 shows a case where the wiring layer 30 has two metal layers 31 and 32, this embodiment is not limited to this, and the wiring layer 30 may have three or more metal layers. In this case, the contact pads 36 and 37 are formed by the lowest metal layer among the multiple metal layers, and the contact pads 38 and 39 are formed by the highest metal layer. In addition, a passivation film is formed by the highest insulating layer.

The rearrangement wiring layer 8 also includes an insulating layer 80 realized by a resin layer such as polyimide, and wiring 82 realized by copper foil or the like. The contact pad 38 is electrically connected to an external connection terminal 91, and the contact pad 39 is electrically connected to the external connection terminal 92 via the wiring 82.

In FIG. 2, each of the external connection terminals 91, 92 has a two-layer structure having a first metal layer 101 and a second metal layer 102. For the first metal layer 101 on the polyimide insulating layer 80 side, for example, a titanium tungsten layer is used to improve adhesion with the polyimide. For the second metal layer 102, for example, a metal layer such as copper or gold is used, which is easy to solder to external terminals and wiring.

Figure 4 shows an example of the configuration of the integrated circuit 10. The integrated circuit 10 includes an oscillator circuit 11 and an output buffer circuit 12. The integrated circuit 10 can also include a logic circuit 13 and a power supply circuit 14.

The oscillator circuit 11 is a circuit that oscillates the vibration element 5. For example, the oscillator circuit 11 is electrically connected to the terminals TXA and TXB and generates an oscillation signal OSC. Specifically, the oscillator circuit 11 is electrically connected to the vibration element 5 via the wiring LA, LB, and the terminals TXA and TXB, and generates the oscillation signal OSC by oscillating the vibration element 5. One of the terminals TXA and TXB is a first terminal, and the other of the terminals TXA and TXB is a second terminal. For example, the oscillator circuit 11 can be realized by a drive circuit for oscillation provided between the terminals TXA and TXB, and passive elements such as capacitors and resistors. The drive circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillator circuit 11, and the drive circuit drives the vibration element 5 with voltage or current to oscillate the vibration element 5. As the oscillator circuit 11, various types of oscillator circuits such as inverter type, Pierce type, Colpitts type, or Hartley type can be used. The oscillator circuit 11 is also provided with a variable capacitance circuit, and the oscillation frequency can be adjusted by adjusting the capacitance of the variable capacitance circuit. The variable capacitance circuit can be realized by a variable capacitance element such as a varactor. Alternatively, the variable capacitance circuit may be realized by a capacitor array and a switch array connected to the capacitor array. For example, the variable capacitance circuit may be configured by a capacitor array having a plurality of capacitors whose capacitance values are weighted in binary, and a switch array having a plurality of switches, each of which turns on and off the connection between each capacitor of the capacitor array and the terminal TXA or TXB. Note that the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows an electrical signal to be transmitted, and is a connection that allows information to be transmitted by an electrical signal. The electrical connection may be a connection via an active element, etc.

The output buffer circuit 12 outputs a clock signal CK based on the oscillation signal OSC. For example, the output buffer circuit 12 buffers the oscillation signal OSC and outputs it to the terminal TCK as a clock signal CK. Then, this clock signal CK is output to the outside via the external connection terminal 91 of the vibration device 1. For example, the output buffer circuit 12 outputs the clock signal CK in a single-ended CMOS signal format. For example, when the output enable signal OE from the terminal TOE is active, the enable signal from the logic circuit 13 becomes active, and the output buffer circuit 12 outputs the clock signal CK obtained by buffering the oscillation signal OSC. On the other hand, when the output enable signal OE is inactive, the output buffer circuit 12 sets the clock signal CK to a fixed voltage level, such as a low level. As a result, the voltage level of the terminal TCK is set to a fixed voltage level. Note that an active signal is, for example, a high level in the case of positive logic, and a low level in the case of negative logic. Also, an inactive signal is, for example, a low level in the case of positive logic, and a high level in the case of negative logic. The output buffer circuit 12 may also output the clock signal CK in a signal format other than CMOS.

The logic circuit 13 is a control circuit that performs various control processes. For example, the logic circuit 13 controls the entire integrated circuit 10 and controls the operation sequence of the integrated circuit 10. The logic circuit 13 may also perform various processes for controlling the oscillator circuit 11 and control the power supply circuit 14. The logic circuit 13 can be realized by an ASIC (Application Specific Integrated Circuit) circuit that is automatically placed and wired, such as a gate array.

The power supply circuit 14 is supplied with a power supply voltage VDD from a terminal TVDD and with a ground voltage GND from a terminal TGND. The power supply circuit 14 then supplies the power supply voltage for each internal circuit of the integrated circuit 10 to each internal circuit. The power supply circuit 14 may generate a reference voltage, a reference current, and the like used in the integrated circuit 10. For example, the power supply circuit 14 has a regulator, and supplies a regulated voltage generated by the regulator to the oscillation circuit 11, the output buffer circuit 12, and the logic circuit 13. In this case, the power supply circuit 14 may have a regulator that generates a regulated voltage supplied to the oscillation circuit 11, and a regulator that generates a regulated voltage supplied to the output buffer circuit 12 and the logic circuit 13.

Figure 5 shows a detailed configuration example of the integrated circuit 10. In Figure 5, a temperature compensation circuit 15, a temperature sensor circuit 16, and a memory 17 are further provided.

The temperature compensation circuit 15 performs temperature compensation of the oscillation signal OSC of the oscillation circuit 11. The temperature compensation of the oscillation signal OSC is temperature compensation of the oscillation frequency of the oscillation circuit 11. The output buffer circuit 12 outputs a clock signal CK based on the temperature-compensated oscillation signal OSC. Specifically, the temperature compensation circuit 15 performs temperature compensation based on temperature detection information from the temperature sensor circuit 16. For example, the temperature compensation circuit 15 generates a temperature compensation voltage based on the temperature detection voltage from the temperature sensor circuit 16, and outputs the generated temperature compensation voltage to the oscillation circuit 11 to perform temperature compensation of the oscillation signal OSC of the oscillation circuit 11. For example, the temperature compensation circuit 15 performs temperature compensation by outputting a temperature compensation voltage to the variable capacitance circuit of the oscillation circuit 11, which becomes the capacitance control voltage of the variable capacitance circuit. In this case, the variable capacitance circuit of the oscillation circuit 11 is realized by a variable capacitance element such as a varactor. Temperature compensation is a process of suppressing and compensating for fluctuations in the oscillation frequency due to temperature fluctuations. For example, the temperature compensation circuit 15 performs analog temperature compensation by polynomial approximation. For example, when the temperature compensation voltage that compensates for the frequency-temperature characteristics of the vibration element 5 is approximated by a polynomial, the temperature compensation circuit 15 performs analog temperature compensation based on the coefficient information of the polynomial. Analog temperature compensation is temperature compensation that is achieved by, for example, adding current signals and voltage signals, which are analog signals. Specifically, the memory 17 stores coefficient information of a polynomial for temperature compensation, and the logic circuit 13 reads this coefficient information from the memory 17 and sets it, for example, in a register of the temperature compensation circuit 15. The temperature compensation circuit 15 then performs analog temperature compensation based on the coefficient information set in the register.

The temperature compensation circuit 15 may perform digital temperature compensation. In this case, the temperature compensation circuit 15 is realized by, for example, a logic circuit. Specifically, the temperature compensation circuit 15 performs digital temperature compensation processing based on temperature detection data, which is temperature detection information from the temperature sensor circuit 16. For example, the temperature compensation circuit 15 obtains frequency adjustment data based on the temperature detection data. Then, the capacitance value of the variable capacitance circuit of the oscillation circuit 11 is adjusted based on the obtained frequency adjustment data, thereby achieving temperature compensation processing of the oscillation frequency of the oscillation circuit 11. In this case, the variable capacitance circuit of the oscillation circuit 11 is realized by a capacitor array having multiple binary-weighted capacitors and a switch array. The memory 17 also stores a lookup table that indicates the correspondence between the temperature detection data and the frequency adjustment data, and the temperature compensation circuit 15 performs temperature compensation processing to obtain the frequency adjustment data from the temperature data using the lookup table read from the memory 17 by the logic circuit 13.

The temperature sensor circuit 16 is a sensor circuit that detects temperature. Specifically, the temperature sensor circuit 16 outputs a temperature-dependent voltage that changes according to the temperature of the environment as a temperature detection voltage. For example, the temperature sensor circuit 16 generates the temperature detection voltage by using a circuit element that has temperature dependency. Specifically, the temperature sensor circuit 16 uses the temperature dependency of the forward voltage of a PN junction to output a temperature detection voltage whose voltage value changes depending on temperature. For example, the base-emitter voltage of a bipolar transistor can be used as the forward voltage of the PN junction.

When performing digital temperature compensation processing, the temperature sensor circuit 16 measures a temperature such as the environmental temperature, and outputs the result as temperature detection data. The temperature detection data is, for example, data that monotonically increases or decreases with respect to temperature. In this case, a temperature sensor circuit that utilizes the temperature dependency of the oscillation frequency of the ring oscillator can be used as the temperature sensor circuit 16. Specifically, the temperature sensor circuit 16 includes a ring oscillator and a counter circuit. The counter circuit counts the output pulse signal, which is the oscillation signal of the ring oscillator, during a count period defined by a clock signal based on the oscillation signal OSC from the oscillation circuit 11, and outputs the count value as temperature detection data.

Memory 17 stores various information used in integrated circuit 10. Memory 17 can be realized, for example, by a non-volatile memory. The non-volatile memory is an EEPROM such as a Floating gate Avalanche injection MOS (FAMOS) memory or a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) memory, but is not limited thereto and may be an OTP (One Time Programmable) memory or a fuse-type ROM. Alternatively, memory 17 may be realized by a volatile memory such as a RAM.

The terminals TXA and TXB in FIG. 4 and FIG. 5 are realized by the contact pads 36 and 37 in FIG. 2 and FIG. 9. That is, the oscillator circuit 11 is electrically connected to the vibration element 5 via the terminals TXA and TXB realized by the contact pads 36 and 37. The terminal TCK is realized by the contact pad 38. That is, the clock signal CK from the output buffer circuit 12 is output to the outside from the external connection terminal 91 via the terminal TCK realized by the contact pad 38. The terminals TVD and TGND are realized by the contact pads 39 and 68 in FIG. 2 and FIG. 9. That is, the power supply voltages VDD and GND are supplied to the integrated circuit 10 via the terminals TVD and TGND realized by the contact pads 39 and 68. Specifically, VDD and GND are supplied to the power supply circuit 14. The terminal TOE is realized by the contact pad 69. That is, the output enable signal OE is input to the integrated circuit 10 via a terminal TOE realized by a contact pad 69. For example, it is input to the logic circuit 13.

Figure 6 shows an example of the configuration of the oscillator circuit 11. As shown in Figure 6, the oscillator circuit 11 includes inverter circuits DV1 and DV2 and variable capacitance circuits CV1 and CV2. The inverter circuit DV1 is a drive circuit for the vibration element 5, and the input node is connected to one end of the vibration element 5 and the output node is connected to the other end of the vibration element 5. The inverter circuit DV2 buffers the output signal of the inverter circuit DV1 and outputs it as an oscillation signal OSC. The inverter circuits DV1 and DV2 are supplied with a regulated power supply voltage VREG1 and GND to operate. The regulated power supply voltage VREG1 is generated by a regulator included in the power supply circuit 14.

One end of the variable capacitance circuit CV1 is connected to one end of the vibration element 5, and the other end is connected to the GND node. One end of the variable capacitance circuit CV2 is connected to the other end of the vibration element 5, and the other end is connected to GND. As described above, these variable capacitance circuits CV1 and CV2 may be realized by a variable capacitance element such as a varactor whose capacitance is controlled by a capacitance control voltage that is a temperature compensation voltage, or may be realized by a circuit having a capacitor array and a switch array, whose capacitance value is controlled by frequency control data.

Figure 7 shows an example of the configuration of the output buffer circuit 12. As shown in Figure 7, the output buffer circuit 12 includes a NAND circuit NA and inverter circuits IV1, IV2, and IV3. In this way, the output buffer circuit 12 is composed of buffer circuits such as a plurality of signal inversion circuits. An oscillation signal OSC, which is an oscillation clock signal from the oscillation circuit 11, is input to the first input node of the NAND circuit NA, and an enable signal EN from the logic circuit 13 is input to the second input node. For example, when the output enable signal OE input from the terminal TOE becomes a high level, which is an active level, the enable signal EN becomes a high level, and the oscillation signal OSC is buffered by the NAND circuit NA and the inverter circuits IV1, IV2, and IV3 and output as a clock signal CK. On the other hand, when the output enable signal OE input from the terminal TOE becomes a low level, which is an inactive level, the enable signal EN becomes a low level, and the output of the output buffer circuit 12 is fixed to a low level.

Next, a method for manufacturing the vibration device 1 of this embodiment will be described. Figure 8 is a manufacturing process diagram showing an example of a method for manufacturing the vibration device 1.

In the integrated circuit formation process (S11), a semiconductor substrate 20 is prepared, and an integrated circuit 10 is formed on the second surface 22, which is the lower surface of the semiconductor substrate 20, as shown in Figures 1 and 2. In the rearrangement wiring layer formation process (S12), a rearrangement wiring layer 8 having, for example, an insulating layer 80, wiring 82, external connection terminals 91, 92, etc. is formed, and contact pads 38, 39, etc. of the integrated circuit 10 are electrically connected to the external connection terminals 91, 92, etc. In the base thinning process (S13), the first surface 21, which is the mounting surface side of the vibration element 5 of the semiconductor substrate 20, is polished to thin the base 2. In other words, the base 2 is thinned.

In the hole forming step (S14), a through hole is formed. Specifically, a hole is formed in the semiconductor substrate 20 by dry etching, and a hole is further formed by wet etching up to the metal layer 31, which is the first metal layer of the wiring layer 30 in FIG. 2. In the insulating layer forming step (S15), the semiconductor substrate 20 is thermally oxidized to form an insulating layer 44, which is an insulating film made of silicon oxide (SiO ₂ ) or a resin layer, on the surface of the semiconductor substrate 20, particularly on the inner surface of the through hole. In the through electrode forming step (S16), the through hole is filled with a conductive material such as copper to form the through electrodes 40, 41. In the vibration element arrangement step (S17), the vibration element 5 is prepared, and the vibration element 5 is bonded to the first surface 21 of the semiconductor substrate 20 via the bonding members 60, 61. In the lid bonding step (S18), the lid 7 is prepared, and the lid 7 is bonded to the base 2 via the bonding members 71, 72 in a reduced pressure environment. In the singulation step (S19), the vibration devices 1 are singulated using a dicing saw or the like. In this manner, the vibration devices 1 are obtained.

As described above, in this embodiment, a first semiconductor wafer having a plurality of bases 2 each having a vibration element 5 and an integrated circuit 10 is attached to a second semiconductor wafer having a plurality of lids 7, thereby bonding the plurality of bases 2 and the plurality of lids 7. The vibration devices 1 are then singulated to manufacture a large number of vibration devices 1. For example, small vibration devices 1 having lengths and widths of about 1 mm to several mm and a thickness of less than 1 mm are manufactured. In this way, it is possible to realize a wafer-level package (WLP) vibration device 1, and it is possible to manufacture the vibration devices 1 at high throughput and low cost. In other words, it is possible to manufacture vibration devices 1 having vibration elements 5 and integrated circuits 10 collectively by wafer-level batch processing.

2. Positional relationship of the output buffer circuit, contact pads, and through electrodes FIG. 9 is a plan view showing the positional relationship of the output buffer circuit 12, contact pads 38, 39, and through electrodes 40, 41 in the vibration device 1 of this embodiment. FIG. 9 also shows the relationship between the positions of the circuits of the integrated circuit 10 and the positions of the through electrodes 40, 41, contact pads 36, 37, 68, 69, and external connection terminals 91, 92, 93, 94. FIG. 9 is a plan view of the base 2 viewed from the negative side in the Z axis direction, and the outer shapes of the through electrodes 40, 41 located on the positive side of the Z axis direction with respect to the base 2 on which the integrated circuit 10 is formed, and the outer shapes of the external connection terminals 91, 92, 93, 94 located on the negative side of the Z axis direction with respect to the base 2 are shown by dotted lines. FIG. 10 shows the positions of the external connection terminals 91, 92, 93, 94 on the bottom surface of the vibration device 1, and is a plan view of the bottom surface of the vibration device 1 viewed from the negative side in the Z axis direction. 9 and 10, external connection terminals 91, 92, 93, and 94 are rectangular, but these terminals do not have to be strictly rectangular, and may be shaped, for example, with chamfered corners, or may be shaped in a way other than rectangular. Also, Fig. 9 shows a layout in which integrated circuit 10 includes temperature compensation circuit 15, temperature sensor circuit 16, etc., but as explained in Fig. 4, integrated circuit 10 may not include temperature compensation circuit 15, temperature sensor circuit 16, etc. In this case, the layout in Fig. 9 may be such that temperature compensation circuit 15, temperature sensor circuit 16, etc. are not provided, and the free space is filled up.

As described above, the vibration device 1 of this embodiment includes a semiconductor substrate 20, a base 2 including through electrodes 40, 41 penetrating between the first surface 21 and the second surface 22 of the semiconductor substrate 20, a vibration element 5 fixed to the first surface 21 of the semiconductor substrate 20 via conductive bonding members 60, 61, and external connection terminals 91, 92, 93, 94 provided on the second surface 22 side of the semiconductor substrate 20 via an insulating layer 80. For example, the vibration device 1 includes an external connection terminal 91 or an external connection terminal 92, which is a first external connection terminal. As shown in FIG. 9, an oscillation circuit 11, an output buffer circuit 12, and contact pads 38, 39, 68, 69 are arranged on the second surface 22 of the semiconductor substrate 20. The oscillation circuit 11 is electrically connected to the vibration element 5 via the through electrodes 40, 41, and oscillates the vibration element 5 to generate an oscillation signal OSC. The output buffer circuit 12 outputs a clock signal CK based on the oscillation signal OSC. For example, the oscillation signal OSC is buffered by the output buffer circuit 12 and output as a clock signal CK. The clock signal CK from the output buffer circuit 12 is then output from the external connection terminal 91 to the outside of the vibration device 1 via the contact pad 38. Since this output buffer circuit 12 is a circuit that drives an external load of the vibration device 1, a current of, for example, 10 mA or more may flow when driving the external load, and the amount of heat generated is very large.

And on the second surface 22 of the semiconductor substrate 20, contact pads 38, 39, 68, 69 electrically connected to external connection terminals 91, 92, 93, 94 are arranged. Here, the external connection terminal 91 and the contact pad 38 are terminals and pads for outputting the clock signal CK. The external connection terminal 92 and the contact pad 39 are terminals and pads for supplying VDD to the integrated circuit 10. The external connection terminal 93 and the contact pad 68 are terminals and pads for supplying GND to the integrated circuit 10. The external connection terminal 94 and the contact pad 69 are terminals and pads for inputting the output enable signal OE. Specifically, the contact pad 39 or the contact pad 38, which is the first contact pad, is arranged on the second surface 22 of the semiconductor substrate 20. The contact pad 39 or the contact pad 38, which is the first contact pad, is electrically connected to the external connection terminal 92 or the external connection terminal 91, which is the first external connection terminal. As shown in Figures 1 and 2, an insulating layer 80 is interposed between the first contact pad and the first external connection terminal, and the first contact pad and the first external connection terminal are electrically connected via, for example, a rearrangement wiring layer 8.

For example, FIG. 9 shows the layout relationship when the first contact pad and the first external connection terminal are the contact pad 39 and the external connection terminal 92 for VDD, respectively. In FIG. 9, the distance between the output buffer circuit 12 and the through electrodes 40 and 41 is Dbx. Here, the shortest distance among the distances between the lines connecting any point in the region of the output buffer circuit 12 and any point in the region of the through electrodes 40 and 41 is the distance Dbx. For example, the distance between the output buffer circuit 12 and the through electrode 40 is Dbx=Dbx1, and the distance between the output buffer circuit 12 and the through electrode 41 is Dbx=Dbx2. Also, the distance between the output buffer circuit 12 and the contact pad 39, which is the first contact pad, is Dbc. Here, the shortest distance among the distances between the lines connecting any point in the region of the output buffer circuit 12 and any point in the region of the contact pad 39 is the distance Dbc. In this case, as shown in FIG. 9, in this embodiment, the relationship Dbc<Dbx holds. For example, the relationship Dbc<Dbx1, Dbc<Dbx2 is established. That is, in a plan view in a direction perpendicular to the first surface 21 of the semiconductor substrate 20, the contact pad 39 is arranged closer to the output buffer circuit 12 than the through electrodes 40, 41. That is, after the vibration element 5 is connected and fixed to the semiconductor substrate 20 on which the oscillation circuit 11, the output buffer circuit 12, and the contact pad 39 are formed, the contact pad 39 is arranged closer to the output buffer circuit 12 than the through electrodes 40, 41 in the circuit layout of the semiconductor substrate 20. For example, the contact pad 39 is arranged so as to be adjacent to the output buffer circuit 12 in a plan view. For example, the output buffer circuit 12 and the contact pad 39 are arranged so as to be adjacent to each other in a plan view so that no other circuit block is interposed between them.

That is, in a WLP vibration device 1 such as that of this embodiment, the vibration element 5 is directly fixed to the semiconductor substrate 20 via the bonding members 60, 61, so heat generated in the output buffer circuit 12 is easily transmitted to the vibration element 5. And since the output buffer circuit 12 is a circuit that drives an external load for the vibration device 1, a large current flows when the external load is driven, and the amount of heat generated is very large. Therefore, the heat generated in the output buffer circuit 12, which generates a large amount of heat, may adversely affect the oscillation characteristics of the vibration element 5.

In this respect, in the vibration device 1 of this embodiment, the relationship Dbc<Dbx is established between the distance Dbc between the output buffer circuit 12 and the contact pad 39 and the distance Dbx between the output buffer circuit 12 and the through electrodes 40 and 41, and the contact pad 39 is disposed near the output buffer circuit 12. As shown in FIG. 1 and FIG. 2, the contact pad 39 is connected to an external connection terminal 92 to which terminals and wiring of an external circuit board or the like are connected. Therefore, heat generated in the output buffer circuit 12 is easily dissipated from the contact pad 39 to the circuit board or the like on which the vibration device 1 is mounted via the external connection terminal 92 connected to the contact pad 39. That is, the small vibration device 1 and the small-area integrated circuit 10 realized by WLP have a small heat capacity, but the external terminals, wiring, and the circuit board on which the terminals and wiring are formed have a large heat capacity. In addition, since the external connection terminal 92 has a larger area and a larger heat capacity than the contact pad 39, as shown in FIG. 1 and FIG. 2, heat is transferred from the contact pad 39 to the external connection terminal 92 below it through a short-path heat conduction path. Here, the contact pad 39 has an area of, for example, about 70 μm to 100 μm on one side, and the external connection terminal 92 has an area of, for example, about 0.19 mm or more on one side. Therefore, heat generated in the output buffer circuit 12 is easily dissipated from the contact pad 39 to the outside via the external connection terminal 92 connected to the contact pad 39. As a result, it is possible to effectively suppress deterioration of the oscillation characteristics of the vibration device 1 caused by heat generation in the output buffer circuit 12.

Figure 11 also shows the layout relationship when the first contact pad and the first external connection terminal are the contact pad 38 and the external connection terminal 91 for the clock signal CK, respectively. In Figure 11, if the distance between the output buffer circuit 12 and the through electrodes 40 and 41 is Dbx, and the distance between the output buffer circuit 12 and the contact pad 38, which is the first contact pad, is Dbc, then the relationship Dbc < Dbx holds. That is, in a plan view, the contact pad 38 is arranged closer to the output buffer circuit 12 than the through electrodes 40 and 41. For example, in a plan view, the contact pad 38 is arranged so as to be adjacent to the output buffer circuit 12. For example, the output buffer circuit 12 and the contact pad 38 are arranged so as to be adjacent to each other in a plan view so that no other circuit block is interposed between them. By arranging the contact pads 38 in the vicinity of the output buffer circuit 12 in this manner, heat generated in the output buffer circuit 12 is easily dissipated from the contact pads 38 to a circuit board or the like on which the vibration device 1 is mounted, via the external connection terminals 91 connected to the contact pads 38. Therefore, it is possible to suppress deterioration of the oscillation characteristics of the vibration device 1 caused by heat generation in the output buffer circuit 12.

In this embodiment, the base 2 has a side SD1 and a side SD2 opposite the side SD1. Side SD1 is the first side, and side SD2 is the second side. The base 2 also has a side SD3 and a side SD4 opposite the side SD3. Side SD3 is the third side, and side SD4 is the fourth side. For example, the base 2 has a rectangular shape having sides SD1, SD2, SD3, and SD4 in a plan view. Note that the rectangular shape does not need to be a strict rectangular shape, and may be a shape in which the corners are chamfered, for example.

As shown in FIG. 9, the through electrodes 40 and 41, the contact pad 39, and the output buffer circuit 12 are arranged in this order from side SD1 to side SD2. For example, the contact pad 39, which is a first contact pad, is arranged in the region between the through electrodes 40 and 41 and the output buffer circuit 12. For example, the center line between the side SD1 and the side SD2 is CL. For example, the distance between the side SD1 and the center line CL is equal to the distance between the side SD2 and the center line CL. In this case, the through electrodes 40 and 41 are arranged in the first region, which is the region between the side SD1 and the center line CL. On the other hand, the output buffer circuit 12 is arranged in the second region, which is the region between the side SD2 and the center line CL. And the contact pad 39 is arranged in a position close to the output buffer circuit 12 in the region between the through electrodes 40 and 41 and the output buffer circuit 12.

In this manner, by arranging the through electrodes 40, 41, the contact pad 39, and the output buffer circuit 12 in this order, heat generated in the output buffer circuit 12 is transferred to the contact pad 39, and then to the through electrodes 40, 41. Therefore, the heat generated in the output buffer circuit 12 is more likely to be dissipated from the contact pad 39 to the outside of the vibration device 1 via the external connection terminal 92 before being transferred to the vibration element 5 via the through electrodes 40, 41. Therefore, it is possible to suppress deterioration of the oscillation characteristics of the vibration device 1 caused by heat generated in the output buffer circuit 12.

In FIG. 9, the first contact pad is the contact pad 39 to which the power supply voltage VDD is supplied. That is, the contact pad 39 electrically connected to the external connection terminal 92 to which VDD is supplied from the outside is the first contact pad, and the distance Dbc between this VDD contact pad 39 and the output buffer circuit 12 is smaller than the distance Dbx between the output buffer circuit 12 and the through electrodes 40 and 41. The external connection terminal 92 for VDD to which the contact pad 39 is connected is connected to an external terminal or wiring for VDD, and the terminal or wiring for VDD has a large heat capacity. Therefore, the heat generated in the output buffer circuit 12 is dissipated from the contact pad 39 through the external connection terminal 92 for VDD to the circuit board on which the vibration device 1 is mounted, etc., and deterioration of the oscillation characteristics of the vibration device 1 caused by heat generation in the output buffer circuit 12 can be suppressed.

On the other hand, in FIG. 11, the first contact pad is contact pad 38, and the through electrodes 40 and 41, the output buffer circuit 12, and the contact pad 38 are arranged in this order from side SD1 to side SD2 of the base 2. For example, the through electrodes 40 and 41 are arranged in the region between the output buffer circuit 12 and side SD1, and the contact pad 38 is arranged in the region between the output buffer circuit 12 and side SD2. For example, the through electrodes 40 and 41 are arranged in the first region, which is the region between side SD1 and the center line CL. On the other hand, the output buffer circuit 12 and the contact pad 38 are arranged in the second region, which is the region between side SD2 and the center line CL, and the contact pad 38 is arranged in the region between the output buffer circuit 12 and side SD2, close to the output buffer circuit 12.

In this manner, by arranging the through electrodes 40, 41, the output buffer circuit 12, and the contact pad 38 in that order, heat generated in the output buffer circuit 12 is more likely to be dissipated from the contact pad 38 to the outside of the vibration device 1 via the external connection terminal 91 before being transferred to the vibration element 5 via the through electrodes 40, 41. Therefore, it is possible to suppress deterioration of the oscillation characteristics of the vibration device 1 caused by heat generated by the output buffer circuit 12.

In addition, in FIG. 11, the first contact pad is a contact pad for outputting a clock signal CK. That is, the contact pad 38 electrically connected to the external connection terminal 91 through which the clock signal CK is output to the outside is the first contact pad, and the distance Dbc between the contact pad 38 for outputting the clock signal and the output buffer circuit 12 is smaller than the distance Dbx between the output buffer circuit 12 and the through electrodes 40, 41. The external connection terminal 91 for outputting the clock signal to which the contact pad 38 is connected is connected to a terminal or wiring for an external clock signal. Therefore, the heat generated in the output buffer circuit 12 is dissipated from the contact pad 38 through the external connection terminal 91 for outputting the clock signal to a circuit board or the like on which the vibration device 1 is mounted, and deterioration of the oscillation characteristics of the vibration device 1 caused by heat generation in the output buffer circuit 12 can be suppressed. Note that in FIG. 9 and FIG. 11, the first contact pad and the first external connection terminal are contact pads and external connection terminals for VDD or clock signal CK, but this embodiment is not limited to this. The first contact pad and the first external connection terminal may be, for example, a contact pad and an external connection terminal for GND or a constant potential signal.

In this embodiment, the vibration device 1 includes a first external connection terminal and a second external connection terminal provided on the second surface 22 side of the semiconductor substrate 20 via an insulating layer 80. A first contact pad electrically connected to the first external connection terminal and a second contact pad electrically connected to the second external connection terminal are arranged on the second surface 22. For example, in FIG. 12, the first external connection terminal is external connection terminal 92, and the second external connection terminal is external connection terminal 91. The first contact pad is contact pad 39, and the second contact pad is contact pad 38. When the distance between the output buffer circuit 12 and the first contact pad, contact pad 39, is Dbc1, and the distance between the output buffer circuit 12 and the second contact pad, contact pad 38, is Dbc2, Dbc1<Dbx and Dbc2<Dbx hold. 12, in a plan view from a direction perpendicular to the first surface 21 of the semiconductor substrate 20, the output buffer circuit 12 is disposed between the contact pad 39 and the contact pad 38. Specifically, at least a portion of the output buffer circuit 12 is disposed between the contact pad 39 and the contact pad 38.

In this way, heat generated in the output buffer circuit 12 is dissipated to the outside from the external connection terminal 92 via the contact pad 39, and also from the external connection terminal 91 via the contact pad 38. In other words, heat generated in the output buffer circuit 12 is dissipated through two heat conduction paths via the two contact pads 39 and 38, making it even easier for the heat generated in the output buffer circuit 12 to be dissipated. Therefore, deterioration of the oscillation characteristics of the vibration device 1 caused by heat generated in the output buffer circuit 12 can be more effectively suppressed.

A temperature compensation circuit 15 that performs temperature compensation for the oscillation signal OSC is disposed on the second surface 22 of the semiconductor substrate 20 between the output buffer circuit 12 and the through electrodes 40, 41. For example, at least a part of the temperature compensation circuit 15 is disposed within the range of the area connecting the output buffer circuit 12 and the through electrodes 40, 41. For example, if the direction from the output buffer circuit 12 to the through electrodes 40, 41 is designated as DR, the temperature compensation circuit 15 is disposed on the direction DR side of the output buffer circuit 12, and the through electrodes 40, 41 are disposed on the direction DR side of the temperature compensation circuit 15. In addition, a temperature sensor circuit 16 is disposed on the direction DR side of the through electrodes 40, 41.

For example, the temperature compensation circuit 15 is a circuit block that consumes less current than the output buffer circuit 12 and is less likely to generate heat than the output buffer circuit 12. Therefore, by arranging such a temperature compensation circuit 15 between the output buffer circuit 12 and the through electrodes 40, 41, the heat generated by the output buffer circuit 12 is less likely to be transmitted to the vibration element 5 via the through electrodes 40, 41, and deterioration of the oscillation characteristics of the vibration device 1 caused by heat generated by the output buffer circuit 12 can be suppressed. In addition, since each circuit block of the integrated circuit 10 can be efficiently arranged within the limited layout area of the integrated circuit 10, it is possible to reduce the layout area of the integrated circuit 10.

In addition, while the output buffer circuit 12 is arranged along side SD3 in FIG. 12, the output buffer circuit 12 may be arranged along side SD2 as shown in FIG. 13. For example, the output buffer circuit 12 is arranged so that the long side of the output buffer circuit 12 is along side SD2. As shown in FIG. 13, a logic circuit 13 is arranged between the output buffer circuit 12 and the through electrodes 40 and 41 on the second surface 22 of the semiconductor substrate 20. For example, the logic circuit 13, which is a control circuit that performs various controls in the integrated circuit 10, is arranged between the output buffer circuit 12 and the through electrodes 40 and 41. Note that, as in FIG. 12, the temperature compensation circuit 15 is arranged between the output buffer circuit 12 and the through electrodes 40 and 41 in FIG. 13 as well.

For example, the logic circuit 13 is a circuit block that consumes less current than the output buffer circuit 12 and is less likely to generate heat than the output buffer circuit 12. Therefore, by arranging such a logic circuit 13 between the output buffer circuit 12 and the through electrodes 40, 41, the heat generated by the output buffer circuit 12 is less likely to be transmitted to the vibration element 5 via the through electrodes 40, 41, and deterioration of the oscillation characteristics of the vibration device 1 caused by heat generated by the output buffer circuit 12 can be suppressed. In addition, each circuit block of the integrated circuit 10 can be efficiently arranged within the limited layout area of the integrated circuit 10, thereby making it possible to reduce the layout area of the integrated circuit 10.

In this embodiment, the temperature sensor circuit 16 is disposed on the second surface 22 of the semiconductor substrate 20. The through electrodes 40, 41 are disposed between the output buffer circuit 12 and the temperature sensor circuit 16. For example, if the direction from the output buffer circuit 12 to the temperature sensor circuit 16 is designated as DR, the through electrodes 40, 41 are disposed on the direction DR side of the output buffer circuit 12, and the temperature sensor circuit 16 is disposed on the direction DR side of the through electrodes 40, 41. For example, it can be said that the temperature sensor circuit 16, the through electrodes 40, 41, and the output buffer circuit 12 are disposed in this order from side SD1 to side SD2.

For example, when the vibration device 1 is started, when the output buffer circuit 12 generates heat, the time until the vibration element 5 is heated and the effect of the heating appears in the oscillation frequency is longer than the time until the effect of the heat appears in the temperature sensor circuit 16. Therefore, by arranging the output buffer circuit 12, the through electrodes 40, 41, and the temperature sensor circuit 16 so that the through electrodes 40, 41 are arranged between the output buffer circuit 12 and the temperature sensor circuit 16, the vibration element 5 electrically connected to the through electrodes 40, 41 is more susceptible to the effect of the heat generated by the output buffer circuit 12 than the temperature sensor circuit 16. For example, the heat generated by the output buffer circuit 12 is transmitted to the vibration element 5 through the through electrodes 40, 41, and then transmitted to the temperature sensor circuit 16. This allows the detected temperature of the temperature sensor circuit 16 to approach the actual temperature of the vibration element 5, and makes it possible to suppress the occurrence of deterioration of the oscillation characteristics caused by the error between the detected temperature in the temperature sensor circuit 16 and the actual temperature of the vibration element 5.

12 and 13, the direction from side SD1 to side SD2 is the first direction, and the direction from side SD3 to side SD4 is the second direction. The first direction is along the X-axis, and the second direction is along the Y-axis. The opposite direction to the first direction is the third direction, and the opposite direction to the second direction is the fourth direction. At this time, the oscillator circuit 11 is arranged on the first direction side of the side SD1, and the through electrodes 40 and 41 are arranged on the first direction side of the oscillator circuit 11. The temperature sensor circuit 16 is arranged on the second direction side of the oscillator circuit 11. The output buffer circuit 12, logic circuit 13, power supply circuit 14, temperature compensation circuit 15, and memory 17 are arranged on the first direction side of the through electrodes 40 and 41. That is, the output buffer circuit 12, logic circuit 13, power supply circuit 14, temperature compensation circuit 15, and memory 17 are arranged in the area between the through electrodes 40 and 41 and the side SD2. In FIG. 12, the temperature compensation circuit 15 is arranged on the second direction side of the output buffer circuit 12, the logic circuit 13 and the power supply circuit 14 are arranged on the second direction side of the temperature compensation circuit 15, and the memory 17 is arranged on the second direction side of the logic circuit 13. On the other hand, in FIG. 13, the logic circuit 13 and the temperature compensation circuit 15 are arranged on the third direction side of the output buffer circuit 12. The power supply circuit 14 is arranged on the third direction side of the logic circuit 13, and the memory 17 is arranged on the second direction side of the logic circuit 13. The third direction is the opposite direction to the first direction, and is the direction from side SD2 toward side SD1.

1 and 2, the joining member 60 includes a bump 62 whose one end is electrically connected to the vibration element 5 and whose other end is electrically connected to the through electrode 40. The joining member 61 also includes a bump (not shown) similar to the bump 62, but its description is omitted here. For example, in FIG. 1 and FIG. 2, the other end of the bump 62 is electrically connected to the through electrode 40 via a terminal 64. As the bump 62, for example, a metal bump such as a gold bump, a silver bump, a copper bump, or a solder bump can be used. By using such a bump 62 such as a metal bump as the joining member 60, the heat generated in the output buffer circuit 12 is easily transmitted from the through electrode 40, etc., through the bump 62, etc. to the vibration element 5. Then, the actual temperature of the vibration element 5 caused by the heat generated by the output buffer circuit 12 can be detected with a small error using the temperature sensor circuit 16.

In this embodiment, as shown in FIG. 1, the vibration device 1 includes a lid 7 that is joined to the base 2 so as to house the vibration element 5. For example, the lid 7 is joined to the base 2 by joining members 71 and 72. By providing such a lid 7, the vibration element 5 can be arranged in a housing space SP that is formed by joining the base 2 and the lid 7. For example, the vibration element 5 can be arranged in a hermetically sealed housing space SP, which makes it possible to suitably protect the vibration element 5 and the like from impact, dust, heat, moisture, and the like.

Here, the lid 7 can be realized by a silicon substrate, like the base 2. This makes the linear expansion coefficients of the base 2 and the lid 7 equal, suppressing the occurrence of thermal stress caused by thermal expansion, and realizing a vibration device 1 with excellent vibration characteristics. In addition, both the base 2 and the lid 7 can be formed by a semiconductor manufacturing process. Therefore, it is possible to manufacture the vibration device 1 with high precision and to reduce its size. However, the lid 7 is not limited to a silicon substrate, and may be realized by a semiconductor substrate such as Ge, GaP, GaAs, or InP.

The vibration device 1 may be configured not to include the lid 7 joined to the base 2. For example, the base 2 in which the vibration element 5 is arranged on the first surface 21 and the integrated circuit 10 is formed on the second surface 22 may be housed in a separate package or in a container that serves as a thermostatic bath in an oven-controlled crystal oscillator (OCXO).

In addition, in this embodiment, the distance between the temperature sensor circuit 16 and the through electrode 41 is smaller than the distance between the output buffer circuit 12 and the through electrode 41, and the temperature sensor circuit 16 is disposed closer to the through electrode 41 than the output buffer circuit 12.

For example, in a conventional temperature-compensated oscillator in which a vibration element is housed in a first recess of a ceramic package and an IC chip is housed in a second recess, heat generated in the output buffer circuit of the IC chip is not easily transmitted to the vibration element. That is, the vibration element is not directly fixed to the IC chip, and the IC chip and the vibration element are only electrically connected by internal wiring of the package, etc., so that heat generated in the output buffer circuit of the IC chip is not easily transmitted to the vibration element through the internal wiring path. In addition, since ceramic, which has a lower thermal conductivity than the semiconductor substrate, is interposed between the vibration element housed in the first recess of the ceramic package and the IC chip housed in the second recess, radiant heat from the IC chip is also not easily transmitted to the vibration element. On the other hand, since the temperature sensor circuit is formed in the same IC chip as the output buffer circuit, heat generated in the output buffer circuit is immediately transmitted to the temperature sensor circuit. Therefore, an error occurs between the temperature detected by the temperature sensor circuit and the actual temperature of the vibration element, and this error causes deterioration of oscillation characteristics such as the oscillation frequency. For example, when the oscillator starts up, the heat generated in the output buffer circuit is immediately transmitted to the temperature sensor circuit in the same IC chip, causing the temperature detected by the temperature sensor circuit to rise immediately. However, because the heat generated in the output buffer circuit is not easily transmitted to the vibration element, the actual temperature of the vibration element does not rise immediately. This causes an error to occur between the temperature detected by the temperature sensor circuit and the actual temperature of the vibration element, resulting in a deterioration of the oscillation characteristics.

In contrast, in this embodiment, the vibration element 5 is fixed to the semiconductor substrate 20 via conductive bonding members 60 and 61, and the distance between the temperature sensor circuit 16 and the through electrode 41 is smaller than the distance between the output buffer circuit 12 and the through electrode 41. In this manner, in this embodiment, the vibration element 5 is directly fixed to the semiconductor substrate 20 via the bonding members 60 and 61, so that heat generated in the output buffer circuit 12 is more easily transmitted to the vibration element 5 than in a conventional oscillator using a ceramic package. That is, in the WLP vibration device 1 of this embodiment, heat generated in the output buffer circuit 12 of the integrated circuit 10 is more easily transmitted to the vibration element 5, and the temperature of the vibration element 5 also rises in a short time due to the heat generated in the output buffer circuit 12. In addition, since there is no ceramic with low thermal conductivity between the output buffer circuit 12 and the vibration element 5, heat generated in the output buffer circuit 12 is more easily transmitted to the vibration element 5 as radiant heat. On the other hand, since the distance between the temperature sensor circuit 16 and the through electrode 41 is small, the temperature sensor circuit 16 can detect the actual temperature of the vibration element 5, which has risen due to heat generation in the output buffer circuit 12, in a short time. That is, the actual temperature of the vibration element 5 is transmitted to the integrated circuit 10 through the through electrode 41, which has a high thermal conductivity, and the temperature sensor circuit 16, which is arranged at a short distance from the through electrode 41, can detect this actual temperature in a short time. For example, when the vibration device 1 is started, the heat generated in the output buffer circuit 12 is transmitted to the vibration element 5 in a short time through the thermal conduction path, so that the actual temperature of the vibration element 5 increases, and the actual temperature of the vibration element 5 is detected by the temperature sensor circuit 16, which is arranged near the through electrode 41, via the through electrode 41. The temperature compensation circuit 15 performs a temperature compensation process based on the detected temperature of the temperature sensor circuit 16, so that temperature compensation of an appropriate oscillation frequency according to the actual temperature of the vibration element 5 is performed. Therefore, it is possible to effectively suppress the occurrence of deterioration of the oscillation characteristics caused by an error between the detected temperature in the temperature sensor circuit 16 and the actual temperature of the vibration element 5.

The temperature sensor circuit 16 is also arranged closer to the side SD1 than the through electrodes 40 and 41. For example, the oscillator circuit 11 is also arranged closer to the side SD1 than the through electrodes 40 and 41, and the temperature sensor circuit 16 and the oscillator circuit 11 are arranged along the side SD1. Specifically, the temperature sensor circuit 16 is arranged at the corner where the side SD1 and the side SD4 intersect. For example, the temperature sensor circuit 16 and the through electrodes 40 and 41 are arranged in a first region, which is, for example, a region between the side SD1 and the center line CL. On the other hand, the output buffer circuit 12 is arranged in a second region, which is a region between the side SD2 and the center line CL. And the temperature sensor circuit 16 is arranged in a position closer to the side SD1 than the through electrodes 40 and 41 in the first region between the side SD1 and the center line CL. In this way, it is possible to effectively use the region between the side SD1 and the through electrodes 40 and 41 and arrange the temperature sensor circuit 16 closer to the through electrodes 41, etc. This allows for an efficient layout of the temperature sensor circuit 16, etc., and by arranging the temperature sensor circuit 16, for example, near the through electrode 41, it is possible to suppress the occurrence of deterioration of the oscillation characteristics caused by an error between the temperature detected by the temperature sensor circuit 16 and the actual temperature of the vibration element 5.

In addition, in the vibration device 1 of this embodiment, as shown in Figures 1, 2, 9, etc., the through electrodes 40, 41 and the external connection terminal 91 are arranged so as not to overlap in a planar view from a direction perpendicular to the first surface 21. For example, the through electrodes 40, 41 electrically connecting the vibration element 5 and the integrated circuit 10 and the external connection terminal 91 from which the clock signal CK is output are arranged so as not to overlap in a planar view from the Z-axis direction. Thus, in this embodiment, in a WLP (Wafer Level Package) vibration device 1 including an integrated circuit 10 having an oscillation circuit 11 and an output buffer circuit 12 and a vibration element 5, the through electrodes 40, 41 electrically connecting the vibration element 5 and the oscillation circuit 11 of the integrated circuit 10 and the external connection terminal 91 for outputting the clock signal CK are arranged so as not to overlap in a planar view. That is, the through electrodes 40, 41, which are part of the wiring electrically connected to the vibration element 5, and the external connection terminal through which an AC signal flows, such as the external connection terminal 91 for outputting the clock signal CK based on the oscillation signal OSC, are arranged so as not to overlap in a plan view, thereby reducing the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91.

For example, in this embodiment, unlike the conventional ceramic package, the vibration element 5 is directly mounted on the semiconductor substrate 20 to form the vibration device 1, which causes the following unique problems. In the WLP package of the small vibration device 1, the integrated circuit 10 is formed on the second surface 22, which is the lower surface of the semiconductor substrate 20 that constitutes a part of the airtight package, and the through electrodes 40, 41, which are called conductive vias or through holes and are electrically connected to the vibration element 5, are formed on the semiconductor substrate 20. The through electrodes 40, 41 to which the vibration element 5 is electrically connected will have a negative effect on the oscillation characteristics such as the oscillation frequency if the terminals or electrodes of the AC signal, which is an alternating current signal, are placed nearby and capacitively coupled. Then, on the second surface 22 side of the semiconductor substrate 20 such as a silicon substrate, a thin insulating layer 80 formed of a resin layer such as polyimide is formed, and further, for example, four external connection terminals 91 to 94 are formed on the lower surface of the insulating layer 80. Here, the thickness of the insulating layer 80 is thinner than that of the semiconductor substrate 20, for example, 0.1 mm or less. As shown in FIG. 2, a thin insulating layer 44 is also formed around the through electrodes 40 and 41. Unlike conventional ceramic packages, a semiconductor substrate 20 that can be a dielectric or a conductor is interposed between the through electrodes 40 and 41 and the external connection terminals 91 to 94. For this reason, if the through electrodes 40 and 41 and the external connection terminal 91 for outputting the clock signal CK, which is an AC signal, are arranged to overlap each other in a plan view, the capacitance coupling becomes large because they are arranged through the thin insulating layers 80 and 44, etc., and this adversely affects the oscillation characteristics. That is, since the capacitance value is inversely proportional to the distance between the electrodes, the capacitance due to the thin insulating layers 80 and 44 becomes large. If the capacitance of the capacitive coupling between the through electrodes 40 and 41 and the external connection terminal 91 becomes large, the signal component of the clock signal CK at the external connection terminal 91 is transmitted as noise to the vibration element 5 or the oscillation circuit 11 through the through electrodes 40 and 41, causing problems such as deterioration of the oscillation characteristics.

In this embodiment, as shown in FIG. 9 etc., the through electrodes 40, 41 electrically connected to the vibration element 5 and the external connection terminal 91 to which the clock signal CK, which is an AC signal, are arranged so as not to overlap in a planar view. By arranging the through electrodes 40, 41 and the external connection terminal 91 so as not to overlap in a planar view in this manner, it is possible to increase the distance between the through electrodes 40, 41 and the external connection terminal 91 compared to when the through electrodes 40, 41 and the external connection terminal 91 are arranged so as to overlap in a planar view. This makes it possible to reduce the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91, and effectively suppress situations such as deterioration of the oscillation characteristics of the vibration element 5.

The external connection terminals 91 to 94 of the vibration device 1 are mounted by connecting them to terminals or wiring of a circuit board or the like on which the vibration device 1 is mounted, for example by soldering. Therefore, it is desirable for the external connection terminals 91 to 94 to be terminals suitable for mounting, for example by soldering, and they are also required to have heat resistance and strength so as not to be damaged during mounting.

In this regard, a method is considered in which the pads of an integrated circuit are used as external connection terminals. For example, pads formed in the top metal layer of a wiring layer are used as external connection terminals. However, integrated circuit pads are not suitable terminals for mounting such as soldering, and because they have a small area and low heat resistance and strength, there is a risk of problems such as breakage during mounting.

In contrast, in the resonator device 1 of this embodiment, external connection terminals 91-94 are provided on the second surface 22 side of the semiconductor substrate 20 via an insulating layer 80. That is, instead of the contact pads 38, 39, 68, and 69 of the integrated circuit 10, the external connection terminals 91-94 are provided separately from these pads, and are formed, for example, in the manufacturing process of the relocation wiring layer 8. Therefore, it becomes possible to use terminals suitable for mounting by soldering or the like as the external connection terminals 91-94. For example, the external connection terminals 91-94 can be made larger in area than the contact pads 38, 39, 68, and 69, and can be made thicker to maintain strength. Therefore, the external connection terminals 91-94 can be easily connected to external terminals and wiring for mounting, and the occurrence of damage during mounting can be suppressed.

On the other hand, if the external connection terminals 91 to 94 are large in area, there is a risk that the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91 will become large. In this regard, in this embodiment, the through electrodes 40, 41 and the external connection terminal 91 are arranged so that they do not overlap in a planar view, so that even if the external connection terminal 91 is large in area, the deterioration of the oscillation characteristics caused by the capacitive coupling can be suppressed. Therefore, according to this embodiment, it is possible to provide the external connection terminals 91 to 94 that are easy to implement by connecting to external terminals and wiring, have high heat resistance and strength, and are not easily damaged, while simultaneously suppressing the deterioration of the oscillation characteristics caused by the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91.

3. Modifications Next, various modifications of this embodiment will be described. For example, FIG. 14 shows another example of the through electrode 40. The through electrode 41 is similar, so its description will be omitted. In FIG. 14, an insulating layer 44 is formed on the inner wall of the through hole of the base 2, and a resin layer 45 is formed further inside the insulating layer 44. The through electrode 40 is formed by a metal layer formed inside the resin layer 45. Such a through electrode 40 allows the vibration element 5 and the oscillation circuit 11 of the integrated circuit 10 to be electrically connected. That is, the vibration element 5 and the contact pad 36 of the integrated circuit 10 are electrically connected by the bonding member 60 composed of the bump 62 and the through electrode 40, and the contact pad 36 is electrically connected to the oscillation circuit 11 as the terminals TXA and TXB in FIG. 4 and FIG. 5, so that the vibration element 5 and the oscillation circuit 11 are electrically connected.

The output buffer circuit 12 may also output differential clock signals CK and CKX to the outside in a signal format such as LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed Current Steering Logic), or differential CMOS (Complementary MOS). That is, the output buffer circuit 12 may have an output driver for LVDS, PECL, HCSL, or differential CMOS. For example, FIG. 15 is a configuration example of an output driver for LVDS. This output driver has a P-type transistor for a current source that flows a drive current of 3.5 mA, P-type and N-type transistors that constitute a differential section that receives differential input signals IN and INX and outputs differential clock signals CK and CKX, and an N-type transistor provided on the VSS side. A bias voltage BSP is applied to the gate of the P-type transistor that serves as a current source. This causes a drive current of 3.5 mA to flow. Figure 16 shows an example of the configuration of an output driver for PECL. This output driver has a P-type transistor that passes a drive current of 15.25 mA, two P-type transistors that form a differential section, and two P-type transistors that form a bias current circuit that passes a bias current of 5.7 mA to the nodes of the clock signals CK and CKX.

Figure 17 is an example of an external connection terminal arrangement when outputting differential clock signals CK and CKX as in Figures 15 and 16. In Figure 17, the vibration device 1 has six external connection terminals, namely external connection terminals 91a, 91b, 92, 93, 94, and 95. The external connection terminals 91a and 91b are terminals from which the differential clock signals CK and CKX are output. The external connection terminals 92 and 93 are terminals for VDD and GND, and the external connection terminal 94 is a terminal for the output enable signal OE. The external connection terminal 95 is an NC (Non Connection) terminal. The external connection terminals 91a, 91b, 92, 93, 94, and 95 in Figure 17 are also provided on the second surface 22 side of the semiconductor substrate 20 of the base 2 in the vibration device 1 via an insulating layer 80. The through electrodes 40, 41 and the external connection terminals 91a, 91b for outputting the differential clock signals CK, CKX are arranged so as not to overlap in a plan view.

As described above, the vibration device of this embodiment includes a semiconductor substrate having a first surface and a second surface that is opposite to the first surface, a base including a through electrode that penetrates between the first surface and the second surface, a vibration element fixed to the first surface via a conductive bonding member, and a first external connection terminal provided on the second surface side via an insulating layer. Also, on the second surface, an oscillation circuit that is electrically connected to the vibration element via the through electrode and that oscillates the vibration element to generate an oscillation signal, an output buffer circuit that outputs a clock signal based on the oscillation signal, and a first contact pad that is electrically connected to the first external connection terminal are arranged. Then, when the distance between the output buffer circuit and the through electrode is Dbx and the distance between the output buffer circuit and the first contact pad is Dbc, Dbc < Dbx.

Thus, the vibration device of this embodiment includes a semiconductor substrate, a base having a through electrode penetrating the semiconductor substrate, a vibration element fixed to the first surface side of the semiconductor substrate via a conductive fixing member, and a first external connection terminal provided on the second surface side via an insulating layer. In addition, a first contact pad connected to the oscillation circuit, the output buffer circuit, and the first external connection terminal is arranged on the second surface of the semiconductor substrate. When the distance between the output buffer circuit and the through electrode is Dbx and the distance between the output buffer circuit and the first contact pad is Dbc, the relationship Dbc<Dbx holds. In this way, in the vibration device of this embodiment, the vibration element is fixed to the semiconductor substrate via a bonding member, so that heat generated in the output buffer circuit is easily transmitted to the vibration element. On the other hand, since the distance Dbc between the output buffer circuit and the first contact pad is small, heat generated in the output buffer circuit is easily dissipated from the first contact pad to the outside of the vibration device via the first external connection terminal connected to the first contact pad. Therefore, it is possible to effectively suppress deterioration of the oscillation characteristics of the vibration device caused by heat generated in the output buffer circuit.

In this embodiment, the base may have a first side and a second side opposite the first side, and the through electrode, the first contact pad, and the output buffer circuit may be arranged in this order from the first side to the second side.

By arranging them in this manner, heat generated in the output buffer circuit is more easily dissipated from the first contact pad via the first external connection terminal to the outside of the vibration device before being transferred to the vibration element via the through electrode, thereby suppressing deterioration of the oscillation characteristics.

In this embodiment, the first contact pad may also be a power supply contact pad to which a power supply voltage is supplied.

In this way, heat generated in the output buffer circuit is dissipated to the outside from the first contact pad via the first external connection terminal for the power supply, which has a large thermal capacity, and deterioration of the oscillation characteristics can be suppressed.

In this embodiment, the base may have a first side and a second side opposite the first side, and the through electrode, the output buffer circuit, and the first contact pad may be arranged in this order from the first side to the second side.

By arranging them in this manner, heat generated in the output buffer circuit is more easily dissipated from the first contact pad via the first external connection terminal to the outside of the vibration device before being transferred to the vibration element via the through electrode, thereby suppressing deterioration of the oscillation characteristics.

In this embodiment, the first contact pad may be a contact pad for outputting a clock signal.

In this way, heat generated in the output buffer circuit is dissipated to the outside from the first contact pad via the external connection terminal for clock signal output, making it possible to suppress deterioration of the oscillation characteristics.

In this embodiment, the second surface may include a second external connection terminal provided via an insulating layer. A second contact pad electrically connected to the second external connection terminal is disposed on the second surface, and when the distance between the output buffer circuit and the first contact pad is Dbc1 and the distance between the output buffer circuit and the second contact pad is Dbc2, Dbc1 < Dbx and Dbc2 < Dbx may be satisfied. In a plan view from a direction perpendicular to the first surface, an output buffer circuit may be disposed between the first contact pad and the second contact pad.

In this way, heat generated in the output buffer circuit is dissipated to the outside from the first external connection terminal via the first contact pad, and also from the second external connection terminal via the second contact pad. Therefore, heat generated in the output buffer circuit is dissipated through two heat conduction paths, making it possible to more effectively suppress deterioration of oscillation characteristics.

In this embodiment, a temperature compensation circuit that performs temperature compensation for the oscillation signal may also be disposed on the second surface between the output buffer circuit and the through electrode.

In this way, by placing a temperature compensation circuit, which generates less heat than the output buffer circuit, between the output buffer circuit and the through electrode, heat from the output buffer circuit is less likely to be transmitted to the vibration element via the through electrode, making it possible to suppress deterioration of the oscillation characteristics.

In this embodiment, a logic circuit may also be arranged on the second surface between the output buffer circuit and the through electrode.

In this way, by placing the logic circuit, which generates less heat than the output buffer circuit, between the output buffer circuit and the through electrode, heat from the output buffer circuit is less likely to be transmitted to the vibration element via the through electrode, making it possible to suppress deterioration of the oscillation characteristics.

In this embodiment, a temperature sensor circuit may be arranged on the second surface, and the through electrode may be arranged between the output buffer circuit and the temperature sensor circuit.

In this way, heat generated in the output buffer circuit is transferred to the vibration element via the through electrode, and then to the temperature sensor circuit. This makes it possible to suppress deterioration of the oscillation characteristics caused by an error between the temperature detected by the temperature sensor circuit and the actual temperature of the vibration element.

In this embodiment, the joining member may also include a bump having one end electrically connected to the vibration element and the other end electrically connected to the through electrode.

By using the bumps as a joining material in this way, heat generated in the output buffer circuit is easily transferred from the through electrode via the bump to the vibration element, making it possible to detect the actual temperature of the vibration element caused by heat generated by the output buffer circuit with little error.

This embodiment may also include a lid that is joined to the base to house the vibration element.

In this way, the vibration element can be placed in the storage space formed by the base and the lid, making it possible to effectively protect the vibration element from impacts, dust, heat, moisture, etc.

Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or similar meaning may be replaced with that different term anywhere in the specification or drawings. All combinations of the present embodiment and modifications are also included in the scope of the present disclosure. The configuration and operation of the vibration device are not limited to those described in the present embodiment, and various modifications are possible.

1...Vibration device, 2...Base, 5...Vibration element, 7...Lid, 8...Rearrangement wiring layer, 10...Integrated circuit, 11...Oscillation circuit, 12...Output buffer circuit, 13...Logic circuit, 14...Power supply circuit, 15...Temperature compensation circuit, 16...Temperature sensor circuit, 17...Memory, 20...Semiconductor substrate, 21...First surface, 22...Second surface, 23, 24...Transistor, 25...Element isolation film, 30...Wiring layer, 31, 32...Metal layer, 33, 34, 35...Insulating layer, 36, 37, 38, 39...contact pads, 40, 41...through electrodes, 44...insulating layer, 45...resin layer, 50...vibration substrate, 52, 53...excitation electrodes, 54, 55...wiring, 56, 57...terminals, 60, 61...bonding members, 62...bumps, 64...terminals, 68, 69...contact pads, 71, 72...bonding members, 80...insulating layer, 82...wiring, 91, 91a, 91b, 92, 93, 94, 95...external connection terminals, 101...first metal layer, 102...second metal layer,
CK, CKX...clock signal, CL...center line, CV1, CV2...variable capacitance circuit, DV1, DV2...inverter circuit, IV1, IV2, IV3...inverter circuit, LA, LB...wiring, NA...NAND circuit, OE...output enable signal, OSC...oscillation signal, SD1, SD2, SD3, SD4...side, SP...accommodating space, TCK, TGND, TOE, TVC, TVDD, TXA, TXB...terminal, Dbx1, Dbx2, Dbx, Dbc1, Dbc2, Dbc...distance

Claims (10)

a semiconductor substrate having a first surface and a second surface opposite to the first surface; and a base including a through electrode extending between the first surface and the second surface;
a vibration element fixed to the first surface via a conductive bonding member;
a first external connection terminal provided on the second surface side via an insulating layer;
Including,
The second surface has
an oscillation circuit electrically connected to the vibration element via the through electrode and configured to oscillate the vibration element to generate an oscillation signal;
an output buffer circuit that outputs a clock signal based on the oscillation signal;
a first contact pad electrically connected to the first external connection terminal;
a logic circuit between the output buffer circuit and the through electrode;
is placed,
When the distance between the output buffer circuit and the through electrode is Dbx and the distance between the output buffer circuit and the first contact pad is Dbc,
A vibration device, characterized in that Dbc<Dbx. 2. The vibrating device according to claim 1,
The base is
A first side and a second side opposite to the first side,
A vibration device, characterized in that the through electrode, the first contact pad, and the output buffer circuit are arranged in this order from the first side to the second side. The vibration device according to claim 2 ,
A vibration device, wherein the first contact pad is a power supply contact pad to which a power supply voltage is supplied. 2. The vibrating device according to claim 1,
The base is
A first side and a second side opposite to the first side,
A vibrating device, characterized in that the through electrode, the output buffer circuit, and the first contact pad are arranged in this order from the first side to the second side. The vibration device according to claim 4 ,
A vibrating device, characterized in that the first contact pad is a contact pad for outputting a clock signal through which the clock signal is output. The vibration device according to claim 1 ,
a second external connection terminal provided on the second surface side via the insulating layer;
The second surface has
a second contact pad is disposed to be electrically connected to the second external connection terminal;
When the distance between the output buffer circuit and the first contact pad is Dbc1 and the distance between the output buffer circuit and the second contact pad is Dbc2,
Dbc1<Dbx and Dbc2<Dbx,
A vibrating device characterized in that, when viewed in a planar view from a direction perpendicular to the first surface, the output buffer circuit is disposed between the first contact pad and the second contact pad. The vibration device according to claim 1 ,
The second surface has
A resonator device, comprising: a temperature compensation circuit that performs temperature compensation for the oscillation signal, disposed between the output buffer circuit and the through electrode. The vibration device according to claim 1 ,
The second surface has
A temperature sensor circuit is provided,
The through electrode is
A vibration device, characterized in that it is disposed between the output buffer circuit and the temperature sensor circuit. 9. The vibration device according to claim 1,
The joining member is
A vibration device comprising a bump having one end electrically connected to the vibration element and the other end electrically connected to the through electrode. 10. The vibration device according to claim 1 ,
A vibration device comprising a lid joined to the base so as to house the vibration element.

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