JP7565561B2 - DETECTION DEVICE, LEARNING DEVICE, DETECTION METHOD, AND DETECTION PROGRAM - Google Patents

Description

The present invention relates to an apparatus, method, and program for detecting circuits that are operating improperly using machine learning in circuit design information.

Traditionally, hardware design and manufacturing processes have become globalized, and competition has led to greater efficiency and lower costs, while circuits have become larger and more complex. Against this background, some design and manufacturing processes are sometimes outsourced to third parties. It has been pointed out that the involvement of third parties poses the risk of inserting circuits (hardware Trojans) that realize unintended unauthorized functions at the design stage.

In most cases, hardware Trojans consist of a trigger circuit that determines the operating conditions of the malicious function, and a payload circuit that realizes the malicious function itself. The trigger circuit determines whether an external input, the value of an internal signal line, or the internal state of the circuit meets a certain condition. The payload circuit causes a decrease in the performance of a normal circuit, such as leaking internal information of the circuit, modifying or stopping normal functions, or increasing power consumption.
From such characteristics of the trigger circuit and the payload circuit, characteristics specific to hardware Trojans in circuit design information described at the gate level are shown (for example, see Non-Patent Document 1).

A representative technique for detecting hardware Trojans based on these features is to extract features such as the number of stages to the nearest primary output port or flip-flop from a netlist, which is information that describes the connections of circuit elements (e.g., logic gates, flip-flops, multiplexers, etc.) at the gate level, and then learn and identify these features using a machine learning algorithm (see, for example, Non-Patent Document 2).
The method of Non-Patent Document 2 consists of learning and identification procedures. In the learning procedure, feature values corresponding to signal lines (nets) included in a netlist are extracted, and a machine learning algorithm is used to train whether the net is a Trojan net that constitutes a hardware Trojan or a normal circuit (normal net). In the identification procedure, feature values of each net included in a netlist that is the target of hardware Trojan detection are used to identify whether it is a Trojan net or a normal net.

M. Oya, Y. Shi, M. Yanagisawa, and N. Togawa, "A score-based classification method for identifying Hardware-Trojans at gate-level netlists," Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 465-470, 2015. K. Hasegawa, M. Yanagisawa, and N. Togawa, "Hardware Trojans classification for gate-level netlists using multi-layer neural networks," Proceedings of the 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) , pp. 227-232, 2017.

In hardware Trojan detection, feature design and optimization are very important for improving detection accuracy.
However, in conventional machine learning-based hardware Trojan detection methods, it was necessary to predetermine effective features and extract them from circuit design information. Therefore, when designing the features, specialized knowledge about hardware design and the properties of hardware Trojans was required. Furthermore, when the circuit design information used as training data changed significantly or when learning and detection were attempted for unknown malicious circuits, it was necessary to redesign new appropriate features.

Furthermore, if an attacker has intimate knowledge of the features, he or she may be able to design a fraudulent circuit that extracts features that are indistinguishable from normal circuits.
As described above, conventional methods have had issues with feature design that prevent hardware Trojan detection technology from being widely used.

The present invention aims to provide a detection device, a detection method, and a detection program that can automatically extract useful features without predefining them and detect hardware Trojans.

The detection device according to the present invention includes a graph acquisition unit that acquires a graph from circuit design information described at the gate level, in which circuit elements are nodes and signal lines connected to the circuit elements are edges; an attribute acquisition unit that assigns to each of the nodes a vector indicating the attribute of the node obtained from the circuit design information as an initial value of the feature of the node; a feature update unit that updates the feature of the node by a node embedding process based on a vector that aggregates the feature of nodes adjacent to each of the nodes; and a determination unit that determines whether each of the circuit elements included in the new circuit design information constitutes a hardware Trojan or not, using a detection model that has learned the labels assigned to the nodes based on the feature of the nodes in the training data.

The feature update unit may repeat updating the features a predetermined number of times while updating an aggregation function that aggregates the features of the adjacent nodes and a weight matrix used when updating the features so as to optimize a loss function based on the distribution of the features in the graph.

The attribute acquisition unit may acquire, as an attribute of the node, a value indicating the type of circuit element corresponding to the node.

The attribute acquisition unit may acquire, as an attribute of the node, a value indicating the type of module that includes a circuit element corresponding to the node in the circuit design information.

The attribute acquisition unit may concatenate a vector that aggregates the attributes of the edges adjacent to the node obtained from the circuit design information to a vector indicating the attributes of the node, and set this as the initial value of the feature of the node.

The attribute acquisition unit may acquire, as an attribute of the edge, a value indicating the type of signal line corresponding to the edge.

The learning device of the present invention learns the detection model used by the detection device based on the feature quantities of the nodes in the training data.

The detection method according to the present invention includes a graph acquisition step of acquiring a graph from circuit design information described at the gate level, in which circuit elements are nodes and signal lines connected to the circuit elements are edges; an attribute acquisition step of assigning to each of the nodes a vector indicating the attribute of the node obtained from the circuit design information as an initial value of the feature of the node; a feature update step of updating the feature of the node by a node embedding process based on a vector that aggregates the feature of nodes adjacent to each of the nodes; and a determination step of determining whether each of the circuit elements included in the new circuit design information constitutes a hardware Trojan or not, using a detection model that has learned the labels assigned to the nodes based on the feature of the nodes in the training data.

The detection program of the present invention is for causing a computer to function as the detection device.

The present invention makes it possible to automatically extract useful features without predefining them and detect hardware Trojans.

FIG. 2 is a diagram illustrating a functional configuration of a detection device according to an embodiment. FIG. 2 is a diagram illustrating an example of a circuit to be subjected to detection of a hardware Trojan in the embodiment. FIG. 10 is a diagram illustrating a graph representation converted from a circuit diagram in an embodiment. 11 is a flowchart illustrating a procedure for node embedding processing by graph learning according to an embodiment. 10 is a flowchart illustrating a process of a learning phase of a detection model in an embodiment. 10 is a flowchart illustrating a detection phase process using a detection model in an embodiment.

An example of an embodiment of the present invention will now be described.
The detection device of this embodiment applies a node embedding technique in graph learning to circuit design information to automatically extract features of circuit elements useful for detecting hardware Trojans from the circuit design information. The detection device uses these features to train a detection model and detects hardware Trojans using the trained detection model.

FIG. 1 is a diagram showing the functional configuration of a detection device 1 according to the present embodiment.
The detection device 1 is an information processing device (computer) including a control unit 10, a storage unit 20, various input/output devices, communication devices, and the like.

The control unit 10 is a part that controls the entire detection device 1, and realizes each function in this embodiment by appropriately reading and executing various programs stored in the memory unit 20. The control unit 10 may be a CPU.

The storage unit 20 is a storage area for various programs for causing the hardware group to function as the detection device 1, various data, and the like, and may be a ROM, a RAM, a flash memory, a hard disk drive (HDD), or the like.
Specifically, the memory unit 20 stores a program (detection program) for causing the control unit 10 to execute each function of this embodiment, as well as a detection model for hardware Trojans, training data for learning the detection model, and the like.

The control unit 10 includes a graph acquisition unit 11, an attribute acquisition unit 12, a feature update unit 13, a learning unit 14, and a judgment unit 15, and these functional units are used to learn the detection model and detect hardware Trojans.

The graph acquisition unit 11 acquires a graph from the circuit design information described at the gate level, in which circuit elements are nodes and signal lines connected to the circuit elements are edges.

The attribute acquiring unit 12 assigns, to each node in the graph, a vector indicating the attribute of the node obtained from the circuit design information as an initial value of the feature amount of the node.
At this time, the attribute acquiring unit 12 acquires, as an attribute of the node, a value indicating the type of the circuit element corresponding to this node. Furthermore, the attribute acquiring unit 12 may acquire, as an attribute of the node, a value indicating the type of the module that includes the circuit element corresponding to this node.

In addition, the attribute acquisition unit 12 may concatenate a vector that aggregates (e.g., averages, sums, etc.) the attributes of edges adjacent to a node obtained from the circuit design information to a vector indicating the attributes of the node, and use this as the initial value of the feature of this node.
At this time, the attribute acquiring unit 12 acquires, as an attribute of the edge, a value indicating the type of the signal line corresponding to this edge.

Specifically, the graph acquisition unit 11 and the attribute acquisition unit 12 obtain a graph representation of the circuit design information as follows:

Let G be a graph corresponding to circuit design information described at the gate level. G is composed of a set V of nodes representing circuit elements (e.g., logic gates, flip-flops, multiplexers, external input/output terminals, etc.) and a set E of edges representing signal lines connecting the circuit elements.

For a node v∈V indicating each circuit element, a vector indicating the attribute of this circuit element is denoted by x _v . x _v is a value indicating the type of the circuit element (e.g., primary input, primary output, logic gate, flip-flop, multiplexer, constant) or the type of module in which the circuit element exists, and is obtained directly from the circuit design information or mechanically by conversion.
In this embodiment, the end points (primary input and primary output) of the circuit are also regarded as circuit elements and are set as nodes of the graph G. Furthermore, a constant refers to a fixed signal of 0 or 1 that is input to a logic gate, for example.

Similarly, for an edge e∈E representing each signal line, a vector indicating the attribute of this signal line is denoted by d _e . d _e is a value indicating the type of signal line (e.g., clock signal, reset signal, other signal line with a special meaning, other general signal line), and is obtained directly from the circuit design information or mechanically by conversion.

For each node v, let l∈L be a label that indicates whether the circuit element corresponding to this node constitutes a hardware Trojan.

FIG. 2 is a diagram showing an example of a circuit to be subjected to detection of hardware Trojans in this embodiment.
In this circuit, three primary inputs a, b, and ci are transformed into two primary outputs s and co by a number of logic gates.
From this circuit diagram, the following graph is obtained, with inputs/outputs and logic gates as nodes and each signal line as an edge.

FIG. 3 is a diagram illustrating a graph representation converted from a circuit diagram in this embodiment.
In this example, a vector having three elements, ie, whether or not it is a primary input, whether or not it is a logic gate, and whether or not it is a primary output, is assigned to each node as the attributes of the node.

For example, the nodes representing the three primary inputs a, b, and ci are each assigned the attribute vector (1, 0, 0), and the nodes representing the two primary outputs s and co are each assigned the attribute vector (0, 0, 1).
Furthermore, the nodes representing the five logic gates are each assigned an attribute vector (0, 1, 0).

The feature update unit 13 updates the features of each node included in the graph by a node embedding process of graph learning based on a vector that aggregates the features of the nodes adjacent to this node.

In graph learning, a set of graphs _DG is used as training data. For each graph G=(V,E) _∈Dtrain in the training data, the feature update unit 13 obtains a feature vector _zv∈Z indicating the feature of each node by using a vector _xv indicating the attribute of each node v∈V.
Here, according to the following literature A, the set Z of feature vectors can be obtained by the following procedure using an aggregation function _fAgg that aggregates (e.g., averages) information from surrounding nodes, a weight matrix W, a concatenation function _fConcat , a set N(v) of nodes adjacent to node v, and a sigmoid function σ.
Document A: William L. Hamilton, Zhitao Ying, Jure Leskovec, "Inductive Representation Learning on Large Graphs", NIPS, pp. 1024-1034, 2017.

Figure 4 is a flowchart showing the steps of node embedding processing using graph learning in this embodiment.

In step S1, the feature updating unit 13 initializes h _v ⁰ by setting the repetition counter k = 0. _{h v} ^k , ∀v∈V indicates the feature vector of each node in the kth trial.
Note that, although h _v ⁰ =x _v and the attribute of the node may be given as the initial value, the attribute of the edge may be linked as described above, and the initial value is not limited to these.

In step S2, the feature update unit 13 increments the counter k by 1 and proceeds to the kth attempt of the following step.

ここで、集約関数ｆ_Ａｇｇは、例えば、平均又は合計といった統計処理が該当し、隣接ノードの数によらず、ベクトルの次元は維持される。 In step S3, the feature updating unit 13 updates the feature vectors for all nodes v∈V by the following calculation.

Here, the aggregation function f _Agg corresponds to a statistical process such as an average or a sum, and the dimension of the vector is maintained regardless of the number of adjacent nodes.

In step S4, the feature amount update unit 13 determines whether or not k = K. If the determination is YES, the process proceeds to step S5, and if the determination is NO, the process returns to step S2.
It should be noted that K is a constant that is set in advance.

In step S5, the feature amount update unit 13 determines a feature vector of each node v, where z _v ←h _v ^K , ∀v∈V.

Here, the feature update unit 13 repeats updating the features a predetermined number of times (K times) while updating the aggregation function _fAgg that aggregates the features of adjacent nodes and the weighting matrix W used when updating the features so as to optimize a loss function based on the distribution of the features in the graph.

なお、近くに存在するノードとは、ノードｖからのホップ数が所定以内のノード、離れた位置に存在するノードとは、ノードｖからのホップ数が所定以上のノードである。 Specifically, if node u is a node near node v, _Pn (v) is a set of nodes that are located away from node v (i.e., negative samples), and Q is the number of negative samples, then the loss function _Jg for optimizing the parameters of the aggregation function _fAgg and the weight matrix W is expressed, for example, as follows (see Document A):

A nearby node is a node that is within a predetermined number of hops from node v, and a distant node is a node that is more than a predetermined number of hops from node v.

In this way, the node embedding process converts the attribute values of each node into a feature vector z that accurately represents the structural characteristics of the circuit, depending on the connection relationships with the surrounding nodes (and edges).

The learning unit 14 learns parameters of the detection model based on the feature amounts of the nodes in the training data and the correct labels assigned to each node.
The detection model f(Z) takes Z as input and outputs a probability L' indicating whether or not each node constitutes a hardware Trojan. The detection model is trained to minimize the error between the output L' and the correct label L by using an algorithm such as a multi-layer perceptron or a random forest.

Figure 5 is a flowchart showing the processing of the learning phase of the detection model in this embodiment.

In step S11, the learning unit 14 acquires training data for learning the detection model.
The training data includes gate-level circuit design information for multiple circuits. The learning unit 14 obtains a set D _train of graphs converted from each circuit design information and a set L of correct labels indicating whether a node v ∈ V in each graph G = (V, E) ∈ D _train constitutes a hardware Trojan.
At this time, the learning unit 14 obtains, from the circuit included in the training data, a vector x which is a set of values indicating the attributes of the circuit elements, and a vector d which is a set of values indicating the attributes of the signal lines.

In step S12, the learning unit 14 obtains a set Z of feature vectors that well represent the characteristics of each circuit element by node embedding processing based on the information obtained in step S11.

In step S13, the learning unit 14 uses the set Z of feature vectors obtained in step S12, associates them with the correct labels obtained in step S11, and learns a detection model using a machine learning algorithm.

The determination unit 15 determines, using the learned detection model, whether or not each of the circuit elements included in the new circuit design information constitutes a hardware Trojan.
Specifically, for example, circuit elements requiring caution are detected by comparing the probability that a circuit element constitutes a hardware Trojan, which is the output of a detection model that uses the features of each node as input, with a predetermined threshold.
When such a circuit element requiring attention is detected in the circuit design information, the circuit design information is analyzed in more detail, either manually or using existing test techniques.

Figure 6 is a flowchart showing the detection phase processing using the detection model in this embodiment.

In step S21, the determination unit 15 acquires test data to be detected. This data includes gate level design information for one or more circuits. The determination unit 15 acquires a set D _test of graphs converted from the respective circuit design information from the graph acquisition unit 11, and acquires attribute vectors x and d of nodes and edges corresponding to the graphs from the attribute acquisition unit 12.

In step S22, the determination unit 15 obtains a set Z of feature vectors that well represent the characteristics of each circuit element from the feature update unit 13, similar to the learning phase.

In step S23, the determination unit 15 uses the detection model learned in the learning phase to determine whether each circuit element corresponding to each vector included in the set Z of feature vectors obtained in step S22 constitutes a hardware Trojan.

According to this embodiment, the detection device 1 expresses the circuit design information described at the gate level as a graph. At this time, the circuit elements are regarded as nodes, the wiring connecting the circuit elements are regarded as edges, and values indicating the attributes of the circuit elements and values indicating the attributes of the wiring are associated with the nodes and edges, respectively. Based on the graph generated in this way, the detection device 1 applies node embedding by graph learning to obtain feature quantities (feature vectors) that well represent the features of each node.
The detection device 1 then uses a machine learning algorithm to learn a detection model based on the feature vectors and ground truth labels obtained from the circuit design information that serves as training data. When detecting hardware Trojans, which are unauthorized circuits, the detection device 1 uses the learned detection model to determine whether a node constitutes a hardware Trojan, based on the feature vectors of each node obtained from the test data in a similar procedure to that for the training data.

The detection device 1 can therefore automatically extract features that are effective for detecting hardware Trojans without having to define them in advance, and use machine learning to detect hardware Trojans that have been mixed in at the circuit design stage. As a result, high detection performance can be expected even for hardware Trojans for which features defined by conventional technology are ineffective. In addition, because the design information for the features is not known to attackers, the risk of circuits being designed to evade detection can be reduced.

The detection device 1 repeats updating the features a predetermined number of times while updating the aggregation function that aggregates the features of adjacent nodes and the weighting matrix used when updating the features so as to optimize a loss function based on the distribution of the features in the graph.
This allows the detection device 1 to appropriately determine features that represent the relationships between nodes in the graph as a whole, for example by making the feature vectors of nearby nodes on the graph similar and by diverging the feature vectors of distant nodes.

The detection device 1 acquires, as attributes of a node, information that can be easily extracted or converted from circuit design information, such as the type of circuit element corresponding to the node, the type of module, etc.
Therefore, the detection device 1 can efficiently determine appropriate feature quantities.

The detection device 1 concatenates a vector that aggregates the attributes of edges adjacent to a node obtained from the circuit design information to a vector indicating the attributes of the node, and sets this as the initial value of the node's features, thereby being able to determine more reliable features that also include signal line information.

The detection device 1 acquires, as an attribute of an edge, information that can be easily extracted or converted from circuit design information, such as the type of signal line corresponding to the edge.
Therefore, the detection device 1 can efficiently determine appropriate feature quantities.

The above-mentioned embodiment can, for example, properly detect the inclusion of hardware Trojans in circuit design information, thereby improving safety in hardware design, and thus contributing to Goal 9 of the United Nations-led Sustainable Development Goals (SDGs) "Build resilient infrastructure, promote sustainable industrialization and foster innovation."

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments. Furthermore, the effects described in the above-described embodiments are merely a list of the most favorable effects resulting from the present invention, and the effects of the present invention are not limited to those described in the embodiments.

The detection method by the detection device 1 is realized by software. When realized by software, the programs that make up this software are installed in an information processing device (computer). These programs may be recorded on removable media such as CD-ROM and distributed to users, or may be distributed by being downloaded to the user's computer via a network. Furthermore, these programs may be provided to the user's computer as a web service via a network without being downloaded.

1. Detection device (learning device)
REFERENCE SIGNS LIST 10 Control unit 11 Graph acquisition unit 12 Attribute acquisition unit 13 Feature amount update unit 14 Learning unit 15 Determination unit 20 Storage unit

Claims (9)

a graph acquisition unit that acquires a graph from the circuit design information described at the gate level, in which circuit elements are nodes and signal lines connected to the circuit elements are edges;
an attribute acquisition unit that assigns, to each of the nodes, a vector indicating an attribute of the node obtained from the circuit design information as an initial value of a feature amount of the node;
a feature updating unit that updates the feature of each of the nodes by a node embedding process based on a vector that aggregates the feature of each of the nodes adjacent to the node;
and a determination unit that determines whether each circuit element included in new circuit design information constitutes a hardware Trojan using a detection model that has learned labels assigned to nodes based on the features of the nodes in training data. The detection device according to claim 1, wherein the feature update unit updates an aggregation function that aggregates the features of the adjacent nodes and a weight matrix used when updating the features to optimize a loss function based on the distribution of the features in the graph, while repeating the update of the features a predetermined number of times. The detection device according to claim 1, wherein the attribute acquisition unit acquires, as an attribute of the node, a value indicating the type of circuit element corresponding to the node. The detection device according to claim 3, wherein the attribute acquisition unit acquires, as an attribute of the node, a value indicating the type of module that includes a circuit element corresponding to the node in the circuit design information. The detection device according to any one of claims 1 to 4, wherein the attribute acquisition unit connects a vector that aggregates the attributes of the edges adjacent to the node obtained from the circuit design information to a vector indicating the attribute of the node, and sets the vector as an initial value of the feature of the node. The detection device according to claim 5, wherein the attribute acquisition unit acquires a value indicating the type of signal line corresponding to the edge as an attribute of the edge. A learning device that learns the detection model used by the detection device according to any one of claims 1 to 6 based on the feature quantities of nodes in the training data. a graph acquisition step of acquiring a graph from the circuit design information described at the gate level, in which circuit elements are nodes and signal lines connected to the circuit elements are edges;
an attribute acquisition step of assigning a vector indicating an attribute of each of the nodes obtained from the circuit design information as an initial value of a feature amount of the node;
a feature updating step of updating the feature of each of the nodes by a node embedding process based on a vector that aggregates the feature of each of the nodes adjacent to the node;
a determination step of determining whether or not each circuit element included in new circuit design information constitutes a hardware Trojan using a detection model that has learned labels assigned to nodes based on the features of the nodes in training data. A detection program for causing a computer to function as a detection device according to any one of claims 1 to 6.

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