JP7554128B2 - Power conversion device and gate signal adjustment method - Google Patents

Description

The present invention relates to a power conversion device and a gate signal adjustment method.

Power conversion devices are used in many fields, including railways, automobiles, and elevators, because they can convert DC power to AC power and also convert AC to DC power in the reverse direction through the switching operation of semiconductor elements. If the upper and lower arm semiconductor elements used in such power conversion devices are turned on at the same time, a short-circuit current will flow, causing the power conversion device to break down. Therefore, to prevent short-circuit current, a dead time is provided in which both semiconductor elements are turned off.

The output voltage of a power conversion device is generated according to switching control by a voltage command. However, the output voltage during the dead time period when the device is completely turned off is unrelated to the control of the voltage command, and depends on whether the direction of the output current flowing through the freewheel diode, etc., is positive or negative. Therefore, the output voltage during the dead time period does not match the desired voltage command, resulting in an output voltage error of the power converter.

Therefore, a power conversion device that reduces the output voltage error by varying the generated dead time is also known (for example, Patent Document 1). In order to reduce this output voltage error, dead time compensation is performed to shift the on or off command of the semiconductor element by the amount of the dead time. The ideal goal of dead time compensation is to make the dead time period due to the preset dead time as close as possible to zero in order to avoid the risk of the semiconductor elements of the upper and lower arms being turned on at the same time.

Therefore, the dead time and dead time compensation are set in consideration of the switching characteristics (response speed) of the semiconductor element. In other words, it is possible to set the dead time compensation so that the gate signal rises to high at a point earlier than the response time of a particular semiconductor element. In this way, by matching the response time of the semiconductor element with the dead time compensation and approaching the ideal target dead time period of zero, the voltage error of the power conversion device can be reduced.

JP 2017-93073 A

The switching characteristics that determine the dead time and dead time compensation differ for each individual semiconductor element, so there is variation in the response time from when the gate signal goes high to when it is turned on. Therefore, with a semiconductor element other than the one used as the standard for dead time compensation, the dead time compensation may not match the preset dead time, and the dead time period may remain longer than the minimum required, so the voltage error reduction effect may not be achieved.

In contrast, it is unrealistic to set an optimal dead time in advance to match the characteristics of each semiconductor element, which varies. In this way, the power conversion device of Patent Document 1 can provide an optimal dead time according to the output current, but the variation in semiconductor elements is on the order of a few μs and does not appear in the error of the output current, so it is not possible to optimize dead time compensation taking into account the variation in semiconductor elements.

The present invention was made in consideration of the above problems, and its purpose is to provide a power conversion device that can reduce voltage errors even when there is variation in the characteristics of the semiconductor elements by adjusting the timing of the gate signal output change in response to differences in the FB delay time measured according to the characteristics of each semiconductor element.

The present invention, which solves the above problem, is a power conversion device equipped with a control unit capable of adjusting the timing difference between when one of at least two semiconductor elements connected in series to a DC power source ends turning on and when the other starts turning on. The control unit has a PWM pulse generation unit that generates a gate signal for the semiconductor element, an FB signal output unit that outputs an FB signal when the gate voltage of the semiconductor element exceeds a predetermined value, an FB delay time calculation unit that calculates the delay time of the output change timing of the FB signal output unit corresponding to the output change timing of the PWM pulse generation unit, a reference FB signal delay time table that specifies a reference time based on the characteristics of a reference semiconductor element for the delay time from when the gate signal is input to when the FB signal is output, and a calculation unit that adjusts the timing of changing the gate signal based on the calculation output of the FB delay time calculation unit so that the change timing of the actual output voltage approaches the change timing of the output voltage command based on the reference FB signal delay time table.

The present invention provides a power conversion device that can reduce voltage errors even when there is variation in the characteristics of semiconductor elements.

1 is a schematic diagram of a railway vehicle according to a first embodiment of the present invention. 1 is a circuit diagram of a three-phase inverter illustrated as a power conversion device according to a first embodiment of the present invention; 11 is a timing chart showing an operational waveform of a forward current in a power conversion device according to a comparative example, illustrating turn-on. 3 is a timing chart of the power conversion device of FIG. 2 when the current flows in a positive direction. 3 is a timing chart of the power conversion device of FIG. 2 when the current flows in the negative direction. FIG. 11 is a circuit diagram of an AC/DC bidirectional power conversion device exemplified as a power conversion device according to a second embodiment of the present invention.

The following describes an embodiment of the present invention using the drawings.

Figure 1 is a schematic diagram showing a railway vehicle (hereinafter, simply referred to as "vehicle") 8 according to a first embodiment of the present invention. As shown in Figure 1, the vehicle 8 moves forward or backward by rotating the wheels 3 driven by the electric motor 5. The electric motor 5 may be either an induction motor or a permanent magnet synchronous motor. In the case of an induction motor, multiple electric motors can be driven by one power conversion device. However, in the case of a permanent magnet synchronous motor, the number of electric motors that can be driven by one power conversion device is limited to one.

When braking to decelerate the vehicle 8, the motor 5 can function as a generator to regenerate power. The regenerated power generated by the motor 5 returns to the overhead line 1 via the power converter 6, filter reactor 15, contactor 14 (Figure 2), and circuit breaker 10. This regenerated power is consumed as power for other vehicles (not shown) via the overhead line 1. As an electrical ground, the low potential side of the power converter 6 is connected to the rail 2 via the wheels 3. The motor 5 is mounted on the bogie 4, which supports the vehicle 8.

When the vehicle 8 is in powered operation, it accelerates by receiving power from the overhead line 1 via the current collector 7. The electrical equipment that drives the vehicle 8, namely the power converter 6, the circuit breaker 10, and the filter reactor 15, are each stored in a separate box and disposed under the floor. Although each electrical equipment shown in FIG. 1 is shown in a separate box, the packaging density may be increased by storing some or all of the electrical equipment in a single box.

The voltage of the overhead line 1 is DC 600V, DC 750V, DC 1500V, DC 3000V, or AC 20kV, 25kV, etc. In the first embodiment, the voltage of the overhead line 1 is DC. The configuration of the motor drive system is described below.

Figure 2 is a circuit diagram of a three-phase inverter exemplified as the power conversion device 6 according to the first embodiment of the present invention. The power conversion device 6 constitutes the main part of a drive system that drives the electric motor 5. This drive system is composed of a circuit breaker 10 capable of appropriately interrupting the power supplied from the overhead line 1, a contactor 14, a filter reactor 15, and the power conversion device 6. The detailed configuration and operation of the power conversion device 6 will be described below.

The power conversion device 6 converts DC power into AC power and drives the electric motor 5. The power conversion device 6 is composed of a filter capacitor 110, switching elements Q1 to Q6, gate drive circuits 101 to 106, anti-parallel freewheeling diodes D1 to D6, current sensors 119a to 119c, and a control unit 100. The gate drive circuits 101 to 106 are located after the gate signal generation unit for controlling the switching elements Q1 to Q6, and also include an FB signal output unit that outputs an FB signal.

Current sensors 119a-119c detect the drive current output by power conversion device 6 to drive motor 5. Control unit 100 constitutes the front stage of the gate signal generation unit and generates gate commands for gate drive circuits 101-106. The switching elements Q1-Q2 are connected in series to constitute the U phase. Similarly, the switching elements Q3-Q4 are connected in series to constitute the V phase. Similarly, the switching elements Q5-Q6 are connected in series to constitute the W phase.

When the switching elements Q1 to Q6 are IGBTs (insulated gate bipolar transistors), anti-parallel freewheeling diodes (hereinafter simply referred to as "diodes") D1 to D6 are required, each connected in anti-parallel to the main terminal of the switching element. The diodes D1 to D6 pass a freewheeling current when the switching elements Q1 to Q6 are off.

In contrast, if the switching elements Q1 to Q6 are MOSFETs (metal oxide semiconductor field effect transistors), the parasitic diodes of the MOSFETs may be used as the diodes D1 to D6. In this way, if the switching elements Q1 to Q6 are MOSFETs or the like and therefore have body diodes, the body diodes of the MOSFETs may be used without connecting diodes in anti-parallel to each of the switching elements Q1 to Q6.

In addition, two switching elements (e.g. Q1 and Q2) connected in series may be housed in the same package to form a 2-in-1 package. The switching elements Q1 to Q6 may be voltage-controlled switching elements such as MOSFETs or IGBTs, or current-controlled switching elements such as thyristors.

The semiconductor material of the switching elements Q1 to Q6 and the diodes D1 to D6 may be Si (silicon) or SiC (silicon carbide) or GaN (gallium nitride), which are semiconductors with a wider band gap than Si. These wide band gap semiconductors can reduce the generated loss compared to Si, allowing the power conversion device 6 to be made smaller.

The power conversion device 6 controls the switching elements Q1 to Q6 using PWM (Pulse Width Modulation) to output pulsed AC power from the filter capacitor 110. This AC power is supplied to the electric motor 5 and converted into mechanical energy to drive the vehicle 8 forward or backward. The initial charging of the filter capacitor 110 is performed using the contactor 12 and resistor 13, which form a charging circuit. With the contactor 14 in the open state, the contactor 12 is closed and initial charging is performed via the resistor 13.

The filter capacitor 110 and the filter reactor 15 form a filter circuit that reduces the noise current flowing from the power conversion device 6 to the overhead line 1. The current sensors 119a to 119 measure the currents of the motor 5 in the U, V, and W phases, respectively. The current sensors may measure any two of the U, V, and W phases and calculate the value of the remaining phase from these values. By doing so, the number of current sensors can be reduced from three to two, making it possible to make the power conversion device 6 smaller and less expensive.

Here, the power conversion device 6 will be described with a focus on the dead time generation and the function of compensating for it. The power conversion device 6 is configured with a control unit 100, a DC power supply 110, a group of switching elements Q1-Q2 (Q3-Q4, Q5-Q6 are also omitted), a gate signal generation unit (control unit 100 and gate drive circuits 101-106), a dead time insertion unit (control unit 100), a bridge circuit (switching elements Q1-Q6 and others), current sensors 119a-119c (collectively 119), and a variable dead time generation unit (control unit 100).

In addition, the power conversion device 6 is exemplified by a group of switching elements Q1-Q2 with a two-level configuration consisting of two elements Q1 and Q2, but it can also be applied to a group of switching elements Q1-QX with a three-level configuration consisting of three elements. The control unit 100 is equipped with a reference FB signal delay time table 112, a correction amount calculation unit 115, and a corrected dead time compensation table 116 as new blocks having characteristic technologies related to the dead time generation and the function of compensating for it, which will be described later.

Switching elements Q1 to Q6 can be switched between on and off states by gate signals. The switching elements Q1-Q2 group forms upper and lower arms by connecting the main terminals of switching element Q1 and switching element Q2 in series. The gate signal generation unit (control unit 100) generates a provisional gate signal from the voltage command value. The dead time insertion unit (control unit 100) inserts dead time into the provisional gate signal to generate a gate signal.

In the bridge circuit, multiple groups of switching elements Q1-Q2, each forming an upper and lower arm, are connected in parallel to a DC power source 110 to convert DC power to AC power. A current detection unit 119 detects the output current of the bridge circuit. A variable dead time generation unit (control unit 100) calculates the dead time according to the current value detected by the current detection unit 119, based on the characteristics of the turn-on delay time and turn-off delay time for the current value flowing through the switching elements.

The on or off state of the switching elements Q1 to Q6 is controlled by the control unit 100. The on or off PWM signal output from the control unit 100 is amplified by each gate drive circuit 101 to 106. The switching elements Q1 to Q6 are controlled by applying the amplified PWM signal between their gates and emitters (between their gates and sources if the switching elements Q1 to Q6 are MOSFETs).

The gate drive circuits 101 to 106 also have the function of outputting an FB (output frequency detection) signal when the gate voltage of the switching elements Q1 to Q6 reaches a predetermined reference value. In other words, the FB signal output unit is built into the gate drive circuits 101 to 106, and outputs an FB signal when the result of comparing the gate voltage with the reference value exceeds the reference value.

The PWM signals that control switching elements Q1 and Q2, which have a pair of main terminals connected in series between the positive and negative power supplies, have dead times during which they are both in the off state at the same time. The PWM signals that control the pairs of switching elements Q1-Q2, Q3-Q4, and Q5-Q6 connected in series in this way all have dead times.

If the dead time is not provided, for example, there will be a time when switching elements Q1 and Q2 are on at the same time. In that case, the filter capacitor 110 will be short-circuited by switching elements Q1 and Q2 that are on at the same time. This short-circuit current may cause the power conversion device 6 to fail.

The control unit 100 is configured to include an FB signal delay time calculation unit 111, a reference FB signal delay time table 112, a reference dead time compensation table 113, a reference PWM signal generation unit 114, a correction amount calculation unit 115, a corrected dead time compensation table 116, a tentative dead time assignment unit 117, and a dead time compensation unit 118.

The FB signal delay time calculation unit 111 has a function of calculating the FB delay time for the PWM signal output from the control unit 100. The reference FB signal delay time table 112 stores an FB signal delay time table of a reference element, and the table has dependencies on voltage, current, temperature, etc. The reference dead time compensation table 113 stores a table of dead time compensation of a reference element, and the table has dependencies on voltage, current, temperature, etc.

The reference PWM signal generating unit 114 generates a reference PWM signal with no dead time so that the power conversion device 6 outputs the desired voltage. The correction amount calculating unit 115 calculates the correction amount for dead time compensation based on the delay time output from the FB delay time calculating unit 111 and the reference FB signal delay time table 112.

The corrected dead time compensation table 116 corrects the dead time compensation table using the reference dead time compensation table 113 and the correction amount calculation unit 115. The tentative dead time assignment unit 117 assigns a dead time to the PWM signal output from the reference PWM signal generation unit 114.

The dead time compensation unit 118 applies dead time compensation to the PWM signal using the corrected dead time compensation table output by the corrected dead time compensation table 116, the PWM signal to which the dead time has been added, and the current of the electric motor 5. The PWM signal to which the dead time compensation has been applied is input to the gate drive circuits 101 to 106 of the switching elements Q1 to Q6.

Figure 3 is a timing chart showing the operating waveform of a forward current in a power conversion device according to a comparative example, indicating turn-on. The horizontal axis of Figure 3 indicates time T [s], and the vertical axis indicates, from top to bottom, E indicates the output voltage command of the power conversion device 6, G indicates the Q1 gate signal (before dead time compensation), J indicates the Q2 gate signal (before dead time compensation), K indicates the Q1 gate voltage (before dead time compensation), M indicates the Q1FB signal (before dead time compensation), N indicates the power conversion device 6 output voltage (before dead time compensation), R indicates the Q1 gate signal (after dead time compensation), and S indicates the power conversion device 6 output voltage (after dead time compensation).

The specifications in FIG. 3 are the same in FIG. 4 and FIG. 5. This power conversion device according to the comparative example is a power conversion device that controls the operation of the power conversion device 6 in FIG. 2 without dead time compensation, and is compared with Example 1. Therefore, in the following, the components of the power conversion device 6 according to the comparative example will be described with the same reference numerals assigned to parts that have the same effect. The waveforms shown in FIG. 3 focus on the operation of the switching elements Q1 and Q2 that constitute the U phase, and assume that the current flowing through the motor 5 is from the power conversion device 6 to the motor 5.

At time t1, the output voltage command of the power conversion device 6 becomes High (Figure 3E). At the same time, Low is input to the gate signal of switching element Q2. After that, at time t2, High (Figure 3G) is input to the gate signal of switching element Q1. The difference between times t1 and t2 shown in Figure 3 is defined as dead time. During the dead time, both switching elements Q1 and Q2 are in the off state, and the output voltage of the power conversion device 6 during that period depends on the direction of the current flowing through the electric motor 5.

When current flows from the power converter 6 to the motor 5, the current flows through the diode D2 connected in inverse parallel to the switching element Q2 during the dead time period, and the output voltage of the power converter 6 becomes Low (Figure 3N). In other words, when current flows from the power converter 6 to the motor 5, the output voltage of the power converter 6 becomes High only when the switching element Q1 is turned on (Figure 3K) (Figure 3N).

Even if a High signal (Figure 3G) is input to the gate signal of switching element Q1 at time t2, there is an operational delay in switching element Q1 and gate drive circuit 101, so in the case of element A, the output voltage of power conversion device 6 becomes High (Figure 3N) at time t3. Here, if the gate voltage that outputs the FB signal (Figure 3M) in gate drive circuits 101-106 is set close to the mirror voltage of switching element Q1, the FB signal (Figure 3M) of switching element Q1 is output from gate drive circuit 101 at time t3.

When comparing the output voltage command of the power conversion device 6 (Figure 3E) with the output voltage of the power conversion device 6 before dead time compensation (Figure 3N), a deviation occurs between the output voltage command value (Figure 3E) and the output voltage (Figure 3N) between times t1 and t3. This deviation becomes an output voltage error of the power conversion device 6 and is a factor that reduces the control performance of the power conversion device 6.

Therefore, by advancing (shifting to the left) the gate signals of switching elements Q1 and Q2 by the difference between time t3 and time t1 of element A, the gate signal of switching element Q1 becomes the gate signal of Q1 after dead time compensation (Figure 3R). This dead time compensation causes the output voltage of power conversion device 6 (Figure 3S) to go high at time t1, matching the output voltage command of power conversion device 6 (Figure 3E), eliminating the voltage error.

Here, it is assumed that the reference dead time compensation table 113 is designed based on the characteristics of element A. In general, switching elements have variations in their electrical operating characteristics, and therefore also have variations in their switching characteristics, which have a large impact on functionality. For example, it is assumed that there is an element B that is the same as element A in terms of the output voltage command of the power conversion device 6 (Figure 3E) and the time when the gate signal of the switching element Q1 goes high (Figure 3K).

However, if the delay time of element B is longer than that of element A due to the effect of variation in the characteristics of the switching elements, the output voltage of the power conversion device 6 (FIG. 3N) becomes High at time t3'. On the other hand, the dead time compensation (FIG. 3R) in the power conversion device 6 according to the comparative example is applied uniformly to all elements, so the dead time compensation using the reference dead time compensation table 113 of element A is applied only for the difference between times t3 and t1 (FIG. 3R).

As a result, the output voltage after dead time compensation of element B in the comparative example (FIG. 3S) does not match the output voltage command of the power conversion device 6, and an error occurs in the output voltage between time t1 and time t1'. It is also possible to provide separate reference dead time compensation tables 113 for element A and element B, but this is unrealistic because it would require measuring the switching characteristics of each element.

Figure 4 is a timing chart when the current of the power conversion device 6 in Figure 2 is in the positive direction. The specifications in Figure 4 are the same as those in Figure 3. The timing chart for element A is omitted because it is the same as that in Figure 3. Below, we will explain the reference FB signal delay time table 112, the reference dead time compensation table 113, the correction amount calculation unit 115, and the corrected dead time compensation table 116, which are newly adopted blocks as characteristic configurations of the present invention.

The reference FB signal delay time table 112 and the reference dead time compensation table 113 are set based on the characteristics of element A. For example, when the current flowing through the motor 5 is positive 500 A, the correction amount calculation unit 115 in the control unit 100 refers to the reference FB signal delay time table 112. In this case, if the FB signal delay time from time t2 to t3 is known as 4 μs and the dead time from time t1 to t2 is 10 μs, the reference dead time compensation table 113 is referenced to read that the reference dead time compensation from t1 to t3 is 10 + 4 = 14 μs.

In the case of element A, by compensating for the 14 μs from time t1 to t3 (E, G, J in FIG. 4) as dead time, the output voltage command (FIG. 4E) of the power conversion device 6 and the rise timing of the output voltage (FIG. 4S) are matched, thereby eliminating voltage error. In other words, while the dead time of 10 μs from time t1 to t2 was set to ensure safety, the accuracy of voltage control can be improved by bringing this dead time as close to zero as possible.

In the case of element B, like element A, the dead time from time t1 to t2 is 10 μs (E, G, J in FIG. 4). Here, the FB signal delay time from t2 to t3' of element B is 6 μs (G, N in FIG. 4). The reference FB signal delay table 112 is 4 μs when referring to the value of element A.

The difference between this reference FB signal delay table 112 and the FB signal delay time of element B, 2 μs, is calculated by the correction amount calculation unit 115. This calculated value of 2 μs and the reference dead time compensation table 113 are used to create the corrected dead time compensation table 116. Specifically, 14 μs is read from the reference dead time compensation table of element A, and 2 μs, the correction amount calculation value, is added to this value to create 16 μs (Figure 4R) as the corrected dead time compensation table 116.

By using this 16 μs to compensate for the dead time of element B, the output voltage (FIG. 4S) matches the output voltage command value (FIG. 4E) of the power conversion device 6, eliminating the voltage error. With the configuration of the power conversion device 6 according to the first embodiment, even if there is variation in the characteristics of the switching elements, such as elements A and B, the dead time compensation table can be corrected to reduce the output voltage error of the power conversion device 6.

Figure 5 is a timing chart when the current in the power conversion device 6 in Figure 2 is in the negative direction. The specifications in Figure 5 are the same as those in Figures 3 and 4. At time t1, the output voltage command of the power conversion device 6 becomes Low (Figure 5E). At the same time, Low (Figure 5G) is input to the gate signal of switching element Q1. After that, at time t2, High (Figure 5J) is input to the gate signal of switching element Q2. The difference between times t1 and t2 (Figures 5G and J) is defined as the dead time.

During the dead time, both switching elements Q1 and Q2 are in the off state, and the output voltage of the power conversion device 6 during this period depends on the direction of the current flowing through the motor 5. When current is flowing from the motor 5 to the power conversion device 6, the current flows through the diode D1 connected in anti-parallel to the switching element Q1 during the dead time, and the output voltage of the power conversion device 6 becomes High (Figure 5N). In other words, when current is flowing from the power conversion device 6 to the motor 5, the output voltage of the power conversion device 6 becomes Low (Figure 5N) only when the switching element Q2 is in the on state (K, M in Figure 5).

During the dead time and during the operation delay time of switching element Q2, the output voltage of power conversion device 6 is High (Fig. 5N), which differs from the output voltage command (Fig. 5E), resulting in a voltage error. Therefore, in the case of element A, by referring to the reference dead time compensation table 113, the gate signal of switching element Q2 is advanced by times t1 to t3 (shifted leftward as shown from J to R in Fig. 5), so that the output voltage command (Fig. 5E) of power conversion device 6 matches the output voltage (Fig. 5S), thereby reducing the voltage error.

For element B, as explained in FIG. 4, the correction amount of dead time compensation is calculated using the calculated value of the FB signal delay time and the reference FB signal delay time table 112, and the corrected dead time compensation table 116 is used to reduce the voltage error due to the characteristic variation of switching element B relative to element A.

Figure 6 is a circuit diagram of an AC/DC bidirectional power conversion device exemplified as a power conversion device 16 according to a second embodiment of the present invention. The power conversion device 16 shown in Figure 6 is capable of bidirectional AC/DC power conversion by highly precisely controlling the semiconductor elements Q1 to Q4.

The power conversion device 6 according to an embodiment of the present invention (hereinafter also referred to as "this device") can be summarized as follows. The control functions including the control unit 100 in this device 6 can be configured by a computer having a memory for storing programs, tables, and various data, and a CPU (arithmetic processing unit), but may also be configured by hardware instead of the computer.

[1] This device 6 is configured with a control unit 100 that is capable of adjusting the timing difference between the end time t1 of the turn-on of one of at least two semiconductor elements Q1, Q2 connected in series to a DC power supply 110 and the start time t3 of the other. The control unit 100 has a PWM pulse generation unit, an FB signal output unit, an FB delay time calculation unit 111, and a reference FB signal delay time table 112.

The PWM pulse generating unit generates gate signals for the semiconductor elements Q1 and Q2. The FB signal output unit outputs an FB signal when the gate voltages of the semiconductor elements Q1 and Q2 exceed a predetermined value. The FB delay time calculation unit 111 calculates the delay time of the output change timing of the FB signal output unit corresponding to the output change timing of the PWM pulse generating unit. The reference FB signal delay time table 112 specifies a reference time based on the characteristics of a reference semiconductor element (e.g. Q1) for the delay time from inputting a gate signal to outputting an FB signal.

In the present device 6, the control unit 100 has a calculation unit that adjusts the time to advance the timing of the output change (rising) of the gate signal based on the calculation output of the FB delay time calculation unit 111 so that the timing of the change of the actual output voltage (N, S in Figures 3 to 5) approaches the timing of the change of the output voltage command E based on the reference FB signal delay time table 112. The present device 6 adjusts the time at which the gate signal is changed (the timing of the output change of the gate signal) according to the difference in the FB delay time actually measured due to the characteristics of each semiconductor element. As a result, the present device 6 can reduce voltage errors even when there is variation in the characteristics of the semiconductor elements.

[2] The calculation unit of [1] above may further include a correction amount calculation unit 115 that calculates a correction amount based on the difference between the delay time output from the FB delay time calculation unit 111 and the reference FB signal delay time table 112. The reference FB signal delay time table 112 specifies a reference time based on the characteristics of the semiconductor element (e.g. Q1) that is the reference described above, and the correction amount calculation unit 115 reflects the difference in the actually measured FB delay time with respect to that reference, thereby individually considering the characteristics of the semiconductor elements that vary, thereby reducing the voltage error.

[3] In the above [2], if the actual measured value is longer than the reference time, the correction amount calculation unit 115 adjusts the timing for changing the gate signal to be advanced (advanced) so as to lengthen the time. Specifically, 14 μs is read from the table from the reference time based on the characteristics of the reference element A, and 2 μs, the correction amount calculation value, is added to this value to lengthen it, resulting in 16 μs (Figure 4R), which is the time to advance the gate signal. By using this 16 μs to compensate for the dead time of element B, the output voltage (Figure 4S) matches the output voltage command value (Figure 4E) of the power conversion device 6, so that the output voltage error of the power conversion device 6 can be reduced.

[4] In the above [3], it is preferable to provide a dead time generation unit that generates the timing of the dead time when the two semiconductor elements connected in series are simultaneously turned off. Such a device 6 is configured with a bridge circuit (switching elements Q1 to Q6, etc.), a gate signal generation unit (control unit 100 and gate drive circuits 101 to 106), a dead time insertion unit (control unit 100), a current sensor 119, and a variable dead time generation unit (control unit 100). This provides a dead time and reliably prevents accidents in which the semiconductor elements of the upper and lower arms are simultaneously turned on. In this way, the device 6 can also generate dead time and provide a function to compensate for it. Note that the effects of the device 6 can be obtained even without providing a dead time, as exemplified in the above [1].

[5] In the above [1], the reference FB signal delay time table 112 is configured with data having dependency on voltage, current, or temperature. For semiconductor elements, known data including temperature characteristics in addition to operating characteristics according to the voltage and current of the main terminals and gate signals is configured in the reference FB signal delay time table 112. With this device 6, precise control can be achieved by using table data with guaranteed reproducibility.

[6] In the above [1], at least one of the semiconductor elements has a base material of silicon or a semiconductor material (SiC, GaN) having a band gap larger than that of silicon. These wide band gap semiconductors can reduce the generated loss compared to Si, so the power conversion device 6 can be made smaller.

[7] In the above [1], at least one of the semiconductor elements is a voltage-driven element such as a MOSFET, an IGBT, or a multi-gate IGBT. In particular, a multi-gate IGBT can achieve even higher efficiency. If the switching elements Q1 to Q6 are MOSFETs and have body diodes, it is possible to use the body diodes of the MOSFETs without connecting diodes in anti-parallel to each of the switching elements Q1 to Q6, which also reduces the number of parts.

[8] The power conversion device (this device) 6 described in any one of [1] to [7] above is suitable for railway vehicles. In other words, this device 6 is suitable for railway vehicles because the voltage of the overhead line 1 is 600V to 3000V DC, or 20kV, 25kV AC, etc., and a large current of up to approximately 500A is repeatedly turned on and off at a desired frequency.

REFERENCE SIGNS LIST 1 overhead line, 2 rail, 3 wheels, 4 bogie, 5 motor, 6 power conversion device, 7 current collector, 8 vehicle, 10 circuit breaker, 12, 14 contactor, 13 resistor, 15 filter reactor, Q1 to Q6 switching elements, D1 to D6 diodes, 110 filter capacitor, 100 control unit, 101 to 106 gate drive circuit, 111 FB signal delay time calculation unit, 112 reference FB signal delay time table, 113 reference dead time compensation table, 114 reference PWM signal generation unit, 115 correction amount calculation unit, 116 corrected dead time compensation table, 117 temporary dead time grant unit, 118 dead time compensation unit, 119a to 119c (collectively 119) current sensor

Claims (15)

A power conversion device including a control unit capable of adjusting a timing difference between a time when one of at least two semiconductor elements connected in series to a DC power source ends turning on and a time when the other semiconductor element starts turning on,
The control unit is
A PWM pulse generating unit that generates a gate signal for the semiconductor element;
an FB signal output unit that outputs an FB signal when a gate voltage of the semiconductor element exceeds a predetermined value;
an FB delay time calculation unit that calculates a delay time of an output change timing of the FB signal output unit corresponding to an output change timing of the PWM pulse generation unit;
a reference FB signal delay time table that specifies a reference time based on the characteristics of the semiconductor element as a reference for the delay time from when the gate signal is input to when the FB signal is output;
a correction amount calculation unit that calculates a correction amount of dead time compensation based on the delay time calculated by the FB delay time calculation unit and the reference FB signal delay time table;
a reference dead time compensation table in which a table of dead time compensation for a reference element is stored;
a corrected dead time compensation table for correcting the reference dead time compensation table by using the reference dead time compensation table and the correction amount of the dead time compensation calculated by the correction amount calculation unit;
a dead time compensation unit that adjusts a timing for changing the gate signal generated by the PWM pulse generation unit based on the corrected dead time compensation table output from the corrected dead time compensation table ;
having
The dead time compensating unit adjusts a timing at which the gate signal is changed to eliminate the dead time.
Power conversion equipment. The dead time compensation unit calculates a correction amount for adjusting the timing based on a difference between the delay time output from the FB delay time calculation unit and a reference FB signal delay time table.
The power conversion device according to claim 1 . the dead time compensating unit adjusts the timing for changing the gate signal so as to be advanced for a longer period when an actual measurement value is longer than the reference time.
The power conversion device according to claim 2 . a dead time generating unit that generates a timing of a dead time during which the two semiconductor elements connected in series are simultaneously turned off;
The power conversion device according to claim 3 . The reference FB signal delay time table is configured to have a dependency on voltage, current, or temperature.
The power conversion device according to claim 1 . At least one of the semiconductor elements is based on silicon or a semiconductor material having a band gap larger than silicon.
The power conversion device according to claim 1 . At least one of the semiconductor elements is a voltage-driven element such as a MOSFET, an IGBT, or a multi-gate IGBT.
The power conversion device according to claim 1 . A railway vehicle equipped with a power conversion device according to any one of claims 1 to 7. A gate signal adjustment method for adjusting a timing difference between a time when one of at least two semiconductor elements connected in series to a DC power source ends turning on and a time when the other of the semiconductor elements starts turning on, comprising the steps of:
generating a gate signal for the semiconductor device;
When the gate voltage of the semiconductor element exceeds a predetermined value, an FB signal is output.
Calculating a delay time of the change timing of the FB signal corresponding to the change timing of the gate signal;
A reference time based on a characteristic of the semiconductor element as a reference is defined in a reference FB signal delay time table with respect to a delay time from when the gate signal is input to when the FB signal is output;
Calculating a correction amount for dead time compensation based on the calculated delay time and the reference FB signal delay time table;
a reference dead time compensation table storing a table of dead time compensation for a reference element and the calculated correction amount of dead time compensation are used to correct the reference dead time compensation table, and the corrected dead time compensation table is defined;
adjusting a timing for changing the generated gate signal based on the corrected dead time compensation table output from the corrected dead time compensation table ;
By adjusting the timing at which the gate signal is changed, dead time is eliminated.
Gate signal adjustment method. Calculating a correction amount for adjusting the gate signal based on a difference between the calculated delay time and a reference FB signal delay time table.
The gate signal adjusting method according to claim 9 . the correction amount is adjusted so as to lengthen the time by which the timing of the gate signal change is advanced when an actual measurement value is longer than the reference time;
The gate signal adjusting method according to claim 10. generating a dead time timing during which the two semiconductor elements connected in series are simultaneously in an off state;
The gate signal adjusting method according to claim 9 . The reference FB signal delay time table is configured to have a dependency on voltage, current, or temperature.
The gate signal adjusting method according to claim 9 . At least one of the semiconductor elements is made of silicon or a semiconductor material having a band gap larger than that of silicon.
The gate signal adjusting method according to claim 9 . At least one of the semiconductor elements is a voltage-driven element such as a MOSFET, an IGBT, or a multi-gate IGBT.
The gate signal adjusting method according to claim 9 .

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