JP7551405B2 - Apparatus, method, and program - Google Patents

Description

The present invention relates to an apparatus, method, and program for performing image processing, including variable magnification processing.

The image processing device has a processing circuit that performs processing such as filtering on input image data. Generally, many reading devices such as scanners, printing devices such as printers, and display devices such as monitors are capable of handling color images and color originals. For this reason, the image processing devices installed in many of these devices are often configured as devices that basically perform color processing. The image processing device has circuits that process three colors for RGB color images, and four colors for CMYK color images, for example. These circuits may have the same function for each color. In other words, the image processing device can have three or four circuits in parallel. There are also products that can handle even more colors (for example, 12 colors) simultaneously, such as recent inkjet printers.

When monochrome (single-color) image data is input to such an image processing device based on color processing, it is possible to efficiently use the parallelized processing units described above. This can improve the processing speed of monochrome (single-color) image data.

Patent document 1 describes a method for parallelizing and speeding up image processing when processing monochrome (single-color) image data in an image processing device that is based on image processing compatible with dot-sequential color image data.

JP 2015-115837 A

However, Patent Document 1 does not anticipate scaling processes that change the size of monochrome images, and does not mention parallelization of scaling processes. Therefore, one embodiment of the present invention aims to reduce processing time by parallelizing image processing, including scaling processes.

One embodiment of the present invention is an apparatus having a division means for dividing an area of monochrome image data into a plurality of band areas, and an image processing means for performing image processing including a scaling process for changing the size of the band areas acquired by the division means according to a predetermined scaling factor, the image processing means being equipped with a plurality of image processing circuits that perform the same operation in parallel, and further having a calculation means for calculating an input line number indicating the number of lines of the band area input to the image processing circuit and an output line number indicating the number of lines of the band area output from the image processing circuit based on the predetermined scaling factor, and when both the input line number and the output line number are smaller than a maximum line number indicating the maximum number of lines of the band area that the image processing circuit can process, the image processing means performs image processing on the plurality of band areas in parallel.

According to one embodiment of the present invention, it becomes possible to parallelize image processing, including scaling processing, thereby shortening processing time.

FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to a first embodiment. FIG. 1 is a diagram for explaining a division process of image data in the first embodiment; FIG. 1 is a diagram for explaining a magnification change process in the first embodiment; 1 is a timing chart of input/output data of an image processing circuit according to a first embodiment; Schematic diagram of an image processing unit in the first embodiment. Flowchart of image processing in the first embodiment FIG. 1 is a diagram for explaining parallel processing of continuous regions, which is executed by an image processing unit in the first embodiment; FIG. 1 is a diagram for explaining parallel processing of intermittent regions, which is executed by an image processing unit in the first embodiment; FIG. 1 is a diagram for explaining sequential processing of continuous regions, which is executed by an image processing unit in the first embodiment; Flowchart of image processing in the second embodiment 11 is a flowchart of image processing according to a modified example of the second embodiment. Flowchart of image processing in the third embodiment

Hereinafter, the embodiments of the present invention will be described in detail. Note that the following embodiments are merely examples for explaining the present invention, and are not intended to limit the present invention to the embodiments. Furthermore, the present invention can be modified in various ways without departing from the gist of the present invention.
[First embodiment]

<Configuration of image processing device>
1 is a block diagram showing the configuration of an image processing device 10 according to this embodiment. The image processing device 10 includes a CPU 100, a RAM 101, a ROM 102, an operation unit 103, a display unit 104, an image processing unit 105, an interface (hereinafter referred to as I/F) unit 106, and a bus 107.

The CPU 100 uses computer programs and data stored in the RAM 101 and ROM 102 to control the operation of the entire image processing device 10 and implements the image processing control method described below.

RAM 101 has a storage area for temporarily storing computer programs and data loaded from an external storage device via I/F unit 106. RAM 101 also has a storage area used by CPU 100 when executing various processes and a storage area used by image processing unit 105 when performing image processing. In other words, RAM 101 can provide various storage areas as appropriate.

ROM 102 stores configuration data and boot programs for the image processing device 10.

The operation unit 103 is composed of input devices such as a keyboard and a mouse. Through the operation unit 103, the operator of the image processing device 10 can input various instructions, and the CPU 100 can receive the input instructions.

The display unit 104 is composed of a CRT or LCD screen, and can display the results of processing by the CPU 100 as images or text.

The image processing unit 105 is composed of a processor capable of executing a computer program and a dedicated image processing circuit (see FIG. 5). For example, when the image processing unit 105 receives a command (job) to execute image processing from the CPU 100, it performs magnification processing (image resizing processing according to the magnification ratio), device correction processing, color conversion, etc. on the input image stored in the RAM 101, and then outputs the processing results. Furthermore, when performing image processing, the image processing unit 105 performs the processing while utilizing the storage area of the RAM 101.

The I/F unit 106 functions as an interface for connecting the image processing device 10 to an external storage device or the Internet. Programs, image data, image processing parameters, and the like stored in the external storage device and to be processed by the CPU 100 are loaded appropriately into the RAM 101 via the I/F unit 106.

Each of the components of the image processing device 10 described above is connected to each other via a bus 107, making it possible to transmit and receive data between the components.

<Image data division processing>
Next, the region division process of image data used in this embodiment will be described. Note that, hereinafter, the region division process of image data will be referred to as "band division process", and image processing for each band region involving the band division process will be referred to as "band processing".

In band processing, for example as shown in FIG. 2, the image area of a single piece of image data 200 is divided into strip-shaped band areas 201 to 20x, and various types of image processing (called sequential processing) are performed sequentially on each of these divided band areas.

The height of each band area may vary depending on the content of the image processing. Also, due to the built-in memory of the image processing circuit, the maximum value of the height of the band area is usually predetermined.

<Magnification processing>
Next, the magnification change process will be described with reference to Fig. 3 and Fig. 4. Here, the magnification change process will be described with an example in which the magnification change rate is 1.5 times in the vertical direction.

First, the band area that is output when the first band area is input to a magnification circuit (specifically, for example, image processing circuit 501 in FIG. 5) will be described with reference to FIG. 3(a). Note that the input pixel data in the first band area that constitutes the input image data is represented as I1, and the output pixel data in the first band area that constitutes the output image data is represented as O1. The pixel data in the other band areas (i.e. the second and subsequent band areas) will be represented in the same manner.

The scaling circuit executes a scaling process, enlarging the band region, represented by 0 to 1 in internal coordinates, by 1.5 times, and holds the pixel values in the enlarged region as pixel values in the region 0 to 1.5. The scaling circuit stores the internal coordinates (1.5 in this case) that indicate to what extent the input pixel data has been scaled. After this scaling process, the scaling circuit performs an output decision to determine whether or not the pixel values can be output.

In the output determination, a determination is made as to whether all the data in the range to be used for the interpolation process is available. For the area between internal coordinates 0 and 1, it is determined that output is possible since pixel values are held, and the pixel values in this area are weighted-averaged as necessary and output. In the case of Figure 3(a), the only pixel value in the area between internal coordinates 0 and 1 in the input image is I1. Therefore, the only pixel value in the area between internal coordinates 0 and 1 in the output image is O1, which matches I1.

Next, a determination is made as to whether pixel data for the area of internal coordinates 1-2 can be output. In the case of FIG. 3(a), the scaling circuit has not yet received pixel data for the next (i.e., second) band area, and therefore determines that output is not possible because the pixel values for the area of internal coordinates 1-2 in the scaled image (called the scaled image) are not complete. At this time, the internal coordinate (1 in this case) indicating how far the scaled image to be output has been scaled is also retained.

Next, we will use Figure 3(b) to explain the pixel data that is output when pixel data I2 of the second band area in the input image data is input to the magnification circuit.

The scaling circuit executes a scaling process, enlarging the band area represented by 1 to 2 in the internal coordinates by 1.5 times, and stores the pixel values in the enlarged area as pixel values in the area 1.5 to 3. The scaling circuit stores the internal coordinates (3 in this case) that indicate to what extent the input pixel data has been scaled.

In the output determination, a determination is made as to whether pixel values corresponding to the area of internal coordinates 1-2 in the scaled image are held. In the case of Figure 3(b), I1 and I2 exist, and it is determined that they hold pixel values from the area of internal coordinates 1-2 in the scaled image. O2 is then generated by taking a weighted average of these pixel values. In generating O2, a weighted average is taken according to the ratio between the part with pixel value I1 and the part with pixel value I2 in the area of internal coordinates 1-2 in the scaled image.

Furthermore, the pixel value I2 in the area between internal coordinates 2 and 3 is also held for the next output band area, so it can be output. In the case of Figure 3(b), the output pixel data O3 is output, and the STALL signal is asserted as shown in Figure 4, so that the input pixel data is not received and is reserved. The reserved input pixel data I3 is controlled so that it is input again in the next clock cycle.

Similarly, if the scaling factor is 1.5x, 3 lines will be output every time 2 lines are input.

To generalize the above, if the magnification ratio expressed as a fraction is n/m (where m and n are both integers), the denominator is the number of input lines and the numerator is the number of output lines, and the magnification process is repeated using the larger number of lines, n or m, as a unit.

<Configuration of image processing circuit>
5 is a schematic diagram of an image processing section that performs image processing on RGB color image data. The image processing section 105 has a plurality of image processing circuits 501 that are arranged in parallel and perform the same operation.

In the case of FIG. 5, data is extracted pixel by pixel from red component image data 502R, the extracted data is input as pixel data to image processing circuit 501R, image processing is performed in image processing circuit 501R, and the processed pixel data is output. When image processing by image processing circuit 501R is completed for all pixels of red component image data 502R, which is the input data, red component image data 503R is obtained as output data.

Similarly, data is extracted pixel by pixel from green component image data 502G, the extracted data is input as pixel data to image processing circuit 501G, image processing is performed in image processing circuit 501G, and the processed pixel data is output. When image processing by image processing circuit 501G is completed for all pixels of green component image data 502G, which is the input data, green component image data 503G is obtained as output data.

Similarly, data is extracted pixel by pixel from yellow component image data 502B, the extracted data is input as pixel data to image processing circuit 501B, image processing is performed in image processing circuit 501B, and the processed pixel data is output. When image processing circuit 501B has completed image processing for all pixels of yellow component image data 502B, which is the input data, yellow component image data 503B is obtained as output data.

Note that while FIG. 5 shows an embodiment in which image processing is performed in parallel using three image processing circuits, the number of image processing circuits is not limited to three and may be any integer equal to or greater than two.

By applying the technology disclosed in Patent Document 1 to the image processing circuit shown in this embodiment, it is possible to parallelize and speed up image processing when processing monochrome image data.

In the following description of this embodiment, the maximum number of lines in the band area (hereinafter referred to as the band line number) input/output to the image processing unit 105 (hereinafter referred to as the maximum line number) is 16. Band areas of 16 lines or less can be processed by the image processing circuit 501, but band areas of 17 lines or more will not be accepted. Note that this number of lines can be increased by increasing the amount of data that can be held inside the image processing circuit.

<Image processing including magnification change processing>
Image processing including the magnification change processing in this embodiment will be described with reference to Fig. 6. In the following, each step in a series of processes will be represented as "S~".

In S600, the CPU 100 calculates the number of lines to be processed based on the magnification ratio. The calculation of the number of lines to be processed in S600 is described in detail below.

In S600, the scaling factor is first converted into a fraction with integer numerators and denominators. Any method may be used to convert the scaling factor into a fraction. For example, if the resolution of the scaling factor is 1%, the scaling factor X can be regarded as a fraction X/1, and the fraction 100X/100 can be obtained by multiplying the numerator and denominator by the reciprocal of the resolution. By simplifying this fraction, it is possible to obtain a scaling factor whose numerator and denominator are both expressed as a fraction with integers.

The number of input lines and the number of output lines are calculated based on the numerator and denominator of the fraction obtained in this way. In other words, the denominator is the number of input lines, and the numerator is the number of output lines. Specifically, when the scaling factor is 1.5x (150%), the fraction is 3/2, and the unit of scaling is 3 lines (the larger of the numerator and denominator). When the scaling factor is 101%, the fraction is 101/100, and the unit of scaling is 101 lines.

In S601, the CPU 100 determines whether the scaling process can be parallelized. If the determination result in S601 is true, the process proceeds to S602. On the other hand, if the determination result in S601 is false, the process proceeds to S603.

The condition (first condition) used to determine whether parallelization is possible in S601 is that both the number of input lines and the number of output lines are equal to or less than the maximum number of lines. In this embodiment, as described above, the maximum number of lines is 16. Therefore, for example, when the scaling factor is 1.5 times, the number of input lines is 2 and the number of output lines is 3, and both the number of input lines and the number of output lines are equal to or less than 16, so the determination result in S601 is true and the process proceeds to S602. Also, for example, when the scaling factor is 101% times, the number of input lines is 100 and the number of output lines is 101, and both the number of input lines and the number of output lines are not equal to or less than 16, so the determination result in S601 is false and the process proceeds to S603.

When the scaling factor is 1.5x, the image processing circuit will repeat processing in units of 3 lines in the subsequent step S602. However, if one band is divided into 3 lines, the number of divided bands will increase, and the overhead of the control time required to execute image processing will increase. For this reason, it is preferable to perform processing with as many lines per band as possible. In this embodiment, the maximum number of lines is set to 16, so the number of output lines is set to 15 lines, which is an integer multiple of 3 lines and closest to 16, and the number of input lines is set to 10 lines, which is 5 times 2 lines, to match this output line number. Setting the number of input lines and the number of output lines in this way enables efficient scaling processing.

Furthermore, when image processing that is performed simultaneously with the scaling process involves image processing that references a group of pixels around a pixel of interest, such as filter processing, the input and output lines must be determined taking into account the overlapping areas. The number of overlapping lines does not affect the calculation that converts the scaling factor into a fraction whose numerator and denominator are integers, but it does affect the maximum number of lines in the image processing circuit. Therefore, when an overlapping area exists, it is necessary to determine whether the scaling process can be parallelized based on the number of lines obtained by subtracting the number of overlapping lines from the maximum number of lines that can be processed by the image processing circuit.

In S602, the image processing unit 105 performs parallel processing. Specifically, the CPU 100 sets parameters such as input image data and a magnification ratio for each of the image processing circuits 501 in the image processing unit 105, and performs parallel processing. FIG. 7 shows an example in which three consecutive bands (30 lines in total) are set as input, and three consecutive bands (45 lines in total) are set as output.

At S603, the image processing unit 105 performs normal sequential processing without parallelization.

For example, when the scaling factor is 101%, the number of output lines is 101, which exceeds the maximum number of lines of 16 in this embodiment, and so this number of output lines cannot be used as is. Therefore, the number of output lines is set to 16, which is the same as the maximum number of lines. Also, the number of input lines is set to 15, which is calculated by multiplying the number of output lines by the inverse of the scaling factor (100/101) and truncating the decimal part.

Then, the CPU 100 sets the above-mentioned parameters in the hardware and executes sequential processing. Figure 9 shows an example of sequential processing in S603, in which, for an input of 15 lines, 16 lines are output only when the output range is a multiple of 101, and 15 lines are output otherwise, thereby achieving 101% enlargement.

<Effects of this embodiment>
In this embodiment, the first condition regarding the magnification ratio is that both the number of input lines and the number of output lines as the number of lines before and after magnification can be expressed as integers and are equal to or less than the maximum number of lines. By using this condition, when performing image processing including magnification processing on image data, it becomes possible to appropriately select whether to execute the processing in parallel or sequentially in the image processing unit. Therefore, it becomes possible to optimally select the execution time of the processing.

In addition, possible criteria for simply determining whether parallelization by an image processing circuit is possible are whether the result of multiplying the number of input lines by the scaling factor is an integer, or whether the scaling factor is an integer. If the former is adopted as the first condition, when the number of input lines is fixed, it is possible to easily make a determination by simply multiplying the number of input lines by the scaling factor, and the optimal control method for the image processing circuit can be selected. On the other hand, if the latter is adopted as the first condition, it is possible to select the optimal control method for the image processing circuit in the enlargement process by simply determining the scaling factor as it is.

In this embodiment, as shown in FIG. 7, an example has been described in which parallel processing is performed on consecutive band areas. However, as shown in FIG. 8, after dividing one page of image data 702 into the number of pieces that can be processed in parallel (the so-called parallelism; in FIG. 8, the image processing unit 105 has three image processing circuits 501, so the parallelism is 3), parallel processing may be performed on non-consecutive band areas.

Second Embodiment
In the first embodiment, a configuration in which either parallel processing or sequential processing is selectively performed is shown (see FIG. 6). In contrast, in the present embodiment, a configuration in which parallel processing is performed as the first image processing and sequential processing is performed as the second image processing is shown. In the following description, the same content as in the previous embodiment will be omitted as appropriate, and the description will focus on the differences from the previous embodiment.

<Image processing including magnification change processing>
Image processing including the variable magnification process in this embodiment will be described below with reference to Fig. 10. Note that this embodiment also uses the image processing device 10 and the image processing unit 105 having the same configuration as those in the first embodiment (see Figs. 1 and 5).

S1000 to S1002 are similar to S600 to S602 in the first embodiment (see Figure 6).

At S1003, the CPU 100 determines whether the second condition is satisfied.

In this way, the second condition is determined based on the magnification ratio and the degree of parallelism (the number of image processing circuits). If the determination result of S1003 is true, the process proceeds to S1004. On the other hand, if the determination result of S1003 is false, the process proceeds to S1006.

For example, in the case of triple parallel processing, the time required for parallel processing as the first round of image processing by hardware is one-third of the time required for sequential processing without parallel processing, thereby reducing the time equivalent to two-thirds of the time that would have been required if sequential processing had been performed. Therefore, if the time required for sequential processing as the second round of image processing by hardware can be reduced to less than this two-thirds of the time, it can be said to be more efficient than sequential processing of the entire image data. In other words, if the number of unprocessed pixels in the image data is reduced to less than two-thirds of the total image data as a result of parallel processing as the first round of image processing by hardware, the condition of S1003 is met.

Here, if the scaling factor is 0.51x, the first condition is not met but the second condition is met, so the result is NO in S1001 and YES in S1003, and the process proceeds to S1004. Also, if the scaling factor is 0.99x, the result is NO in S1001 and NO in S1003, and the process proceeds to S1006, so neither the first nor the second condition is met.

At S1004, the CPU 100 divides the user's desired scaling factor (hereinafter referred to as the desired scaling factor) into a first scaling factor and a second scaling factor. Here, the first scaling factor is a scaling factor whose numerator and denominator are both expressed as integers, and the second scaling factor is derived by dividing the desired scaling factor by the first scaling factor. After dividing the desired scaling factor, the image processing unit 105 executes parallel processing using the first scaling factor to perform high-speed image processing. Then, the image data obtained by the parallel processing by the image processing unit 105 is temporarily stored in the RAM 101.

Here, the denominator in the first magnification ratio is fixed at 16, the maximum number of lines, and the magnification ratio resulting from the first and second magnification ratios is equal to or greater than the magnification ratio resulting from the desired magnification ratio. For example, if the desired magnification ratio is 51%, the first magnification ratio will be 9/16, and the second magnification ratio will be 0.51÷(9÷16)=0.91.

In S1005, the image processing unit 105 reads the image data temporarily stored in S1004 from the RAM 101, and sequentially performs image processing on the read image data, including magnification processing according to the second magnification ratio.

At S1006, the image processing unit 105 sequentially performs image processing including scaling processing according to the desired scaling factor.

In the above embodiment, overhead in control is ignored. Therefore, in practice, faster processing can be achieved more reliably by using a threshold smaller than the predetermined threshold that corresponds to two-thirds of the time required for sequential processing in the first image processing run by hardware.

In addition, in the above embodiment, an example was shown in which the parallelism was three, i.e., the image processing unit had three image processing circuits, but the more parallelism there is, the more time it is possible to save for the second image processing by hardware.

As another use case for reducing and copying an image, there is a case where two original pages are copied onto one sheet of paper (so-called 2-in-1). In such a case, the condition used in S1003 may be a simple condition of whether the original image is reduced by image scaling. If such a condition is used, the user does not need to separately set the scaling factor.

<Effects of this embodiment>
In this embodiment, a form in which parallel processing and sequential processing are executed by one image processing circuit (hardware) (S1004 to S1005 in FIG. 10) has been described. However, there are cases in which the CPU 100 is in a state of not doing anything (so-called idle state) during the hardware processing, in which case resources are not effectively utilized. Therefore, as shown in FIG. 11, the second image processing is made to be executed by the CPU 100 as software processing (S1105), and the hardware processing and software processing are run in parallel, thereby realizing high-speed processing. However, since it is considered that the processing performance is lower when the image processing is executed by the CPU than when the image processing is executed by the image processing circuit, the above-mentioned judgment condition of less than two-thirds of the time may be reviewed, and a judgment condition based on the performance of the CPU and memory may be used.

Moreover, recent CPUs are often multi-core. On the other hand, image processing devices may execute multiple jobs in parallel to speed up processing. When more than half of the multiple CPU cores are idle (specifically, for example, when the CPU usage rate is less than 50%), it is highly likely that there are no jobs being executed in parallel, or that a job with a low load is being executed. Therefore, in such cases, it is possible to make effective use of resources by using the CPU to perform image processing, including magnification processing, sequentially.

As described above, in this embodiment, the second condition regarding the magnification ratio is that the formula (1) is satisfied. By using this condition, when performing image processing including magnification processing on image data, the image processing circuit can first execute parallel processing and then execute sequential processing, thereby shortening the execution time of the processing.

[Third embodiment]
In the above embodiment, an example was shown in which an image was scaled at a desired scale, but there were cases in which parallel processing could not be performed depending on the scale (S603 in FIG. 6, 1006 in FIG. 10). Therefore, in this embodiment, in a specific operation mode, parallel processing is always performed to meet high-speed processing requirements.

<Image processing including magnification change processing>
Image processing including the variable magnification process in this embodiment will be described below with reference to Fig. 12. Note that this embodiment also uses the image processing device 10 and image processing unit 105 having the same configuration as in the first embodiment (see Figs. 1 and 5).

At S1200, the CPU 100 determines whether the image processing device 10 is operating in a specific operation mode. If the determination result at S1200 is true, the process proceeds to S1201. On the other hand, if the determination result at S1200 is false, the process proceeds to the processing of the first or second embodiment described above. Note that the specific operation mode may be, for example, a mode that prioritizes processing speed, such as a draft mode when the image processing device 10 is a printer, or a pre-scan mode or a high-compression PDF creation mode when the image processing device 10 is a scanner.

In S1202, the CPU 100 performs the same determination as in S601 in the first embodiment (see FIG. 6). If the determination result in S1202 is true, the process proceeds to S1204. On the other hand, if the determination result in S1202 is false, the process proceeds to S1203.

At S1203, the CPU 100 performs a conversion process (called approximate conversion) that approximates the desired magnification ratio to a magnification ratio that can be processed in parallel by the image processing unit 105. The approximate conversion method, for example, assigns the number of input lines to the denominator and the number of output lines to the numerator, and further changes the denominator from 1 to the maximum number of lines. Then, by changing the numerator from 1 to the maximum number of lines for each changed denominator, the denominator and numerator that minimize the error from the desired magnification ratio are selected. For example, in the case of 101% enlargement as exemplified in the first embodiment, 1/1 is used as the magnification ratio that can be processed in parallel by the image processing unit 105. Also, in the case of 51% reduction as exemplified in the second embodiment, 1/2 is used as the magnification ratio that can be processed in parallel by the image processing unit 105.

In S1204, the image processing unit 105 performs parallel processing. In this step, if the determination in S1202 is true, the desired scaling factor is used as is, whereas if the determination is false, the scaling factor approximated in S1203 is used.

<Effects of this embodiment>
As described above, in this embodiment, the third condition is that the image processing device is operating in a specific operation mode. By using this condition, when image processing including magnification processing is performed on image data, parallel processing is always performed by the image processing circuit depending on the operation mode. Therefore, it is possible to optimize the execution time of image processing depending on the operation mode.

[Other embodiments]
The present invention can also be realized by a process in which a program for realizing one or more functions of the above-mentioned embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) for realizing one or more functions. The above-mentioned embodiments may be used in appropriate combination.

10 Image processing device 100 CPU
105 Image processing unit

Claims (15)

A dividing means for dividing an area of monochrome image data into a plurality of band areas;
an image processing means for performing image processing including a magnification process for changing a size of the band area acquired by the dividing means according to a predetermined magnification, the image processing means including a plurality of image processing circuits each performing the same operation, in parallel;
An apparatus having
a calculation means for calculating an input line number indicating the number of lines of the band area input to the image processing circuit and an output line number indicating the number of lines of the band area output from the image processing circuit, based on the predetermined magnification ratio;
when both the number of input lines and the number of output lines are smaller than a maximum number of lines indicating a maximum number of lines of the band area that can be processed by the image processing circuit, the image processing means performs image processing on a plurality of the band areas in parallel;
An apparatus comprising: each of the number of input lines and the number of output lines is an integer;
2. The apparatus of claim 1 . the calculation means converts the predetermined scaling factor into a fraction whose numerator and denominator are both integers, and calculates the number of input lines and the number of output lines by multiplying the numerator and denominator by an integer.
3. Apparatus according to claim 1 or 2. the integer-multiplied denominator and the integer-multiplied numerator are equal to or less than the maximum number of lines;
4. The apparatus according to claim 3. A dividing means for dividing an area of monochrome image data into a plurality of band areas;
an image processing means for performing image processing including a magnification process for changing a size of the band area acquired by the dividing means according to a predetermined magnification, the image processing means including a plurality of image processing circuits each performing the same operation, in parallel;
An apparatus having
when a value obtained by multiplying the input line number indicating the number of lines of the band area input to the image processing circuit by the predetermined magnification is an integer, the image processing means performs image processing on the plurality of band areas in parallel.
An apparatus comprising: A dividing means for dividing an area of monochrome image data into a plurality of band areas;
an image processing means for performing image processing including a magnification process for changing a size of the band area acquired by the dividing means according to a predetermined magnification, the image processing means including a plurality of image processing circuits each performing the same operation, in parallel;
An apparatus having
When the predetermined magnification ratio is an integer, the image processing means performs image processing on the plurality of band regions in parallel.
An apparatus comprising: 7. The apparatus according to claim 1, further comprising a first determination means for determining whether the following formula (1) is satisfied:

The device according to any one of claims 1 to 6, further comprising a first determination means for determining whether the original image is reduced by resizing according to the magnification ratio. a derivation unit that derives a first magnification ratio and a second magnification ratio based on the predetermined magnification ratio when the result of the determination by the first determination unit is true,
the first magnification factor is a magnification factor whose numerator and denominator are both expressed as integers,
The second magnification ratio is derived by dividing the predetermined magnification ratio by the first magnification ratio.
9. Apparatus according to claim 7 or 8. The image processing means includes:
the image processing for the plurality of band regions using the first magnification ratio is performed in parallel at the same time;
performing the image processing using the second magnification ratio sequentially;
10. The apparatus of claim 9. A CPU,
a first determination means for determining whether the CPU usage rate is less than a predetermined threshold;
a derivation means for deriving a first magnification ratio and a second magnification ratio based on the predetermined magnification ratio when a result of the determination by the first determination means is true;
and
the image processing means performs the image processing for the plurality of band regions using the first magnification ratio in parallel and simultaneously;
the CPU sequentially performs the image processing using the second magnification ratio;
7. Apparatus according to any one of the preceding claims. A second determination means for determining whether the device is operating in a specific operation mode;
a conversion means for converting the predetermined magnification ratio into a value that can be processed by the image processing means when the result of the determination by the second determination means is true;
12. Apparatus according to any one of claims 7 to 11, further comprising: the image processing means is provided with a first image processing circuit, a second image processing circuit, and a third image processing circuit as the plurality of image processing circuits;
If the input image data is RGB color image data,
the first image processing circuit performs the image processing on the R color image data,
the second image processing circuit performs the image processing on the G color image data,
the third image processing circuit performs the image processing on the B color image data;
13. Apparatus according to any one of the preceding claims. A dividing means for dividing an area of monochrome image data into a plurality of band areas;
an image processing means for performing image processing including a magnification process for changing a size of the band area acquired by the dividing means according to a predetermined magnification, the image processing means including a plurality of image processing circuits each performing the same operation, in parallel;
1. A method carried out in an apparatus having
calculating an input line number indicating the number of lines of the band area input to the image processing circuit and an output line number indicating the number of lines of the band area output from the image processing circuit based on the predetermined magnification ratio;
when both the number of input lines and the number of output lines are smaller than a maximum number of lines that indicates a maximum number of lines of the band area that can be processed by the image processing circuit, the image processing means performs image processing on a plurality of the band areas in parallel;
The method according to claim 1, further comprising: A program for causing a computer to execute the method according to claim 14.

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