JP7546012B2 - Chip Resistors - Google Patents

Description

The present invention relates to a chip resistor.

The internal electrodes (top, back and side electrodes) constituting part of the electrodes of the chip resistor mainly contain Ag. When sulfur gas ( _H2S , _SO2 , etc.) is present in the surrounding environment of the electronic device in which the chip resistor is used, the internal electrodes combine with the sulfur gas to produce black silver sulfide ( _Ag2S ). Since silver sulfide has electrical insulation properties, if the sulfurization of the internal electrodes progresses, the internal electrodes may break, i.e., the electrodes of the chip resistor may break.

For these reasons, as disclosed in Patent Document 1, for example, chip resistors have been known in which the material of the upper electrode of the internal electrodes is an Ag-Pd alloy. Although the Ag-Pd alloy is a material with excellent sulfur resistance, it has the disadvantage of being expensive and therefore less economical.

Patent Document 1 also discloses a chip resistor that further includes a top electrode that is located on the top electrode and is made of an epoxy resin containing metal particles such as Ag and carbon particles. The top electrode is less susceptible to sulfurization than the top electrode, and is less expensive than an electrode made of an Ag-Pd alloy. Therefore, a chip resistor that includes a top electrode has the advantage of being economical while also having sulfurization resistance.

Here, the chip resistor with the top electrode has a Ni plating layer (intermediate electrode) covering the top electrode. The top electrode contains carbon particles. The higher the carbon particle content, the better the sulfurization resistance of the top electrode. However, if the carbon particle content exceeds a specified amount, the adhesion between the Ni plating layer and the top electrode decreases, and the Ni plating layer may peel off. If the Ni plating layer peels off, sulfur gas may penetrate to the internal electrodes (top electrode and side electrode), and there is a concern that the electrodes of the chip resistor may break due to the progression of sulfurization of the internal electrodes.

In addition, typically, the surface of the resistor is covered with a protective film made of a paste containing epoxy resin, as in the chip resistor disclosed in Patent Document 2.

Depending on how the chip resistor is used, the temperature of the Ni plating layer (intermediate electrode) covering the internal electrode may rise significantly. At this time, a thermal shock may occur at the tip of the Ni plating layer (the boundary between the Ni plating layer and the protective film in a plan view). If this thermal shock acts on the protective film, a crack will occur in the protective film. If this crack progresses toward the internal electrode, the internal electrode will be exposed. At this time, if sulfur gas is present in the environment surrounding the electronic device in which the chip resistor is used, the internal electrode may combine with the sulfur gas as mentioned above, and the electrode of the chip resistor may break.

JP 2013-258292 A JP 2012-151195 A

In view of the above-mentioned circumstances, the present invention aims to provide a chip resistor and a manufacturing method thereof that improves anti-sulfuration performance while suppressing costs. In view of the above-mentioned circumstances, the present invention also aims to provide a chip resistor and a manufacturing method thereof that can prevent disconnection of the electrode due to sulfuration even if a crack develops in the protective film due to thermal shock occurring on the electrode.

The chip resistor provided by the first aspect of the present invention is a chip resistor comprising: a substrate having a mounting surface and a mounting surface facing in opposite directions; a pair of upper electrodes arranged on both ends of the mounting surface of the substrate; a portion arranged on the side of the substrate between the mounting surface and the mounting surface of the substrate; and a portion overlapping the mounting surface and the mounting surface when viewed in the thickness direction of the substrate, the side electrode being conductive to the upper electrodes; a resistor mounted on the mounting surface of the substrate between the pair of upper electrodes; an intermediate electrode covering the side electrodes; and an external electrode covering the intermediate electrode. The chip resistor is characterized by having a first protective layer that is less susceptible to sulfurization than the upper electrode, which is located between the upper electrode and the intermediate electrode and is arranged in contact with the upper electrode and the side electrode; and a second protective layer that is conductive and is located between the first protective layer and the intermediate electrode and is arranged in contact with the first protective layer, the side electrode, and the intermediate electrode.

In the practice of the present invention, the first protective layer preferably contains carbon particles.

In the practice of the present invention, the first protective layer is preferably an electrical insulator.

In the practice of the present invention, the second protective layer preferably contains Ag.

In the practice of the present invention, the side electrodes are preferably made of a Ni-Cr alloy.

In the implementation of the present invention, preferably, the substrate further includes a pair of back electrodes arranged on both ends of the mounting surface, and the side electrodes are electrically connected to the back electrodes.

In the practice of the present invention, the back electrode is preferably covered by the intermediate electrode.

In the practice of the present invention, the substrate is preferably an electrical insulator.

In the practice of the present invention, the substrate is preferably made of alumina.

In the practice of the present invention, the resistor preferably has a serpentine shape in plan view.

In the practice of the present invention, the resistor preferably comprises RuO ₂ or an Ag-Pd alloy.

In the implementation of the present invention, preferably, a trimming groove penetrating the resistor is formed in the resistor.

In the practice of the present invention, the intermediate electrode and the external electrode preferably consist of a plating layer.

In the practice of the present invention, the intermediate electrode preferably comprises a Ni plating layer.

In the practice of the present invention, the external electrodes preferably consist of a Sn-plated layer.

In the implementation of the present invention, it is preferable to further include a protective film that covers the resistor and a portion of the upper electrode.

In the practice of the present invention, preferably, a portion of the first protective layer is covered with the protective film.

In the practice of the present invention, the protective film preferably has a lower protective film and an upper protective film.

In the practice of the present invention, the lower protective film preferably includes glass.

In the practice of the present invention, the upper protective film preferably contains an epoxy resin.

The method for manufacturing a chip resistor provided by the second aspect of the present invention is characterized by comprising the steps of: preparing a sheet-like substrate having a mounting surface and a mounting surface facing opposite each other; forming an upper surface electrode having a pair of regions spaced apart from each other on the mounting surface of the sheet-like substrate; mounting a resistor that is conductive to the upper surface electrode on a region of the mounting surface of the sheet-like substrate sandwiched between the pair of regions; forming a first protective layer that is less susceptible to sulfurization than the upper surface electrode on the upper surface of the upper surface electrode; forming a second protective layer that is conductive on the upper surface of the first protective layer; dividing the sheet-like substrate into a plurality of strip-like substrates; forming side electrodes that are conductive to the upper surface electrode and in contact with the first protective layer and the second protective layer on the side surfaces, the mounting surface, and the mounting surface located along both ends of the longitudinal direction of the strip-like substrate; and forming an intermediate electrode that covers the side electrode and the second protective layer, and an external electrode that covers the intermediate electrode.

In carrying out the present invention, preferably, in the step of forming the first protective layer, the first protective layer is formed by a method using printing.

In carrying out the present invention, preferably, in the step of forming the second protective layer, the second protective layer is formed by a method using printing.

In carrying out the present invention, preferably, in the step of forming the side electrode, the side electrode is formed by physical vapor deposition.

In the practice of the present invention, the physical vapor deposition is preferably a sputtering method.

In the implementation of the present invention, preferably, in the step of mounting the resistor, the resistor is mounted by a method using printing or a method using physical vapor deposition and photolithography.

In carrying out the present invention, it is preferable to further include a step of dividing the belt-shaped substrate into a plurality of individual pieces before the step of forming the intermediate electrode and the external electrode.

In carrying out the present invention, preferably, in the steps of forming the intermediate electrode and the external electrode, the intermediate electrode and the external electrode are formed by plating.

The present invention preferably further includes a step of forming a back electrode having a pair of regions spaced apart from each other on the mounting surface of the sheet-like substrate.

In carrying out the present invention, it is preferable to further include a step of forming a trimming groove in the resistor that penetrates the resistor.

The present invention preferably further includes a step of forming a protective film that covers the resistor, the upper electrode, and each of a portion of the first protective layer.

In the practice of the present invention, the step of forming the protective film preferably includes a step of forming a lower protective film and a step of forming an upper protective film.

The chip resistor provided by the third aspect of the present invention is a chip resistor comprising: a substrate having a mounting surface and an assembly surface facing in opposite directions; a pair of upper electrodes arranged on both ends of the mounting surface of the substrate; a resistor mounted between the pair of upper electrodes on the mounting surface of the substrate; a protective film covering the resistor and a part of the upper electrodes; a part arranged on the side of the substrate between the mounting surface and the assembly surface of the substrate; a part overlapping the mounting surface and the assembly surface in a plan view of the substrate; and a side electrode electrically connected to the upper electrode; an intermediate electrode covering the side electrode; and an external electrode covering the intermediate electrode, the protective film having a lower protective film and an upper protective film laminated together, the lower protective film being made of a material more resistant to thermal shock than the upper protective film, and a part of the upper electrode being covered by the lower protective film.

In the practice of the present invention, preferably, a portion of each of the upper electrode and the upper protective film is covered by the side electrode.

In the implementation of the present invention, preferably, a protective layer that covers at least a portion of the upper surface of the upper electrode and has properties that make it less susceptible to sulfurization than the upper electrode is provided, and at least a portion of the protective layer is covered by the side electrode.

In the practice of the present invention, preferably, a portion of the protective layer is covered by the upper protective film.

In the practice of the present invention, the protective layer preferably contains carbon particles.

In the practice of the present invention, the protective layer is preferably an electrical insulator.

In the practice of the present invention, the lower protective film preferably includes glass.

In the practice of the present invention, the upper protective film preferably contains an epoxy resin.

In the practice of the present invention, the side electrodes are preferably made of a Ni-Cr alloy.

In the implementation of the present invention, preferably, the substrate further includes a pair of back electrodes arranged on both ends of the mounting surface, and the side electrodes are electrically connected to the back electrodes.

In the practice of the present invention, the back electrode is preferably covered by the intermediate electrode.

In the practice of the present invention, the substrate is preferably an electrical insulator.

In the practice of the present invention, the substrate is preferably made of alumina.

In the implementation of the present invention, preferably, a trimming groove penetrating the resistor is formed in the resistor.

In the practice of the present invention, the intermediate electrode and the external electrode preferably consist of a plating layer.

In the practice of the present invention, the intermediate electrode preferably comprises a Ni plating layer.

In the practice of the present invention, the external electrodes preferably consist of a Sn-plated layer.

The method for manufacturing a chip resistor provided by the fourth aspect of the present invention is characterized by comprising the steps of: preparing a sheet-like substrate having a mounting surface and a mounting surface facing in opposite directions; forming an upper surface electrode having a pair of regions spaced apart from each other on the mounting surface of the sheet-like substrate; mounting a resistor that is conductive to the upper surface electrode on a region of the mounting surface of the sheet-like substrate sandwiched between the pair of regions; forming a lower protective film that covers the resistor and a part of the upper surface electrode; forming an upper protective film that covers the lower protective film; dividing the sheet-like substrate into a plurality of strip-like substrates; forming side electrodes that are conductive to the upper surface electrode on the side surfaces, the mounting surface, and the mounting surface located along both ends of the longitudinal direction of the strip-like substrate; and forming intermediate electrodes that cover the side electrodes and external electrodes that cover the intermediate electrodes.

In the practice of the present invention, preferably, in the step of forming the side electrode, the side electrode is formed by covering a portion of each of the top electrode and the upper protective film with the side electrode.

The present invention preferably further includes a step of forming a protective layer that covers at least a portion of the upper surface of the upper electrode and has characteristics that make it less susceptible to sulfurization than the upper electrode.

In carrying out the present invention, preferably, in the step of forming the protective layer, the protective layer is formed by a printing method.

In carrying out the present invention, preferably, in the step of forming the side electrode, the side electrode is formed by covering at least a portion of the protective layer with the side electrode.

In carrying out the present invention, preferably, in the step of forming the upper protective film, a portion of the protective layer is covered with the upper protective film, thereby forming the upper protective film.

In carrying out the present invention, preferably, in the step of forming the lower protective film, the lower protective film is formed by a method using printing.

In the practice of the present invention, preferably, in the step of forming the upper protective film, the upper protective film is formed by a method using printing.

In carrying out the present invention, preferably, in the step of forming the side electrode, the side electrode is formed by physical vapor deposition.

In the practice of the present invention, the physical vapor deposition is preferably a sputtering method.

In carrying out the present invention, preferably, in the process of forming the intermediate electrode and the external electrode, the intermediate electrode and the external electrode are formed by plating.

In carrying out the present invention, it is preferable to further include a step of dividing the belt-shaped substrate into a plurality of individual pieces before the step of forming the intermediate electrode and the external electrode.

The present invention preferably further includes a step of forming a back electrode having a pair of regions spaced apart from each other on the mounting surface of the sheet-like substrate.

In carrying out the present invention, it is preferable to further include a step of forming a trimming groove in the resistor that penetrates the resistor.

The chip resistor according to the present invention has a first protective layer located between the upper electrode and the intermediate electrode and arranged in contact with the upper electrode and the side electrode. Therefore, the upper electrode is configured to be covered with the first protective layer. The first protective layer has a property that is less susceptible to sulfurization than the upper electrode. Therefore, the first protective layer prevents the upper electrode from being sulfurized, and disconnection of the upper electrode is avoided. In addition to the first protective layer, the chip resistor according to the present invention has a second protective layer located between the first protective layer and the intermediate electrode and arranged in contact with the first protective layer, the side electrode, and the intermediate electrode. The first protective layer is configured to be covered with the second protective layer and the side electrode, which have conductivity. Therefore, the intermediate electrode is configured not to be in contact with the first protective layer. Therefore, peeling of the plating layer constituting the intermediate electrode can be avoided. As described above, by providing the first protective layer and the second protective layer, it is possible to improve the sulfurization resistance performance while suppressing the cost of the chip resistor.

The chip resistor according to the present invention has a lower protective film and an upper protective film laminated on each other, and a part of the upper electrode is covered by the lower protective film. The lower protective film is made of a material that is more resistant to thermal shock than the upper protective film. Therefore, even if a crack occurs in the upper protective film due to a thermal shock occurring at the tip of the plating layer, which is an intermediate electrode and an external electrode (the boundary between the plating layer and the upper protective film in a plan view), the lower protective film prevents the crack from progressing. Therefore, the upper electrode is not exposed due to the crack, and sulfur gas generated around the chip resistor does not enter the upper electrode through the crack. Therefore, even if a crack occurs in the upper protective film due to a thermal shock occurring to the electrode, it is possible to prevent the electrode from being broken due to sulfurization.

Other features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

1 is a plan view showing a chip resistor according to a first embodiment of the present invention; 2 is a cross-sectional view taken along line II-II in FIG. FIG. 3 is a partially enlarged cross-sectional view of a part of FIG. 2 . 2 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 1; 2 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 1; 2 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 1; 2 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 1; 2 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 1; 2 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 1; 2 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 1; 2 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 1; 2 is a perspective view showing a process for manufacturing the chip resistor shown in FIG. 1; 2 is a perspective view showing a process for manufacturing the chip resistor shown in FIG. 1; 2 is a perspective view showing a process for manufacturing the chip resistor shown in FIG. 1; 2 is a perspective view showing a process for manufacturing the chip resistor shown in FIG. 1; FIG. 11 is a plan view showing a chip resistor according to a second embodiment of the present invention. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 16. FIG. 13 is a plan view showing a chip resistor according to a third embodiment of the present invention. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. FIG. 20 is a partially enlarged cross-sectional view of a portion of FIG. 19 . 19 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 18. 19 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 18. 19 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 18. 19 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 18. 19 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 18. 19 is a plan view showing a process for manufacturing the chip resistor shown in FIG. 18. 19 is a perspective view showing a process for manufacturing the chip resistor shown in FIG. 18. 19 is a perspective view showing a process for manufacturing the chip resistor shown in FIG. 18. 19 is a perspective view showing a process for manufacturing the chip resistor shown in FIG. 18. 19 is a perspective view showing a process for manufacturing the chip resistor shown in FIG. 18. FIG. 13 is a plan view showing a chip resistor according to a fourth embodiment of the present invention. This is a cross-sectional view taken along line XXXII-XXXII in Figure 31. FIG. 33 is a partially enlarged cross-sectional view of a portion of FIG. 32 . 32 is a plan view showing a process for manufacturing the chip resistor of FIG. 31.

The embodiment of the present invention will be described with reference to the attached drawings.

First Embodiment
A chip resistor A1 according to a first embodiment of the present invention will be described with reference to Figures 1 to 3. For ease of understanding, intermediate electrodes 34, external electrodes 35, and a protective film 5, which will be described later, are omitted from Figure 1.

The chip resistor A1 shown in these figures is of a type that is surface-mounted on the circuit board of various electronic devices. The chip resistor A1 of this embodiment comprises a substrate 1, a resistive element 2, an electrode 3, a protective layer 4, and a protective film 5. In this embodiment, the chip resistor A1 is rectangular in plan view. The chip resistor A1 of this embodiment is a so-called thick-film (metal glaze film) chip resistor.

As shown in Figures 1 and 2, the substrate 1 is a member for mounting the resistive element 2 and for mounting the chip resistor A1 on a circuit board of various electronic devices. The substrate 1 is an electrical _insulator . In this embodiment, the substrate 1 is made of alumina ( _Al2O3 ), for example. In order to easily dissipate heat generated by the resistive element 2 to the outside when the chip resistor A1 is in use, the substrate 1 is preferably made of a material with high thermal conductivity. The substrate 1 has a mounting surface 11, a mounting surface 12, and a side surface 13. In this embodiment, the substrate 1 is rectangular in plan view.

The mounting surface 11 is the upper surface of the substrate 1 shown in FIG. 2, and is the surface on which the resistor 2 is mounted. The mounting surface 12 is the lower surface of the substrate 1 shown in FIG. 2, and is the surface used when mounting the chip resistor A1 to a circuit board of various electronic devices. The mounting surface 11 and the mounting surface 12 face in opposite directions. As shown in FIGS. 1 and 2, the side surface 13 is a pair of surfaces that are perpendicular to the mounting surface 11 and the mounting surface 12 and face in the longitudinal direction of the substrate 1 (direction X shown in FIG. 1). The side surface 13 is located between the mounting surface 11 and the mounting surface 12.

The resistor 2 is an element that performs functions such as limiting or detecting a current. In this embodiment, the resistor 2 has a strip shape extending in the direction X shown in FIG. 1 in a plan view. The resistor 2 is made of a paste containing a metal such as _RuO2 or an Ag-Pd alloy. In this embodiment, the resistor 2 has a strip shape in a plan view, but the shape may be any shape, such as a serpentine shape. The resistor 2 has a trimming groove 21.

As shown in Figs. 1 and 2, the trimming groove 21 is a groove that penetrates the resistor 2 in the thickness direction. The trimming groove 21 forms an opening on the side surface along the longitudinal direction of the resistor 2 (direction X shown in Fig. 1). In this embodiment, the trimming groove 21 that is L-shaped in plan view is formed in the resistor 2. The trimming groove 21 is formed to adjust the resistance value of the resistor 2 to a specified value.

As shown in Figs. 1 to 3, the electrodes 3 are a pair of spaced apart members that are electrically connected to the resistor 2 and interconnect the chip resistor A1 with the wiring pattern of the circuit board of various electronic devices. The electrodes 3 are disposed on both sides of the resistor 2 in the direction X shown in Fig. 1. In this embodiment, the electrodes 3 include a top electrode 31, a back electrode 32, a side electrode 33, an intermediate electrode 34, and an external electrode 35.

As shown in Figs. 1 to 3, the top electrode 31 has a pair of regions that are spaced apart and disposed at both ends on the mounting surface 11 of the substrate 1. The top electrode 31 is rectangular in plan view. A portion of the top electrode 31 is sandwiched between the mounting surface 11 and the resistor 2. Therefore, the resistor 2 is electrically connected to the top electrode 31. The top electrode 31 is made of a paste containing Ag, for example.

As shown in Figs. 1 to 3, the back electrode 32 has a pair of regions that are spaced apart from each other and disposed at both ends on the mounting surface 12 of the substrate 1. The shape of the back electrode 32 in a plan view is substantially the same as that of the top electrode 31 (not shown). Like the top electrode 31, the back electrode 32 is made of a paste that contains, for example, Ag. Note that the back electrode 32 can be omitted.

As shown in Figs. 1 to 3, the side electrode 33 has a pair of regions that are spaced apart from each other and are arranged on the side surface 13 of the substrate 1. The side electrode 33 covers parts of the top electrode 31, the back electrode 32, and the protective layer 4 in addition to the side surface 13. That is, the side electrode 33 has a portion arranged on the side surface 13 and a portion that overlaps with the mounting surface 11 and the mounting surface 12 of the substrate 1 when viewed in the thickness direction of the substrate 1. The top electrode 31 and the back electrode 32 are electrically connected to each other by the side electrode 33. Therefore, the resistor 2 is electrically connected to the back electrode 32 by the top electrode 31 and the side electrode 33. In this embodiment, the side electrode 33 is made of, for example, a Ni-Cr alloy. The material of the side electrode 33 may be any metal that is conductive and has properties that are difficult to sulfurize.

As shown in Figs. 2 and 3, the intermediate electrode 34 is a pair of parts that are spaced apart from each other and cover the back electrode 32, the side electrode 33, and the protective layer 4. In this embodiment, the intermediate electrode 34 is made of, for example, a Ni plating layer. The intermediate electrode 34 functions to protect the electrode 3 from heat and impact.

As shown in Figures 2 and 3, the external electrodes 35 are a pair of spaced apart portions that cover the intermediate electrode 34. In this embodiment, the external electrodes 35 are made of, for example, a Sn plating layer. When solder is applied to the external electrodes 35 and the external electrodes 35 are integrated with the solder, the chip resistor A1 is interconnected with the wiring patterns of the circuit boards of various electronic devices. In this embodiment, since the intermediate electrode 34 is made of a Ni plating layer, it is difficult to apply solder directly to the intermediate electrode 34. Therefore, an external electrode 35 made of a Sn plating layer is required.

As shown in Figures 1 to 3, the protective layer 4 is a pair of members spaced apart from each other and covers at least a portion of the upper electrode 31. In this embodiment, the protective layer 4 has a first protective layer 41 and a second protective layer 42. The protective layer 4 serves to prevent sulfurization of the upper electrode 31.

The first protective layer 41 has a pair of regions spaced apart from each other and formed on the upper surface of the upper electrode 31 shown in FIG. 2 and FIG. 3. The first protective layer 41 is less susceptible to sulfurization than the upper electrode 31. The first protective layer 41 is located between the upper electrode 31 and the intermediate electrode 34, and is disposed in contact with the upper electrode 31 and the side electrode 33. In this embodiment, the first protective layer 41 is made of a paste containing glass and a metal oxide such as Ru, carbon particles (carbon black), and an epoxy resin. In this case, the first protective layer 41 is conductive. Here, the first protective layer 41 may be an electrical insulator. The first protective layer 41, which is an electrical insulator, is made of a paste containing, for example, glass.

The second protective layer 42 has a pair of regions spaced apart from each other and formed on the upper surface of the first protective layer 41 shown in Figures 2 and 3. The second protective layer 42 is conductive. The second protective layer 42 is located between the first protective layer 41 and the intermediate electrode 34, and is disposed in contact with the first protective layer 41, the side electrode 33, and the intermediate electrode 34. In this embodiment, the second protective layer 42 is made of a paste containing, for example, Ag and an epoxy resin.

As shown in Figs. 1 to 3, the protective film 5 is a member that covers the resistor 2 and functions to protect the resistor 2 from the outside. The protective film 5 has a lower protective film 51 and an upper protective film 52. The lower protective film 51 covers the surface of the resistor 2 (the upper surface of the resistor 2 shown in Fig. 2). The lower protective film 51 is made of a paste containing glass, for example. The upper protective film 52 covers a part of the substrate 1, the resistor 2, and a part of the upper electrode 31. In this embodiment, a part of the first protective layer 41 is covered by the upper protective film 52. Here, a part of the upper protective film 52 may be covered by the first protective layer 41. The upper protective film 52 is made of a paste containing epoxy resin, for example.

Next, a method for manufacturing the chip resistor A1 will be described with reference to Figures 4 to 15. Figures 4 to 11 are plan views showing the steps involved in the method for manufacturing the chip resistor A1. Figures 12 to 15 are perspective views showing the steps involved in the method for manufacturing the chip resistor A1. For ease of understanding, the lower protective film 51 of the protective film 5 is omitted in Figures 10 to 15. For ease of understanding, Figures 12 and 13 ignore the respective thicknesses of the resistor 2, upper electrode 31, side electrode 33, first protective layer 41, second protective layer 42 and upper protective film 52.

First, as shown in FIG. 4, a sheet-like substrate 81 made of alumina is prepared. The sheet-like substrate 81 has a mounting surface 11 and a mounting surface 12. The mounting surface 11 and the mounting surface 12 face in opposite directions. FIG. 4 shows the mounting surface 11 of the sheet-like substrate 81. On the mounting surface 11, a plurality of primary division grooves 811 are formed in the vertical direction shown in FIG. 4, and a plurality of secondary division grooves 812 are formed in the horizontal direction shown in FIG. 4 in a checkerboard pattern. The same number of primary division grooves 811 and secondary division grooves 812 are also formed on the mounting surface 12 opposite to the mounting surface 11 (not shown). The positions of the primary division grooves 811 and secondary division grooves 812 in a plan view are the same on both the mounting surface 11 and the mounting surface 12. The section formed by the primary division grooves 811 and the secondary division grooves 812 is the area corresponding to the substrate 1 of the chip resistor A1.

5, an upper electrode 31 is formed on the mounting surface 11 of the sheet-like substrate 81 so as to straddle the primary division groove 811 of the sheet-like substrate 81. In addition, a back electrode 32 is formed on the mounting surface 12 of the sheet-like substrate 81 so as to straddle the primary division groove 811 (not shown). The positions and sizes of the upper electrode 31 and the back electrode 32 in a plan view are approximately the same. In this embodiment, the upper electrode 31 and the back electrode 32 are formed by printing a paste containing Ag and glass frit on the mounting surface 11 and the mounting surface 12 using a silk screen, respectively, and firing in a firing furnace. Through this process, the upper electrode 31 and the back electrode 32 having a pair of regions spaced apart from each other are formed on the mounting surface 11 and the mounting surface 12.

Next, as shown in FIG. 6, the resistor 2 that is conductive to the upper electrode 31 is mounted on the mounting surface 11 of the sheet-like substrate 81 in the region sandwiched between the pair of regions of the upper electrode 31. In this embodiment, the resistor 2 is mounted by printing a paste made of a metal such as RuO2 or an Ag-Pd alloy containing glass frit using a silk screen, and then firing it in a firing furnace.

7, a first protective layer 41 having a property of being less susceptible to sulfurization than the upper electrode 31 is formed on the upper surface of the upper electrode 31 and in the region sandwiched by the resistor 2. In this embodiment, the first protective layer 41 is formed by printing a paste containing glass and metal oxide such as Ru, carbon particles, and epoxy resin using a silk screen and hardening it. In this case, the first protective layer 41 has electrical conductivity. When the first protective layer 41 is an electrical insulator, it is formed by printing a paste containing glass using a silk screen and baking it in a baking furnace. Here, when forming the first protective layer 41 having electrical conductivity, a gap is provided between the first protective layer 41 and the resistor 2 in a plan view so that the first protective layer 41 does not contact the resistor 2. This is because the resistance value of the chip resistor A1 fluctuates when the first protective layer 41 contacts the resistor 2. By this process, a part of the upper electrode 31 is covered with the first protective layer 41.

Next, as shown in FIG. 8, a conductive second protective layer 42 is formed on the upper surface of the first protective layer 41. In this embodiment, the second protective layer 42 is formed by printing a paste containing Ag and epoxy resin using a silk screen and then curing it. When forming the second protective layer 42, the first protective layer 41 is exposed at the end of the second protective layer 42 adjacent to the resistor 2. By this process, a part of the first protective layer 41 is covered with the second protective layer 42.

Next, as shown in FIG. 9, a lower protective film 51 is formed to cover the surface of the resistor 2. In this embodiment, the lower protective film 51 is formed by printing a paste containing glass using a silk screen and firing it in a firing furnace. In the process of forming the trimming groove 21 in the resistor 2, which is the process after the above process, the groove is formed by a laser, so that a thermal shock acts on the resistor 2 and fine particles are generated in the resistor 2. Therefore, the lower protective film 51 functions to alleviate the thermal shock and prevent the fine particles from reattaching to the resistor 2, which would cause the resistance value of the resistor 2 to fluctuate.

Next, as shown in FIG. 10, a trimming groove 21 penetrating the resistor 2 is formed in the resistor 2. The trimming groove 21 is formed by a laser trimming device (not shown). The procedure for forming the trimming groove 21 is as follows. First, the trimming groove 21 is formed from one side to the other side of a pair of side surfaces along the longitudinal direction of the resistor 2 so as to be perpendicular to the direction of the current flowing through the resistor 2. Next, after the resistance value of the resistor 2 rises to a value close to the required value of the chip resistor A1, the trimming groove 21 is formed by changing the direction by 90° so as to be parallel to the direction of the current flowing through the resistor 2 (the longitudinal direction of the resistor 2). When the resistance value of the resistor 2 reaches the required value of the chip resistor A1, the formation of the trimming groove 21 is completed. By this process, a trimming groove 21 having an L-shape in plan view is formed in the resistor 2. The trimming groove 21 is formed with a probe (not shown) for measuring the resistance value in contact with both longitudinal ends of the resistor 2.

11, an upper protective film 52 is formed on the mounting surface 11 of the sheet-like substrate 81. At this time, in addition to the resistor 2, a part of each of the upper electrode 31 and the first protective layer 41 is covered by the upper protective film 52. The second protective layer 42 is not covered by the upper protective film 52. In this embodiment, the upper protective film 52 is formed in a plurality of strips extending along the primary dividing groove 811 of the sheet-like substrate 81 so as to straddle the secondary dividing groove 812 of the sheet-like substrate 81. In this embodiment, the upper protective film 52 is formed by printing a paste containing an epoxy resin using a silk screen and hardening it. The upper protective film 52 may be formed so as to be separated for each resistor 2, similar to the lower protective film 51 of the protective film 5 shown in FIG. 9.

Next, as shown in FIG. 12, the sheet-like substrate 81 is cut along the primary dividing grooves 811 of the sheet-like substrate 81 to divide it into a plurality of strip-like substrates 86. At this time, side surfaces 13 are formed on both sides of the strip-like substrate 86 along the longitudinal direction of the strip-like substrate 86.

Next, as shown in FIG. 13, side electrodes 33 are formed on the side surfaces 13 located along both ends of the longitudinal direction of the belt-shaped substrate 86 and on parts of the mounting surface 11 and the mounting surface 12. In this embodiment, the side electrodes 33 are formed by depositing a Ni-Cr alloy film by physical vapor deposition (PVD) such as sputtering. When forming the side electrodes 33, the side surfaces 13 and parts of the surfaces of the second protective layer 42 and the back electrode 32 arranged perpendicular to the side surfaces 13 are integrally covered by the side electrodes 33 (the back electrode 32 is not shown). At this time, the side electrodes 33 contact the ends of the second protective layer 42, the first protective layer 41, the upper electrode 31, and the back electrode 32 along the side surfaces 13. This process allows the upper electrode 31 and the back electrode 32 to be electrically connected to each other by the side electrodes 33.

Next, as shown in FIG. 14, the belt-shaped substrate 86 is cut at the secondary dividing grooves 812 of the belt-shaped substrate 86 and divided into a plurality of individual pieces 87. At this time, the shape of the side electrode 33 becomes a U-shape that sandwiches the substrate 1. The side electrode 33 is also formed on a portion of the mounting surface 11 and the mounting surface 12 of the substrate 1, which are located at both ends of the side electrode 33 formed on a portion of the surface of each of the second protective layer 42 and the back electrode 32 (the back electrode 32 is not shown).

Next, as shown in FIG. 15, an intermediate electrode 34 that covers the back electrode 32, the side electrode 33, and the second protective layer 42, and an external electrode 35 that covers the intermediate electrode 34 are formed on the individual piece 87 (the back electrode 32 is not shown). In this embodiment, the intermediate electrode 34 is formed by Ni plating, and the external electrode 35 is formed by Sn plating. This process forms a pair of electrodes 3 that are conductive to the resistor 2. Through the above processes, the chip resistor A1 is manufactured.

Next, we will explain the effects of chip resistor A1.

According to this embodiment, the chip resistor A1 has a first protective layer 41 that is located between the top electrode 31 and the intermediate electrode 34 and is disposed in contact with the top electrode 31 and the side electrode 33. Therefore, at least a portion of the top electrode 31 is covered with the first protective layer 41. The first protective layer 41 contains carbon particles, and therefore has the characteristic of being less susceptible to sulfurization than the top electrode 31. Therefore, the first protective layer 41 prevents the top electrode 31 from being sulfurized, and disconnection of the top electrode 31 is avoided.

In addition to the first protective layer 41, the chip resistor A1 also has a second protective layer 42 that is located between the first protective layer 41 and the intermediate electrode 34 and is disposed in contact with the first protective layer 41, the side electrode 33, and the intermediate electrode 34. The second protective layer 42 is conductive because it contains Ag. The first protective layer 41 is covered with the second protective layer 42 and the side electrode 33, which is also conductive. Therefore, the intermediate electrode 34 is not in contact with the first protective layer 41, which contains carbon particles. Therefore, peeling of the Ni plating layer that is the intermediate electrode 34 can be avoided.

As described above, by providing a first protective layer 41 that is less susceptible to sulfurization than the upper electrode 31 that contains carbon particles, and a second protective layer 42 that contains Ag and has electrical conductivity, it is possible to reduce the cost of the chip resistor A1 while improving its sulfurization resistance.

Most of the sulfurization gas that causes sulfurization of the upper electrode 31 and the like in the chip resistor A1 enters the chip resistor A1 along the interface between the plating layer that constitutes the intermediate electrode 34 and the external electrode 35 and the upper protective film 52 of the protective film 5. Therefore, by configuring the first protective layer 41 so that a portion of it is covered by the upper protective film 52, the effect of blocking the sulfurization gas that enters along the interface is greater. Note that even if the first protective layer 41 is configured to cover a portion of the upper protective film 52, the sulfurization resistance of the chip resistor A1 is ensured.

If sulfurizing gas enters along the interface, the second protective layer 42 containing Ag will be preferentially sulfurized. In other words, the second protective layer 42 performs a function similar to that of a sacrificial electrode. In addition, since the second protective layer 42 is configured not to come into contact with the top electrode 31 due to the first protective layer 41 and the side electrode 33, even if the second protective layer 42 is sulfurized, the top electrode 31 will not be sulfurized. Therefore, by having the second protective layer 42 containing Ag, it is possible to further improve the sulfurization resistance performance of the chip resistor A1.

By using a Ni-Cr alloy as the material for the side electrode 33, which is conductive and resistant to sulfurization, the side electrode 33 will not sulfurize. This avoids disconnection of the side electrode 33 and prevents sulfurization of the top electrode 31 via the side electrode 33. In addition, since the side electrode 33 is formed by physical vapor deposition using a sputtering method or the like, the first protective layer 41 in contact with the side electrode 33 can be made an electrical insulator. In this case, the first protective layer 41 is made of a paste containing glass, for example, which makes it possible to further reduce the cost of the chip resistor A1.

Second Embodiment
A chip resistor A2 according to a second embodiment of the present invention will be described with reference to Fig. 16 and Fig. 17. In these figures, elements that are the same as or similar to those of the chip resistor A1 described above are given the same reference numerals, and duplicated descriptions will be omitted.

For ease of understanding, FIG. 16 omits the intermediate electrode 34, the external electrode 35, and the protective film 5. In this embodiment, the chip resistor A2 is rectangular in plan view.

The chip resistor A2 of this embodiment differs from the chip resistor A1 in the planar shape of the resistor 2 and the configuration of the protective film 5. In this embodiment, the planar shape of the resistor 2 is serpentine. The resistor 2 of this shape can be formed by a method using photolithography after mounting the resistor 2 on the mounting surface 11 of the substrate 1 by physical vapor deposition such as sputtering. In this case, the resistor 2 is made of, for example, a Ni-Cr alloy. In other words, the chip resistor A2 of this embodiment is a so-called thin film chip resistor. Also, in this embodiment, the lower protective film 51 of the protective film 5 is omitted.

Next, we will explain the effects of chip resistor A2.

In this embodiment, like the chip resistor A1, the chip resistor A2 is provided with a first protective layer 41 that is less susceptible to sulfurization than the upper electrode 31 that contains carbon particles, and a second protective layer 42 that contains Ag and has electrical conductivity, thereby making it possible to reduce the cost of the chip resistor A2 while improving its sulfurization resistance. In addition, by making the planar shape of the resistor 2 serpentine, the resistance value of the chip resistor A2 can be made relatively higher than that of the chip resistor A1, and the accuracy of the resistance value can be improved.

Third Embodiment
A chip resistor A3 according to a third embodiment of the present invention will be described with reference to Figures 18 to 20. In these figures, elements that are the same as or similar to those of the chip resistor A1 described above are given the same reference numerals, and duplicated descriptions will be omitted.

For ease of understanding, FIG. 18 omits the intermediate electrode 34 and the external electrode 35. The chip resistor A3 of this embodiment is a so-called thick-film chip resistor, similar to the chip resistor A1. In this embodiment, the chip resistor A3 is rectangular in plan view.

The chip resistor A3 of this embodiment differs from the chip resistor A1 in that the protective layer 4 is omitted and the configuration of the electrodes 3 and protective film 5 is different.

The electrode 3 in this embodiment, like the chip resistor A1, has a top electrode 31, a back electrode 32, a side electrode 33, an intermediate electrode 34, and an external electrode 35. Of these, the configurations of the side electrode 33, the intermediate electrode 34, and the external electrode 35 differ from those of the chip resistor A1.

As shown in Figs. 18 to 20, the side electrode 33 is a portion disposed on the side surface 13 of the substrate 1. The side electrode 33 covers the side surface 13 as well as a portion of the top electrode 31, the back electrode 32, and the upper protective film 52. That is, the side electrode 33 has a portion disposed on the side surface 13 and a portion overlapping the mounting surface 11 and the mounting surface 12 of the substrate 1 in a plan view of the substrate 1. The side electrode 33 provides electrical continuity between the top electrode 31 and the back electrode 32. Therefore, the resistor 2 is electrically connected to the back electrode 32 by the top electrode 31 and the side electrode 33. In this embodiment, the side electrode 33 is made of, for example, a Ni-Cr alloy. The material of the side electrode 33 may be any metal that is electrically conductive and difficult to sulfurize.

As shown in Figures 19 and 20, the intermediate electrode 34 is a portion that covers the back electrode 32 and the side electrode 33. In this embodiment, the intermediate electrode 34 is made of, for example, a Ni plating layer.

As shown in Figures 19 and 20, the external electrode 35 is a portion that covers the intermediate electrode 34. In this embodiment, the external electrode 35 is made of, for example, a Sn plating layer.

As shown in Figures 18 to 20, the protective film 5 is a member that covers the resistor 2 and functions to protect the resistor 2 from the outside. The protective film 5 has a lower protective film 51 and an upper protective film 52. The lower protective film 51 and the upper protective film 52 are laminated on top of each other. The lower protective film 51 and the upper protective film 52 are both electrical insulators. In this embodiment, the lower protective film 51 is made of a material that is more resistant to thermal shock than the upper protective film 52.

The lower protective film 51 is a portion that covers the resistor 2. The lower protective film 51 is located below the upper protective film 52 shown in Figs. 19 and 20. The lower protective film 51 covers not only the resistor 2 but also part of the surface of the upper electrode 31 (the upper surface of the upper electrode 31 shown in Figs. 19 and 20). As shown in Fig. 18, the lower protective film 51 extends outward toward the side surface 13 of the substrate 1 beyond the boundary between the side electrode 33 and the upper protective film 52 in a plan view of the chip resistor A3. The lower protective film 51 is made of a paste containing glass, for example.

The upper protective film 52 is a portion that covers each part of the substrate 1 and the upper electrode 31, and the lower protective film 51 that covers the resistor 2. The upper protective film 52 is located above the lower protective film 51 shown in Figures 19 and 20. In this embodiment, a portion of the upper protective film 52 is covered by the side electrode 33. The upper protective film 52 is made of a paste containing, for example, epoxy resin.

Next, the method for manufacturing the chip resistor A3 will be described with reference to Figures 21 to 30. Figures 21 to 6 are plan views showing the steps in the method for manufacturing the chip resistor A3. Figures 27 to 30 are perspective views showing the steps in the method for manufacturing the chip resistor A3. For ease of understanding, Figures 27 and 28 ignore the thicknesses of the resistor 2, upper electrode 31, side electrode 33, lower protective film 51, and upper protective film 52.

First, as shown in FIG. 21, a sheet-like substrate 81 made of alumina is prepared. The sheet-like substrate 81 has a mounting surface 11 and a mounting surface 12. The mounting surface 11 and the mounting surface 12 face in opposite directions. FIG. 21 shows the mounting surface 11 of the sheet-like substrate 81. On the mounting surface 11, a plurality of primary division grooves 811 are formed in the vertical direction shown in FIG. 21, and a plurality of secondary division grooves 812 are formed in the horizontal direction shown in FIG. 21 in a checkerboard pattern. The same number of primary division grooves 811 and secondary division grooves 812 are formed on the mounting surface 12 as on the mounting surface 11 (not shown). The positions of the primary division grooves 811 and secondary division grooves 812 in a plan view are the same on both the mounting surface 11 and the mounting surface 12. The section formed by the primary division grooves 811 and the secondary division grooves 812 is the region that becomes the substrate 1 of the chip resistor A3.

22, an upper electrode 31 is formed on the mounting surface 11 of the sheet-like substrate 81 so as to straddle the primary division groove 811 of the sheet-like substrate 81. In addition, a back electrode 32 is formed on the mounting surface 12 of the sheet-like substrate 81 so as to straddle the primary division groove 811 (not shown). The positions of the upper electrode 31 and the back electrode 32 in a plan view are approximately the same. In this embodiment, the upper electrode 31 and the back electrode 32 are formed by printing a paste containing Ag and glass frit on the mounting surface 11 and the mounting surface 12 using a silk screen, respectively, and firing in a firing furnace. Through this process, the upper electrode 31 and the back electrode 32 having a pair of regions spaced apart from each other are formed on the mounting surface 11 and the mounting surface 12.

Next, as shown in FIG. 23, the resistor 2 that is conductive to the upper electrode 31 is mounted on the mounting surface 11 of the sheet-like substrate 81 in the region sandwiched between the pair of regions of the upper electrode 31. In this embodiment, the resistor 2 is mounted by printing a paste made of a metal such as RuO2 or an Ag-Pd alloy containing glass frit using a silk screen, and then firing it in a firing furnace.

Next, as shown in FIG. 24, a lower protective film 51 is formed to cover the surface of the resistor 2. In this embodiment, the lower protective film 51 is formed by printing a paste containing glass using a silk screen and firing it in a firing furnace. Through this process, the surface of the resistor 2 and a part of the upper electrode 31 are covered with the lower protective film 51.

25, a trimming groove 21 penetrating the resistor 2 is formed in each resistor 2. The trimming groove 21 is formed by a laser trimming device (not shown). The procedure for forming the trimming groove 21 is the same as the procedure for forming the trimming groove 21 in the chip resistor A1 shown in FIG. 10 described above. This process forms the trimming groove 21 in an L-shape in plan view in the resistor 2. The trimming groove 21 is formed with a probe (not shown) for measuring resistance in contact with the exposed portion of a pair of upper electrodes 31 that sandwich the resistor 2.

26, the upper protective film 52 is formed on the mounting surface 11 of the sheet-like substrate 81. At this time, the lower protective film 51 covering the surface of the resistor 2 and a part of the upper electrode 31, and a part of the upper electrode 31 are covered by the upper protective film 52. In this embodiment, the upper protective film 52 is formed in a plurality of strips extending along the primary dividing groove 811 of the sheet-like substrate 81 so as to straddle the secondary dividing groove 812 of the sheet-like substrate 81. In this embodiment, the upper protective film 52 is formed by printing a paste containing epoxy resin using a silk screen and hardening it. Note that the upper protective film 52 may be formed so as to be separated for each resistor 2, similar to the lower protective film 51 shown in FIG. 24.

Next, as shown in FIG. 27, the sheet-like substrate 81 is cut along the primary dividing grooves 811 of the sheet-like substrate 81 to divide it into a plurality of belt-like substrates 86. At this time, side surfaces 13 are formed on both sides of the belt-like substrate 86 along the longitudinal direction of the belt-like substrate 86.

28, side electrodes 33 are formed on the side surfaces 13 located along both ends of the longitudinal direction of the belt-shaped substrate 86 and on parts of the mounting surface 11 and the mounting surface 12. In this embodiment, the side electrodes 33 are formed by depositing a Ni-Cr alloy by physical vapor deposition such as sputtering. When forming the side electrodes 33, the side electrodes 33 are integrally covered with the side surfaces 13 and parts of the surfaces of the upper electrode 31, the back electrode 32, and the upper protective film 52 arranged perpendicular to the side surfaces 13 (the back electrode 32 is not shown). At this time, the side electrodes 33 contact the ends of the upper electrode 31 and the back electrode 32 along the side surfaces 13. This process allows the upper electrode 31 and the back electrode 32 to be electrically connected to each other by the side electrodes 33.

29, the belt-shaped substrate 86 is cut at the secondary dividing grooves 812 of the belt-shaped substrate 86 and divided into a plurality of individual pieces 87. At this time, the shape of the side electrode 33 becomes a U-shape that sandwiches the substrate 1. The side electrode 33 is also formed on parts of the mounting surface 11 and the mounting surface 12 of the substrate 1, which are located on both sides of the side electrode 33 formed on parts of the surfaces of the upper electrode 31 and the back electrode 32.

Next, as shown in FIG. 30, an intermediate electrode 34 that covers the back electrode 32 and the side electrode 33, and an external electrode 35 that covers the intermediate electrode 34 are formed on the individual piece 87 (the back electrode 32 is not shown). In this embodiment, the intermediate electrode 34 is formed by Ni plating, and the external electrode 35 is formed by Sn plating. This process forms a pair of electrodes 3 that are conductive to the resistor 2. Through the above process, the chip resistor A3 is manufactured.

Next, we will explain the effects of chip resistor A3.

According to this embodiment, the chip resistor A3 has a lower protective film 51 and an upper protective film 52 laminated to each other, and a part of the upper electrode 31 is covered by the lower protective film 51. The lower protective film 51 is made of a material that is more resistant to thermal shock than the upper protective film 52. Therefore, even if a crack occurs in the upper protective film 52 due to a thermal shock occurring at the tip of the plating layer that is the intermediate electrode 34 and the external electrode 35 (the boundary between the plating layer and the upper protective film 52 in a plan view), the lower protective film 51 suppresses the progression of the crack. Therefore, since the upper electrode 31 is not exposed due to the crack, the sulfur gas generated around the chip resistor A3 does not enter the upper electrode 31 through the crack. Therefore, even if a crack occurs in the upper protective film 52 due to a thermal shock occurring on the electrode 3, it is possible to prevent the electrode 3 from being broken due to sulfurization.

By using a Ni-Cr alloy, which is conductive and resistant to sulfurization, as the material for the side electrode 33, sulfurization of the side electrode 33 is suppressed. This prevents the side electrode 33 from breaking, and also prevents the top electrode 31 from sulfurizing through the side electrode 33. In addition, since the side electrode 33 is formed by physical vapor deposition using a method such as sputtering, the adhesion performance with the upper protective film 52, which is an electrical insulator, is improved. This prevents the Ni plating layer, which is the intermediate electrode 34, from peeling off along with the side electrode 33, eliminating the concern that a part of the top electrode 31 would be exposed due to the peeling and that the exposed part would be sulfurized.

Fourth Embodiment
A chip resistor A4 according to a fourth embodiment of the present invention will be described with reference to Figures 31 to 33. In these figures, elements that are the same as or similar to those of the chip resistor A1 described above are given the same reference numerals, and duplicated descriptions will be omitted.

For ease of understanding, FIG. 31 omits the intermediate electrode 34 and the external electrode 35. The chip resistor A4 of this embodiment is a so-called thick-film chip resistor, similar to the chip resistor A1. In this embodiment, the chip resistor A4 is rectangular in plan view.

The chip resistor A4 of this embodiment differs from the chip resistor A1 in the configuration of the protective layer 4 and protective film 5.

As shown in Figs. 31 to 33, the protective layer 4 is a member having a pair of regions spaced apart from each other and formed on the upper surface of the upper electrode 31. The protective layer 4 has a property of being less susceptible to sulfurization than the upper electrode 31. In this embodiment, the protective layer 4 covers a part of each of the upper electrode 31 and the lower protective film 51. The protective layer 4 does not have to cover a part of the lower protective film 51. In this embodiment, each part of the protective layer 4 is covered by the side electrode 33 and the upper protective film 52, respectively, and is in contact with the side electrode 33 on the surface aligned with the side surface 13 of the substrate 1. The protective layer 4 according to this embodiment is made of a paste containing glass and metal oxide such as Ru, carbon particles (carbon black), and epoxy resin, as with the first protective layer 41 of the chip resistor A1. In this case, the protective layer 4 is conductive. The protective layer 4 may be an electrical insulator made of a paste containing glass, for example.

As shown in Figures 31 to 33, the protective film 5 is a member that covers the resistor 2 and functions to protect the resistor 2 from the outside. The protective film 5 has a lower protective film 51 and an upper protective film 52. The lower protective film 51 and the upper protective film 52 are laminated on top of each other. The lower protective film 51 and the upper protective film 52 are both electrical insulators. The material of the lower protective film 51 in this embodiment is the same as that of the lower protective film 51 of the chip resistor A3, and the material of the upper protective film 52 is the same as that of the chip resistor A3.

The lower protective film 51 is a portion that covers the resistor 2. The lower protective film 51 is located below the upper protective film 52 shown in Figures 32 and 33. As with the chip resistor A3, the lower protective film 51 covers not only the resistor 2 but also part of the surface of the upper electrode 31 (the upper surface of the upper electrode 31 shown in Figures 32 and 33). As shown in Figure 31, the lower protective film 51 extends outward toward the side surface 13 of the substrate 1 beyond the boundary between the side electrode 33 and the upper protective film 52 in a plan view of the chip resistor A4.

The upper protective film 52 is a portion that covers each of the substrate 1 and the protective layer 4, and the lower protective film 51 that covers the resistor 2. The upper protective film 52 is located above the lower protective film 51 shown in Figures 32 and 33. In this embodiment, a portion of the upper protective film 52 contacts the side electrode 33, the intermediate electrode 34, and the external electrode 35.

Next, a method for manufacturing the chip resistor A4 will be described with reference to FIG. 34. In the manufacturing of the chip resistor A3 described above, the steps of preparing the sheet-like substrate 81 shown in FIG. 21 and FIG. 22, forming the upper electrode 31, mounting the resistor 2 shown in FIG. 23, forming the lower protective film 51 shown in FIG. 24, and forming the trimming groove 21 shown in FIG. 25 are the same in the manufacturing of the chip resistor A4.

As shown in FIG. 34, after forming the trimming groove 21 in the resistor 2, a protective layer 4 having a property of being less susceptible to sulfurization than the upper electrode 31 is formed in the portion where the upper electrode 31 is exposed. In this embodiment, the protective layer 4 is formed by printing a paste containing glass and a metal oxide such as Ru, carbon particles, and epoxy resin using a silk screen and hardening it. In this case, the protective layer 4 is conductive. When the protective layer 4 is to be an electrical insulator, it is formed by printing a paste containing glass using a silk screen and firing it in a firing furnace. Through this process, the portion where the upper electrode 31 is exposed and a part of the lower protective film 51 are covered with the protective layer 4.

Next, an upper protective film 52 is formed on the mounting surface 11 of the sheet-like substrate 81. At this time, the lower protective film 51, which covers the surface of the resistor 2 and part of the upper electrode 31, and part of the protective layer 4 are covered by the upper protective film 52. The method of forming the upper protective film 52 is the same as the method of forming the upper protective film 52 in the process of the method of manufacturing the chip resistor A3 shown in FIG. 26. After forming the upper protective film 52, the process of manufacturing the chip resistor A4 is the same as that of the chip resistor A3.

Next, we will explain the effects of chip resistor A4.

In this embodiment, as in the chip resistor A3, a portion of the upper electrode 31 is covered with the lower protective film 51, so that even if a crack occurs in the upper protective film 52 due to a thermal shock to the electrode 3, it is possible to prevent disconnection of the electrode 3 due to sulfurization. In addition, by providing the protective layer 4, the upper surface of the upper electrode 31 is covered by the protective layer 4 in addition to the lower protective film 51. The protective layer 4 has characteristics that make it less susceptible to sulfurization than the upper electrode 31. Therefore, it is possible to further improve the sulfurization resistance of the chip resistor A4 compared to the chip resistor A3.

The chip resistor according to the present invention is not limited to the above-mentioned embodiment. The specific configuration of each part of the chip resistor according to the present invention can be freely designed in various ways.

A1, A2, A3, A4: Chip resistor 1: Substrate 11: Mounting surface 12: Mounting surface 13: Side surface 2: Resistor 21: Trimming groove 3: Electrode 31: Top electrode 32: Back electrode 33: Side electrode 34: Intermediate electrode 35: External electrode 4: Protective layer 41: First protective layer 42: Second protective layer 5: Protective film 51: Lower protective film 52: Upper protective film 81: Sheet-like substrate 811: Primary dividing groove 812: Secondary dividing groove 86: Band-like substrate 87: Individual piece X: Direction

Claims (9)

a substrate having a mounting surface and a mounting surface facing in opposite directions and a side surface located between the mounting surface and the mounting surface;
A pair of upper surface electrodes disposed on both ends of the mounting surface;
a resistor mounted on the mounting surface between the pair of upper surface electrodes;
a protective film that covers the resistor and a portion of each of the pair of upper electrodes;
a side electrode having a first portion disposed on the side surface, a second portion overlapping the mounting surface in a plan view, and a third portion overlapping the mounting surface in a plan view , the side electrode being electrically connected to one of the pair of upper surface electrodes;
an intermediate electrode covering the side electrode;
an outer electrode covering the intermediate electrode;
the protective film includes a lower protective film and an upper protective film laminated on the lower protective film,
a material having a thermal shock resistance greater than that of the upper protective film is distributed throughout the lower protective film;
each of the pair of upper electrodes has a first surface and a second surface facing the same side as the mounting surface;
the second surface is located between the first surface and the first portion in a first direction in which the pair of upper surface electrodes are separated from each other,
the first surface is entirely covered with the lower protective film,
the second surface is entirely covered with the upper protective film,
a dimension of the first surface in the first direction is greater than a dimension of the second surface in the first direction;
a portion of either of the pair of upper electrodes and a portion of the upper protective film are covered by the second portion ,
In the plan view, the second portion, the intermediate electrode, and the external electrode all overlap the lower protective film. The chip resistor according to claim 1, wherein the lower protective film includes glass. The chip resistor according to claim 1 or 2, wherein the upper protective film contains an epoxy resin. A pair of back electrodes are disposed on both ends of the mounting surface,
4. The chip resistor according to claim 1 , wherein the side electrode is electrically connected to one of the pair of rear electrodes . The chip resistor according to claim 4 , wherein one of the pair of rear electrodes is covered with the intermediate electrode . 6. The chip resistor according to claim 1, wherein the resistor element has a trimming groove formed therein and penetrating the resistor element . The chip resistor according to claim 1 , wherein the intermediate electrode and the external electrodes are made of a plating layer . The chip resistor according to claim 7 , wherein the intermediate electrode is made of a Ni plating layer . The chip resistor according to claim 7 , wherein the external electrodes are made of a Sn plating layer .

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