JP7221759B2 - time measurement circuit - Google Patents

Description

The present invention relates to a time measurement circuit capable of highly accurate time measurement.

A technique called TDC (Time-to-Digital Converter) using gate delay of a logic circuit (see Non-Patent Document 1) is widely known for high-resolution time measurement on the order of psec. This TDC is generally configured based on a DLL (Delay Locked Loop) or a PLL (Phase Locked Loop). There is a problem that it is difficult to realize low power consumption because it is necessary to operate the TDC before starting measurement.

For example, ultrasonic flowmeters for gas meters need to measure the difference in ultrasonic propagation time with low power consumption, high accuracy, and high resolution, so the operating period of the high-speed counter (oscillation period of the high-speed clock) must be as short as possible. There is However, as described above, the DLL-type TDC and the PLL-type TDC require time to stabilize the oscillation of the delay circuit, so the oscillation period of the high-speed clock becomes longer, which is disadvantageous in terms of power consumption.

When aiming at low power consumption operation by minimizing the operation time of the TDC (oscillation time of the high-speed clock), for example, a ring oscillator type configuration disclosed in Patent Document 1 is conceivable.
FIG. 25 is a circuit diagram showing the configuration of a conventional ring oscillator type TDC. A ring oscillator type TDC receives a 1-bit binary number "1"(1'b1) as a D input, an oscillation start signal ROSC_START as a clock input, an oscillation stop signal ROSC_STOP as a reset input, and outputs an oscillation enable signal TDC_EN. It consists of a flip-flop circuit 10, a ring oscillator 11 that generates a high-speed clock TAP[2] during a period when the oscillation enable signal TDC_EN is significant, and a high-speed counter 12 that counts the high-speed clock.

FIG. 26 is a timing chart for explaining the operation of the ring oscillator type TDC of FIG. The D flip-flop circuit 10 receives a 1-bit binary number "1" (1'b1) as a D input, an oscillation start signal ROSC_START as a clock input, and an oscillation stop signal ROSC_STOP as a reset input. It outputs an oscillation enable signal TDC_EN that becomes significant (High) at the rise of the start signal ROSC_START and becomes insignificant (Low) at the rise of the oscillation stop signal ROSC_STOP.

The ring oscillator 11 includes a NAND circuit 110 that takes a NAND circuit of an oscillation enable signal TDC_EN and a high-speed clock TAP[2], a buffer circuit 111-1 that receives the output TAP[0] of the NAND circuit 110, and a buffer circuit. A buffer circuit 111-2 receives the output TAP[1] of 111-1 and outputs the output TAP[2] as a high-speed clock. The ring oscillator 11 generates a clock TAP[2] faster than the low-speed clock (ROSC_STOP) as shown in FIG. 26 while the oscillation enable signal TDC_EN output from the D flip-flop circuit 10 is significant.
The high-speed counter 12 counts the rises of the high-speed clock TAP[2] and outputs the counting result HS_CNT.

However, in the ring oscillator type TDC shown in FIG. 25, depending on the timing of the oscillation stop signal ROSC_STOP, as indicated by 100 in FIG. There is a problem that the oscillator 11 outputs and the value of the count result HS_CNT of the high-speed counter 12 becomes unstable, making it impossible to measure the correct time. Hereinafter, in the present invention, a minute width pulse generated at such an unintended timing is called a glitch.

For example, assuming that the frequency of the high-speed clock TAP[2], which is the output of the ring oscillator 11, is 600 MHz, the fact that the count value of the high-speed counter 12 increases by "1" due to a glitch means that the measured time value is 1.00% higher than the expected value. 67 nsec is a large value. Ultrasonic flowmeters such as those disclosed in Patent Document 1 are required to measure time with sub-nano-order accuracy to measure minute flow rates, so the measured flow rate value differs from the expected value by ±1.67 ns. Specifications cannot meet product specifications.

Japanese Patent No. 4661714

Stephan Henzler, “Time-to-Digital Converters,” Springer, 2010

SUMMARY OF THE INVENTION It is an object of the present invention to provide a time measuring circuit capable of realizing low power consumption operation and accurate time measurement.

The time measuring circuit (first embodiment) of the present invention is configured to output an oscillation enable signal that becomes significant at the timing of input of a start signal from the outside and becomes insignificant at the timing of input of a stop signal from the outside. an oscillation circuit configured to generate a first clock during a period in which the oscillation enable signal is significant; the first clock; and a second clock obtained by inverting the first clock. a first counter configured to count a first clock masked with the stop signal; and a first counter configured to count a first clock masked with the stop signal; a second counter configured to count a second clock that has been received, and a counter that does not generate a clock input with an unacceptable time width among the count results of the first and second counters and a selector configured to select the counting result obtained by and the time interval from the input of the start signal to the input of the stop signal based on the counting result selected by the selector after the input of the stop signal and a time calculator configured to calculate the time.

In one configuration example of the time measurement circuit of the present invention, the selector operates the first counter when the phase of the first clock is in a range from 0° to less than a predetermined first phase value smaller than 180°. and selecting the counting result of the second counter when the phase of the first clock is less than a predetermined second phase value of 180° or more and less than 360° from the first phase value is selected, and the count result of the first counter is selected in the range where the phase of the first clock is greater than or equal to the second phase value and less than 360 degrees.
Further, in one configuration example of the time measurement circuit of the present invention, the logic circuit includes a buffer circuit that receives a first clock output from the oscillation circuit, and a buffer circuit that receives the first clock output from the oscillation circuit. an inverter configured to generate the inverted second clock; a first OR circuit configured to OR-mask the first clock output from the buffer circuit with the stop signal; and a second OR circuit configured to OR-mask the second clock output from the inverter with the stop signal.

Further, the time measuring circuit (second embodiment) of the present invention outputs an oscillation enable signal that becomes significant at the timing of the input of the start signal from the outside and becomes meaningless at the timing of the input of the stop signal from the outside. an oscillation circuit configured to generate a first clock during a significant period of the oscillation enable signal; and a second clock masked with the stop signal. a logic circuit configured to generate a clock; a first counter configured to count said first clock; a second counter configured to count said second clock; a selector configured to select a counting result obtained by one of the counting results of the first and second counters in which a clock input having an unacceptable time width does not occur; and the stop signal. and a time calculation unit configured to calculate the time interval from the input of the start signal to the input of the stop signal based on the count result selected by the selector after the input of be.

In one configuration example of the time measurement circuit of the present invention, the selector operates the second counter when the phase of the first clock is in a range from 0° to less than a predetermined first phase value smaller than 180°. and if the phase of the first clock is less than a predetermined second phase value of 180° or more and less than 360° from the first phase value, the counting result of the first counter is selected, and the counting result of the second counter is selected in the range where the phase of the first clock is greater than or equal to the second phase value and less than 360 degrees.
In one configuration example of the time measurement circuit of the present invention, the logic circuit is configured to OR-mask the first clock output from the oscillation circuit with the stop signal to generate the second clock. It is characterized by being composed of an OR circuit.

A time measurement circuit (third embodiment) of the present invention includes a test execution unit configured to test the time measurement circuit, a first start signal input from the outside during normal operation, a first A stop signal is selected and output, a second start signal and a second stop signal output from the test execution unit are selected and output during test execution, and a third stop signal is output when the test is completed. and an operation setting circuit configured as described above, which is significant at the timing of input of the first start signal or the second start signal and is insignificant at the timing of input of the first stop signal or the third stop signal an oscillation circuit configured to generate a first clock during a significant period of the oscillation enable signal; and the first clock; , a second clock obtained by inverting the first clock with the first stop signal or the second stop signal, respectively; and a logic circuit configured to mask the first stop signal or the second clock. a first counter configured to count a first clock masked with a second stop signal; and a second clock masked with the first stop signal or the second stop signal. and a counting result obtained by one of the counting results of the first and second counters that does not generate a clock input with an unacceptable time width is selected. and a time from the input of the first start signal to the input of the first stop signal based on the count result selected by the selector after the input of the first stop signal in normal times a time calculation unit configured to calculate an interval, wherein the test execution unit tests the oscillator circuit by comparing count results of the first and second counters during test execution. It is characterized by

In one configuration example of the time measurement circuit of the present invention, the selector operates the first counter when the phase of the first clock is in a range from 0° to less than a predetermined first phase value smaller than 180°. and selecting the counting result of the second counter when the phase of the first clock is less than a predetermined second phase value of 180° or more and less than 360° from the first phase value is selected, and the count result of the first counter is selected in the range where the phase of the first clock is greater than or equal to the second phase value and less than 360 degrees.
Further, in one configuration example of the time measurement circuit of the present invention, when the phase of the first clock is the value immediately before the first phase value, when the phase of the first clock is the first phase value, Alternatively, the counting result of the first counter and the counting result of the second counter at the time of the value immediately after the first phase value are obtained and compared, and further, the phase of the first clock is the phase of the first clock. The count result of the first counter and the count of the second counter at the time of the value immediately before the phase value of 2, at the time of the second phase value, or at the time of the value immediately after the second phase value It is characterized by acquiring and comparing the results.
Further, in one configuration example of the time measurement circuit of the present invention, the test execution unit detects the oscillation when the acquired count result of the first counter and the acquired count result of the second counter match. If the circuit is determined to be normal and the counting result of the first counter and the counting result of the second counter do not match, it is determined that the oscillation circuit is out of order. .

Further, in one configuration example of the time measurement circuit of the present invention, when the phase of the first clock is the value immediately before the first phase value, when the phase of the first clock is the first phase value, or when obtaining the counting result of the first counter and the counting result of the second counter at the value immediately after the first phase value, subtract 1 from the obtained counting result of the second counter. After that, the counting result of the first counter and the counting result of the second counter are compared.
Further, in one configuration example of the time measurement circuit of the present invention, the logic circuit includes a buffer circuit that receives a first clock output from the oscillation circuit, and a buffer circuit that receives the first clock output from the oscillation circuit. an inverter configured to generate the inverted second clock; and masking the first clock later than the second clock and masking the first clock later than the second clock during test execution. a fourth stop signal for canceling; and a fifth stop signal for masking the second clock before the first clock and canceling the mask before the first clock, a mask release timing control circuit configured to be generated from the second stop signal; and a first clock output from the buffer circuit that is OR-masked with the first stop signal or the fourth stop signal. and a second OR circuit configured to OR-mask the second clock output from the inverter with the first stop signal or the fifth stop signal wherein the oscillation circuit, the buffer circuit, and the inverter operate so that the second clock becomes significant before the first clock when the oscillation enable signal becomes significant. It is characterized by

In one configuration example of the time measurement circuit of the present invention, the time calculation unit calculates the count selected by the selector when the phase of the first clock is in the range of the first phase value or more and less than 360°. The time interval is calculated after subtracting 1 from the count result when the result is captured.
Further, in one configuration example of the time measurement circuit of the present invention, an encoder that outputs a signal indicating a phase value of the output of the oscillation circuit is further provided, and the selector performs the first 1 or the counting result of the second counter.

According to the present invention, a logic circuit for masking a first clock generated by an oscillation circuit and a second clock obtained by inverting the first clock with a stop signal, and a first clock masked with the stop signal. a first counter that counts the clock of the second clock masked by the stop signal; a second counter that counts the second clock masked by the stop signal; Low power consumption operation and accurate time measurement independent of the input timing of the stop signal can be realized by providing a selector for selecting the counting result obtained by the counter in which is not generated.

Further, in the present invention, a logic circuit that generates a second clock by masking a first clock generated by an oscillation circuit with a stop signal, a first counter that counts the first clock, and a second clock. A second counter for counting and a selector are provided for selecting the counting result obtained by the one of the counting results of the first and second counters in which the clock input of the unacceptable time width is not generated. As a result, low power consumption operation and accurate time measurement independent of the input timing of the stop signal can be realized.

Further, in the present invention, a logic circuit that masks a first clock generated by an oscillation circuit and a second clock obtained by inverting the first clock with a first stop signal or a second stop signal, respectively. , a first counter counting the first clock masked with the first stop signal or the second stop signal, and a second counter counting the second clock masked with the first stop signal or the second stop signal. 2 counters, and a selector for selecting the counting result obtained by the one of the counting results of the first and second counters in which the clock input of the unacceptable time width is not generated. , low power consumption operation and accurate time measurement independent of the input timing of the stop signal can be realized. Further, in the present invention, the oscillation circuit can be tested by providing the operation setting circuit and the test execution section.

FIG. 1 is a circuit diagram showing the configuration of a time measuring circuit according to a first embodiment of the invention. FIG. 2 is a timing chart explaining the operation of the time measuring circuit according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing the configuration of the edge detection circuit of the time measurement circuit according to the first embodiment of the present invention. FIG. 4 is a diagram showing the relationship between high-speed clocks and timing signals in the first embodiment of the present invention. FIG. 5 is a timing chart for explaining the method of correcting the count result of the high-speed clock in the first embodiment of the present invention. FIG. 6 is a timing chart for explaining the method of correcting the count result of the high-speed clock in the first embodiment of the present invention. FIG. 7 is a timing chart for explaining a method of correcting the counting result of high-speed clocks according to the first embodiment of the present invention. FIG. 8 is a timing chart for explaining the method of correcting the count result of the high-speed clock in the first embodiment of the present invention. FIG. 9 is a diagram for explaining whether correction of the counting result of the high-speed clock is necessary in the first embodiment of the present invention. FIG. 10 is a circuit diagram showing the configuration of a time measuring circuit according to the second embodiment of the invention. FIG. 11 is a diagram showing the relationship between high-speed clocks and timing signals in the second embodiment of the present invention. FIG. 12 is a timing chart for explaining a method of correcting the counting result of the high-speed clock in the second embodiment of the present invention. 13A and 13B are timing charts for explaining a method of correcting the count result of the high-speed clock in the second embodiment of the present invention. FIG. 14 is a timing chart for explaining a method of correcting the counting result of high-speed clocks in the second embodiment of the present invention. FIG. 15 is a timing chart for explaining a method of correcting the counting result of high-speed clocks according to the second embodiment of the present invention. 16A and 16B are diagrams for explaining the necessity of correction of the counting result of the high-speed clock in the second embodiment of the present invention. FIG. 17 is a circuit diagram showing the configuration of a time measuring circuit according to the third embodiment of the invention. FIG. 18 is a circuit diagram showing the configuration of the operation setting circuit of the time measuring circuit according to the third embodiment of the present invention. FIG. 19 is a circuit diagram showing the configuration of the mask release timing control circuit of the time measuring circuit according to the third embodiment of the present invention. FIG. 20 is a block diagram showing the configuration of the time calculator of the time measuring circuit according to the third embodiment of the present invention. FIG. 21 is a timing chart for explaining the test operation of the time measuring circuit according to the third embodiment of the present invention. FIG. 22 is a timing chart for explaining the operation of the mask release timing control circuit during testing of the time measuring circuit according to the third embodiment of the present invention. FIG. 23 is a timing chart for explaining the operation of the mask release timing control circuit during testing of the time measuring circuit according to the third embodiment of the present invention. FIG. 24 is a block diagram showing a configuration example of a computer that implements the time calculation section of the time measurement circuit according to the first to third embodiments of the present invention. FIG. 25 is a circuit diagram showing a configuration example of a conventional ring oscillator type TDC. FIG. 26 is a timing chart for explaining the operation of a conventional ring oscillator type TDC.

[First embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of a time measuring circuit according to the first embodiment of the present invention. The time measurement circuit receives a 1-bit binary number "1"(1'b1) as a D input, an external oscillation start signal ROSC_START as a clock input, an external oscillation stop signal ROSC_STOP as a reset input, and an oscillation enable signal. A D flip-flop circuit 10 that outputs TDC_EN, a ring oscillator 11a (oscillation circuit) that generates a high-speed clock TAP[15] (first clock) during a significant period of the oscillation enable signal TDC_EN, and a high-speed clock TAP[15]. ] to output a high-speed clock RCLK1 (first clock), an inverter 14 to output a high-speed clock RCLK2 (second clock) obtained by inverting the high-speed clock TAP[15], and a buffer circuit 13 OR circuit 15 for outputting the logical sum result of the output RCLK1 of the inverter 14 and the oscillation stop signal ROSC_STOP as the high-speed clock ROSC_CLK1, and the OR circuit 16 for outputting the logical sum result of the output RCLK2 of the inverter 14 and the oscillation stop signal ROSC_STOP as the high-speed clock ROSC_CLK2. and

The time measurement circuit includes a high-speed counter 12a (first counter) that counts the high-speed clock ROSC_CLK1, a high-speed counter 12b (second counter) that counts the high-speed clock ROSC_CLK2, an oscillation stop signal ROSC_STOP, and a low-speed clock MCLK. An edge detection circuit 17 for detecting the rising edge of the oscillation stop signal ROSC_STOP, a D flip-flop circuit 18a for latching the 8-bit count result HS_CNT1[8:0] of the high-speed counter 12a, and an 8-bit count of the high-speed counter 12b. A DD flip-flop circuit 18b that latches the count result HS_CNT2[8:0], an encoder 19 that outputs a 5-bit timing signal HS_PHASE[4:0] indicating the phase value of the output of the ring oscillator 11a, and a D flip-flop circuit. A selector 20 that selects one of the 8-bit outputs LATCH1[8:0] and LATCH2[8:0] of 18a and 18b. and a time calculator 21 for calculating the time interval until the oscillation stop signal ROSC_STOP rises.

Buffer circuit 13 , inverter 14 , and OR circuits 15 and 16 constitute logic circuit 22 .
The ring oscillator 11a includes a NAND circuit 110 for NANDing the oscillation enable signal TDC_EN and the high-speed clock TAP[15]; , and 16 D flip-flop circuits 112-1 to 112-16 having the outputs of the NAND circuit 110 and the buffer circuits 111-1 to 111-15 as D inputs and the oscillation stop signal ROSC_STOP as the clock input. be done.

The operation of the time measurement circuit of this embodiment will be described below. FIG. 2 is a timing chart for explaining the operation of the time measurement circuit.
The D flip-flop circuit 10 receives a 1-bit binary number "1"(1'b1) as a D input, an oscillation start signal ROSC_START as a clock input, and an oscillation stop signal ROSC_STOP as a reset input. It outputs an oscillation enable signal TDC_EN that becomes significant (High) and becomes insignificant (Low) at the rise of the oscillation stop signal ROSC_STOP.

The ring oscillator 11a generates a clock TAP[15] faster than the low-speed clock MCLK while the oscillation enable signal TDC_EN output from the D flip-flop circuit 10 is significant.

The buffer circuit 13 receives the high-speed clock TAP[15] output from the ring oscillator 11a and outputs a high-speed clock RCLK1. The inverter 14 outputs a high-speed clock RCLK2 obtained by logically inverting the high-speed clock TAP[15] output from the ring oscillator 11a. The buffer circuit 13 is inserted to match the phases of the high-speed clocks RCLK1 and RCLK2.

The OR circuit 15 outputs the result of ORing the high-speed clock RCLK1 output from the buffer circuit 13 and the oscillation stop signal ROSC_STOP as the high-speed clock ROSC_CLK1. The OR circuit 16 outputs the result of ORing the high-speed clock RCLK2 output from the inverter 14 and the oscillation stop signal ROSC_STOP as the high-speed clock ROSC_CLK2.

Edge detection circuit 17 detects 8-bit count result HS_CNT1[8:0] of high-speed counter 12a and 8-bit count result HS_CNT2[8:0] of high-speed counter 12b based on oscillation stop signal ROSC_STOP and low-speed clock MCLK. , a high-speed counter reset signal HS_CNT_CLR for resetting the high-speed counters 12a and 12b, and a capture permission indicating that valid data is stored in the D flip-flop circuits 18a and 18b. It generates signals HS_CNT_EN.

FIG. 3 is a circuit diagram showing the configuration of the edge detection circuit 17. As shown in FIG. The edge detection circuit 17 includes a D flip-flop circuit 170 having an oscillation stop signal ROSC_STOP as a clock input, and an inverter 171 having a D input of the D flip-flop circuit 170 which is an inverted signal of the output signal STOP_DET of the D flip-flop circuit 170 . , a D flip-flop circuit 172 with the output signal STOP_DET of the D flip-flop circuit 170 as the D input and the low-speed clock MCLK as the clock input, and a D flip-flop circuit 172 with the output signal of the D flip-flop circuit 172 as the D input and the low-speed clock MCLK as the clock input. a D flip-flop circuit 173 with the output signal of the D flip-flop circuit 173 as the D input and the low-speed clock MCLK as the clock input; the output signal of the D flip-flop circuit 173 and the D flip-flop circuit 174 An XOR circuit 175 that outputs the result of the exclusive OR of the output signals of , as a capture enable signal HS_CNT_LAT, and a D flip-flop that receives the capture enable signal HS_CNT_LAT as a D input, receives the low-speed clock MCLK as a clock input, and outputs a capture enable signal HS_CNT_EN. It is composed of a circuit 176 and a D flip-flop circuit 178 that outputs a high-speed counter reset signal HS_CNT_CLR with a D input of the fetch enable signal HS_CNT_LAT and a result of inverting the low-speed clock MCLK as a clock input.

The high-speed counter 12a counts the rises of the high-speed clock ROSC_CLK1 while the high-speed counter reset signal HS_CNT_CLR is insignificant (High), and outputs an 8-bit count result HS_CNT1[8:0]. The high-speed counter 12b counts the rises of the high-speed clock ROSC_CLK2 while the high-speed counter reset signal HS_CNT_CLR is insignificant (High), and outputs an 8-bit count result HS_CNT2[8:0]. The count results HS_CNT1[8:0] and HS_CNT2[8:0] of these high-speed counters 12a and 12b are initialized to 0 at the fall of the high-speed counter reset signal HS_CNT_CLR.

The D flip-flop circuit 18a latches the 8-bit count result HS_CNT1[8:0] of the high-speed counter 12a at the rise of the capture enable signal HS_CNT_LAT, and holds it until the next rise of the capture enable signal HS_CNT_LAT. The D flip-flop circuit 18b latches the 8-bit count result HS_CNT2[8:0] of the high-speed counter 12b at the rise of the capture enable signal HS_CNT_LAT, and holds it until the next rise of the capture enable signal HS_CNT_LAT.

Based on the 16-bit signal ROSC_PHASE[15:0] output from the D flip-flop circuits 112-1 to 112-16, the encoder 19 generates a 5-bit timing signal HS_PHASE[15:0] indicating the phase value of the output of the ring oscillator 11a. 4:0] is output. The timing signal HS_PHASE[4:0] is a 5-bit signal obtained by encoding the 16-bit signal ROSC_PHASE[15:0].

Based on the 5-bit timing signal HS_PHASE[4:0] output from the encoder 19, the selector 20 outputs the 8-bit count results LATCH1[8:0] and LATCH2[ 8:0], the count result obtained by the high-speed counter in which no glitch (counting error) has occurred is selected as the true value.

The time calculation unit 21 takes in the counting result output from the selector 20 when the take-in enable signal HS_CNT_EN becomes significant (High). The time calculation unit 21 calculates the time interval from the rise of the oscillation start signal ROSC_START to the rise of the oscillation stop signal ROSC_STOP based on the obtained count result.

Since the ring oscillator type TDC receives the oscillation start signal ROSC_START indicating the start of measurement, the ring oscillator 11a starts oscillating. However, as described above, depending on the timing of the oscillation stop signal ROSC_STOP, a glitch may occur in the output of the ring oscillator 11a, causing the high-speed counter to malfunction.

Therefore, in the present embodiment, the output TAP[15] of the ring oscillator 11a and its inverted signal are counted by separate high-speed counters 12a and 12b, respectively, and from the obtained count results, the count result for which no glitch occurs is By selecting , low power consumption operation and accurate time measurement are realized.

More specifically, the high-speed clock RCLK1 obtained by passing the high-speed clock TAP[15] output from the ring oscillator 11a through the buffer circuit 13 and the high-speed clock RCLK2 obtained by logically inverting the high-speed clock TAP[15] by the inverter 14 are The OR circuits 15 and 16 OR-mask the oscillation stop signal ROSC_STOP, respectively, and the OR-masked high-speed clocks ROSC_CLK1 and ROSC_CLK2 are counted by separate high-speed counters 12a and 12b, respectively.

Depending on the timing at which the oscillation start signal ROSC_START is received, the above-mentioned glitch may occur. Since it can be determined, the counting result obtained by the high-speed counter with no glitch may be selected as the true value.

FIG. 4 shows the relationship between the high-speed clocks RCLK1 and RCLK2 and the timing signals HS_PHASE[4:0]. In FIG. 4, the minimum Low width (Min Error) that cannot be accepted by the high-speed counters 12a and 12b and the boundary between the selection of LATCH1[8:0] and LATCH2[8:0] determined based on this Min Error are showing. Δt in FIG. 4 indicates the delay time per stage of the delay circuit (NAND circuit 110 and buffer circuits 111-1 to 111-15) of ring oscillator 11a.

In this embodiment, the selector 20 detects that a glitch (counting error) has occurred in the 8-bit count results LATCH1[8:0] and LATCH2[8:0] latched by the D flip-flop circuits 18a and 18b. The count result obtained by the non-existent high speed counter is selected as the true value. Such selection can be made based on the value of the 5-bit timing signal HS_PHASE[4:0].

In the example of FIG. 4, the selector 20 selects the phase of the high-speed clock RCLK1 from 0° (the value of the timing signal HS_PHASE[4:0] is 0) to a predetermined first phase value smaller than 180° (in this embodiment, 101.25°, the value of the timing signal HS_PHASE[4:0] is less than 9), the count result LATCH1[8:0] is selected.

Also, the selector 20 sets the phase of the high-speed clock RCLK1 to a predetermined second phase value (281.25° in this embodiment, timing signal HS_PHASE[4: 0] is less than 25), the count result LATCH2[8:0] is selected, and the count result LATCH1[8:0] is selected when the phase of the high-speed clock RCLK1 is greater than or equal to the second phase value and less than 360°. select.

That is, when the selector 20 selects one of the 8-bit count results LATCH1[8:0] and LATCH2[8:0], the elapsed time from the fall of the high-speed clocks RCLK1 and RCLK2 is the lowest. The count result of the high-speed counter that counts the high-speed clock that exceeds the time obtained by adding a predetermined margin to the width (Min Error) is selected as the true value.

For example, the elapsed time from the fall of the high-speed clock RCLK2 does not have a sufficient margin for the minimum Low width (Min Error), and the elapsed time from the fall of the high-speed clock RCLK1 has a sufficient margin to the minimum Low width. In the period, the selector 20 selects the count result LATCH1[8:0], the elapsed time from the fall of the high-speed clock RCLK1 does not have enough margin for the minimum Low width, and the time from the fall of the high-speed clock RCLK2 is The count result LATCH2[8:0] is selected in a period in which the elapsed time has a sufficient margin for the minimum Low width.

At the time of actual design, based on the data sheet and circuit layout information of the IC (Integrated Circuit) manufacturing company, the range of HS_PHASE that causes Low width violation and the boundary of the selection of LATCH1[8:0] and LATCH2[8:0] and will be determined. In the example of FIG. 4, the boundaries are determined on the assumption that the minimum Low width holding period (Min Error) of the clock of the flip-flops constituting the high-speed counters 12a and 12b is 250 ps and the TDC resolution is 50 ps.

With respect to the glitch generated by the asynchronous input of the oscillation stop signal ROSC_STOP to the ring oscillator 11a, the high-speed clocks RCLK1 and RCLK2 are OR-masked with the oscillation stop signal ROSC_STOP, and the high-speed clocks ROSC_CLK1 and ROSC_CLK2 are generated by the high-speed counter 12a and the high-speed counter 12a. 12b can be used as the clock.

However, depending on the phase relationship between the high-speed clocks ROSC_CLK1, ROSC_CLK2 and the oscillation stop signal ROSC_STOP, the time calculation unit 21 subtracts 1 from the count result LATCH1[8:0] or LATCH2[8:0] before starting oscillation. It is necessary to calculate the time interval from the rise of the signal ROSC_START to the rise of the oscillation stop signal ROSC_STOP.

For example, the example of FIG. 5 shows the case where the rise of the oscillation stop signal ROSC_STOP is received at the timing when the value of the timing signal HS_PHASE[4:0] is 0 (the phase of the high-speed clock RCLK1 is 0°). At 101 in FIG. 5, a glitch occurs in the high speed clock ROSC_CLK2. The selector 20 selects the count result LATCH1[8:0] (HS_CNT1[8:0]) by the above operation. If the value of the timing signal HS_PHASE[4:0] is 0 when the fetch enable signal HS_CNT_EN becomes significant (High), the time calculation unit 21 subtracts 1 from the fetched count result LATCH1[8:0]. No need.

The example of FIG. 6 shows the case where the rise of the oscillation stop signal ROSC_STOP is received at the timing when the value of the timing signal HS_PHASE[4:0] is 9 (the phase of the high-speed clock RCLK1 is 101.25°). The selector 20 selects the count result LATCH2[8:0] (HS_CNT2[8:0]) by the above operation. If the value of the timing signal HS_PHASE[4:0] is 9 at the time when the fetch enable signal HS_CNT_EN becomes significant (High), the time calculation unit 21 subtracts 1 from the fetched count result LATCH2[8:0]. Then calculate the time interval.

The example of FIG. 7 shows the case where the rise of the oscillation stop signal ROSC_STOP is received at the timing when the value of the timing signal HS_PHASE[4:0] is 16 (the phase of the high-speed clock RCLK1 is 180°). At 102 in FIG. 7, a glitch occurs on the high speed clock ROSC_CLK1. The selector 20 selects the count result LATCH2[8:0] (HS_CNT2[8:0]) by the above operation. If the value of the timing signal HS_PHASE[4:0] is 16 at the time when the fetch enable signal HS_CNT_EN becomes significant (High), the time calculation unit 21 subtracts 1 from the fetched count result LATCH2[8:0]. Then calculate the time interval.

The example of FIG. 8 shows the case where the rise of the oscillation stop signal ROSC_STOP is received at the timing when the value of the timing signal HS_PHASE[4:0] is 25 (the phase of the high-speed clock RCLK1 is 281.25°). The selector 20 selects the count result LATCH1[8:0] (HS_CNT1[8:0]) by the above operation. If the value of the timing signal HS_PHASE[4:0] is 25 at the time when the fetch enable signal HS_CNT_EN becomes significant (High), the time calculation unit 21 subtracts 1 from the fetched count result LATCH1[8:0]. Then calculate the time interval.

FIG. 9 shows whether or not the above counting results need to be corrected in FIG. When the phase of the high-speed clock RCLK1 is in the range of the first phase value or more and less than 360°, the time calculation unit 21 subtracts 1 from the count result when the count result selected by the selector 20 is received. The interval should be calculated.

In this embodiment, the delay circuit (the NAND circuit 110 and the buffer circuits 111-1 to 111-15) of the ring oscillator 11a has 16 stages (TAP[0] to TAP[15]). Other than 16 is not a problem for the present invention. However, if the number of stages is a power of 2, then the count values (LATCH1[8:0], LATCH2[8:0]) of the high-speed counters 12a and 12b and the phase value (HS_PHASE[4:0]) of the ring oscillator 11a can simplify the concatenation of

For example, when LATCH1[8:0] is selected, the time measurement value is {LATCH1[8:0], HS_PHASE[4:0]}. obtained by A proposal for simplifying the combination of the count value and the phase value when the number of stages of the ring oscillator 11a is not a power of 2 is described in Japanese Patent No. 2868266, for example.

[Second embodiment]
Next, a second embodiment of the invention will be described. In the first embodiment, both the signal RCLK1 obtained by passing the high-speed clock TAP[15] output from the ring oscillator 11a through the buffer circuit 13 and the signal RCLK2 obtained by logically inverting the high-speed clock TAP[15] by the inverter 14 are However, without preparing the inverted signal of the output of the ring oscillator 11a, the high-speed clock TAP[15] output from the ring oscillator 11a is masked with a signal that does not mask. may be prepared, each signal may be counted by another high-speed counter, and then the counting result obtained by the high-speed counter with no glitch may be selected.

FIG. 10 is a circuit diagram showing the configuration of the time measuring circuit according to this embodiment, and the same components as in FIG. 1 are given the same reference numerals. The time measuring circuit of this embodiment includes a D flip-flop circuit 10, a ring oscillator 11a (oscillation circuit), high-speed counters 12a and 12b (first and second counters), an edge detection circuit 17, and a D flip-flop circuit. The high-speed clock ROSC_CLK2 is obtained by ORing the high-speed clock ROSC_CLK1 (TAP[15]) output from the circuits 18a and 18b, the encoder 19, the selector 20a, the time calculator 21, and the ring oscillator 11a and the oscillation stop signal ROSC_STOP. and an OR circuit 23 (logic circuit) that outputs as .

The structure and operation of D flip-flop circuit 10 and ring oscillator 11a are as described in the first embodiment.
The high-speed counter 12a of this embodiment counts the rises of the high-speed clock ROSC_CLK1 (TAP[15]) output from the ring oscillator 11a while the high-speed counter reset signal HS_CNT_CLR is insignificant (High), Output the count result HS_CNT1[8:0].

On the other hand, the OR circuit 23 outputs the result of ORing the high-speed clock ROSC_CLK1 (TAP[15]) and the oscillation stop signal ROSC_STOP as the high-speed clock ROSC_CLK2. The high-speed counter 12b counts the rises of the high-speed clock ROSC_CLK2 while the high-speed counter reset signal HS_CNT_CLR is insignificant (High), and outputs an 8-bit count result HS_CNT2[8:0].

The operations of edge detection circuit 17, D flip-flop circuits 18a and 18b, and encoder 19 are as described in the first embodiment.
In this embodiment as well, the selector 20a generates glitches (counting errors) among the 8-bit count results LATCH1[8:0] and LATCH2[8:0] latched by the D flip-flop circuits 18a and 18b. However, since the buffer circuit 13 and the inverter 14 are not used, the phase ( The value of the timing signal HS_PHASE[4:0]) is different from that of the first embodiment.

FIG. 11 shows the relationship between ROSC_CLK1 (TAP[15]) and timing signals HS_PHASE[4:0]. In the example of FIG. 11, the selector 20a is arranged such that the phase of the high-speed clock ROSC_CLK1 (TAP[15]) input to the high-speed counter 12a is from 0° (the value of the timing signal HS_PHASE[4:0] is 0) to 180°. The count result LATCH2[8:0] is selected in the range below a small predetermined first phase value (123.75° in this embodiment, the value of the timing signal HS_PHASE[4:0] is 11).

Further, the selector 20a sets the phase of the high-speed clock ROSC_CLK1 (TAP[15]) to a predetermined second phase value (303.75° in this embodiment, 303.75°, When the value of the timing signal HS_PHASE[4:0] is less than 27), the count result LATCH1[8:0] is selected, and the phase of the high-speed clock ROSC_CLK1 (TAP[15]) is greater than or equal to the second phase value and less than 360°. In the range of , the count result LATCH2[8:0] is selected.

In the example of FIG. 11, as in FIG. 4, the boundary is determined on the assumption that the minimum Low width holding period (Min Error) of the clock of the flip-flops constituting the high-speed counters 12a and 12b is 250 ps and the TDC resolution is 50 ps. ing.

As in the first embodiment, the time calculator 21 takes in the counting result output from the selector 20a at the rise of the take-in permission signal HS_CNT_LAT, and determines the time interval from the rise of the oscillation start signal ROSC_START to the rise of the oscillation stop signal ROSC_STOP. Calculate
Thus, in this embodiment, the same effect as in the first embodiment can be obtained.

Also in this embodiment, the time calculation unit 21 subtracts 1 from the count result LATCH1[8:0] or LATCH2[8:0] depending on the phase relationship between the high-speed clock ROSC_CLK2 and the oscillation stop signal ROSC_STOP. Therefore, it is necessary to calculate the time interval from the rise of the oscillation start signal ROSC_START to the rise of the oscillation stop signal ROSC_STOP.

However, as described above, in this embodiment, the phase of the high-speed clock ROSC_CLK1 (TAP[15]) (the value of the timing signal HS_PHASE[4:0]), which serves as a boundary for switching the selection of the selector 20a, is the first. Since this embodiment differs from the first embodiment, the judgment as to whether or not to correct the counting result also differs from that of the first embodiment.

For example, the example of FIG. 12 shows the case where the rise of the oscillation stop signal ROSC_STOP is received at the timing when the value of the timing signal HS_PHASE[4:0] is 0 (the phase of ROSC_CLK1 (TAP[15]) is 0°). . At 103 in FIG. 12, a glitch occurs in the high speed clock ROSC_CLK1. The selector 20 selects the count result LATCH2[8:0] (HS_CNT2[8:0]) by the above operation. If the value of the timing signal HS_PHASE[4:0] is 0 when the fetch enable signal HS_CNT_EN becomes significant (High), the time calculation unit 21 subtracts 1 from the fetched count result LATCH2[8:0]. No need.

In the example of FIG. 13, the rising edge of the oscillation stop signal ROSC_STOP is received at the timing when the value of the timing signal HS_PHASE[4:0] is 11 (the phase of the high-speed clock ROSC_CLK1 (TAP[15]) is 123.75°). showing. The selector 20 selects the count result LATCH1[8:0] (HS_CNT1[8:0]) by the above operation. If the value of the timing signal HS_PHASE[4:0] is 11 at the time when the fetch enable signal HS_CNT_EN becomes significant (High), the time calculation unit 21 subtracts 1 from the fetched count result LATCH1[8:0]. Then calculate the time interval.

The example of FIG. 14 shows the case where the rise of the oscillation stop signal ROSC_STOP is received at the timing when the value of the timing signal HS_PHASE[4:0] is 16 (the phase of the high-speed clock ROSC_CLK1 (TAP[15]) is 180°). there is At 104 in FIG. 14, a glitch occurs in the high speed clock ROSC_CLK2. The selector 20 selects the count result LATCH1[8:0] (HS_CNT1[8:0]) by the above operation. If the value of the timing signal HS_PHASE[4:0] is 16 at the time when the fetch enable signal HS_CNT_EN becomes significant (High), the time calculation unit 21 subtracts 1 from the fetched count result LATCH1[8:0]. Then calculate the time interval.

In the example of FIG. 15, the rising edge of the oscillation stop signal ROSC_STOP is received at the timing when the value of the timing signal HS_PHASE[4:0] is 27 (the phase of the high-speed clock ROSC_CLK1 (TAP[15]) is 303.75°). showing. The selector 20 selects the count result LATCH2[8:0] (HS_CNT2[8:0]) by the above operation. If the value of the timing signal HS_PHASE[4:0] is 27 at the time when the fetch enable signal HS_CNT_EN becomes significant (High), the time calculation unit 21 subtracts 1 from the fetched count result LATCH2[8:0]. Then calculate the time interval.

FIG. 16 shows the necessity of correction of the counting result described above in FIG. As in the first embodiment, when the time calculation unit 21 acquires the count result selected by the selector 20 when the phase of the high-speed clock RCLK1 is in the range of the first phase value or more and less than 360°, this The time interval can be calculated after subtracting 1 from the count result.

[Third embodiment]
A third embodiment of the present invention will now be described. FIG. 17 is a circuit diagram showing the configuration of the time measuring circuit according to this embodiment, and the same components as in FIGS. 1 and 10 are denoted by the same reference numerals. The time measurement circuit of this embodiment includes a D flip-flop circuit 10, a ring oscillator 11a (oscillating circuit), high-speed counters 12a and 12b (first and second counters), a buffer circuit 13, an inverter 14, An edge detection circuit 17a, D flip-flop circuits 18a and 18b, an encoder 19, a selector 20, a time calculator 21a, an oscillation start signal ROSC_START (first start signal) input from the outside during normal operation, and an oscillation stop. A signal ROSC_STOP (first stop signal) is selected and output, and a start signal DBG_START (second start signal) and a stop signal DBG_STOP (second stop signal) output from a test execution unit, which will be described later, are output during test execution. and an operation setting circuit 24 for selecting and outputting and for outputting a stop signal ROSC_STOPb (third stop signal) at the end of the test.

Further, the time measurement circuit of this embodiment includes a stop signal for masking the high-speed clock RCLK1 later than the high-speed clock RCLK2 and unmasking it later than the high-speed clock RCLK2, and a high-speed clock RCLK2 as the high-speed clock. A mask release timing control circuit 25 that generates a stop signal for masking before RCLK1 and releasing mask before high-speed clock RCLK1 from a stop signal ROSC_STOPa output from an operation setting circuit 24, and high-speed clock RCLK1. An OR circuit 26 that outputs the result of the logical sum of the stop signals output from the mask release timing control circuit 25 as the high-speed clock ROSC_CLK1, and the result of the logical sum of the high-speed clock RCLK2 and the stop signal output from the mask release timing control circuit 25. as a high-speed clock ROSC_CLK2.

Buffer circuit 13 , inverter 14 , mask release timing control circuit 25 , and OR circuits 26 and 27 constitute logic circuit 28 .
As shown in FIG. 17, this embodiment differs from the first embodiment in that an operation setting circuit 24 capable of starting the ring oscillator 11a by the START and STOP signals (DBG_START, DBG_STOP) from the time measuring circuit 21a and a high-speed clock A mask release timing control circuit 25 for controlling the mask release timing of RCLK1 and RCLK2 and OR circuits 26 and 27 are added.

18 is a circuit diagram showing the configuration of the operation setting circuit 24, and FIG. 19 is a circuit diagram showing the configuration of the mask release timing control circuit 25. As shown in FIG. As shown in FIG. 18, the operation setting circuit 24 selects either the oscillation stop signal ROSC_STOP or the stop signal DBG_STOP output from the time calculation unit 21a according to the selection instruction signal ROSC_SEL output from the time calculation unit 21a. , a selector 240 that outputs a stop signal ROSC_STOPa, and a selector 241 that selects either the oscillation start signal ROSC_START or the start signal DBG_START output from the time calculation unit 21a according to the selection instruction signal ROSC_SEL and outputs the selected signal as the start signal ROSC_STARTa. , and an AND circuit 242 that outputs the result of ANDing the stop signal ROSC_STOPa output from the selector 240 and the negation of the test instruction signal ROSC_TEST output from the time calculator 21a as the stop signal ROSC_STOPb.

The D flip-flop circuit 10 of this embodiment uses the start signal ROSC_STARTa output from the operation setting circuit 24 instead of the oscillation start signal ROSC_START as the clock input, and the clock input from the operation setting circuit 24 instead of the oscillation stop signal ROSC_STOP. The stop signal ROSC_STOPb is used as a reset input.

The D flip-flop circuits 112-1 to 112-16 of the ring oscillator 11a of this embodiment receive the stop signal ROSC_STOPb as a clock input instead of the oscillation stop signal ROSC_STOP.

The edge detection circuit 17a of this embodiment receives the stop signal ROSC_STOPa instead of the oscillation stop signal ROSC_STOP. The capture enable signal HS_CNT_LAT that becomes significant (High) at the fall of the low-speed clock MCLK, the high-speed counter reset signal HS_CNT_CLR that becomes significant (Low) at the fall of the capture enable signal HS_CNT_LAT, and the oscillation stop signal ROSC_STOPa are A fetch enable signal HS_CNT_EN delayed by 1/2 clock is generated.

FIG. 20 is a block diagram showing the configuration of the time calculator 21a of this embodiment. The time calculator 200 realizes the same function as the time calculator 21 of the first and second embodiments. The test execution section 201 tests the delay circuit (the NAND circuit 110 and the buffer circuits 111-1 to 111-15) of the ring oscillator 11a.

The operation of the time measurement circuit of this embodiment will be described below. FIG. 21 is a timing chart for explaining the operation of the time measurement circuit of this embodiment during testing. During test execution, the test execution unit 201 outputs the test instruction signal ROSC_TEST as shown in FIG. It is set to a significant High level, and the selection instruction signal ROSC_SEL is set to a High level.

The selector 240 of the operation setting circuit 24 selects the stop signal DBG_STOP from the oscillation stop signal ROSC_STOP and the stop signal DBG_STOP output from the test execution unit 201 when the selection instruction signal ROSC_SEL is at High level, and outputs the stop signal ROSC_STOPa. output as

The selector 241 of the operation setting circuit 24 selects the start signal DBG_START from the oscillation start signal ROSC_START and the start signal DBG_START output from the test execution unit 201 when the selection instruction signal ROSC_SEL is at High level, and outputs the start signal ROSC_STARTa. output as

The AND circuit 242 of the operation setting circuit 24 outputs the result of ANDing the stop signal ROSC_STOPa output from the selector 240 and the negation of the test instruction signal ROSC_TEST output from the test execution unit 201 as the stop signal ROSC_STOPb. As a result, the stop signal ROSC_STOPb is insignificant (Low) while the test instruction signal ROSC_TEST is at High level during the test. Further, the stop signal ROSC_STOPb becomes significant (High) when the stop signal DBG_STOP rises, for example, when the test instruction signal ROSC_TEST becomes Low after the end of the test according to an instruction from the user.

Therefore, the D flip-flop circuit 10 sets the oscillation enable signal TDC_EN to significant (High) at the first rise of the start signal ROSC_STARTa (DBG_START) during the test, and sets the oscillation enable signal TDC_EN to insignificant (Low) at the rise of the stop signal ROSC_STOPb. Therefore, the ring oscillator 11a free-runs while the oscillation enable signal TDC_EN is high.

Note that when the test instruction signal ROSC_TEST becomes Low in a normal state and the oscillation stop signal ROSC_STOP is input, the oscillation stop signal ROSC_STOP is output as the stop signal ROSC_STOPb.

During test execution, the test execution unit 201 periodically issues the stop signal DBG_STOP in synchronization with the low-speed clock MCLK, but the ring oscillator 11a does not stop even if the stop signal DBG_STOP goes high.

Then, the test execution unit 201 acquires the 5-bit timing signal HS_PHASE[4:0] output from the encoder 19 at the rise of the stop signal DBG_STOP, and based on the value of this timing signal HS_PHASE[4:0], The 8-bit count results LATCH1[8:0] and LATCH2[8:0] latched by the D flip-flop circuits 18a and 18b are obtained.

The frequency of the ring oscillator 11a is not fixed and is not synchronized with the low-speed clock MCLK. Therefore, even if the test execution unit 201 periodically obtains the timing signal HS_PHASE[4:0], the obtained values are random. Change.

Based on the value of this timing signal HS_PHASE[4:0], the test execution unit 201 sets the phase of the high-speed clock RCLK1 to the first phase value (101.25°, the value of the timing signal HS_PHASE[4:0] to 9). ) (the value of the timing signal HS_PHASE[4:0] is 8), the count results LATCH1[8:0] and LATCH2[8:0] are acquired and compared. Also, the test execution unit 201 may acquire and compare the count results LATCH1[8:0] and LATCH2[8:0] when the phase of the high-speed clock RCLK1 is the first phase value. Further, the test execution unit 201 calculates the count results LATCH1[8:0] and LATCH2 when the phase of the high-speed clock RCLK1 is the value immediately after the first phase value (the value of the timing signal HS_PHASE[4:0] is 10). [8:0] may be obtained and compared. In FIG. 21, these timings are represented by Phase1.

In addition, the test execution unit 201 determines that the phase of the high-speed clock RCLK1 is the value (timing signal HS_PHASE[4:0]) immediately before the second phase value (281.25°, the value of timing signal HS_PHASE[4:0] is 25). ] is 24), the count results LATCH1[8:0] and LATCH2[8:0] are acquired and compared. Further, the test execution unit 201 may acquire and compare the count results LATCH1[8:0] and LATCH2[8:0] when the phase of the high-speed clock RCLK1 is the second phase value. Also, the test execution unit 201 calculates the count results LATCH1[8:0] and LATCH2 when the phase of the high-speed clock RCLK1 is the value immediately after the second phase value (the value of the timing signal HS_PHASE[4:0] is 26). [8:0] may be obtained and compared. In FIG. 21, these timings are represented by Phase2.

At these Phase1 and Phase2 timings, the values of the count results LATCH1[8:0] and LATCH2[8:0] should both be count values that do not cause a Low width violation in the high-speed counters 12a and 12b. The execution unit 201 compares the count results LATCH1[8:0] and LATCH2[8:0] obtained at the timing of Phase1, and similarly compares the count results LATCH1[8:0] and LATCH2[8:0] obtained at the timing of Phase2. 8:0].

Then, if the count results LATCH1[8:0] and LATCH2[8:0] match, the test execution unit 201 detects the delay circuit (the NAND circuit 110 and the buffer circuits 111-1 to 111-1) of the ring oscillator 11a. 111-15) is normal, and if the count results LATCH1[8:0] and LATCH2[8:0] do not match, it is determined that the delay circuit is out of order. As a method for outputting the determination result, for example, there is a method of displaying the content of the determination result or transmitting the information of the determination result to the outside.

Since the phase relationship between the high-speed clocks RCLK1 and RCLK2 and the oscillation stop signal ROSC_STOP is asynchronous, the timing of mask release by the oscillation stop signal ROSC_STOP is controlled by the mask release timing control circuit 25 when performing the test as in this embodiment. There is a need.

As shown in FIG. 19, the mask release timing control circuit 25 includes an AND circuit 250 that outputs the result of ANDing the high-speed clock RCLK1 output from the buffer circuit 13 and the test instruction signal ROSC_TEST output from the time calculation section 21a. , an AND circuit 251 that outputs the result of ANDing the high-speed clock RCLK2 output from the inverter 14 and the test instruction signal ROSC_TEST, and the stop signal ROSC_STOPa output from the operation setting circuit 24 as the D input. , a D flip-flop circuit 253 with a stop signal ROSC_STOPa as a clock input, and an output STOP_RCLK2_D2 of the D flip-flop circuit 253 as a D input. It is composed of a D flip-flop circuit 254 which receives the output of the AND circuit 250 as a clock input.

The OR circuit 26 outputs the result of ORing the high-speed clock RCLK1, the output STOP_RCLK1_D3 (fourth stop signal) of the D flip-flop circuit 254 of the mask release timing control circuit 25, and the stop signal ROSC_STOPa as the high-speed clock ROSC_CLK1.

The OR circuit 27 outputs the result of ORing the high-speed clock RCLK2, the output STOP_RCLK2_D2 (fifth stop signal) of the D flip-flop circuit 253 of the mask release timing control circuit 25, and the stop signal ROSC_STOPa as the high-speed clock ROSC_CLK2.

FIG. 22 is a timing chart for explaining the operation of the mask release timing control circuit 25. FIG. Note that FIG. 22 shows the case where the value of the timing signal HS_PHASE[4:0] is 24 or 25. FIG. The ring oscillator 11a, the buffer circuit 13, and the inverter 14 of the first to third embodiments are configured such that when the oscillation enable signal TDC_EN becomes significant (High), the high-speed clock RCLK2 rises, the high-speed clock RCLK1 rises, and the high-speed clock RCLK1 rises. The high-speed clocks RCLK2 and RCLK1 are alternately raised such that the clock RCLK2 rises→the high-speed clock RCLK1 rises.

Therefore, as indicated by 105 in FIG. 22, at the start of operation, high-speed counter 12b (HS_CNT2[8:0]) and high-speed counter 12a (HS_CNT1[8:0]) start counting up in this order. Therefore, as shown in the timing chart of FIG. 22, when the mask is released, the mask is released in the order of the rise of the high-speed clock RCLK2→the rise of the high-speed clock RCLK1→the rise of the high-speed clock RCLK2→the rise of the high-speed clock RCLK1. Control.

STOP_RCLK2_D1 in FIG. 22 indicates the output of the D flip-flop circuit 252, STOP_RCLK2_D2 indicates the output of the D flip-flop circuit 253, and STOP_RCLK1_D3 indicates the output of the D flip-flop circuit 254. FIG. The output STOP_RCLK2_D2 of the D flip-flop circuit 253 is used in the OR circuit 27 to mask the high-speed clock RCLK2. Also, the output STOP_RCLK1_D3 of the D flip-flop circuit 254 is used in the OR circuit 26 to mask the high-speed clock RCLK1.

In this way, the output STOP_RCLK2_D2 of the D flip-flop circuit 253 falls before the output STOP_RCLK1_D3 of the D flip-flop circuit 254, and the high-speed clock RCLK2 is unmasked before the high-speed clock RCLK1. As shown, even when the mask is released, the high-speed counter 12b (HS_CNT2[8:0]) and the high-speed counter 12a (HS_CNT1[8:0]) resume counting in this order.

In this embodiment, the count results LATCH1[8:0] and LATCH2[8:0] are compared at the timings of Phase1 and Phase2 as described above. 26 (when the phase of the high-speed clock RCLK1 is the value immediately before the second phase value, the second phase value, or the value immediately after the second phase value), if there is no failure in the delay circuit of the ring oscillator 11a. , 107 in FIG. 22, the count results LATCH1[8:0] and LATCH2[8:0] always match.

On the other hand, if the timing signal HS_PHASE[4:0] has a value of 8, 9, or 10 (the phase of high-speed clock RCLK1 is the value immediately before the first phase value, the first phase value, or the value immediately after the first phase value). ), the high-speed clock ROSC_CLK2 rises one more time than ROSC_CLK1, as shown in FIG. LATCH2[8:0] has a count value larger by one.

Therefore, when the value of the timing signal HS_PHASE[4:0] is 8, 9, or 10, the test execution unit 201 subtracts 1 from the count result LATCH2[8:0] and then counts the count result LATCH1[8:0]. 0] is compared with LATCH2[8:0] after subtraction, and if the count result LATCH1[8:0] and LATCH2[8:0] match, the delay circuit of the ring oscillator 11a is normal. If the count results LATCH1[8:0] and LATCH2[8:0] do not match, it is determined that the delay circuit is out of order.

The normal operation is the same as in the first embodiment. As described above, when the test is executed, the test instruction signal ROSC_TEST becomes High level, so the AND circuits 250 and 251 of the mask release timing control circuit 25 enable the operation of the mask release timing control circuit 25 . On the other hand, since the test instruction signal ROSC_TEST is normally at Low level, the operation of the mask release timing control circuit 25 is disabled (outputs of AND circuits 250 and 251 are always at Low level).

Normally, the OR circuit 26 outputs the result of ORing the high-speed clock RCLK1 output from the buffer circuit 13 and the stop signal ROSC_STOPa (ROSC_STOP) as the high-speed clock ROSC_CLK1, similarly to the OR circuit 15 of the first embodiment. . Like the OR circuit 16, the OR circuit 27 outputs the result of the OR of the high speed clock RCLK2 output from the inverter 14 and the stop signal ROSC_STOPa (ROSC_STOP) as the high speed clock ROSC_CLK2.

By using the self-test function of this embodiment, it is not necessary to select a tester capable of controlling the interval between the oscillation start signal ROSC_START and the oscillation stop signal ROSC_STOP with a resolution of several tens of ps as an IC shipping inspection tester. Since the test can be performed without inputting the start signal ROSC_START and the oscillation stop signal ROSC_STOP, it is possible to shorten the test time of the IC equipped with the time measurement circuit. As a result, this embodiment can contribute to IC cost reduction.

The time calculation units 21 and 21a of the time measurement circuits described in the first to third embodiments are implemented by a computer having a CPU (Central Processing Unit), a storage device, and an interface, and a program that controls these hardware resources. can be realized. A configuration example of this computer is shown in FIG. The computer includes a CPU 300 , a storage device 301 and an interface device (hereinafter abbreviated as I/F) 302 . The selector 20, the edge detection circuits 17, 17a, the D flip-flop circuits 18a, 18b, the encoder 19, the operation setting circuit 24, and the mask release timing control circuit 25 are connected to the I/F 302. FIG. In such a computer, a program for implementing the present invention is stored in storage device 301 . The CPU 300 executes the processes described in the first to third embodiments according to programs stored in the storage device 301 .

INDUSTRIAL APPLICABILITY The present invention can be applied to techniques for measuring time on the order of psec.

10, 18a, 18b, 112-1 to 112-16, 252 to 254... D flip-flop circuit 11a... Ring oscillator 12a, 12b... High speed counter 13, 111-1 to 111-15... Buffer circuit 14... Inverter 15, 16, 2326, 27 OR circuit 17, 17a Edge detection circuit 19 Encoder 20, 20a, 240, 241 Selector 21, 21a, 200 Time calculator 22, 28 Logic Circuits 24 Operation setting circuit 25 Mask release timing control circuit 110 NAND circuit 201 Test execution section 242, 250, 251 AND circuit.

Claims (14)

a flip-flop circuit configured to output an oscillation enable signal that becomes significant at the timing of the input of the start signal from the outside and becomes insignificant at the timing of the input of the stop signal from the outside;
an oscillator circuit configured to generate a first clock during a period in which the oscillation enable signal is significant;
a logic circuit configured to mask the first clock and a second clock obtained by inverting the first clock with the stop signal;
a first counter configured to count a first clock masked with the stop signal;
a second counter configured to count a second clock masked with the stop signal;
a selector configured to select, from among the count results of the first and second counters, the count result obtained by the counter that does not generate a clock input with an unacceptable time width;
A time calculation unit configured to calculate a time interval from the input of the start signal to the input of the stop signal based on the count result selected by the selector after the input of the stop signal. time measurement circuit. The time measurement circuit according to claim 1,
The selector selects the counting result of the first counter when the phase of the first clock is in a range from 0° to less than a predetermined first phase value smaller than 180°, and selects the phase of the first clock. is less than a predetermined second phase value of 180° or more and less than 360° from the first phase value, the counting result of the second counter is selected, and the phase of the first clock is the phase of the first clock. A time measuring circuit, wherein the counting result of the first counter is selected in a range of phase values of 2 or more and less than 360°. 3. The time measurement circuit according to claim 1 or 2,
The logic circuit is
a buffer circuit having an input of a first clock output from the oscillation circuit;
an inverter configured to generate the second clock obtained by inverting the first clock output from the oscillation circuit;
a first OR circuit configured to OR-mask the first clock output from the buffer circuit with the stop signal;
and a second OR circuit configured to OR-mask the second clock output from the inverter with the stop signal. a flip-flop circuit configured to output an oscillation enable signal that becomes significant at the timing of the input of the start signal from the outside and becomes insignificant at the timing of the input of the stop signal from the outside;
an oscillator circuit configured to generate a first clock during a period in which the oscillation enable signal is significant;
a logic circuit configured to generate a second clock by masking the first clock with the stop signal;
a first counter configured to count the first clock;
a second counter configured to count the second clock;
a selector configured to select, from among the count results of the first and second counters, the count result obtained by the counter that does not generate a clock input with an unacceptable time width;
A time calculation unit configured to calculate a time interval from the input of the start signal to the input of the stop signal based on the count result selected by the selector after the input of the stop signal. time measurement circuit. In the time measurement circuit according to claim 4,
The selector selects the counting result of the second counter when the phase of the first clock is in a range from 0° to less than a predetermined first phase value smaller than 180°, and selects the phase of the first clock. is less than a predetermined second phase value of 180° or more and less than 360° from the first phase value, the counting result of the first counter is selected, and the phase of the first clock is the first A time measuring circuit, wherein the counting result of the second counter is selected in a range of phase values of 2 or more and less than 360°. The time measurement circuit according to claim 4 or 5,
The time measurement, wherein the logic circuit comprises an OR circuit configured to generate the second clock by OR-masking the first clock output from the oscillation circuit with the stop signal. circuit. a test execution unit configured to test the timing circuit;
Selects and outputs the first start signal and the first stop signal input from the outside during normal operation, and selects the second start signal and the second stop signal output from the test execution unit during test execution. and an operation setting circuit configured to output a third stop signal at the end of the test;
so as to output an oscillation enable signal that becomes significant at the timing of input of the first start signal or the second start signal and becomes insignificant at the timing of input of the first stop signal or the third stop signal. a configured flip-flop circuit;
an oscillator circuit configured to generate a first clock during a period in which the oscillation enable signal is significant;
a logic circuit configured to mask the first clock and a second clock obtained by inverting the first clock with the first stop signal or the second stop signal, respectively;
a first counter configured to count a first clock masked with the first stop signal or the second stop signal;
a second counter configured to count a second clock masked with the first stop signal or the second stop signal;
a selector configured to select, from among the count results of the first and second counters, the count result obtained by the counter that does not generate a clock input with an unacceptable time width;
It is configured to calculate the time interval from the input of the first start signal to the input of the first stop signal based on the count result selected by the selector after the input of the first stop signal in normal times. and a time calculation unit,
The time measurement circuit, wherein the test execution unit tests the oscillation circuit by comparing count results of the first and second counters during test execution. The time measurement circuit according to claim 7,
The selector selects the counting result of the first counter when the phase of the first clock is in a range from 0° to less than a predetermined first phase value smaller than 180°, and selects the phase of the first clock. is less than a predetermined second phase value of 180° or more and less than 360° from the first phase value, the counting result of the second counter is selected, and the phase of the first clock is the phase of the first clock. A time measuring circuit, wherein the counting result of the first counter is selected in a range of phase values of 2 or more and less than 360°. The time measurement circuit according to claim 8,
The test execution unit performs the test when the phase of the first clock is a value immediately before the first phase value, when it is the first phase value, or when it is a value immediately after the first phase value. The count result of the first counter and the count result of the second counter are obtained and compared, and when the phase of the first clock is the value immediately before the second phase value, the second phase value is obtained. or a value immediately after the second phase value, the counting result of the first counter and the counting result of the second counter are obtained and compared. measurement circuit. In the time measurement circuit according to claim 9,
The test execution unit determines that the oscillation circuit is normal when the acquired count result of the first counter and the acquired count result of the second counter match, and counts the count of the first counter. A time measuring circuit that determines that the oscillation circuit is out of order when the result and the counting result of the second counter do not match. In the time measurement circuit according to claim 9 or 10,
The test execution unit performs the test when the phase of the first clock is a value immediately before the first phase value, when it is the first phase value, or when it is a value immediately after the first phase value. When the counting result of the first counter and the counting result of the second counter are obtained, after subtracting 1 from the obtained counting result of the second counter, the counting result of the first counter and the A time measuring circuit that compares the count result of a second counter. The time measurement circuit according to any one of claims 7 to 11,
The logic circuit is
a buffer circuit having an input of a first clock output from the oscillation circuit;
an inverter configured to generate the second clock obtained by inverting the first clock output from the oscillation circuit;
a fourth stop signal for masking the first clock later than the second clock and unmasking the second clock later than the second clock during test execution; A mask release timing control circuit configured to generate a fifth stop signal for masking prior to one clock and releasing mask prior to the first clock from the second stop signal. and,
a first OR circuit configured to OR-mask the first clock output from the buffer circuit with the first stop signal or the fourth stop signal;
a second OR circuit configured to OR-mask the second clock output from the inverter with the first stop signal or the fifth stop signal;
The oscillator circuit, the buffer circuit, and the inverter are characterized in that when the oscillation enable signal becomes significant, the second clock becomes significant before the first clock. time measurement circuit. In the time measurement circuit according to any one of claims 2, 5 and 8,
The time calculation unit subtracts 1 from the count result selected by the selector when the phase of the first clock is in the range of the first phase value or more and less than 360 degrees. A time measuring circuit, wherein the time interval is calculated from the time interval. The time measurement circuit according to any one of claims 1 to 13,
further comprising an encoder that outputs a signal indicating the phase value of the output of the oscillation circuit;
The time measuring circuit, wherein the selector selects one of the counting results of the first and second counters based on the signal output from the encoder.

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