JP7294149B2 - semiconductor equipment - Google Patents

Description

The disclosure described herein relates to a semiconductor device that includes a semiconductor chip and a heat dissipation member.

2. Description of the Related Art As disclosed in Patent Document 1, a semiconductor device including a semiconductor chip, a heat sink block, and a heat dissipation member is known. A semiconductor chip is provided between the heat sink block and the heat dissipation member. Each of the heat sink block and the heat dissipation member is connected to the semiconductor chip through solder.

JP 2003-158147 A

Solder is connected to the semiconductor chip as described above. The edge side of the solder has fewer heat transfer paths than the central side. Therefore, the thermal resistance tends to be high on the end side of the solder, and the range of temperature change tends to increase. Thermal expansion and contraction may damage the solder (conductive member).

Therefore, an object of the disclosure described in this specification is to provide a semiconductor device in which damage to a conductive member is suppressed.

One disclosed is a semiconductor substrate (11) having a first main surface (11a) arranged in the thickness direction and a second main surface (11b) on the back side thereof, and a semiconductor substrate (11) arranged in a plane direction along a plane orthogonal to the thickness direction. a plurality of semiconductor elements (12) formed on a semiconductor substrate in the manner described above, a first current-carrying electrode (20) formed on the first main surface, and a second current-carrying electrode (21) formed on the second main surface. a semiconductor chip (10) provided;
a first heat dissipation member (50) connected to the first conducting electrode via a first conductive member (92);
a second heat dissipation member (62) connected to the second current-carrying electrode via a second conductive member (93);
The first attachment area of the first conductive member attached to the first main surface side on which the first current-carrying electrode is formed is the first attachment area of the second conductive member attached to the second main surface side on which the second current-carrying electrode is formed. The area is narrower than the second attachment region,
The conducting ability of the semiconductor elements aligned in the thickness direction with the central side of the first attachment area is higher than the conducting ability of the semiconductor elements separated from the central side of the first attaching area in the planar direction,
a plurality of IGBTs (13) and a plurality of diodes (14) are formed as the plurality of semiconductor elements inside the semiconductor substrate,
A conductive region (18) connected to one of the first conductive electrodes and the second conductive electrodes of the plurality of semiconductor elements includes a collector layer for forming the IGBT and a conductive region (18) for forming the diode. a cathode layer of
Due to the difference in the formation ratio of the collector layer and the cathode layer per unit formation region, there is a difference in the current carrying capacity per unit formation region of the plurality of IGBTs.

According to this, the temperature of the semiconductor element (12) spaced apart from the central side of the first attachment region in the plane direction is difficult to rise. An increase in the width of change in the temperature of the semiconductor element (12) is suppressed. Therefore, an increase in the width of change in the temperature of the first conductive member (92) located near the semiconductor element (12) is suppressed. An increase in the expansion and contraction length of the first conductive member (92) due to temperature change is suppressed. Damage to the first conductive member (92) due to thermal expansion and contraction is suppressed.

It should be noted that the reference numbers in parentheses above merely indicate the correspondence with the configurations described in the embodiments described later, and do not limit the technical scope in any way.

1 is a cross-sectional view showing a schematic configuration of a semiconductor device; FIG. 1 is a perspective view for explaining an RC-IGBT formed on a semiconductor chip; FIG. 1 is a plan view of a semiconductor chip according to a first embodiment; FIG. 3 is an enlarged cross-sectional view for explaining a connection state on the end side of a semiconductor chip; FIG. FIG. 8 is a plan view of a semiconductor chip according to a second embodiment; FIG. 4 is a plan view for explaining the formation density of IGBTs;

Embodiments will be described below with reference to the drawings.

(First embodiment)
A semiconductor device 100 according to the present embodiment will be described with reference to FIGS. 1 to 4. FIG. Accordingly, the three directions that are orthogonal to each other are hereinafter referred to as the x-direction, the y-direction, and the z-direction. A direction along a plane orthogonal to the z-direction is simply referred to as a planar direction. The z direction corresponds to the thickness direction.

A semiconductor device 100 is a power card applied to a power conversion device such as an inverter or a converter. The semiconductor device 100 has a flat shape with a thin thickness in the z direction. The semiconductor device 100 has active elements and passive elements. These active and passive elements generate heat when energized. In order to suppress temperature rise due to such heat generation, the semiconductor device 100 is provided in the cooler 200 shown in FIG.

<Cooler>
The cooler 200 has a first cooling section 210 and a second cooling section 220 in which a coolant flows. The first cooling section 210 and the second cooling section 220 are arranged in a manner facing each other while being spaced apart in the z-direction.

An electrical insulating member 230 having excellent thermal conductivity is provided on each facing surface of the first cooling section 210 and the second cooling section 220 . The semiconductor device 100 is provided between the electrical insulating member 230 provided on the facing surface of the first cooling section 210 and the electrical insulating member 230 provided on the facing surface of the second cooling section 220 . The semiconductor device 100 is in contact with each of these two electrical insulating members 230 in a manner facing each other in the z-direction.

To the cooler 200, a spring body (not shown) applies an urging force such that the first cooling section 210 and the second cooling section 220 approach each other in the z direction. This biasing force increases the contact area between the semiconductor device 100 and the electrical insulating member 230 provided between the first cooling section 210 and the second cooling section 220 . Thermal resistance between the semiconductor device 100 and the electrical insulating member 230 is reduced.

Due to this mechanical configuration, the heat generated in the semiconductor device 100 is transferred to the coolant flowing inside the first cooling section 210 via the electrical insulating member 230 and the first cooling section 210 . At the same time, the heat generated in the semiconductor device 100 is transferred to the coolant flowing inside the second cooling section 220 via the electrical insulating member 230 and the second cooling section 220 . Thus, the semiconductor device 100 is cooled on both sides. Thereby, the temperature rise of the semiconductor device 100 is suppressed.

As described above, the cooler 200 shown in FIG. 1 has a so-called double-sided cooling configuration. However, the configuration of the cooler 200 is not limited to the above example. As the configuration of the cooler 200, for example, a single-sided cooling configuration can be adopted.

<Semiconductor device>
As shown in FIG. 1 , the semiconductor device 100 has a semiconductor chip 10 , terminals 50 , main conductive portions 60 , conducting terminals 70 , signal terminals 80 and sealing resin 90 .

The main conductive portion 60, the current-carrying terminals 70, and the signal terminals 80 are part of a lead frame (not shown). The semiconductor chip 10 and the terminal 50 are connected to this lead frame. These are partially covered with a sealing resin 90 . A portion of the lead frame exposed outside the sealing resin 90 is selectively removed. Thereby, the main conductive portion 60, the current-carrying terminal 70, and the signal terminal 80 are formed. At the same time, the semiconductor device 100 is manufactured. It should be noted that the main conductive portion 60, the energizing terminals 70, and part of the signal terminals 80 may be composed of a metal plate separate from the lead frame.

As shown in FIG. 1, the main conductive portion 60 has an upper conductive portion 61 and a lower conductive portion 62 . The conducting terminal 70 has an upper conducting terminal 71 and a lower conducting terminal 72 . The upper conducting terminal 71 and the upper conducting portion 61 are integrally connected. The lower conductive terminal 72 and the lower conductive portion 62 are integrally connected.

The upper conductive portion 61 and the lower conductive portion 62 are spaced apart so as to face each other in the z direction. A semiconductor chip 10 and a terminal 50 are provided between the upper conductive portion 61 and the lower conductive portion 62 .

The semiconductor chip 10 has a first principal surface 11a and a second principal surface 11b aligned in the z-direction. The first main surface 11 a side of the semiconductor chip 10 is connected to the upper conductive portion 61 via the terminal 50 . The second main surface 11 b side of the semiconductor chip 10 is connected to the lower conductive portion 62 . With such a configuration, the semiconductor chip 10 is electrically connected to the upper conductive portion 61 and the lower conductive portion 62, respectively.

The tip side of each of the upper conductive terminal 71 and the lower conductive terminal 72 is exposed to the outside of the sealing resin 90 . The tip end sides of the upper energization terminal 71 and the lower energization terminal 72 are connected to conductive busbars forming the energization path of the power converter. As a result, the current of the power converter flows through the main conductive portion 60 , the terminal 50 and the semiconductor chip 10 between the upper conducting terminal 71 and the lower conducting terminal 72 .

The semiconductor chip 10 is connected to signal terminals 80 via wires 81 . The tip side of the signal terminal 80 is exposed outside the sealing resin 90 . The tip side of this signal terminal 80 is connected to a driver board for controlling the drive of the power converter.

Note that the semiconductor device 100 may have a plurality of semiconductor chips 10 instead of one. The semiconductor device 100 may have terminals 50 , main conductive portions 60 , conducting terminals 70 , and signal terminals 80 corresponding to each of the plurality of semiconductor chips 10 . However, the semiconductor device 100 may share some of the terminals 50 , the main conductive portions 60 , the conducting terminals 70 , and the signal terminals 80 corresponding to the plurality of semiconductor chips 10 . The constituent elements of the semiconductor device 100 will be individually described below.

<Semiconductor chip>
The semiconductor chip 10 has a semiconductor substrate 11 and a semiconductor element 12 formed on this semiconductor substrate 11 . The outer shape of the semiconductor chip 10 is roughly the same as the outer shape of the semiconductor substrate 11 .

The semiconductor substrate 11 is made of a semiconductor material such as Si, SiC, or GaN. The semiconductor substrate 11 has a flat plate shape with a thin thickness in the z direction. The semiconductor substrate 11 has two main surfaces aligned in the z direction. One of these two main surfaces corresponds to the above-described first main surface 11a. The other of the two main surfaces corresponds to the second main surface 11b. A semiconductor element 12 is formed inside between the first main surface 11a and the second main surface 11b of the semiconductor substrate 11 .

The semiconductor element 12 is an RC (Reverse Conducting)-IGBT forming part of the circuit of the power conversion device. The IGBT 13 and the diode 14 included in the RC-IGBT have a vertical structure in which current flows between the first main surface 11a and the second main surface 11b of the semiconductor substrate 11 .

In addition to the IGBT 13 and the diode 14, the semiconductor substrate 11 is formed with a sensor element such as a temperature-sensitive diode for detecting the temperature of the semiconductor substrate 11 (not shown).

Inside the semiconductor substrate 11, a plurality of impurity-containing layers forming the IGBTs 13 and the diodes 14 are formed. Specifically, as shown in FIG. 2, the first electrode layer 15, the base layer 16, the drift layer 17, and the second electrode layer 18 are semiconductors in this order from the first main surface 11a toward the second main surface 11b. It is formed inside the substrate 11 .

The first electrode layer 15 has an emitter layer 15a and a contact layer 15b. The emitter layers 15a and the contact layers 15b are alternately arranged in the y direction. Although not shown, the second electrode layer 18 has a collector layer and a cathode layer. The collector layer and the cathode layer are arranged in a planar direction perpendicular to the z-direction.

Each of the emitter layer 15a, the drift layer 17, and the cathode layer shown above is an N-type semiconductor. Each of the contact layer 15b, base layer 16, and collector layer is a P-type semiconductor.

Further, as shown in FIG. 2, in the semiconductor substrate 11, a plurality of trench gate electrodes 19 penetrating halfway through the drift layer 17 via the first electrode layer 15 and the base layer 16 are formed in addition to the above-described impurity containing layers. It is Each of the plurality of trench gate electrodes 19 extends in the y direction. A plurality of trench gate electrodes 19 are spaced apart in the x direction.

The IGBT 13 is composed of an emitter layer 15a, a contact layer 15b, a base layer 16, a drift layer 17, a trench gate electrode 19, and a collector layer located within a z-direction projection region of the collector layer. The diode 14 is composed of an emitter layer 15a, a contact layer 15b, a base layer 16, a drift layer 17, and a cathode layer located within the z-direction projection area of the cathode layer.

As shown in FIG. 1, an emitter electrode 20 is formed on the first main surface 11a of the semiconductor substrate 11. As shown in FIG. Emitter electrode 20 is electrically connected to each of emitter layer 15a and contact layer 15b located on the first main surface 11a side. A collector electrode 21 is formed on the second main surface 11b. The collector electrode 21 is electrically connected to each of the collector layer and the cathode layer located on the second main surface 11b side. With the above configuration, the IGBT 13 and the diode 14 are connected in parallel between the emitter electrode 20 and the collector electrode 21 .

As shown in FIG. 2, the emitter layers 15a and the contact layers 15b are alternately arranged in the y direction between two trench gate electrodes 19 spaced apart in the x direction. Due to this arrangement, a plurality of minute IGBTs 13 with the energized regions partitioned are spaced apart in the y direction. Similarly, a plurality of minute diodes 14 with a sectioned conducting area are arranged in the y direction with a space therebetween. The IGBT 13 corresponds to a switch element.

Note that FIG. 2 shows an example in which the plurality of trench gate electrodes 19 extend in the y direction and are spaced apart in the x direction. That is, an example is shown in which a plurality of trench gate electrodes 19 are laid out in stripes on a plane perpendicular to the z-direction. However, the layout of the trench gate electrode 19 is not limited to the above example. For example, a configuration in which a plurality of trench gate electrodes 19 are laid out in a grid pattern or honeycomb pattern may be employed. A configuration in which the emitter layers 15a and the contact layers 15b are alternately arranged in the x direction can also be adopted. In the case of such a configuration, a plurality of minute IGBTs 13 and diodes 14 are aligned not only in the y direction but also in the x direction. A plurality of minute IGBTs 13 and diodes 14 are arranged in a planar direction.

As shown in FIGS. 1 and 3, emitter electrode 20 is partially formed on first main surface 11a. Unlike this, the collector electrode 21 is formed entirely on the second main surface 11b.

The impurity-containing layer forming the IGBT 13 and the diode 14 described above is formed directly below the emitter electrode 20 . Therefore, the conducting region of the IGBT 13 and the diode 14 is mainly directly under the emitter electrode 20 .

As shown in FIG. 3, an electrode pad 22 is formed in addition to the emitter electrode 20 on the first main surface 11a. Emitter electrode 20 and electrode pad 22 are separated from each other on first main surface 11a.

In this embodiment, electrode pads 22 for the following five uses are formed on the first main surface 11a. That is, electrode pads 22 for the gate electrode of the IGBT 13, the Kelvin emitter for detecting the potential of the emitter electrode 20, the current sense, the anode potential of the temperature sensitive diode, and the cathode potential thereof are formed on the first main surface 11a. It is

These five electrode pads 22 are spaced apart in the x-direction. At the same time, the five electrode pads 22 are separated from the emitter electrode 20 in the y direction. The terminal 50 described above is electrically connected to the emitter electrode 20 so as to face it in the z-direction.

<Terminal>
Terminal 50 electrically and thermally connects upper conductive portion 61 and semiconductor chip 10 . The terminal 50 is made of a metallic material such as Cu or its alloy having electrical conductivity and thermal conductivity.

The terminal 50 has a substantially rectangular parallelepiped shape. The terminal 50 is provided between the upper conductive portion 61 and the semiconductor chip 10 in the z direction. The upper surface 50a of the terminal 50 is arranged to face the first connection surface 61a of the upper conductive portion 61 in the z-direction. A lower surface 50b of the terminal 50 is arranged to face the emitter electrode 20 of the semiconductor chip 10 in the z direction.

<Main conductive part>
The main conductive portion 60 has a function of electrically connecting the semiconductor chip 10 and the conducting terminal 70 . In addition, the main conductive portion 60 also functions to dissipate heat generated in the semiconductor chip 10 . The main conductive portion 60 is made of a metal material such as Cu or its alloy having electrical conductivity and thermal conductivity.

As described above, the main conductive portion 60 has the upper conductive portion 61 and the lower conductive portion 62 . As shown in FIG. 1, the first connection surface 61a of the upper conductive portion 61 and the second connection surface 62a of the lower conductive portion 62 are arranged in a manner to face each other while being spaced apart in the z direction. A semiconductor chip 10 and a terminal 50 are provided between the upper conductive portion 61 and the lower conductive portion 62 . A terminal 50 is provided on the upper conductive portion 61 side. A semiconductor chip 10 is provided on the lower conductive portion 62 side.

A first solder 91 is interposed between the first connection surface 61 a of the upper conductive portion 61 and the upper surface 50 a of the terminal 50 . Upper conductive portion 61 and terminal 50 are electrically and mechanically connected via first solder 91 .

A second solder 92 is interposed between the lower surface 50 b of the terminal 50 and the emitter electrode 20 of the semiconductor chip 10 . Terminal 50 and emitter electrode 20 are electrically and mechanically connected via second solder 92 . A region of the emitter electrode 20 to which the second solder 92 is attached corresponds to a first attachment region.

A third solder 93 is interposed between the collector electrode 21 of the semiconductor chip 10 and the second connection surface 62 a of the lower conductive portion 62 . Collector electrode 21 and lower conductive portion 62 are electrically and mechanically connected via third solder 93 . A region of the collector electrode 21 to which the third solder 93 is attached corresponds to a second attachment region.

With the connection configuration described above, the semiconductor element 12 of the semiconductor chip 10 is electrically connected to the upper conductive portion 61 and the lower conductive portion 62 .

As shown in FIG. 1, the first connection surface 61a side of the upper conductive portion 61 to which the terminal 50 is connected and the second connection surface 62a side of the lower conductive portion 62 to which the semiconductor chip 10 is connected are sealed. It is coated with resin 90 . However, the first heat radiation surface 61b on the back side of the first connection surface 61a in the upper conductive portion 61 and the second heat radiation surface 62b on the back side of the second connection surface 62a in the lower conductive portion 62 are exposed from the sealing resin 90. It is

The electric insulating member 230 is in contact with the first heat radiation surface 61b and the second heat radiation surface 62b exposed from the sealing resin 90, respectively. Due to this configuration, Joule heat generated in the semiconductor device 100 due to energization is actively conducted to the cooler 200 via the electrical insulating member 230 .

<Conducting terminal>
The energization terminal 70 functions as a connection terminal with a bus bar that constitutes the energization path of the power conversion circuit. A current between the emitter and the collector of the IGBT 13 and a current between the anode and the cathode of the diode 14 flow through the conducting terminal 70 .

As described above, the conducting terminal 70 has the upper conducting terminal 71 and the lower conducting terminal 72 . As shown in FIG. 1, the upper conducting terminal 71 is integrally connected to the upper conducting portion 61 . The lower conducting terminal 72 is integrally connected to the lower conducting portion 62 . A sealing resin 90 covers the connection side of each of the plurality of conducting terminals with the conducting portion. Further, the tip side of each of the plurality of conducting terminals is exposed from the sealing resin 90 . A bus bar forming a current path of the above-described power conversion device is connected to the distal end side of the current-carrying terminal by laser welding or the like.

<Signal terminal>
The signal terminal 80 functions as a connection terminal with the driver board. As described above, the semiconductor chip 10 has five electrode pads 22 formed thereon. The semiconductor device 100 has five signal terminals 80 corresponding to these five electrode pads 22 respectively. These five electrode pads 22 and five signal terminals 80 are electrically connected via wires 81 .

A wire 81 connection side of the signal terminal 80 is covered with a sealing resin 90 . The tip side of the signal terminal 80 is exposed from the sealing resin 90 . The tip side of the signal terminal 80 is connected to the driver board by soldering or the like.

<Encapsulation resin>
The sealing resin 90 is made of epoxy resin, for example. The sealing resin 90 is molded by, for example, a transfer molding method. As shown in FIG. 1, the sealing resin 90 has one surface 90a and a back surface 90b arranged in the z direction, and a side surface 90c connecting them.

The first heat radiation surface 61 b of the upper conductive portion 61 exposed from the sealing resin 90 is flush with the one surface 90 a of the sealing resin 90 . An electrical insulating member 230 on the first cooling section 210 side is in contact with each of the first heat radiation surface 61b and the one surface 90a.

Similarly, the second heat dissipation surface 62b of the lower conductive portion 62 exposed from the sealing resin 90 is flush with the rear surface 90b of the sealing resin 90. As shown in FIG. The electrical insulating member 230 on the side of the second cooling section 220 is in contact with each of the second heat radiation surface 62b and the back surface 90b.

Further, the leading end sides of the conductive terminals 70 and the signal terminals 80 are exposed from the side surface 90 c of the sealing resin 90 . The exposed surface of the conducting terminal 70 and the exposed surface of the signal terminal 80 on the side surface 90c are separated in the y direction. The leading end sides of the energizing terminal 70 and the signal terminal 80 extend in the y-direction so as to be separated from the sealing resin 90 .

<Conductive member>
As described above, the semiconductor chip 10, the terminals 50, and the main conductive portion 60 are connected by the first to third solders 91-93. Therefore, as shown in FIGS. 1 and 4, the thickness in the z direction is constant on the central side of the plane orthogonal to the z direction of the plurality of solders. On the other hand, the end sides of the plurality of solders on the plane orthogonal to the z-direction are meniscus-shaped thin-walled portions having a thin thickness in the z-direction. 4, illustration of the first solder 91, the emitter electrode 20, and the collector electrode 21 is omitted.

<Thin part>
The first solder 91 adheres to the first connecting surface 61 a of the upper conductive portion 61 and the upper surface 50 a of the terminal 50 . The area of the first connection surface 61a is wider than that of the upper surface 50a. Therefore, the first solder 91 wets and spreads between the first connection surface 61a and the top surface 50a, and also wets and spreads outside the region of the first connection surface 61a facing the top surface 50a in the z direction. A thin portion of the first solder 91 is formed outside the region of the first connection surface 61a facing the upper surface 50a. The thin portion of the first solder 91 has an annular shape surrounding the upper surface 50a of the terminal 50 in the circumferential direction around the z direction.

The second solder 92 adheres to the lower surface 50b of the terminal 50 and the emitter electrode 20 of the semiconductor chip 10. As shown in FIG. The area of the lower surface 50 b is narrower than that of the emitter electrode 20 . Therefore, the second solder 92 wets and spreads between the lower surface 50b and the emitter electrode 20, and also wets and spreads outside the region of the emitter electrode 20 facing the lower surface 50b in the z direction. A thin portion of the second solder 92 is formed outside the region of the emitter electrode 20 facing the lower surface 50b. The thin portion of the second solder 92 has an annular shape surrounding the lower surface 50b of the terminal 50 in the circumferential direction around the z-direction.

The third solder 93 adheres to the collector electrode 21 on the second main surface 11 b of the semiconductor chip 10 and the second connecting surface 62 a of the lower conductive portion 62 . The area of the collector electrode 21 is narrower than that of the second connection surface 62a. Therefore, the third solder 93 wets and spreads between the collector electrode 21 and the second connection surface 62a, and also wets and spreads outside the region of the second connection surface 62a facing the collector electrode 21 in the z direction. A thin portion of the third solder 93 is formed outside the region facing the collector electrode 21 on the second connection surface 62a. The thin portion of the third solder 93 has an annular shape surrounding the collector electrode 21 in the circumferential direction around the z direction.

Terminal 50 corresponds to a first heat radiation member. The second solder 92 corresponds to the first conductive member. The emitter electrode 20 corresponds to the first conducting electrode. The collector electrode 21 corresponds to a second conducting electrode. The third solder 93 corresponds to a second conductive member. The lower conductive portion 62 corresponds to a second heat dissipation member.

<Thin part of the second solder>
FIG. 3 shows a projection area of the lower surface 50b of the terminal 50 onto the emitter electrode 20 along the z-direction surrounded by a dashed line. At the same time, the region where the emitter electrode 20 is formed is shown surrounded by a solid line.

As clearly shown in FIG. 3, the projection area of the lower surface 50b of the terminal 50 along the z-direction toward the emitter electrode 20 is within the formation area of the emitter electrode 20 on the first main surface 11a. Therefore, an annular region is formed between the dashed demarcation line indicating the end of the projection region of the lower surface 50 b and the solid demarcation line indicating the end of the emitter electrode 20 . A meniscus-shaped thin portion of the second solder 92 is formed in this annular region. A thin portion of the second solder 92 is connected to the end side region of the emitter electrode 20 . In FIG. 4, a boundary line BL is illustrated by a dashed line on the boundary between the projection area of the lower surface 50b and the outside thereof.

<Heat dissipation performance>
As described above, the emitter electrode 20 is partially formed on the first main surface 11a of the semiconductor substrate 11, and the collector electrode 21 is formed entirely on the second main surface 11b. As shown in FIGS. 2 and 3, the emitter electrode 20 is formed on the central side of the semiconductor substrate 11, but the formation area on the edge side of the semiconductor substrate 11 is small.

Therefore, on the central side of the semiconductor substrate 11, Joule heat generated in the semiconductor chip 10 is transferred to the main conductive portion through both the second solder 92 attached to the emitter electrode 20 and the third solder 93 attached to the collector electrode 21. 60 is thermally conducted. However, Joule heat generated in the semiconductor chip 10 is conducted to the main conductive portion 60 via the third solder 93 attached to the collector electrode 21 on the edge side of the semiconductor substrate 11 . For this reason, the heat dissipation performance of the edge side of the semiconductor substrate 11 is about half that of the center side. Due to such a difference in heat dissipation performance, it is desirable to have a configuration in which the current carrying capacity on the edge side of the semiconductor substrate 11 is half or less of the current carrying capacity on the central side of the semiconductor substrate 11 .

<Electrical capacity difference>
As described with reference to FIG. 2, the semiconductor substrate 11 is formed with a plurality of small IGBTs 13 and diodes 14 each having a sectioned conducting region. By adopting the configuration illustrated below for the plurality of IGBTs 13 and diodes 14 , it is possible to provide a difference in current-carrying capability between the plurality of IGBTs 13 and diodes 14 . It is possible to provide a difference in current-carrying capability between the IGBT 13 and the diode 14 included per unit formation area. In the following, a configuration in which the current carrying capacity of the IGBTs 13 included in each unit formation region is differentiated will be exemplified.

As shown in FIG. 2, the length of one emitter layer 15a in the y direction is L1. Let L2 be the length in the y direction of a pair of the emitter layer 15a and the contact layer 15b arranged in the y direction. The value of L1/L2 is varied in the planar direction. By doing so, it is possible to provide a difference in the easiness of formation of the channel of the first electrode layer 15 included in each unit formation area. A difference can be provided in the amount of saturation current during a short circuit. As a result, a difference can be provided in the energization capability of the IGBTs 13 included in each unit formation area. Emitter layer 15a corresponds to a first impurity layer. Contact layer 15b corresponds to a second impurity layer. It should be noted that the dimensions of the lengths L1 and L2 can be changed by changing the formation pattern of the mask used when forming the first electrode layer 15 in the wafer process. Therefore, it is not necessary to add a new manufacturing process.

For example, L1/L2=0.8 on the center side of the semiconductor substrate 11 in the planar direction, and L1/L2=0.2 on the edge side of the semiconductor substrate 11 . By doing so, the conducting ability of the IGBTs 13 on the edge side of the semiconductor substrate 11 becomes lower than the conducting ability of the IGBTs 13 on the central side of the semiconductor substrate 11 . Particularly in the case of the above example, the current carrying capacity of the edge side of the semiconductor substrate 11 is less than half that of the central side.

Moreover, the formation area (contact area) of the emitter electrode 20 with respect to the emitter layer 15a provided for each of the plurality of IGBTs 13 is made different. By narrowing this contact area, it is possible to lower the current-carrying capacity.

A difference is provided in the formation density per unit formation area of the IGBTs 13 in the planar direction. For example, by providing a difference in adjacent intervals between the plurality of trench gate electrodes 19, a difference is provided in the density of formation of the IGBTs 13 per unit formation area. By increasing the distance between adjacent trench gate electrodes 19, the density of the regions of the IGBT 13 connected to the trench gate electrodes 19 can be reduced. By narrowing the formation density of the channels, the current carrying capacity can be lowered.

A gate voltage is applied to some of the plurality of trench gate electrodes 19 . Some of the plurality of trench gate electrodes 19 are activated and others are deactivated. By doing so, a difference is provided in the channel formation density per unit formation area. Thereby, a difference is provided in the energization capability of the IGBT 13 per unit formation area. In this configuration, the intervals between adjacent trench gate electrodes 19 may be constant.

A ratio of the trench gate electrodes 19 to which a gate voltage is applied among the plurality of trench gate electrodes 19 is made smaller on the edge side of the semiconductor substrate 11 than on the center side. For example, the ratio of the trench gate electrodes 19 to which the gate voltage is applied is less than half on the edge side of the semiconductor substrate 11 compared to the center side. As a result, the conducting capability of the IGBTs 13 on the edge side of the semiconductor substrate 11 is less than half of the conducting capability of the IGBTs 13 on the central side of the semiconductor substrate 11 .

A difference is provided in the impurity concentration of the emitter layer 15a and the collector layer provided for each of the plurality of IGBTs 13 . By lowering the impurity concentration, the current carrying capacity can be lowered. The emitter layer 15a and the collector layer correspond to conductive regions.

A defect is formed inside the semiconductor substrate 11 . Then, the number of defects is differentiated between the plurality of IGBTs 13 . The larger the number of defects, the shorter the hole lifetime. Therefore, by increasing the number of defects, the current-carrying capacity can be lowered.

The trench gate electrode 19 described above comprises a gate oxide film. By providing a difference in the thickness of the gate oxide film, a difference is provided in the conduction capability of the IGBT 13 included in each unit formation area. The thicker the gate oxide film, the more difficult it is to form a channel. Therefore, by thickening the gate oxide film, the current-carrying ability can be lowered.

Further, by providing a difference in the impurity concentration of the base layer 16, a difference is provided in the conduction capability of the IGBTs 13 included in each unit formation region. As the impurity concentration of the base layer 16 increases, it becomes more difficult to form a channel. Therefore, by increasing the impurity concentration of the base layer 16, the current carrying capability can be lowered. The first electrode layer 15 corresponds to the first conductive region. The second electrode layer 18 corresponds to the second conductive region. The base layer 16 corresponds to the conductive layer.

A difference is provided in the formation ratio of the collector layer and the cathode layer included in the second electrode layer 18 . As the formation ratio of the cathode layer to the collector layer increases, the current-carrying capability of the IGBT 13 included per unit formation area in the planar direction can be lowered.

It should be noted that the semiconductor substrate 11 may employ a configuration in which only active elements, such as the IGBT 13 , which constitute the circuit of the power conversion device, are formed as the semiconductor elements 12 .

In this modified example, in order to provide a difference in the current-carrying capability of the IGBT 13 included in each unit formation region, as described above, a difference is provided in the contact area between the impurity-containing layer constituting the IGBT 13 and the emitter electrode 20, or a semiconductor device is used. A plurality of non-conducting regions may be formed on the substrate 11 . By providing a difference in the formation ratio of the energized region and the non-energized region included in each unit formation region, it is possible to provide a difference in the energized region included in each unit formation region.

In this embodiment, by adopting at least one of the configurations described above, a difference is provided in the current-carrying capability of the plurality of minute IGBTs 13 formed on the semiconductor substrate 11 . More specifically, the IGBT 13 facing the center side of the emitter electrode 20 formed on the first main surface 11a of the semiconductor substrate 11 in the z direction faces the end side of the emitter electrode 20 in the z direction rather than the conducting capability of the IGBT 13. The energization capability of the IGBT 13 is lowered. In other words, the conduction capability of the IGBTs 13 aligned in the z-direction with the end side of the adhesion region is lower than the conduction capability of the IGBTs 13 aligned in the z-direction with the center side of the adhesion region of the second solder 92 that is entirely attached to the emitter electrode 20 . lowering

Referring to FIG. 3, the conduction capability of the IGBTs 13 aligned in the z-direction with the central side of the second solder 92 immediately below the projection area of the lower surface 50b of the terminal 50 surrounded by the dashed line is made constant. IGBTs 13 aligned in the z-direction with the end side of the annular second solder 92 located between the dashed demarcation line indicating the end of the projection area of the lower surface 50 b and the solid demarcation line indicating the end of the emitter electrode 20 . It reduces the current carrying capacity. That is, the current-carrying capability of the meniscus-shaped thin portion of the second solder 92 and the IGBT 13 arranged in the z-direction is lowered.

In FIG. 4 , regions with different current-carrying capabilities of the IGBTs 13 included in each unit formation region are clearly shown by providing different hatchings on the semiconductor substrate 11 . It is shown that the rougher the hatching density, the lower the current-carrying ability. In the semiconductor substrate 11, the density of the hatching applied is made coarser in the order of the region immediately below the center side of the adhesion region of the second solder 92, the region immediately below the end side of the adhesion region of the second solder 92, and the non-formation region of the IGBT 13 in this order. ing.

With such a configuration, the IGBT 13 with a constant current-carrying capacity and the portion of the second solder 92 with a constant thickness in the z-direction are aligned in the z-direction. At the same time, the IGBT 13 having a low current-carrying capacity and the thin portion of the second solder 92 having a small thickness in the z-direction are arranged in the z-direction.

In addition, a difference may be provided in the current carrying capacity of the IGBTs 13 directly below the projection area of the lower surface 50 b of the terminal 50 . For example, the conducting ability of the IGBTs 13 positioned on the end side of the projection area may be lower than the conducting ability of the IGBTs 13 positioned on the central side of the projection area.

<Effect>
According to the configuration described so far in this embodiment, the conduction capability of the IGBTs 13 arranged in the z-direction on the end side separated from the center side of the emitter electrode 20 in the plane direction is low. Therefore, the temperature of the IGBT 13 is difficult to rise. An increase in the width of change in the temperature of the IGBT 13 is suppressed. Therefore, an increase in the width of change in the temperature of the second solder 92 located near the IGBT 13 is suppressed. An increase in the expansion/contraction length of the second solder 92 due to temperature change is suppressed. Damage to the second solder 92 due to thermal expansion and contraction is suppressed.

The shape of the end side of the second solder 92 in the planar direction is determined depending on the shapes of the terminal 50 and the emitter electrode 20 to be bonded. Therefore, the end side of the second solder 92 tends to include locations where local stress concentration is likely to occur. In addition, the temperature of the second solder 92 tends to rise due to the small number of heat transfer paths. The IGBT 13 having a low current-carrying capacity is positioned near the end of the second solder 92 . Due to such a configuration, it is possible to suppress the occurrence of damage on the end side of the second solder 92 due to thermal expansion and contraction due to temperature change.

A thin portion of the second solder 92 is formed on the end side of the emitter electrode 20 . The thin portion has a meniscus shape with a thin thickness in the z direction. This thin portion and the IGBT 13 having a low current-carrying capacity are arranged in the z-direction. Due to such a configuration, an increase in the width of change in the temperature of the thin portion of the second solder 92 is suppressed. Damage to the thin portion of the second solder 92 with low strength due to thermal expansion and contraction due to temperature change is suppressed.

(Second embodiment)
Next, a second embodiment will be described with reference to FIGS. 5 and 6. FIG. The semiconductor devices according to the embodiments and modifications described below have many points in common with those according to the above-described embodiments. Therefore, the description of the common parts will be omitted, and the different parts will be mainly described below. Also, hereinafter, the same reference numerals are given to the same elements as those shown in the above-described embodiment.

In the first embodiment, the example in which the second solder 92 is attached to the entire surface of the emitter electrode 20 is shown. An example in which the semiconductor element 12 is formed immediately below the second solder 92 attached to the emitter electrode 20 on the semiconductor substrate 11 is shown.

On the other hand, in this embodiment, the second solder 92 is attached to part of the emitter electrode 20 . Then, the semiconductor element 12 is formed directly below the second solder 92 attached to the emitter electrode 20 on the semiconductor substrate 11 and outside the region directly below. In FIG. 5, a formation region A in which the semiconductor element 12 is formed outside immediately below the second solder 92 is indicated by hatching. A configuration in which the emitter electrode 20 is not formed in the semiconductor element 12 in the formation region A can also be adopted. The semiconductor element 12 positioned outside directly below the second solder 92 corresponds to the semiconductor element positioned in the outer region.

As described in the first embodiment, five electrode pads 22 are spaced apart in the x-direction and arranged side by side on the first main surface 11a. The formation regions A described above are formed at both ends of the five electrode pads 22 and between them.

The second solder 92 is not adhered to the emitter electrode 20 of the semiconductor element 12 formed in this forming area A. As shown in FIG. Therefore, the semiconductor element 12 in the formation region A has a lower heat dissipation property. There is a possibility that the temperature of this formation area A may rise locally.

In order to avoid the local temperature rise described above, the current carrying capability of the IGBT 13 included in the formation region A is lower than the current carrying capability of the IGBT 13 formed immediately below the second solder 92 .

In order to provide a difference in the energization capability of the IGBT 13, the configuration shown in the first embodiment may be appropriately adopted. For example, as specifically shown in FIG. 6, the y-direction length L2 of a pair of emitter layer 15a and contact layer 15b arranged in the y-direction is constant. Instead of the y-direction length L1 of one emitter layer 15a formed directly under the second solder 92, the y-direction length of the emitter layer 15a included in the formation region A outside the second solder 92 is Shorten the length L1'. In FIG. 6 , a dividing line LL is illustrated by a dashed line on the boundary between the region of the semiconductor substrate 11 aligned directly below the second solder 92 and the outside thereof.

By doing so, the conducting ability of the IGBTs 13 included in the formation region A can be lowered. A local increase in the temperature of the formation region A is suppressed. Variation in the temperature distribution of the semiconductor chip 10 is suppressed. At the same time, since the semiconductor element 12 is also formed in the formation region A, the output of the semiconductor chip 10 is improved.

The semiconductor device 100 according to the present embodiment includes components equivalent to those of the semiconductor device 100 described in the first embodiment. Therefore, it goes without saying that the same effect can be obtained.

Although the preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present disclosure.

DESCRIPTION OF SYMBOLS 10... Semiconductor chip 11... Semiconductor substrate 11a... 1st main surface 11b... 2nd main surface 12... Semiconductor element 13... IGBT 14... Diode 15... First electrode layer 15a... Emitter layer 15b Contact layer 16 Base layer 18 Second electrode layer 19 Trench gate electrode 20 Emitter electrode 21 Collector electrode 50 Terminal 61 Upper conductive portion 62 Lower conductive portion 91 ...first solder 92...second solder 93...third solder 100...semiconductor device

Claims (14)

A semiconductor substrate (11) having a first main surface (11a) arranged in a thickness direction and a second main surface (11b) on the back side thereof, and the semiconductor substrate arranged in a plane direction along a plane orthogonal to the thickness direction. a plurality of semiconductor elements (12) formed on a semiconductor device, a first current-carrying electrode (20) formed on the first main surface, and a second current-carrying electrode (21) formed on the second main surface. a chip (10);
a first heat radiation member (50) connected to the first conducting electrode via a first conductive member (92);
a second heat dissipation member (62) connected to the second current-carrying electrode via a second conductive member (93);
A first attachment region of the first conductive member attached to the first main surface side on which the first conducting electrode is formed is attached to the second main surface side on which the second conducting electrode is formed. The area is narrower than the second attachment region of the second conductive member,
The conducting capability of the semiconductor element aligned in the thickness direction with the central side of the first attachment region is higher than the conducting capability of the semiconductor element spaced apart from the central side of the first attaching region in the planar direction. cage,
A plurality of IGBTs (13) and a plurality of diodes (14) are formed as the plurality of semiconductor elements inside the semiconductor substrate,
A conductive region (18) connected to one of the first conductive electrodes and the second conductive electrodes of the plurality of semiconductor elements includes a collector layer for forming the IGBT and a conductive region (18) for forming the diode. a cathode layer of
A semiconductor device having a difference in current carrying capacity per unit formation region of the plurality of IGBTs due to a difference in formation ratio between the collector layer and the cathode layer per unit formation region. Compared to the conducting ability of the semiconductor elements arranged in the thickness direction with the central side of the first attaching area, the conducting ability of the semiconductor elements separated from the central side of the first attaching area in the planar direction is half or less. A semiconductor device according to claim 1. 2. The semiconductor element aligned in the thickness direction with the central side of the first attachment region has a higher electrical conductivity than the semiconductor element aligned in the thickness direction with the end side of the first attachment region. 3. The semiconductor device according to claim 2. 4. The semiconductor device according to claim 3, wherein at least part of an end side of said first attachment region is positioned outside a region projected onto said first main surface along said thickness direction of said first heat radiation member. Conductivity of the semiconductor element aligned in the thickness direction with respect to the central side of the first attachment region is higher than that of the semiconductor element positioned outside the first attachment region on the first main surface. 5. The semiconductor device according to claim 1. 6. The semiconductor device according to any one of claims 1 to 5, wherein a difference in formation area of said first conducting electrodes of said plurality of semiconductor elements results in a difference in conducting ability of said plurality of semiconductor elements. 7. The semiconductor according to any one of claims 1 to 6, wherein a difference in formation density per unit formation region of said plurality of semiconductor elements results in a difference in current carrying capability per unit formation region of said plurality of semiconductor elements. Device. The semiconductor substrate includes a first impurity layer (15a) forming part of the semiconductor element, and a plurality of conducting regions of the semiconductor element positioned between the plurality of first impurity layers in the planar direction. A partitioning second impurity layer (15b) is formed,
8. The plurality of semiconductor elements according to claim 7, wherein a difference in length ratio of said first impurity layer and said second impurity layer in said plane direction causes a difference in current carrying capability per unit formation region of said plurality of semiconductor elements. semiconductor device. 8. The plurality of trench gate electrodes (19) formed on the semiconductor substrate have a difference in adjacent spacing in the planar direction, so that there is a difference in formation density per unit formation area of the plurality of semiconductor elements. The semiconductor device according to . A plurality of trench gate electrodes (19) formed on the semiconductor substrate spaced apart in the planar direction have different ratios of gate voltages applied thereto, so that each of the plurality of semiconductor elements per unit formation region 8. The semiconductor device according to claim 7, wherein there is a difference in current-carrying capability between the two. Conduction of the plurality of semiconductor elements due to difference in impurity concentration of the conductive regions (15, 18) connected to at least one of the first current-carrying electrodes and the second current-carrying electrodes of the plurality of semiconductor elements. 11. The semiconductor device according to any one of claims 1 to 10, having different capabilities. a conductive layer (16) between a first conductive region (15) connected to the first conductive electrode and a second conductive region (18) connected to the second conductive electrode in the plurality of semiconductor elements; 12. The semiconductor device according to any one of claims 1 to 11, wherein a difference in impurity concentration results in a difference in current-carrying capability of the plurality of semiconductor elements. 13. The semiconductor device according to any one of claims 1 to 12, wherein a difference in the number of defects formed inside said semiconductor substrate results in a difference in current carrying capability of said plurality of semiconductor elements. A plurality of trench gate electrodes (19) formed on the semiconductor substrate have different thicknesses of gate oxide films, so that the plurality of semiconductor elements have different current-carrying capabilities. The semiconductor device described.

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