JP7268035B2 - パッケージ構造、半導体装置およびパッケージ構造の形成方法 - Google Patents
パッケージ構造、半導体装置およびパッケージ構造の形成方法 Download PDFInfo
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Description
Claims (24)
- 第1方向の一方を向く主面を有する金属部材と、
前記主面の少なくとも一部に接して配置された樹脂部材と、を備えており、
前記主面は、粗化領域を含んでおり、
前記粗化領域には、各々が、前記主面から窪み、かつ、表面が前記主面よりも粗面である複数の第1線状溝が形成されており、
前記複数の第1線状溝は、各々が前記第1方向に直交する第2方向に延びており、かつ、前記第1方向および前記第2方向に直交する第3方向に並んでおり、
前記樹脂部材は、前記複数の第1線状溝の各々に充填されており、
前記複数の第1線状溝の各々は、前記第1方向に見て、前記粗化領域の前記第2方向の一方の端縁から他方の端縁まで一続きに繋がっている、
パッケージ構造。 - 前記複数の第1線状溝の各々は、前記第1方向に見て、前記第2方向に延びる直線状である、
請求項1に記載のパッケージ構造。 - 前記主面は、前記粗化領域において、前記第3方向に隣り合う2つの第1線状溝に挟まれた隆起部を備えており、
前記隆起部は、前記第1方向に見て、前記粗化領域の前記第2方向の一方の端縁から他方の端縁まで一続きに繋がっている、
請求項2に記載のパッケージ構造。 - 前記粗化領域には、各々の表面が前記主面よりも粗面である複数の第2線状溝が、さらに形成されており、
前記複数の第2線状溝は、各々が前記第3方向に延びており、かつ、前記第2方向に並んでおり、
前記複数の第1線状溝の各々と前記複数の第2線状溝の各々とは、前記第1方向に見て、交差している、
請求項2に記載のパッケージ構造。 - 前記粗化領域は、交差底面と、非交差底面とを含んでおり、
前記交差底面は、前記第1方向に見て、前記第1線状溝および前記第2線状溝の両方に重なり、
前記非交差底面は、前記第1方向に見て、前記第1線状溝あるいは前記第2線状溝のいずれか一方にのみ重なり、
前記交差底面は、前記非交差底面よりも前記第1方向において前記主面から離間している、
請求項4に記載のパッケージ構造。 - 前記複数の第2線状溝の各々は、前記第1方向に見て直線状である、
請求項4または請求項5に記載のパッケージ構造。 - 隣り合う2つの前記第1線状溝の間隔と、隣り合う2つの前記第2線状溝の間隔とは、略同じである、
請求項6に記載のパッケージ構造。 - 前記複数の第1線状溝の各々は、前記第2方向に直交する断面における端縁が湾曲している、
請求項1ないし請求項7のいずれか一項に記載のパッケージ構造。 - 各前記第1線状溝の表面には、前記粗化領域において前記複数の第1線状溝によって形成される凹凸よりも、微細な凹凸が形成されている、
請求項1ないし請求項8のいずれか一項に記載のパッケージ構造。 - 前記複数の第1線状溝の表層は、前記金属部材の素材の酸化物で構成された酸化物層である、
請求項1ないし請求項9のいずれか一項に記載のパッケージ構造。 - 前記複数の第1線状溝は、所定のピッチ寸法で並んでいる、
請求項1ないし請求項10のいずれか一項に記載のパッケージ構造。 - 前記第1線状溝の幅は、10~200μmである、
請求項1ないし請求項11のいずれか一項に記載のパッケージ構造。 - 前記第1線状溝の幅に対する、前記第1線状溝の深さの割合は、0.2~1.2である、
請求項1ないし請求項12のいずれか一項に記載のパッケージ構造。 - 請求項1ないし請求項13のいずれか一項に記載のパッケージ構造を備える半導体装置であって、
第1スイッチング素子と、
各々が前記第1スイッチング素子に導通する第1端子および第2端子と、を備えており、
前記樹脂部材は、前記第1スイッチング素子、前記第1端子の一部および前記第2端子の一部を覆っており、
前記粗化領域は、前記第1端子に設けられている、
半導体装置。 - 前記第1端子は、前記樹脂部材に覆われた第1パッド部と、前記樹脂部材から露出した第1端子部とを含んでおり、
前記粗化領域は、前記第1パッド部のうち前記第1端子部に繋がる側の端縁部分に形成されている、
請求項14に記載の半導体装置。 - 前記粗化領域は、さらに前記第2端子に設けられている、
請求項15に記載の半導体装置。 - 前記第2端子は、前記樹脂部材に覆われた第2パッド部と、前記樹脂部材から露出した第2端子部とを含んでおり、
前記粗化領域は、前記第2パッド部のうち前記第2端子部に繋がる側の端縁部分に形成されている、
請求項16に記載の半導体装置。 - 前記第1方向の前記一方を向く基板主面を有する絶縁基板と、
前記基板主面に配置され、前記第1スイッチング素子が導通接合された第1導電部材と、をさらに備えており、
前記第1端子は、前記第1導電部材に導通接合されている、
請求項17に記載の半導体装置。 - 前記粗化領域は、前記第1導電部材の前記第1スイッチング素子が接合された側の面の少なくとも一部に設けられている、
請求項18に記載の半導体装置。 - 前記基板主面に配置され、前記第1導電部材と離間する第2導電部材と、
前記第2導電部材に導通接合され、前記第1スイッチング素子とは異なる第2スイッチング素子と、
前記第2導電部材に導通接合された第3端子と、をさらに備えており、
前記第3端子は、前記樹脂部材に覆われた第3パッド部および前記樹脂部材から露出した第3端子部を含んでおり、
前記第2スイッチング素子は、前記第1導電部材に導通している、
請求項18または請求項19に記載の半導体装置。 - 前記粗化領域は、前記第2導電部材の前記第2スイッチング素子が接合された側の面の少なくとも一部に設けられている、
請求項20に記載の半導体装置。 - 前記第1方向において、前記第2端子部と前記第3端子部との間に挟まれた絶縁部材をさらに備えており、
前記絶縁部材の一部は、前記第1方向にみて、前記第2端子部および前記第3端子部に重なる、
請求項20または請求項21に記載の半導体装置。 - 第1方向の一方を向く主面を有する金属部材を準備する工程と、
前記主面の少なくとも一部を粗化処理して、粗化領域を形成する粗化処理工程と、
少なくとも前記粗化領域に接するように樹脂部材を形成する樹脂部材形成工程と、を含んでおり、
前記粗化領域には、各々が、前記主面から窪み、かつ、表面が前記主面よりも粗面である複数の第1線状溝が形成されており、
前記複数の第1線状溝は、各々が前記第1方向に直交する第2方向に延びており、かつ、前記第1方向および前記第2方向に直交する第3方向に並んでおり、
前記樹脂部材は、前記複数の第1線状溝の各々に充填されており、
前記複数の第1線状溝の各々は、前記第1方向に見て、前記粗化領域の前記第2方向の一方の端縁から他方の端縁まで一続きに繋がっている、
パッケージ構造の形成方法。 - 前記粗化処理工程では、前記金属部材にレーザ光を照射することにより前記複数の第1線状溝を形成する、
請求項23に記載のパッケージ構造の形成方法。
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