JP7132076B2 - CT device - Google Patents

Description

One aspect of the present invention relates to a CT apparatus and method of operation thereof.

Note that one embodiment of the present invention is not limited to the above technical field. A technical field of one embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition of matter. Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, and the like. Driving methods or their manufacturing methods can be mentioned as an example.

Note that a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are modes of a semiconductor device. Storage devices, display devices, imaging devices, electronic devices, and the like may include semiconductor devices. A semiconductor device may also refer to a memory device, a display device, an imaging device, an electronic device, or the like.

Computed tomography apparatus (hereinafter referred to as CT apparatus) are widely used, especially for medical purposes. A CT apparatus can acquire a cross-sectional image of the inside of a subject such as a human body. For example, Patent Document 1 discloses a CT apparatus that can easily and appropriately reconstruct thick slices from thin-slice projection data.

Also, a technique for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device in which a transistor including an oxide semiconductor and having extremely low off-state current is used in a pixel circuit.

JP 2016-198507 A JP 2011-119711 A

A CT apparatus generally acquires a cross-sectional image by irradiating an object with X-rays and measuring the transmitted X-rays with a detector. In this case, if the subject is a human body, the health condition may be affected by exposure to X-rays. Further, in a general CT apparatus, a gantry provided with an X-ray source and an X-ray detector or a cradle on which a subject is arranged is rotated. In this case, the configuration of the device may become complicated and the cost may increase. In addition, noise may occur in acquired cross-sectional images due to vibrations when rotating the gantry or cradle.

An object of one embodiment of the present invention is to provide a CT apparatus to which a flexible semiconductor device is attached. Another object is to provide a CT apparatus with a simple configuration. Another object is to provide a low-cost CT apparatus. Alternatively, another object is to provide a CT apparatus that can acquire cross-sectional images with little noise. Another object is to provide a CT apparatus with high safety. Another object is to provide a CT apparatus including a semiconductor device with high light detection sensitivity. Another object is to provide a CT apparatus that operates at high speed. Another object is to provide a CT apparatus with low power consumption. Another object is to provide a CT apparatus having a light-emitting device capable of emitting high-intensity light. Another object is to provide a highly reliable CT apparatus. Another object is to provide a novel CT apparatus. Another object is to provide a novel semiconductor device or the like.

Another object is to provide a method for operating a CT apparatus to which a flexible semiconductor device is attached. Another object of the present invention is to provide a method of operating a CT apparatus with a simple configuration. Another object of the present invention is to provide a method of operating a CT apparatus at a low cost. Another object of the present invention is to provide a method of operating a CT apparatus capable of acquiring cross-sectional images with little noise. Another object of the present invention is to provide a method of operating a CT apparatus with high safety. Another object is to provide a method for operating a CT apparatus including a semiconductor device with high light detection sensitivity. Another object is to provide a method of operating a CT apparatus that operates at high speed. Another object is to provide a method of operating a CT apparatus with low power consumption. Alternatively, another object is to provide a method of operating a CT apparatus having a light-emitting device capable of emitting high-intensity light. Another object of the present invention is to provide a method of operating a CT apparatus with high reliability. Another object of the present invention is to provide a novel method of operating a CT apparatus. Another object is to provide a novel semiconductor device or the like.

The description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Problems other than these are self-evident from the descriptions of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the descriptions of the specification, drawings, claims, etc. is.

One embodiment of the present invention is a CT apparatus having a gantry, in which a semiconductor device is attached to a hollow portion of the gantry, pixels are provided in a matrix in the semiconductor device, and the pixels perform photoelectric conversion. A CT apparatus having a device and a light emitting device.

Alternatively, in the above aspect, the light-emitting device may have a function of emitting infrared light.

Alternatively, in the above aspect, the pixel has a first transistor and a second transistor, one electrode of the light emitting device is electrically connected to one of the source or drain of the first transistor, A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, and the second transistor has a metal oxide in a channel formation region, and the metal oxide includes In and Zn and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

Alternatively, one embodiment of the present invention is a CT apparatus including a gantry and a cradle, wherein a semiconductor device is attached to a cavity of the gantry, and the semiconductor device includes first pixels and first pixels. a first pixel having a first photoelectric conversion device and a first light emitting device; a second pixel having a second photoelectric conversion device and a second light emitting device; and a light-emitting device, wherein the first light that is light emitted from the first light-emitting device is applied to a subject placed in the cradle, and the first light transmitted through the subject is emitted from the first The second light, which is detected by the photoelectric conversion device and emitted from the second light emitting device, is applied to the subject, and the second light transmitted through the subject is transmitted to the first photoelectric conversion device. It is a CT apparatus detected by.

Alternatively, in the above aspect, the first light emitting device and the second light emitting device may have the function of emitting infrared light.

Alternatively, in the above aspect, the first pixel has a first transistor and a second transistor, the second pixel has a third transistor and a fourth transistor, One electrode of the first light emitting device is electrically connected to one of the source or drain of the first transistor, and the gate of the first transistor is electrically connected to one of the source or drain of the second transistor. one electrode of the second light emitting device is electrically connected to one of the source or drain of the third transistor, and the gate of the third transistor is connected to one of the source or drain of the fourth transistor. The second and fourth transistors are electrically connected and have metal oxides in their channel forming regions, and the metal oxides include In, Zn and M (M is Al, Ti, Ga, Sn, Y , Zr, La, Ce, Nd or Hf).

Alternatively, in the above aspect, the semiconductor device may have flexibility.

According to one embodiment of the present invention, a CT apparatus to which a flexible semiconductor device is attached can be provided. Alternatively, it is possible to provide a CT apparatus with a simple configuration. Alternatively, a low cost CT apparatus can be provided. Alternatively, it is possible to provide a CT apparatus capable of acquiring cross-sectional images with little noise. Alternatively, a highly safe CT apparatus can be provided. Alternatively, a CT apparatus including a semiconductor device with high light detection sensitivity can be provided. Alternatively, it is possible to provide a CT apparatus that operates at high speed. Alternatively, a CT apparatus with low power consumption can be provided. Alternatively, it is possible to provide a CT apparatus having a light emitting device capable of emitting light of high intensity. Alternatively, a highly reliable CT apparatus can be provided. Alternatively, a novel CT apparatus can be provided. Alternatively, a novel semiconductor device or the like can be provided.

Alternatively, it is possible to provide a method of operating a CT apparatus to which a flexible semiconductor device is attached. Alternatively, it is possible to provide a method of operating a CT apparatus with a simple configuration. Alternatively, it is possible to provide a method of operating a low-cost CT apparatus. Alternatively, it is possible to provide a method of operating a CT apparatus capable of acquiring cross-sectional images with little noise. Alternatively, it is possible to provide a method of operating a CT apparatus with high safety. Alternatively, a method for operating a CT apparatus having a semiconductor device with high light detection sensitivity can be provided. Alternatively, it is possible to provide a method of operating a CT apparatus that operates at high speed. Alternatively, it is possible to provide a method of operating a CT apparatus with low power consumption. Alternatively, it is possible to provide a method of operating a CT apparatus having a light emitting device capable of emitting light of high intensity. Alternatively, it is possible to provide a method of operating a CT apparatus with high reliability. Alternatively, it is possible to provide a novel method of operating a CT apparatus. Alternatively, a novel semiconductor device or the like can be provided.

Note that the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the descriptions of the specification, drawings, and claims.

The figure explaining the structural example of a CT apparatus. FIGS. 1A and 1B are diagrams each illustrating a configuration example of a semiconductor device; FIG. The figure explaining an example of the operation|movement method of CT apparatus. 4A and 4B are diagrams for explaining a configuration example of a semiconductor device and a configuration example of a CT apparatus; The figure explaining the structural example of a CT apparatus. FIGS. 1A and 1B are diagrams each illustrating a configuration example of a semiconductor device; FIG. FIGS. 1A and 1B are diagrams each illustrating a configuration example of a semiconductor device; FIG. FIGS. 1A and 1B are diagrams each illustrating a configuration example of a semiconductor device; FIG. 3A and 3B are diagrams for explaining a configuration example of a pixel; FIG. 3A and 3B are diagrams for explaining a configuration example of a pixel; FIG. 4A and 4B are diagrams for explaining an example of a pixel operation method; FIG. 3A and 3B are diagrams for explaining a configuration example of a pixel; FIG. 4A and 4B are diagrams for explaining an example of a configuration of a pixel and an example of an operation method of the pixel; FIG. 3A and 3B are diagrams for explaining a configuration example of a pixel; FIG. 3A and 3B are diagrams for explaining a configuration example of a pixel; FIG. 4A and 4B are diagrams for explaining a structure example of a transistor; A diagram explaining the market image.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the descriptions of the embodiments shown below.

In the configuration of the invention to be described below, the same reference numerals are used in common for the same parts or parts having similar functions in different drawings, and repeated description thereof will be omitted. Moreover, when referring to similar functions, the hatch patterns may be the same and no particular reference numerals may be attached.

Also, the position, size, range, etc. of each configuration shown in the drawings may not represent the actual position, size, range, etc., for the sake of easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

Note that the terms "film" and "layer" can be interchanged depending on the case or situation. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term “insulating film” can be changed to the term “insulating layer”.

In this specification and the like, a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes called an oxide semiconductor. In other words, an OS FET can be referred to as a transistor including a metal oxide or an oxide semiconductor.

In addition, in this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Metal oxides containing nitrogen may also be referred to as metal oxynitrides.

(Embodiment 1)
In this embodiment, a configuration example of a CT apparatus that is one embodiment of the present invention will be described with reference to drawings.

<Configuration example 1 of CT apparatus>
FIG. 1A is a diagram showing a configuration example of a CT apparatus 10, which is a CT apparatus according to one aspect of the present invention. A CT apparatus 10 has a gantry 11 and a cradle 12 .

A cavity 21 is provided in the gantry 11 , and a semiconductor device 20 is provided so as to be attached to the sidewall of the cavity 21 . A subject 22 is placed on the cradle 12 .

In FIG. 1A, the semiconductor device 20 is hatched. Here, the semiconductor device 20 preferably has flexibility. As a result, the semiconductor device 20 can be attached to the side wall of the cavity 21 even if the side wall of the cavity 21 has a curved surface as shown in FIG. 1(A).

The gantry 11 has a function of acquiring a cross-sectional image of the subject entering the cavity 21 . In the CT apparatus 10 , a cross-sectional image of the subject 22 can be obtained by entering the cradle 12 with the subject 22 placed therein into the cavity 21 .

In this specification and the like, a CT apparatus refers to any apparatus that has a function of acquiring a cross-sectional image of a subject.

The cradle 12 has a function of transporting the subject 22 to the cavity 21 . By moving the cradle 12 with the subject 22 placed thereon to the cavity 21 , the subject 22 can be transported to the cavity 21 .

FIG. 1B is a cross-sectional view taken along the dashed line A1-A2 in FIG. As shown in FIG. 1B, the semiconductor device 20 can be provided so as to cover the subject 22 . For example, the semiconductor device 20 can be attached to the entire sidewall of the cavity 21 .

As shown in FIG. 1B, pixels 30 are arranged in the semiconductor device 20 . Therefore, it is possible to configure such that the subject 22 entering the cavity 21 is surrounded by the pixels 30 .

<Structure Example 1 of Semiconductor Device>
FIG. 2 is a block diagram showing a configuration example of the semiconductor device 20 when the semiconductor device 20 is cut along the two-dot chain line B1-B2 in FIG. 1(A). The semiconductor device 20 has a pixel array 40 having pixels 30 arranged in a matrix, a gate driver circuit 41 and a source driver circuit 42 . A photoelectric conversion device 31 and a light emitting device 32 are provided in the pixel 30 .

The gate driver circuit 41 is electrically connected to the pixels 30 via wiring extending in the row direction. The source driver circuit 42 is electrically connected to the pixels 30 via wiring extending in the column direction.

Gate driver circuit 41 has a function of selecting a row of pixel array 40 . The source driver circuit 42 has a function of outputting, to the outside of the semiconductor device 20 , imaging data according to the illuminance of the light with which the photoelectric conversion device 31 is exposed. Also, the source driver circuit 42 has a function of controlling the light emission luminance of the light emitting device 32 .

As shown in FIG. 2, the two-dot chain line B1-B2 in FIG. 1A can correspond to the column direction of the pixel array . In this case, the direction perpendicular to B1-B2 can correspond to the row direction of the pixel array 40. FIG. For example, as shown in FIG. 1B, when the cross section of the semiconductor device 20 in the A1-A2 direction perpendicular to B1-B2 is circular, the circumferential direction can be the row direction of the pixel array 40. can.

<Example of Operation Method of Semiconductor Device>
FIGS. 3A, 3B, and 3C show an example of a method of operating the semiconductor device 20 using a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 1A. Note that FIGS. 3A, 3B, and 3C show one row of pixels 30, and show a case where 32 pixels 30 are provided per row. Other diagrams showing cross-sectional views taken along the dashed-dotted line A1-A2 in FIG. 1A may also show the case where 32 pixels 30 are provided per row.

In this specification and the like, the plurality of pixels 30 are described as pixel 30[1], pixel 30[2], and the like to distinguish them. For example, as shown in FIGS. 3A, 3B, and 3C, when the semiconductor device 20 has a circular cross section, the pixels 30[1] to 30[32] are arranged clockwise. can be configured. In addition, other elements may also be denoted in the same manner in order to distinguish between multiple elements.

In addition, in FIGS. 3A, 3B, and 3C, the same hatching as that of the light emitting device 32 shown in FIG. . Further, the pixels 30 that perform exposure by the photoelectric conversion device 31, that is, detect the light irradiated to the pixel 30, are given the same hatching as the photoelectric conversion device 31 shown in FIG.

In FIG. 3A, the light emitting device 32 provided in the pixel 30[1] emits light 38 to irradiate the subject 22, and the light 38 transmitted through the subject 22 is provided in the pixel 30[17]. It shows the case where the photoelectric conversion device 31 is detected. In other words, when the photoelectric conversion device 31 provided in the pixel 30 provided with the light emitting device 32 emitting the light 38 is arranged in the opposite direction to the subject 22, the light 38 is detected by the photoelectric conversion device 31. is shown. Here, the directions in which the light 38 is emitted are indicated by solid arrows. Similar notations are also used in other drawings showing an example of the operation method of the semiconductor device 20 .

Next, the light-emitting device 32 provided in the pixel 30[2] emits light to irradiate the subject 22, and the light transmitted through the subject 22 is transferred to the photoelectric conversion device provided in the pixel 30[18]. 31. Similarly, the light-emitting device 32 sequentially emits light from pixel 30[3] to pixel 30[32], pixel 30[19] to pixel 30[32], and pixel 30[1] to pixel 30[16]. Light is detected by the photoelectric conversion device 31 . The above is an example of the operation method of the pixels 30 in one row.

Through the above operation, a cross-sectional image of the subject 22 can be acquired. The above operation can be performed, for example, for each row of pixels 30 in all rows. Alternatively, the above operation can be performed simultaneously for two or more rows of pixels 30 . The row on which the above operation is performed can be selected by the gate driver circuit 41 shown in FIG. That is, the light emitting device 32 provided in the pixels 30 on the selected row can emit light, and the photoelectric conversion device 31 provided on the pixels 30 on the selected row can detect the light.

The CT apparatus 10 can acquire cross-sectional images of the subject 22 without rotating the gantry 11 or the cradle 12 . As a result, the configuration of the CT apparatus 10 can be simplified, so that the cost of the CT apparatus 10 can be reduced. Also, since no vibration occurs when the gantry 11 or the cradle 12 is rotated, cross-sectional images with little noise can be obtained.

The subject 22 is not limited to a human body. For example, it may be a living body other than the human body, such as an animal, a fish, an insect, or the like. In this case, it is possible to perform pathological diagnosis of a living body other than the human body. Alternatively, the subject 22 may be food or industrial products. In this case, nondestructive inspection such as foreign matter inspection and failure analysis can be performed. In particular, if the subject 22 is a thin object, the transmittance of the light emitted from the light emitting device 32 through the subject 22 is preferably increased.

The light emitted from the light emitting device 32 is preferably infrared light, for example. Infrared light has a smaller effect on the health condition of the human body than X-rays and the like. Therefore, when the subject 22 is a human body, the safety of the subject 22 can be enhanced. Even if the subject 22 is other than the human body, by using infrared light as the light emitted from the light emitting device 32, it is possible to improve the safety of the operator of the CT apparatus 10. The safety of the CT apparatus 10 can be enhanced. Also, visible light such as red light may be emitted from the light emitting device 32 .

In this specification and the like, infrared light indicates light with a wavelength of 0.7 μm or more and 1000 μm or less, for example. For example, near-infrared light having a wavelength of 0.7 μm or more and 2.5 μm or less may be simply referred to as infrared light. Alternatively, near-infrared light and mid-infrared light having a wavelength of 2.5 μm or more and 10 μm or less may simply be referred to as infrared light. In this specification and the like, red light indicates light with a wavelength of 0.6 μm or more and 0.75 μm or less, for example.

Here, when the subject 22 is a living body such as a human body, the wavelength of light emitted from the light emitting device 32 is preferably 0.65 μm or more and 1.8 μm or less, particularly 0.65 μm or more and 1.1 μm or less. Light of this wavelength has a high transmittance for both blood and water. Therefore, pathological diagnosis and the like can be performed accurately.

Note that the light emitting devices 32 provided in all the pixels 30 may not have the function of emitting light of the same wavelength. For example, pixels 30 provided with light-emitting devices 32 emitting light of 0.65 μm or more and less than 0.8 μm and pixels 30 provided with light-emitting devices 32 emitting light of 0.8 μm or more may be provided in a mixed manner. . Accordingly, when the subject 22 is a human body or the like, pathological diagnosis can be performed while detecting blood vessels, particularly veins. That is, by providing photoelectric conversion devices 31 that emit light of different wavelengths together, the CT apparatus 10 can have many functions.

FIG. 3A shows the case where light emitted by the light-emitting device 32 provided in one pixel 30 is detected by the photoelectric conversion device 31 provided in one pixel 30; One aspect of the invention is not limited to this. When the light emitted by the light emitting device 32 spreads, for example, the light emitted by the light emitting device 32 provided in one pixel 30 may be detected by the photoelectric conversion devices 31 provided in two or more pixels 30. good.

In FIG. 3B, the light-emitting device 32 provided in the pixel 30[1] emits light to irradiate the subject 22, and the light transmitted through the subject 22 is emitted from the pixels 30[16] to 30[ 18] is detected by the photoelectric conversion device 31 provided in FIG. That is, a case is shown in which the light emitted by the light emitting device 32 is detected by the photoelectric conversion device 31 provided in three adjacent pixels 30 .

After the light emission by the light emitting device 32 provided in the pixel 30[1] is completed, for example, the light emitting device 32 provided in the pixel 30[2] emits light to irradiate the subject 22. is detected by photoelectric conversion devices 31 provided in the pixels 30[17] to 30[19]. Next, the light-emitting device 32 provided in the pixel 30[3] emits light to irradiate the subject 22, and the light transmitted through the subject 22 is provided in the pixels 30[18] to 30[20]. Detected by the photoelectric conversion device 31 . Similarly, the light-emitting devices 32 sequentially emit light from the pixels 30[4] to 30[32], and the photoelectric conversion devices 31 provided in the corresponding pixels 30 detect the light. The above is an example of the operation method of the pixels 30 in one row.

In the above operating method, one pixel 30 is exposed to light emitted from three pixels 30 . For example, the pixel 30[18] is exposed to light emitted from the light-emitting devices 32 provided in the pixels 30[1] to 30[3]. Therefore, since the amount of exposure to the pixels 30 can be increased, the light detection sensitivity of the semiconductor device 20 can be increased.

Alternatively, after the light emission by the light emitting device 32 provided in the pixel 30[1] is completed, the light emitting device 32 provided in the pixel 30[4] emits light, and the subject 22 is irradiated with the light. Light transmitted through the sample 22 may be detected by the photoelectric conversion device 31 provided in the pixels 30[19] to 30[21]. In this case, all the photoelectric conversion devices 31 can be exposed without causing all the light emitting devices 32 to emit light. As described above, the CT apparatus 10 can be operated at high speed.

3A and 3B, one light-emitting device 32 emits light at one time; however, one embodiment of the present invention is not limited to this. For example, a plurality of light emitting devices 32 may emit light at once. In FIG. 3C, the light-emitting devices 32 provided in the pixels 30[32], the pixels 30[1], and the pixels 30[2] emit light, irradiate the subject 22, and pass through the subject 22. A case is shown in which the emitted light is detected by the photoelectric conversion devices 31 provided in the pixels 30[16] to 30[18]. That is, the light emitting devices 32 provided in the three adjacent pixels 30 emit light at once, and the photoelectric conversion devices 31 provided in the three adjacent pixels 30 detect the light. .

After the light emission by the light-emitting devices 32 provided in the pixels 30[32], the pixels 30[1], and the pixels 30[2] is completed, the pixels provided in the pixels 30[3] to 30[5], for example, The light emitting device 32 that is present emits light at once to irradiate the subject 22 . Light transmitted through the subject 22 is detected by the photoelectric conversion device 31 provided in the pixels 30[19] to 30[21]. Similarly, the light-emitting device 32 sequentially emits light from pixel 30[6] to pixel 30[31], pixel 30[22] to pixel 30[32], and pixel 30[1] to pixel 30[15]. Light is detected by the photoelectric conversion device 31 . The above is an example of the operation method of the pixels 30 in one row.

In the operation method described above, the CT apparatus 10 can be operated at a higher speed than when the light emitting devices 32 emit light one by one. In addition, since one pixel 30 is exposed to light emitted from three pixels 30, the amount of exposure to the pixel 30 can be increased, and the light detection sensitivity of the semiconductor device 20 can be increased. can.

Alternatively, after the light emission by the light-emitting devices 32 provided in the pixels 30[32], the pixels 30[1], and the pixels 30[2] is finished, the light-emitting devices provided in the pixels 30[1] to 30[3] Light may be emitted by the light emitting device 32 that is present. In this case, since the amount of exposure to the pixels 30 can be further increased, the light detection sensitivity of the semiconductor device 20 can be further increased.

<Structure Example 2 of Semiconductor Device>
Although the semiconductor device 20 having the structure illustrated in FIG. 2 includes one gate driver circuit and one source driver circuit, one embodiment of the present invention is not limited to this. FIG. 4A shows a modification of the semiconductor device 20 having the configuration shown in FIG. 2, and the semiconductor device shown in FIG. 20 configuration.

The source driver circuit 42a is electrically connected to the pixels 30 provided in the left half column of the pixel array 40 via wiring extending in the column direction. The source driver circuit 42b is electrically connected to the pixels 30 provided in the right half column of the pixel array 40 via wiring extending in the column direction. That is, for example, when 32 columns of pixels 30 (pixels 30[1] to 30[32]) are provided in the pixel array 40, the source driver circuit 42a electrically connects the pixels 30[1] to 30[16]. The source driver circuit 42b can be electrically connected to the pixels 30[17] to 30[32].

FIG. 4B is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 1A. In FIG. 4B, in the case where the semiconductor device 20 has the configuration shown in FIG. are shown by hatching. Also, the pixels 30 for detecting light by the photoelectric conversion device 31 are indicated by hatching similar to that of the photoelectric conversion device 31 .

As shown in FIG. 4B, for example, the light-emitting devices 32 provided in the pixels 30[1] to 30[16] electrically connected to the source driver circuit 42a emit light. For example, the photoelectric conversion device 31 provided in the pixels 30[17] to 30[32] electrically connected to the source driver circuit 42b detects light transmitted through the subject 22. FIG. Note that the light-emitting devices 32 provided in the pixels 30[17] to 30[32] electrically connected to the source driver circuit 42b are caused to emit light, and the pixels electrically connected to the source driver circuit 42a Light transmitted through the subject 22 may be detected by the photoelectric conversion devices 31 provided in the pixels 30[1] to 30[16].

As described above, in the semiconductor device 20 having the structure illustrated in FIG. 4A, the pixel 30 that emits light and the pixel 30 that detects light can be separated. Therefore, even if all the light-emitting devices 32 emit light and all the photoelectric conversion devices 31 do not detect light, the semiconductor device 20 can acquire a cross-sectional image of the subject 22 . Therefore, the CT apparatus 10 can be operated at high speed.

<Configuration example 2 of CT apparatus>
In the gantry 11 having the structure shown in FIGS. 1A and 1B, the semiconductor device 20 is attached to the entire side wall of the hollow portion 21; however, one embodiment of the present invention is not limited to this. FIGS. 5A and 5B are modifications of FIGS. 1A and 1B, and the semiconductor device 20 is attached to part of the side wall of the hollow portion 21, which is different from FIG. It differs from the configuration shown in A) and (B).

In the gantry 11 having the configuration shown in FIG. 5B, among pixels 30[1] to 30[32], pixels 30[1] to 30[4] and pixels 30[13] to 30[20] , and the pixels 30[29] to 30[32] are not provided. In other words, the configuration is such that the pixels 30 are not provided above the subject 22 . Also, the pixels 30 at positions opposite to the subject 22 (below the subject 22 in FIG. 5B) at positions where the pixels 30 are omitted are also omitted. In the gantry 11 having the configuration shown in FIG. 5B, the semiconductor device 20 provided with the pixels 30[5] to 30[12] and the pixels 30[21] to 30[28] are provided. The semiconductor device 20 may be another semiconductor device. In other words, it can be said that the gantry 11 configured as shown in FIG. Note that three or more semiconductor devices 20 may be attached to the side wall of the hollow portion 21 . For example, four semiconductor devices 20 may be attached to the side wall of the cavity 21, six semiconductor devices may be attached, eight semiconductor devices may be attached, or sixteen semiconductor devices may be attached. may be When a plurality of semiconductor devices 20 are provided, if the semiconductor device 20 is provided at a position opposite to the object 22 from the position where the semiconductor device 20 is provided, the light emitting device 32 provided in one of the semiconductor devices 20 emits light. This is preferable because the photoelectric conversion device 31 provided in the other semiconductor device 20 can efficiently receive the emitted light.

Since the semiconductor device 20 can be miniaturized by configuring the gantry 11 as shown in FIGS. 5A and 5B, the semiconductor device 20 can be manufactured at low cost. Therefore, the CT apparatus 10 can be made inexpensive. In addition, since the number of pixels 30 included in one semiconductor device 20 can be reduced, the CT apparatus 10 can be operated at high speed.

<Structure Example 3 of Semiconductor Device>
Although all the pixels 30 have both the photoelectric conversion device 31 and the light-emitting device 32 in FIG. 2 and the like, one embodiment of the present invention is not limited to this. FIG. 6 is a modification of the semiconductor device 20 having the configuration shown in FIG. 2, and differs from the configuration of the semiconductor device 20 shown in FIG.

By configuring the semiconductor device 20 as shown in FIG. 6, the light receiving area of the photoelectric conversion device 31 can be increased for the pixels 30 in which the light emitting device 32 is not provided. Therefore, the light detection sensitivity of the semiconductor device 20 can be enhanced. Here, the lower the directivity of the light emitted by the light emitting device 32, the more the light emitted by the light emitting device 32 spreads. Exposure can be performed.

<Structure Example 4 of Semiconductor Device>
FIG. 7 is a block diagram showing a configuration example of the semiconductor device 20. As shown in FIG. A semiconductor device 20 configured as shown in FIG. 7 includes layers 51 and 52 . The layers 51 and 52 are provided by laminating each other.

Layer 51 is provided with a pixel array 40 having pixels 30 arranged in a matrix. Gate driver circuits 41 and source driver circuits 42 are provided in layer 52 .

The semiconductor device 20 having the configuration shown in FIG. 7 has a region where the pixel array 40 provided in the layer 51 and the gate driver circuit 41 and the source driver circuit 42 provided in the layer 52 overlap. For example, some pixels 30 have a region that overlaps with the gate driver circuit 41 or the source driver circuit 42 .

In FIG. 7, the positional relationship between the layers 51 and 52 is indicated by a one-dot chain line and a white circle. overlapping each other. Note that the same notation is used in other drawings as well.

By configuring the semiconductor device 20 as shown in FIG. 7, the frame of the semiconductor device 20 can be narrowed. As a result, the dead space (the range in which the cross-sectional image of the subject 22 cannot be acquired) can be reduced.

In addition, the gate driver circuit 41 and the source driver circuit 42 provided in the layer 52 can be configured to have overlapping regions without being clearly separated. This area is assumed to be area 43 . With the configuration having the region 43, the area occupied by the gate driver circuit 41 and the source driver circuit 42 can be reduced. Therefore, even when the area of the pixel array 40 is small, the gate driver circuit 41 and the source driver circuit 42 can be provided without protruding from the pixel array 40 . Alternatively, the areas of the gate driver circuit 41 and the source driver circuit 42 that do not overlap with the pixel array 40 can be reduced. As described above, the frame of the semiconductor device 20 can be made narrower than when the region 43 is not provided, and the dead space can be reduced.

FIG. 7 illustrates a structure in which one gate driver circuit 41 and one source driver circuit 42 are provided in the layer 52; however, one embodiment of the present invention is not limited to this. For example, a plurality of gate driver circuits 41 and a plurality of source driver circuits 42 may be provided in the layer 52 . FIG. 8 is a modification of the configuration shown in FIG. 7, and shows a configuration example of the semiconductor device 20 in which the layer 52 is provided with the gate driver circuits 41 and the source driver circuits 42 arranged in 3 rows and 3 columns. Note that the layer 52 may be provided with the gate driver circuits 41 and the source driver circuits 42 arranged in two rows and two columns, or may be provided with the gate driver circuits 41 and the source driver circuits 42 arranged in four rows and four columns. may Also, the number of rows and the number of columns of the gate driver circuits 41 and the source driver circuits 42 provided in the layer 52 may be different.

In FIG. 8, the electrical connection relationship between the pixel 30 and the gate driver circuit 41 and the source driver circuit 42 is omitted for clarity of illustration. It is electrically connected to the driver circuit 42 . Further, in FIG. 8, the same number of pixel arrays 40 as the gate driver circuits 41 and the source driver circuits 42 are provided in the layer 51 .

In the semiconductor device 20 configured as shown in FIG. 8 , the operation of the pixels 30 can be controlled for each pixel array 40 . As a result, for example, a cross-sectional image of the subject 22 can be acquired only for a required portion. For example, when the CT apparatus 10 is used for pathological diagnosis, only cross-sectional images near the affected area can be obtained. Alternatively, when the CT apparatus 10 is used for non-destructive inspection, it is possible to inspect only a portion where an abnormality is desired to be detected, for example, a portion where the reliability of the test object 22, which is a product, is greatly reduced when an abnormality occurs. As described above, the CT apparatus 10 can be operated at high speed. Moreover, power consumption of the CT apparatus 10 can be reduced.

<Pixel circuit configuration example 1>
FIG. 9A is a circuit diagram illustrating a configuration example of the pixel 30. FIG. The pixel 30 has an imaging circuit 100 and a light emitting circuit 110 . The imaging circuit 100 includes a photoelectric conversion device 31 , a transistor 103 , a transistor 104 , a transistor 105 , a transistor 106 , and a capacitor 108 . Note that a structure in which the capacitor 108 is not provided may be employed.

One electrode (cathode) of the photoelectric conversion device 31 is electrically connected to one of the source and drain of the transistor 103 . The other of the source and drain of the transistor 103 is electrically connected to one of the source and drain of the transistor 104 . One of the source and drain of the transistor 104 is electrically connected to one electrode of the capacitor 108 . One electrode of the capacitor 108 is electrically connected to the gate of the transistor 105 . One of the source and drain of the transistor 105 is electrically connected to one of the source and drain of the transistor 106 .

Here, a wiring connecting the other of the source and the drain of the transistor 103, the other of the source and the drain of the transistor 104, one electrode of the capacitor 108, and the gate of the transistor 105 is a node FD. The node FD can function as a charge storage portion.

The other electrode (anode) of the photoelectric conversion device 31 is electrically connected to the wiring 121 . A gate of the transistor 103 is electrically connected to the wiring 127 . The other of the source and the drain of the transistor 104 and the other of the source and the drain of the transistor 105 are electrically connected to the wiring 122 . A gate of the transistor 104 is electrically connected to the wiring 126 . A gate of the transistor 106 is electrically connected to the wiring 128 . The other electrode of the capacitive element 108 is electrically connected to a reference potential line such as a GND wiring, for example. The other of the source and drain of the transistor 106 is electrically connected to the wiring 129 .

The lighting circuit 110 has a lighting device 32 . One electrode of the light emitting device 32 is electrically connected to the wiring 130 . The other electrode of the light emitting device 32 is electrically connected to a reference potential line such as GND wiring. In this configuration, since there is no electrical connection between the imaging circuit 100 and the light emitting circuit 110, the input potential to the light emitting device 32 and the timing of light emission can be controlled independently.

The wiring 127 and the wiring 128 can function as signal lines that control conduction of each transistor. The wiring 129 can function as an output line.

The wiring 121 and the wiring 122 function as power supply lines. In the structure shown in FIG. 9A, the cathode side of the photoelectric conversion device 31 is electrically connected to the transistor 103, and the node FD is reset to a high potential to operate. potential higher than that of the wiring 121).

Also, the wiring 130 has a function of controlling the potential supplied to one electrode of the light emitting device 32 . The wiring is arranged so that the voltage of the light-emitting device 32 (the difference between the potential of one electrode of the light-emitting device 32 and the potential of the other electrode of the light-emitting device 32) is forward biased during the period in which the light-emitting device 32 emits light. 130 is controlled. On the other hand, the potential of the wiring 130 is controlled so that the voltage of the light emitting device 32 is reverse biased during the period in which the light emitting device 32 is not caused to emit light. For example, when the potential of the other electrode of the light-emitting device 32 is grounded, the potential of the wiring 130 is set to a positive potential during the period when the light-emitting device 32 is emitted, and the potential of the wiring 130 is grounded during the period when the light-emitting device 32 is not emitted. potential or negative potential.

FIG. 9B shows a structure in which a transistor 107 is added to the structure of FIG. 9A. One of the source or drain of transistor 107 is electrically connected to one electrode of light emitting device 32 . The other of the source and drain of the transistor 107 is electrically connected to the wiring 130 . A gate of the transistor 107 is electrically connected to the wiring 131 . The wiring 131 functions as a signal line that controls conduction of the transistor 107 .

In the pixel 30 having the structure shown in FIG. 9B, the wiring 131 can be electrically connected to the gate driver circuit 41, and the wiring 130 can be electrically connected to the source driver circuit . Thereby, light emission/non-light emission of the light emitting device 32 can be controlled for each pixel 30 . Also, by controlling the potential of the wiring 130 , the light emission luminance of the light emitting device 32 can be controlled for each pixel 30 . For example, when acquiring a cross-sectional image of a subject with low infrared transmittance, the potential of the wiring 130 is increased to increase the emission luminance of the light-emitting device 32 to obtain a cross-sectional image of the subject with high infrared transmittance. In the case of acquisition, the potential of the wiring 130 can be reduced to lower the light emission luminance of the light emitting device 32 .

Note that the wiring 130 does not have to be electrically connected to the source driver circuit 42 . In this case, the wiring 130 can function as, for example, a power supply line.

9A and 9B show the structure in which the cathode of the photoelectric conversion device 31 is electrically connected to either the source or the drain of the transistor 103, as shown in FIGS. Alternatively, the anode of the photoelectric conversion device 31 may be electrically connected to either the source or the drain of the transistor 103 .

10A and 10B, one electrode of the photoelectric conversion device 31 is electrically connected to the wiring 122 and the other electrode of the photoelectric conversion device 31 is connected to one of the source and the drain of the transistor 103. electrically connected. In addition, the other of the source and drain of the transistor 104 is electrically connected to the wiring 132 .

The wiring 132 functions as a power supply line or a reset potential supply line. 10A and 10B, the anode side of the photoelectric conversion device 31 is electrically connected to the transistor 103, and the node FD is reset to a low potential to operate. 132 is set to a low potential (a potential lower than that of the wiring 122).

The description of FIGS. 9A and 9B can be referred to for the description of the light emitting device 32 shown in FIGS. 10A and 10B and its connection form with peripheral elements.

The transistor 103 has a function of controlling the potential of the node FD. The transistor 104 has a function of resetting the potential of the node FD. The transistor 105 functions as a source follower circuit and can output the potential of the node FD to the wiring 129 as imaging data. The transistor 106 has a function of selecting a pixel for which imaging data is output.

A transistor including a metal oxide for a channel formation region (hereinafter referred to as an OS transistor) is preferably used as the transistor 103 and the transistor 104 . An OS transistor has a characteristic of extremely low off-state current. By using OS transistors for the transistors 103 and 104, the period in which charge can be held in the node FD can be significantly increased. Therefore, it is not necessary to immediately read out the acquired imaging data after the pixels 30 acquire the imaging data by performing the exposure operation to the pixels 30, that is, the charge accumulation operation. For example, the imaging data can be read after all the pixels 30 have acquired the imaging data. As a result, image data can be obtained in a short period of time, and an image with little distortion can be obtained even when imaging a moving object. For example, even if the subject 22 is a living animal, fish, insect, or the like, a cross-sectional image without distortion can be acquired.

When a transistor having a relatively high off-state current, such as a transistor using Si for a channel formation region (hereinafter referred to as a Si transistor), is used in the pixel 30, the data potential tends to flow out from the charge storage portion. Therefore, in order to retain image data in the pixels 30 for a long period of time, it is necessary to separately provide a memory circuit or the like, and complex operations must be performed at high speed. On the other hand, when OS transistors are used for the transistors 103 and 104, almost no data potential flows out from the charge storage portion, so that captured data can be easily held for a long time.

An OS transistor is also preferably used for the transistor 107 illustrated in FIGS. 9B and 10B. As described above, since the OS transistor has extremely low off-state current, current flow to the light-emitting device 32 can be suppressed when the transistor 107 is off. Thereby, it is possible to suppress the occurrence of noise in the cross-sectional image acquired by the semiconductor device 20 .

Note that an OS transistor may be applied to the transistors 105 and 106 as well. Alternatively, an OS transistor and a Si transistor may be used in any combination. Alternatively, all the transistors may be OS transistors or Si transistors. Si transistors include transistors containing amorphous silicon, transistors containing crystalline silicon (typically low-temperature polysilicon, monocrystalline silicon, etc.), and the like.

Next, an example of the operation of the imaging circuit 100 shown in FIGS. 9A and 9B will be described with reference to the timing chart of FIG. 11A. Note that in the description of the timing charts in this specification, a high potential is represented by "H" and a low potential is represented by "L". It is assumed that the wiring 121 is always supplied with "L" and the wiring 122 is always supplied with "H".

In the period T1, when the potential of the wiring 126 is set at "H", the potential of the wiring 127 is set at "H", and the potential of the wiring 128 is set at "L", the transistors 103 and 104 are turned on, and the potential of the wiring 123 is applied to the node FD. H" is supplied (reset operation).

In the period T2, when the potential of the wiring 126 is set at "L", the potential of the wiring 127 is set at "H", and the potential of the wiring 128 is set at "L", the transistor 104 is turned off and the supply of the reset potential is cut off. Further, the potential of the node FD is lowered according to the illuminance of the light with which the photoelectric conversion device 31 is irradiated (exposure operation).

In the period T3, when the potential of the wiring 126 is set at "L", the potential of the wiring 127 is set at "L", and the potential of the wiring 128 is set at "L", the transistor 103 is turned off, and the potential of the node FD is determined and held. (hold operation). At this time, by using OS transistors with low off-state current as the transistors 103 and 104 which are connected to the node FD, unnecessary charge leakage from the node FD can be suppressed, and the data retention time can be extended. can.

In the period T4, when the potential of the wiring 126 is set at "L", the potential of the wiring 127 is set at "L", and the potential of the wiring 128 is set at "H", the transistor 106 is turned on, and the source follower operation of the transistor 105 increases the potential of the node FD. is read out to the wiring 129 (read operation).

The above is an example of the operation of the imaging circuit 100 shown in FIGS.

The imaging circuit 100 shown in FIGS. 10A and 10B can be operated according to the timing chart of FIG. 11B. Note that the wiring 122 is always supplied with "H" and the wiring 132 is always supplied with "L". The basic operation is the same as the description of the timing chart of FIG. 11(A).

12A and 12B show a structure in which the transistors 103 to 107 included in the pixel 30 having the structure shown in FIG. 9B are provided with back gates. FIG. 12A shows a structure in which the back gate is electrically connected to the front gate, which has the effect of increasing the on current. FIG. 12B shows a structure in which the back gate is electrically connected to a wiring capable of supplying a constant potential, and the threshold voltage of the transistor can be controlled.

Alternatively, a structure in which each transistor can operate appropriately, such as a combination of FIGS. Further, the pixel circuit may include a transistor with no back gate. Note that the structure in which a transistor has a back gate can be applied to any of the structures shown in FIGS.

<Pixel circuit configuration example 2>
FIG. 13A is a circuit diagram illustrating a configuration example of the light emitting circuit 110. FIG. A light-emitting circuit 110 having a structure illustrated in FIG. 13A includes a transistor 211, a transistor 213, a transistor 221, a capacitor 215, a capacitor 217, and a light-emitting device 32. FIG. The light emitting circuit 110 is electrically connected to wirings 231a and 231b functioning as signal lines, and is electrically connected to wirings 232a and 232b functioning as data lines. Here, the wirings 231a and 231b can be electrically connected to the gate driver circuit 41 shown in FIG. 2, for example, and the wirings 232a and 232b can be electrically connected to the source driver circuit 42 shown in FIG. can be connected to

One of the source and drain of the transistor 211 is electrically connected to one electrode of the capacitor 215 . One of the source and drain of the transistor 213 is electrically connected to the other electrode of the capacitor 215 . The other electrode of the capacitor 215 is electrically connected to one electrode of the capacitor 217 . One electrode of the capacitor 217 is electrically connected to the gate of the transistor 221 . One of the source or drain of transistor 221 is electrically connected to one electrode of light emitting device 32 .

A gate of the transistor 211 is electrically connected to the wiring 231a. A gate of the transistor 213 is electrically connected to the wiring 231b. The other of the source and the drain of the transistor 211 is electrically connected to the wiring 232a. The other of the source and the drain of the transistor 213 is electrically connected to the wiring 232b. The other electrode of the capacitor 217 is electrically connected to the wiring 235 . The other of the source and drain of the transistor 221 is electrically connected to the wiring 237 . The other electrode of light emitting device 32 is electrically connected to wiring 239 .

Here, a wiring that connects the other of the source and the drain of the transistor 211 and one electrode of the capacitor 215 is a node N1. A wiring that connects the other of the source and drain of the transistor 213, the other electrode of the capacitor 215, one electrode of the capacitor 217, and the gate of the transistor 221 is a node N2.

The wiring 235 can be a common wiring for, for example, all the light emitting circuits 110 provided in the semiconductor device 20 . In this case, the potential supplied to the wiring 235 is the common potential. A constant potential can be supplied to the wirings 237 and 239 . For example, the wiring 237 can be supplied with a high potential and the wiring 239 can be supplied with a low potential.

The transistor 221 has the function of controlling the current supplied to the light emitting device 32 . Specifically, the transistor 221 has a function of supplying the light emitting device 32 with a current corresponding to the potential of the node N2. The capacitor 217 functions as a storage capacitor. Capacitive element 217 may be omitted.

Note that although FIG. 13A shows a structure in which the anode side of the light-emitting device 32 is electrically connected to the transistor 221, the transistor 221 may be electrically connected to the cathode side. In this case, the potential of the wiring 237 can be low and the potential of the wiring 239 can be high.

By turning off the transistor 211, the light emitting circuit 110 can hold the potential of the node N1. By turning off the transistor 213, the potential of the node N2 can be held. Further, by turning off the transistor 213 and writing a predetermined potential to the node N1 through the transistor 211, capacitive coupling through the capacitor 215 changes the potential of the node N2 according to the change in the potential of the node N1. can be made

OS transistors can be used as the transistors 211 and 213 . As described above, the OS transistor has extremely low off-state current. By using OS transistors for the transistors 211 and 213, the period in which charges can be held at the nodes N1 and N2 can be significantly increased. Accordingly, the frequency of potential writing to the nodes N1 and N2 can be reduced as compared with the case where transistors with high off-state current are used as the transistors 211 and 213 . Therefore, power consumption of the CT apparatus 10 can be reduced.

An OS transistor can also be applied to the transistor 221 . Thereby, it is possible to suppress the flow of current to the light emitting device 32 when the transistor 221 is in the off state. Thereby, it is possible to suppress the occurrence of noise in the cross-sectional image acquired by the semiconductor device 20 .

Next, an example of the operation of the light emitting circuit 110 shown in FIG. 13A is described with reference to the timing chart of FIG. 13B.

In the operation shown in FIG. 13B, one frame period is divided into a period T1 and a period T2. A period T1 is a period in which a potential is written to the node N2, and a period T2 is a period in which a potential is written to the node N1.

In the period T1, a potential for turning on the transistor is supplied to both the wiring 231a and the wiring 231b. A potential _Vref which is a fixed potential is supplied to the wiring 232a, and a potential _Vw is supplied to the wiring 232b.

A potential V _ref is supplied from the wiring 232a through the transistor 211 to the node N1. Further, the potential _Vw is supplied from the wiring 232b through the transistor 213 to the node N2. Therefore, the capacitive element 215 holds the potential difference V _w −V _ref .

Subsequently, in the period T2, a potential for turning on the transistor 211 is supplied to the wiring 231a, and a potential for turning off the transistor 213 is supplied to the wiring 231b. A potential V _data is supplied to the wiring 232a, and a predetermined constant potential is supplied to the wiring 232b. Note that the potential of the wiring 232b may be floating.

A potential V _data is supplied to the node N1 through the transistor 211 . At this time, due to capacitive coupling by the capacitor 215, the potential of the node N2 changes by the potential _dV in accordance with the potential Vdata.

Here, the potential dV is roughly determined by the capacitance value of the capacitor 215 , the capacitance value of the capacitor 217 , and the capacitance value of the gate capacitance of the transistor 221 . When the capacitance value of the capacitor 215 is sufficiently larger than the sum of the capacitance value of the capacitor 217 and the gate capacitance of the transistor 221, the potential dV is close to the potential difference V _data -V _ref .

In the period T2, the potential of the node N2 has a value that depends on the potential _Vw and the potential _Vdata . Therefore, the light emission luminance of the light emitting device 32 is luminance corresponding to the potential of the wiring 232a and the potential of the wiring 232b. For example, when acquiring a cross-sectional image of a subject with low infrared transmittance, the values of the potential _Vw and the potential _Vdata can be increased to increase the emission luminance of the light emitting device 32 . On the other hand, when acquiring a cross-sectional image of a subject with high infrared transmittance, the light emission luminance of the light emitting device 32 can be lowered by decreasing the values of the potential _Vw and the potential _Vdata .

Further, when the potential V _data is higher than the potential V _ref and the potential V _ref is lower than the ground potential, for example, the potential of the node N2 in the period T2 is higher than both the potential V _w and the potential V _data . For example, when the potential V _ref is the ground potential, the potential of the node N2 in the period T2 is close to "V _w +V _data ". Therefore, a potential exceeding the maximum potential that can be generated by the source driver circuit 42 or the like electrically connected to the wirings 232a and 232b can be supplied to the node N2. Therefore, since the light emitting device 32 can emit light with high brightness, a clear cross-sectional image can be acquired even if the subject 22 has a low infrared transmittance. Moreover, since the source driver circuit 42 and the like do not have to have a high withstand voltage, the cost of the CT apparatus 10 can be reduced.

For example, when the subject 22 is a human body, the transmittance of infrared rays in the subject 22 may be lower than the transmittance of X-rays. Therefore, when the brightness of the infrared rays emitted from the light emitting device 32 is low, the cross-sectional image of the subject 22 may not be obtained correctly. Therefore, by configuring the light-emitting circuit 110 as shown in FIG. 13A, the brightness of the infrared rays emitted from the light-emitting device 32 can be increased, and the cross-sectional image of the subject 22 can be acquired correctly.

Note that the light-emitting circuit 110 is not limited to the circuit illustrated in FIG. 13A, and may have a structure in which a transistor, a capacitor, or the like is added. For example, by adding one transistor and one capacitor to the structure shown in FIG. 13A, the number of nodes capable of holding a potential can be increased to three. In other words, the light-emitting circuit 110 can be provided with one more node capable of holding a potential in addition to the nodes N1 and N2. Thereby, the potential of the node N2 can be made higher. Therefore, a larger current can flow through the light-emitting device 32, so that the luminance of the light-emitting device 32 can be further increased.

A circuit 201 is a circuit excluding the transistor 211, the transistor 213, and the capacitor 215 in the light-emitting circuit 110 having the structure illustrated in FIG. 14A to 14C are diagrams illustrating configuration examples of the circuit 201. FIG. A circuit 201 having the structure shown in FIG. 14A includes a capacitor 217, a transistor 221, and a light-emitting device 32, similarly to the circuit 201 having the structure shown in FIG.

In the circuit 201 having the structure illustrated in FIG. 14A, the gate of the transistor 221 and one electrode of the capacitor 217 are electrically connected to the node N2. One of the source and drain of the transistor 221 is electrically connected to the wiring 237 . The other of the source and drain of the transistor 221 is electrically connected to the other electrode of the capacitor 217 . The other electrode of the capacitive element 217 is electrically connected to one electrode of the light emitting device 32 . The other electrode of light emitting device 32 is electrically connected to wiring 239 .

A circuit 201 having the structure shown in FIG. 14B also includes a capacitor 217, a transistor 221, and a light-emitting device 32, similarly to the circuit 201 having the structure shown in FIG.

In the circuit 201 having the structure illustrated in FIG. 14B, the gate of the transistor 221 and one electrode of the capacitor 217 are electrically connected to the node N2. One electrode of the light emitting device 32 is electrically connected to the wiring 237 . The other electrode of light emitting device 32 is electrically connected to one of the source or drain of transistor 221 . The other of the source and drain of the transistor 221 is electrically connected to the other electrode of the capacitor 217 . The other electrode of the capacitor 217 is electrically connected to the wiring 239 .

FIG. 14C shows a configuration example of the circuit 201 in which a transistor 225 is added to the circuit 201 shown in FIG. 14A. One of the source and drain of the transistor 225 is electrically connected to the other of the source and drain of the transistor 221 and the other electrode of the capacitor 217 . The other of the source or drain of transistor 225 is electrically connected to one electrode of light emitting device 32 . A gate of the transistor 225 is electrically connected to the wiring 241 . A wiring 241 functions as a signal line that controls conduction of the transistor 225 .

In the light-emitting circuit 110 including the circuit 201 having the structure shown in FIG. 14C, even if the potential of the node N2 is higher than or equal to the threshold voltage of the transistor 221, current does not flow to the light-emitting device 32 unless the transistor 225 is turned on. Not flowing. Therefore, malfunction of the semiconductor device 20 can be suppressed.

<Example of cross-sectional configuration of pixel>
FIG. 15 is a cross-sectional view for explaining a configuration example of the pixel 30. As shown in FIG. In the pixel 30, a transistor, a photoelectric conversion device 31, a light emitting device 32, and the like are provided between the substrate 360 and the substrate 350. FIG. Note that FIGS. 15A and 15B show structural examples of the transistor 103 and the transistor 107 as transistors.

Here, the substrates 360 and 350 are flexible substrates (hereinafter referred to as flexible substrates). Thereby, the semiconductor device 20 can be made flexible.

As shown in FIG. 15, the pixel 30 can have a laminated structure of layers 101 and 102 . Layer 101 is provided with substrate 360 , insulating layer 386 , insulating layer 381 , transistor 103 and transistor 107 , and insulating layer 382 . The transistors 103 and 107 are provided between the insulating layers 381 and 382 . In addition, an insulating layer 385 and an insulating layer 384 are provided so as to cover channel formation regions, source regions, and drain regions of the transistors 103 and 107 . An insulating layer 383 is provided between the insulating layer 384 and the insulating layer 382 .

An adhesive layer 363 is provided between the substrate 360 and the insulating layer 386 , and the adhesive layer 363 bonds the substrate 360 to the insulating layer 386 .

A conductive layer 321 is provided to be electrically connected to one of the source and the drain of the transistor 103, and a conductive layer 322 is provided to be electrically connected to the other of the source and the drain of the transistor 103. FIG. Further, a conductive layer 323 is provided so as to be electrically connected to one of the source and the drain of the transistor 107, and a conductive layer 324 is provided so as to be electrically connected to the other of the source and the drain of the transistor 107. FIG. Note that the conductive layers 321 to 324 are sometimes called wirings. Another conductive layer provided in the semiconductor device attached to the CT apparatus of one embodiment of the present invention may also be referred to as a wiring.

For at least one of the insulating layers 381 to 386, a material into which impurities such as water and hydrogen are difficult to diffuse is preferably used. Accordingly, since the insulating layer can function as a barrier film, entry of impurities into the transistors 103, 107, and the like can be effectively suppressed. Therefore, the reliability of the CT apparatus of one embodiment of the present invention can be improved.

The transistors provided in the layer 101, such as the transistors 103 and 107, are preferably thin film transistors such as OS transistors. As a result, elements such as transistors provided in the layer 101 can be isolated without providing an element isolation layer such as a field oxide film. Therefore, the CT apparatus 10 can be manufactured by a simple method.

The layer 102 is provided with an insulating layer 332 , a light emitting device 32 , a photoelectric conversion device 31 and an insulating layer 333 . The layer 102 is also provided with a substrate 350 , an insulating layer 354 and a filter 351 . Substrate 360 and substrate 350 are sealed via sealing layer 352 . An adhesive layer 353 is provided between the substrate 350 and the insulating layer 354 , and the substrate 350 is attached to the insulating layer 354 by the adhesive layer 353 .

An insulating layer 332 is provided to cover the conductive layers 321 to 324 , and the light-emitting device 32 and the photoelectric conversion device 31 are provided over the insulating layer 332 .

The light-emitting device 32 can have a configuration in which a conductive layer 35, an EL layer 36, and a conductive layer 37 are stacked in this order from the insulating layer 332 side. That is, the light emitting device 32 can be an EL (Electro-Luminescence) device. Further, the photoelectric conversion device can have a structure in which the conductive layer 33, the active layer 34, and the conductive layer 37 are stacked in order from the insulating layer 332 side.

Here, the conductive layer 35 and the conductive layer 33 can be formed in the same process. Specifically, an insulating film is formed over the conductive layers 321 to 324 and the insulating layer 332, and an opening reaching the conductive layer 321 and an opening reaching the conductive layer 323 are provided in the insulating film. , forming the insulating layer 332 . Next, after forming a conductive film over the insulating layer 332 and in the opening, patterning is performed by a photolithography method or the like. After that, the conductive film is processed by an etching method or the like according to the formed pattern. Through the above steps, the conductive layers 35 and 33 can be formed.

The conductive layer 35 can function as a pixel electrode of the light emitting device 32 . The conductive layer 33 can function as a pixel electrode of the photoelectric conversion device 31 . Also, the conductive layer 37 can serve as both a common electrode for the light emitting device 32 and a common electrode for the photoelectric conversion device 31 . Therefore, the semiconductor device 20 having the pixel 30 having the configuration shown in FIG. 15 can be manufactured by a simpler method than the case of forming the pixel electrode and common electrode of the light emitting device and the electrode and common electrode of the photoelectric conversion device in different steps. can be made. Therefore, the CT apparatus 10 can be made inexpensive.

In the pixel 30 having the configuration shown in FIG. 15, the potential supplied to the common electrode of the light emitting device 32 and the potential supplied to the common electrode of the photoelectric conversion device 31 are equal. Therefore, when the pixel 30 has the configuration shown in FIG. 10B, for example, the configuration shown in FIG. 15 can be applied. Note that when the structure shown in FIG. 15 is applied to the pixel 30 having the structure shown in FIG. 10B, the wiring 122 and the wiring 130 are electrically connected. 10A and 10B, a wiring electrically connected to one electrode of the photoelectric conversion device 31, one of the source and the drain of the transistor 105, may not be electrically connected by the wiring 122 . That is, the power line electrically connected to one electrode of the photoelectric conversion device 31 and the power line electrically connected to one of the source and drain of the transistor 105 may be different.

The conductive layer 35 is electrically connected to the conductive layer 323 through an opening provided in the insulating layer 332 . The conductive layer 33 is electrically connected to the conductive layer 321 through an opening provided in the insulating layer 332 . An insulating layer 333 is provided to cover the ends of the conductive layer 35 and the conductive layer 33 .

The filter 351 is provided so as to have a region overlapping the photoelectric conversion device 31 and the light emitting device 32 . Filter 351 has a function of absorbing light of a specific wavelength. For example, it has a function of absorbing visible light (wavelength of 400 nm or more and 700 nm or less). Alternatively, it has a function of absorbing light with a wavelength of 400 nm or more and 650 nm or less, for example. Alternatively, it has a function of absorbing light with a wavelength of 400 nm or more and 600 nm or less, for example. Note that the filter 351 may have a function of absorbing light with a wavelength of less than 400 nm, such as ultraviolet light and X-rays.

By providing the filter 351 so as to have a region overlapping with the light emitting device 32 , only light of a specific wavelength such as infrared light can be emitted from the light emitting device 32 to the outside of the pixel 30 . Moreover, by providing the filter 351 so as to have a region overlapping the photoelectric conversion device 31 , it is possible to suppress light of wavelengths other than the light of the specific wavelength from entering the photoelectric conversion device 31 . Accordingly, light other than the light emitted from the light emitting device 32 to the outside of the pixel 30 can be prevented from entering the photoelectric conversion device 31 . As described above, the light detection sensitivity of the semiconductor device 20 can be increased. Therefore, the reliability of the CT apparatus 10 can be improved. Note that the filter 351 may not be provided.

The sealing layer 352 can be provided between the photoelectric conversion device 31 and the light emitting device 32 and the filter 351 and the insulating layer 354 . The sealing layer 352 has a function of preventing oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light emitting device 32 and the photoelectric conversion device 31 .

The materials and the like of each component of the pixel 30 will be described below.

As described above, flexible substrates are used as substrates 360 and 350 . As the flexible substrate, a substrate using a film is preferable, and a substrate using a resin film is particularly preferable. Accordingly, the flexibility of the semiconductor device of one embodiment of the present invention can be increased, and the weight and thickness of the semiconductor device can be reduced.

Examples of flexible substrates include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, polyethersulfone ( PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE ) resin, ABS resin, cellulose nanofiber, and the like can be used. Alternatively, glass having a thickness that is flexible may be used.

For the adhesive layer 363 and the adhesive layer 353, various curable adhesives such as photocurable adhesives such as ultraviolet curable adhesives, reaction curable adhesives, thermosetting adhesives, and anaerobic adhesives can be used. Alternatively, an adhesive sheet or the like may be used.

As insulating films included in the semiconductor device 20, such as the insulating layers 381 to 386, the insulating layers 332, 333, 354, and the gate insulating layer of a transistor, for example, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, Alternatively, a nitride oxide insulating film can be used. The insulating film can be formed with a single layer or stacked layers. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, and tantalum oxide films. . Examples of the nitride insulating film include a silicon nitride film, an aluminum nitride film, and the like. Examples of the oxynitride insulating film include a silicon oxynitride film and the like. As the nitride oxide insulating film, a silicon nitride oxide film or the like can be given.

In this specification and the like, “silicon oxynitride” refers to a composition in which the oxygen content is higher than the nitrogen content. In this specification and the like, “silicon oxynitride” refers to a composition in which the nitrogen content is higher than the oxygen content.

Tungsten (W), molybdenum (Mo), zirconium (Zr ), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al ), copper (Cu), silver (Ag), or an alloy thereof, or a metal nitride thereof.

A light-transmitting conductive layer can be used as the conductive layer 37 . For example, when the light emitting device 32 has a function of emitting infrared light, a translucent conductive layer that transmits infrared light can be used as the conductive layer 37 . For example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (ITO), indium tin oxide containing titanium oxide, indium zinc An oxide, indium tin oxide to which silicon oxide is added, or the like can be used. Alternatively, cadmium tin oxide (CTO) or the like can be used.

The EL layer 36 has a light-emitting material. That is, it can be said that the EL layer 36 is a light-emitting layer. The light-emitting device 32 is classified according to whether the light-emitting material is an organic compound or an inorganic compound, and the former is generally called an organic EL device, and the latter is called an inorganic EL device.

In the organic EL device, when a voltage is applied, electrons are injected from one electrode and holes are injected from the other electrode into the EL layer. Then, recombination of these carriers (electrons and holes) causes the light-emitting organic compound to form an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

The EL layer can be formed by a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements according to the element structure. A dispersion-type inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. A thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and the light-emitting mechanism is localized light emission utilizing inner-shell electronic transition of metal ions.

The light-emitting device 32 can emit light of various wavelengths depending on the material forming the EL layer 36 . In one embodiment of the present invention, a material that emits light having a peak in near-infrared light is used for the material forming the EL layer 36 . For example, materials that emit light at wavelengths of 720 nm, 760 nm, 850 nm, 900 nm, and near these wavelengths may be used depending on the application.

Note that in one embodiment of the present invention, an organometallic iridium complex that emits near-infrared light is preferably used as a light-emitting material (also referred to as a guest material or a dopant material) of the EL layer 36 . The organometallic iridium complex preferably has a dimethylphenyl skeleton and a quinoxaline skeleton. Further, the organometallic iridium complex is typically bis{4,6-dimethyl-2-[3-(3,5-dimethylphenyl)-2-quinoxalinyl-κN]phenyl-κC}(2, 2′,6,6′-Tetramethyl-3,5-heptanedionato-κ ² O,O′)iridium (III) (abbreviation: Ir(dmdpq) ₂ (dpm)) and the like can be used. By using the organometallic iridium complex, an imaging device with high quantum efficiency or high luminous efficiency can be provided.

Further, as the substance (that is, host material) used for dispersing the organometallic iridium complex, examples include 2,3-bis(4-diphenylaminophenyl)quinoxaline (abbreviation: TPAQn) and aryl such as NPB. In addition to compounds having an amine skeleton, carbazole derivatives such as CBP, 4,4',4''-tris(carbazol-9-yl)triphenylamine (abbreviation: TCTA), and bis[2-(2-hydroxyphenyl ) pyridinato]zinc (abbreviation: Znpp ₂ ), bis[2-(2-hydroxyphenyl)benzoxazolato]zinc (abbreviation: Zn(BOX) ₂ ), bis(2-methyl-8-quinolinolato)(4- Metal complexes such as phenylphenolato)aluminum (abbreviation: BAlq) and tris(8-quinolinolato)aluminum (abbreviation: Alq ₃ ) are preferred. Polymer compounds such as PVK can also be used.

As a material (host material) used for dispersing the organometallic iridium complex, N-(1,1′-biphenyl-4-yl)-N-[4-(9-phenyl-9H- Carbazol-3-yl)phenyl]-9,9-dimethyl-9H-fluoren-2-amine (abbreviation: PCBBiF) is preferably used.

The active layer 34 has a laminated structure in which a p-type semiconductor and an n-type semiconductor are laminated to realize a pn junction, or a laminated structure in which a p-type semiconductor, an i-type semiconductor, and an n-type semiconductor are laminated to realize a pin junction. etc.

As a semiconductor used for the active layer 34, an inorganic semiconductor such as silicon or an organic semiconductor containing an organic compound can be used. In particular, when the active layer 34 has an organic semiconductor material and the EL layer 36 has an organic compound as a light-emitting material, the EL layer 36 and the active layer 34 of the light-emitting device 32 can be formed by the same manufacturing apparatus. It is preferable because

When an organic semiconductor material is used for the active layer 34, an electron-accepting organic semiconductor material such as fullerene ₍ eg, C60, _C70 , etc.) or a derivative thereof can be used as the n-type semiconductor material. As the material of the p-type semiconductor, an electron-donating organic semiconductor material such as copper (II) phthalocyanine (CuPc) or tetraphenyldibenzoperiflanthene (DBP) can be used. . The active layer 34 may have a laminated structure (pn laminated structure) of an electron-accepting semiconductor material and an electron-donating semiconductor material. may be a laminated structure (pin laminated structure) provided with a bulk heterostructure layer co-deposited with . In addition, for the purpose of suppressing dark current when light is not irradiated, a layer that functions as a hole blocking layer is provided around (upper or lower side) the above pn laminated structure or pin laminated structure. Alternatively, a layer functioning as an electron blocking layer may be provided.

When the light-emitting device 32 has an EL layer 36 as a light-emitting layer and the active layer 34 provided in the photoelectric conversion device 31 has an organic semiconductor material, the semiconductor device 20 can be made thinner. Thereby, the flexibility of the semiconductor device 20 can be enhanced.

As the sealing layer 352, in addition to an inert gas such as nitrogen or argon, an ultraviolet curing resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), EVA (ethylene vinyl acetate), or the like can be used. Also, the sealing layer 352 may contain a desiccant.

As part of the sealing layer 352, a protective layer such as silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like may be provided. Note that the adhesive layer 363 and the adhesive layer 353 can also have a material similar to the material that the sealing layer 352 can have.

<Cross-sectional structure example of OS transistor>
FIG. 16A shows a detailed configuration example of an OS transistor that can be applied to the transistor 103 and the like. In the OS transistor illustrated in FIG. 16A, an insulating layer is provided over a stack of a metal oxide layer and a conductive layer, and grooves reaching the metal oxide layer are provided in the insulating layer and the conductive layer. It is a self-aligned configuration in which the drain electrode 306 is formed.

The OS transistor can have a structure including a channel formation region 310 , a source region 303 , and a drain region 304 which are formed in the metal oxide layer 307 , a gate electrode 301 , a gate insulating layer 302 , and a back gate electrode 335 . can. Here, at least the gate insulating layer 302 and the gate electrode 301 are provided in the trench. A metal oxide layer 308 may also be provided in the trench. In addition, the insulating layer 385 functions as a gate insulating layer of the back gate electrode 335 .

Note that the metal oxide layer 307 preferably contains at least indium. In particular, it preferably contains indium and zinc. More preferably, it is an In--M--Zn oxide containing indium, zinc, and another kind of metal. M is selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. It can be one type or multiple types.

When the metal oxide layer 307 is an In--M--Zn oxide, the sputtering target used for forming the In--M--Zn oxide may have an In atomic ratio equal to or higher than the M atomic ratio. preferable. The atomic ratios of the metal elements in such a sputtering target are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1: 3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1: 6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc. is mentioned.

A target containing a polycrystalline oxide is preferably used as the sputtering target because the metal oxide layer 307 having crystallinity can be easily formed. Note that the atomic ratio of the metal oxide layer 307 to be deposited includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target. For example, when the composition of the sputtering target used for the metal oxide layer 307 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the formed metal oxide layer 307 is In: Ga:Zn may be close to 4:2:3 [atomic number ratio].

When the atomic ratio is described as In:Ga:Zn=4:2:3 or its vicinity, when the atomic ratio of In is 4, the atomic ratio of Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. Further, when describing that the atomic ratio is In:Ga:Zn=5:1:6 or its vicinity, when the atomic ratio of In is 5, the atomic ratio of Ga is greater than 0.1 2 or less, including the case where the atomic number ratio of Zn is 5 or more and 7 or less. Further, when describing that the atomic ratio is In:Ga:Zn=1:1:1 or its vicinity, when the atomic ratio of In is 1, the atomic ratio of Ga is greater than 0.1. 2 or less, including the case where the atomic number ratio of Zn is greater than 0.1 and 2 or less.

Also, the metal oxide layer 307 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wider energy gap than silicon in this manner, off-state current of a transistor can be reduced.

A metal oxide with a low carrier concentration is preferably used for the metal oxide layer 307 . In the case of lowering the carrier concentration of the metal oxide, the impurity concentration in the metal oxide should be lowered to lower the defect level density. In this specification and the like, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

In particular, hydrogen contained in the metal oxide reacts with oxygen bound to the metal atom to form water, which may cause oxygen vacancies in the metal oxide. If the channel formation region in the metal oxide contains oxygen vacancies, the transistor may have normally-on characteristics. Furthermore, a defect in which hydrogen is added to an oxygen vacancy functions as a donor, and an electron, which is a carrier, may be generated. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron that is a carrier. Therefore, a transistor using a metal oxide containing a large amount of hydrogen tends to have normally-on characteristics.

Defects with hydrogen in oxygen vacancies can function as donors for metal oxides. However, it is difficult to quantitatively evaluate the defects. Therefore, metal oxides are sometimes evaluated not by the donor concentration but by the carrier concentration. Therefore, in this specification and the like, instead of the donor concentration, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the metal oxide. In other words, the “carrier concentration” described in this specification and the like may be rephrased as “donor concentration”.

Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is less than 1×10 ²⁰ atoms/cm ³ , preferably 1×10 ¹⁹ atoms/cm It is less than ³ , more preferably less than 5×10 ¹⁸ atoms/cm ³ , still more preferably less than 1×10 ¹⁸ atoms/cm ³ . By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be imparted.

Further, the carrier concentration of the metal oxide in the channel forming region is preferably 1×10 ¹⁸ cm ⁻³ or less, more preferably less than 1×10 ¹⁷ cm ⁻³ , and 1×10 ¹⁶ cm ⁻³ . It is more preferably less than 1×10 ¹³ cm ⁻³ , even more preferably less than 1×10 ¹² cm ⁻³ , even more preferably less than 1×10 12 cm −3 . Although there is no particular limitation on the lower limit of the carrier concentration of the metal oxide in the channel forming region, it can be, for example, 1×10 ⁻⁹ cm ⁻³ .

As shown in FIG. 16B, the OS transistor may have a self-aligned structure in which a source region 303 and a drain region 304 are formed in a metal oxide layer using a gate electrode 301 as a mask.

Alternatively, as shown in FIG. 16C, a non-self-aligned top-gate transistor in which the source electrode 305 or the drain electrode 306 and the gate electrode 301 overlap with each other may be used.

The back gate electrode 335 may be electrically connected to the gate electrode 301 which is the front gate of the transistor provided opposite to it, as in the cross-sectional view of the transistor in the channel width direction shown in FIG. Note that FIG. 16D shows the transistor in FIG. 16A as an example, but the same applies to transistors with other structures. Further, a structure in which a fixed potential different from that of the front gate can be supplied to the back gate electrode 335 may be employed.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 2)
<Configuration of CAC-OS>
This embodiment describes a structure of a CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one embodiment of the present invention.

A CAC-OS is, for example, one structure of a material in which elements constituting a metal oxide are unevenly distributed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following description, one or more metal elements are unevenly distributed in the metal oxide, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof. The mixed state is also called a mosaic shape or a patch shape.

For example, CAC-OS in In—Ga—Zn oxide (In—Ga—Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) is indium oxide (hereinafter, InO _X1 (X1 is a real number greater than 0), or indium zinc oxide (hereinafter referred to as In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z2 are real numbers greater than 0)), and the like; Gallium oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers greater than 0) ) and the like, and the material is separated into a mosaic shape, and the mosaic InO _X1 or In _X2 Zn _Y2 O _Z2 is uniformly distributed in the film (hereinafter also referred to as a cloud shape). is.

In other words, CAC-OS is a composite metal oxide having a structure in which a region containing GaO 2 _X3 as a main component and a region containing In _{2 X2} Zn _Y2 O _Z2 or InO 2 _X1 as a main component are mixed. In this specification, for example, the first region means that the atomic ratio of In to the element M in the first region is greater than the atomic ratio of In to the element M in the second region. Assume that the concentration of In is higher than that of the region No. 2.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. Representative examples are represented by InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _(1+x0) Ga _(1−x0) O ₃ (ZnO) _m0 (−1≦x0≦1, m0 is an arbitrary number). Crystalline compounds are mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (C-Axis Aligned Crystal) structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

CAC-OS, on the other hand, relates to the material composition of metal oxides. CAC-OS is a material composition containing In, Ga, Zn, and O, in which a region that is observed in the form of nanoparticles containing Ga as the main component in part and nanoparticles containing In as the main component in part. The regions observed in a pattern refer to a configuration in which the regions are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS the crystal structure is a secondary factor.

Note that CAC-OS does not include a stacked structure of two or more films with different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.

In some cases, a clear boundary cannot be observed between a region containing GaO _X3 as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component.

Instead of gallium, aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. CAC-OS contains one or more of the metal elements, part of which is observed in the form of nanoparticles containing the metal element as the main component, and part of which contains nanoparticles containing In as the main component. The regions observed as particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.

CAC-OS can be formed, for example, by a sputtering method under the condition that the substrate is not intentionally heated. Further, when the CAC-OS is formed by a sputtering method, one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the film forming gas. good. Further, the flow rate ratio of oxygen gas to the total flow rate of film formation gas during film formation is preferably as low as possible. .

CAC-OS is characterized by the fact that no clear peak is observed when measured using θ/2θ scanning by the Out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. have. That is, it can be seen from the X-ray diffraction that no orientations in the ab plane direction and the c-axis direction of the measurement region are observed.

In addition, CAC-OS has an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam). A point is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure with no orientation in the planar direction and the cross-sectional direction.

Further, for example, in CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) reveals a region in which GaO _X3 is the main component. , and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are unevenly distributed and mixed.

CAC-OS has a structure different from IGZO compounds in which metal elements are uniformly distributed, and has properties different from those of IGZO compounds. That is, the CAC-OS phase-separates into a region containing GaO 2 _X3 or the like as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO 2 _X1 as a main component, and a region containing each element as a main component. has a mosaic structure.

Here, a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component has higher conductivity than a region containing GaO _X3 or the like as a main component. That is, when carriers flow through a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component, conductivity as a metal oxide is developed. Therefore, a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is distributed like a cloud in the metal oxide, so that a high field effect mobility (μ) can be realized.

On the other hand, a region containing GaO _X3 or the like as a main component has higher insulating properties than a region containing In _{X2 ZnY2} O _Z2 or InO _X1 as a main component. That is, by distributing the region containing _GaOx3 and the like as the main component in the metal oxide, it is possible to suppress leakage current and realize good switching operation.

Therefore, when CAC-OS is used for a semiconductor element, the insulation property caused by GaO 2 _X3 or the like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO 2 _X1 act in a complementary manner. On-current (I _on ) and high field effect mobility (μ) can be achieved.

In addition, a semiconductor element using CAC-OS has high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices including displays.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 3)
In this embodiment, a market image in which the semiconductor device of one embodiment of the present invention can be used will be described.

<Market image>
First, FIG. 17 shows a market image in which the semiconductor device of one embodiment of the present invention can be used. In FIG. 17, a region 701 represents a product region (OS Display) applicable to a display (Display) using a transistor having an oxide semiconductor in a channel formation region, and a region 702 represents a product region (OS Display) in which an oxide semiconductor is used in the channel formation region. A product area (OS LSI analog) in which an LSI (Large Scale Integration) to which a transistor having an oxide semiconductor is applied is analog-applicable. It represents a product area (OS LSI digital) that can be applied to (digital). A semiconductor device of one embodiment of the present invention can be suitably used in three regions, regions 701, 702, and 703 illustrated in FIG. 17, in other words, three large markets.

In FIG. 17, a region 704 represents a region where the regions 701 and 702 overlap, a region 705 represents a region where the regions 702 and 703 overlap, and a region 706 represents the regions 701 and 703. A region 703 represents an overlapping region, and a region 707 represents an overlapping region of the regions 701, 702, and 703, respectively.

In OS displays, for example, FET structures such as a bottom gate type OS FET (BG OSFET) and a top gate type OS FET (TG OS FET) can be preferably used. Note that the bottom gate OS FET includes a channel etch FET and a channel protection FET. The top gate type OS FET also includes a TGSA (top gate self-aligned) type FET.

Also, in OS LSI analog and OS LSI digital, for example, a gate-last type OS FET (GL OS FET) can be preferably used.

Note that each of the transistors described above includes a single gate transistor with one gate electrode, a dual gate transistor with two gate electrodes, and a transistor with three or more gate electrodes. Among dual gate transistors, it is particularly preferable to use a transistor with an S-channel (surrounded channel) structure.

Note that in this specification and the like, a transistor having an S-channel structure means a transistor structure in which a channel formation region is electrically surrounded by electric fields of one and the other of a pair of gate electrodes.

Products included in the OS Display (region 701) include products having LCDs (liquid crystal displays), ELs (Electro Luminescence), and LEDs (Light Emitting Diodes) as display devices. Alternatively, it is also preferable to combine the above display device with Q-Dots (Quantum Dots).

Note that in this embodiment, EL includes organic EL and inorganic EL. In addition, in the present embodiment, LEDs include micro LEDs, mini LEDs, and macro LEDs. In this specification and the like, light emitting diodes with a chip area of 10000 μm ² or less are micro LEDs, light emitting diodes with a chip area of 10000 μm ² or more and 1 mm ² or less are mini LEDs, and light emitting diodes with a chip area of 1 mm ² or more. is sometimes referred to as a macro LED.

Products included in the OS LSI analog (area 702) include sound source localization devices that support various frequency ranges (for example, audible sound with a frequency of 20 Hz to 20 kHz, or ultrasonic waves with a frequency of 20 kHz or higher), or batteries. Control devices (battery control ICs, battery protection ICs, battery management systems) and the like are included.

Products included in the OS LSI digital (region 703) include memory devices, CPU (Central Processing Unit) devices, GPU (Graphics Processing Unit) devices, FPGA (field-programmable gate array) devices, power devices, and OS LSIs. and a Si LSI are laminated or mixed to form a hybrid device, a light-emitting device, and the like.

Products included in area 704 include display devices having infrared sensors or near-infrared sensors in the display area, signal processing devices with sensors having OS FETs, implantable biosensor devices, and the like. Products included in the area 705 include a processing circuit including an A/D (Analog to Digital) conversion circuit, an AI (Artificial Intelligence) device including the processing circuit, and the like. Products included in the area 706 include display devices to which Pixel AI technology is applied. In this specification and the like, Pixel AI technology refers to technology that utilizes a memory configured by an OS FET or the like mounted in a pixel circuit of a display.

Products included in the area 707 include composite products that combine all the products included in the areas 701 to 706 .

As described above, the semiconductor device of one embodiment of the present invention can be applied to any product region as shown in FIG. That is, the semiconductor device of one embodiment of the present invention can be applied to many markets.

Note that the structure described in this embodiment can be combined with any of the other embodiments described in this specification and the like as appropriate.

This embodiment can be appropriately combined with the description of other embodiments.

10 CT apparatus 11 Gantry 12 Cradle 20 Semiconductor device 21 Cavity 22 Subject 30 Pixel 31 Photoelectric conversion device 32 Light emitting device 33 Conductive layer 34 Active layer 35 Conductive layer 36 EL layer 37 Conductive layer 38 Light 40 Pixel array 41 Gate driver circuit 42 Source driver circuit 42a Source driver circuit 42b Source driver circuit 43 Region 51 Layer 52 Layer 100 Imaging circuit 101 Layer 102 Layer 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Capacitive element 110 Light emitting circuit 121 Wiring 122 Wiring 123 Wiring 126 Wiring 127 Wiring 128 wiring 129 wiring 130 wiring 131 wiring 132 wiring 201 circuit 211 transistor 213 transistor 215 capacitor 217 capacitor 221 transistor 225 transistor 231a wiring 231b wiring 232a wiring 232b wiring 235 wiring 237 wiring 239 wiring 241 wiring 301 gate electrode 302 gate insulating layer 303 source region 304 drain region 305 source electrode 306 drain electrode 307 metal oxide layer 308 metal oxide layer 310 channel formation region 321 conductive layer 322 conductive layer 323 conductive layer 324 conductive layer 332 insulating layer 333 insulating layer 335 back gate electrode 350 substrate 351 Filter 352 Sealing layer 353 Adhesive layer 354 Insulating layer 360 Substrate 363 Adhesive layer 381 Insulating layer 382 Insulating layer 383 Insulating layer 384 Insulating layer 385 Insulating layer 386 Insulating layer 701 Area 702 Area 703 Area 704 Area 705 Area 706 Area 707 Area

Claims (3)

having a gantry,
A semiconductor device is attached to the cavity of the gantry,
Pixels are provided in a matrix in the semiconductor device,
The pixel is a CT apparatus having a photoelectric conversion device and a light emitting device,
having a first conductive layer, a second conductive layer, a third conductive layer, an active layer, and an EL layer;
The first conductive layer has a region functioning as a first electrode of the photoelectric conversion device,
the second conductive layer has a region that functions as a first electrode of the light emitting device;
The first conductive layer and the second conductive layer are arranged in the same layer,
the third conductive layer has a region functioning as a second electrode of the photoelectric conversion device and a region functioning as a second electrode of the light emitting device;
the active layer has a region sandwiched between the first conductive layer and the third conductive layer;
A CT apparatus, wherein the EL layer has a region sandwiched between the second conductive layer and the third conductive layer. In claim 1,
A CT apparatus, wherein the active layer has a region in contact with the EL layer. In claim 1 or claim 2,
the pixel has a first transistor and a second transistor;
the source or drain of the first transistor is electrically connected to the first conductive layer;
the source or drain of the second transistor is electrically connected to the second conductive layer;
The first transistor is arranged to have an overlap with the photoelectric conversion device,
The CT apparatus, wherein the second transistor is arranged to have an overlap with the light emitting device.

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