JP7129476B2 - Laminate and its manufacturing method - Google Patents

Description

The present invention relates to a laminate on which a semiconductor element can be mounted and a manufacturing method thereof.

2. Description of the Related Art With the miniaturization, thickness reduction, and high density of electronic components, miniaturization, thickness reduction, and high density are being demanded for module substrates on which semiconductor elements are mounted to obtain electronic components. In order to meet such demands, it is important to mount semiconductor elements on a narrow mounting surface. From this point of view, for example, Patent Document 1 below discloses a module substrate having a space (cavity portion) for incorporating a semiconductor element.

JP 2015-60912 A

Other module substrates or electronic components may be connected to a module substrate having a space for embedding a semiconductor element, and metal bumps are formed on the base material to connect to the other module substrate or electronic components. It is conceivable to embed the semiconductor element at a position different from the formation position of the metal bump on the substrate. Here, when forming the metal bumps on the base material, a method of forming an insulating layer having openings on the base material and then forming the metal bumps in the openings by plating is conceivable. In this case, if a thick metal layer (for example, copper foil) is used as the power supply layer for plating, the power supply layer is removed when it is necessary to remove the power supply layer from the viewpoint of suppressing noise generation after forming the metal bumps. The process may become complicated. Therefore, a method for easily obtaining a laminate that can be used as a module substrate for mounting a semiconductor element is desired.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a laminate capable of easily obtaining a laminate on which a semiconductor element can be mounted. Another object of the present invention is to provide a laminate obtained by such a manufacturing method.

One aspect of the method for producing a laminate according to the present invention is a substrate having an electrode layer on the surface, an electroless plated layer disposed on at least the electrode layer, and disposed on the substrate, and an insulating layer having an opening through which the plating layer including the electroless plating layer is exposed. Electroplating is performed on a substrate to form a metal bump in the opening in contact with the plating layer.

According to such a laminate manufacturing method, a plated layer including an electroless plated layer can be used as the power supply layer for forming the metal bumps. Then, when it is necessary to remove the power supply layer from the viewpoint of suppressing noise generation after forming the metal bump, it is possible to easily remove the plated layer including the relatively thin electroless plated layer. Therefore, it is possible to easily obtain a laminate on which a semiconductor element can be mounted. Moreover, according to the above-described method for manufacturing a laminate, it is not necessary to form the power supply layer after forming the insulating layer on the base material, and the manufacturing process of the laminate capable of mounting the semiconductor element is complicated. can be suppressed. Furthermore, according to the laminated body obtained by the above-described laminated body manufacturing method, it is possible to incorporate the semiconductor element (three-dimensional mounting) at a position different from the formation position of the metal bump on the base material, and Since it is possible to connect to other semiconductor elements, module substrates, or electronic parts via bumps, it is possible to achieve miniaturization, thinning, or high density of electronic parts including semiconductor elements.

One aspect of the method for manufacturing a laminate according to the present invention may further include a step of obtaining the insulating layer by forming openings in the insulator placed on the substrate before the bump forming step. .

One aspect of the method for manufacturing a laminate according to the present invention further comprises an electroless plated layer forming step of forming the electroless plated layer by applying electroless plating to the electrode layer before the bump forming step. It's okay. One aspect of the method for producing a laminate according to the present invention further comprises the step of forming a protective layer having openings through which the electrode layers are exposed on the substrate before the electroless plating layer forming step. good.

One aspect of the method for manufacturing a laminate according to the present invention may further include an insulating layer removing step of removing the insulating layer after the bump forming step. One aspect of the method for manufacturing a laminate according to the present invention further includes a step of removing, after the insulating layer removing step, a portion of the electroless plated layer located at a position different from the metal bump forming position. It's okay. One aspect of the method for manufacturing a laminate according to the present invention may further include the step of forming a protective layer covering the electrode layer after the insulating layer removing step.

In one aspect of the method for manufacturing a laminate according to the present invention, the electroless plated layer may be exposed through the opening of the insulating layer.

One aspect of the laminate according to the present invention includes a substrate having an electrode layer on its surface, an electroless plated layer disposed at least on the electrode layer, and the electroless plated layer on the electroless plated layer. and a metal bump in contact with the plating layer.

According to such a laminate, the semiconductor element can be embedded (three-dimensional mounting) at a position different from the formation position of the metal bumps on the base material, and other semiconductor elements and modules can be mounted through the metal bumps. Since it can be connected to a substrate or an electronic component, it is possible to achieve miniaturization, thinning, or high density of an electronic component including a semiconductor element.

The metal bump may be in contact with the electroless plating layer on one side surface of the laminate according to the present invention.

In one aspect of the laminate and its manufacturing method according to the present invention, the electrode layer may be a circuit pattern. The length of the metal bump in the stacking direction of the electrode layer and the electroless plated layer may be 10 μm or more, and may exceed 150 μm. Between the metal bump and the base material, the electrode layer and the electroless plated layer may not be adjacent to each other in a direction perpendicular to the stacking direction of the electrode layer and the electroless plated layer. The layer and the electroless plated layer may be adjacent to each other in a direction perpendicular to the stacking direction.

ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the laminated body which can obtain simply the laminated body which can mount a semiconductor element can be provided. Moreover, according to this invention, the laminated body obtained by such a manufacturing method can be provided.

FIG. 1 is a schematic cross-sectional view for explaining an example of a method for manufacturing a laminate. FIG. 2 is a schematic cross-sectional view for explaining an example of a method for manufacturing a laminate. FIG. 3 is a schematic cross-sectional view for explaining an example of a method for manufacturing a laminate. FIG. 4 is a schematic cross-sectional view for explaining an example of a method for manufacturing a laminate. FIG. 5 is a schematic cross-sectional view for explaining another example of the method for manufacturing a laminate. FIG. 6 is a schematic cross-sectional view for explaining another example of the method for manufacturing a laminate. FIG. 7 is a schematic cross-sectional view for explaining another example of the method for manufacturing a laminate. FIG. 8 is a schematic cross-sectional view for explaining another example of the method for manufacturing a laminate.

In this specification, a numerical range indicated using "to" indicates a range including the numerical values before and after "to" as the minimum and maximum values, respectively. In the numerical ranges described stepwise in this specification, the upper limit value or lower limit value of the numerical range at one step may be replaced with the upper limit value or lower limit value of the numerical range at another step. "A or B" may include either A or B, or may include both.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with appropriate reference to the drawings. However, the present invention is not limited to the following embodiments. The sizes of the components in each figure are conceptual, and the relative sizes of the components are not limited to those shown in each figure. In each figure, the same or corresponding parts are denoted by the same reference numerals, and redundant explanations are omitted.

A method for producing a laminate according to the present embodiment includes a base material having an electrode layer on its surface, an electroless plated layer disposed on at least the electrode layer, and the electroless plated layer disposed on the base material. and an insulating layer (first insulating layer) having an opening through which the plated layer including the electrolytic plated layer is exposed. Electrolytic plating is applied to a substrate to form a metal bump in the opening in contact with the plated layer. Have a process. The laminate according to this embodiment can be obtained by the method for manufacturing a laminate according to this embodiment. The laminate according to the present embodiment includes a substrate having an electrode layer on its surface, an electroless plated layer disposed at least on the electrode layer, and a plating including the electroless plated layer on the electroless plated layer. a metal bump contacting the layer.

The laminate according to this embodiment can be used as a module substrate for mounting a semiconductor element. The laminate according to this embodiment has a space for mounting a semiconductor element at a position different from the formation position of the metal bumps on the substrate. The fact that the laminate according to the present embodiment includes a plated layer including an electroless plated layer and metal bumps can be confirmed by the crystalline state of the constituent materials of these members, and can be confirmed by, for example, a metallurgical microscope. can. A circuit pattern, for example, can be used as the electrode layer. The laminate according to this embodiment may further include an insulating layer disposed on the base material and having openings, and the metal bumps may be disposed in the openings.

The plated layer only needs to include an electroless plated layer, and the outermost layer of the plated layer does not have to be an electroless plated layer. That is, the plated layer may be, for example, an aspect composed of an electroless plated layer, or an aspect having an electroless plated layer and an electrolytic plated layer disposed on the electroless plated layer. The thickness of the electroplated layer arranged on the electroless plated layer is, for example, 1 to 5 μm. In the laminate according to this embodiment, the metal bumps may be in contact with the electroless plated layer, and may be in contact with the electrolytic plated layer arranged on the electroless plated layer. Also, the electroless plated layer may be exposed from the opening of the insulating layer, and the electrolytic plated layer disposed on the electroless plated layer may be exposed from the opening of the insulating layer.

The method for manufacturing a laminate according to the present embodiment may include a substrate preparation step, a plating layer formation step, or an insulating layer formation step before the bump formation step. , a plating layer forming step and an insulating layer forming step are provided in this order. In the substrate preparation step, a substrate having an electrode layer on its surface is prepared. The plating layer forming step may include an electroless plating layer forming step of forming an electroless plating layer by applying electroless plating to the electrode layer disposed on the surface of the base material. It may have an electrolytic plated layer forming step of forming an electrolytic plated layer by subjecting the formed electroless plated layer to electrolytic plating. When the plating layer is an electroless plating layer, an electroless plating layer forming step can be performed as the plating layer forming step. In the insulating layer forming step, an insulating layer is obtained by forming openings in the insulator arranged on the substrate.

The manufacturing method of the laminate according to the present embodiment may include an insulating layer removing step of removing the insulating layer formed in the insulating layer forming step after the bump forming step.

The method for manufacturing a laminate according to the present embodiment may include, after the insulating layer removing step, a plating layer removing step of removing a portion of the plating layer that is located at a position different from the metal bump formation position. By removing a part of the plating layer, it is easy to suppress noise caused by the plating layer. When the plating layer has an electroless plating layer and an electroplating layer arranged on the electroless plating layer, the plating layer removing step is arranged at a position different from the formation position of the metal bump in the electroplating layer. It may have an electroless plated layer removing step of removing the portion where the metal bump is formed, and may have an electroless plated layer removing step of removing a portion arranged at a position different from the position where the metal bump is formed in the electroless plated layer. . The electrolytic plated layer removing step and the electroless plated layer removing step may be performed individually or simultaneously. That is, the electroless plated layer may be removed after the electrolytic plated layer is removed, or may be removed simultaneously with the electrolytic plated layer. By removing a part of the electroplated layer and/or the electroless plated layer, noise caused by these plated layers can be easily suppressed. When the plated layer is an electroless plated layer, an electroless plated layer removing step can be performed as the plated layer removing step. Before the electroless plated layer removal step, the electroless plated layer is removed from the metal bump formation position (the metal bump formation position in the direction orthogonal to the stacking direction of the electrode layer and the electroless plated layer. Contact between the metal bump and the plating layer). The first portion (exposed portion; the portion not covered with the insulating layer before the insulating layer removing step) arranged in the same position) and the second portion arranged in a position different from the metal bump forming position. portion (unexposed portion; the portion covered with the insulating layer before the insulating layer removing step), and at least part of the second portion is removed in the electroless plating layer removing step. be.

The laminate according to this embodiment may further include a protective layer (second insulating layer) that covers the electrode layer. The method for manufacturing a laminate according to this embodiment may include a protective layer forming step of forming a protective layer (second insulating layer) covering the electrode layer. The protective layer forming step can be performed before the electroless plated layer forming step and/or after the insulating layer removing step. The protective layer may cover the electrode layer while the protective layer is in contact with the electrode layer, and covers the electrode layer via a layer (for example, an electroless plated layer) disposed between the electrode layer and the protective layer. you can

The thickness of the electroless plating layer in the stacking direction of the electrode layer and the electroless plating layer may be within the following range. The thickness of the electroless plated layer may be 0.1 μm or more, 0.7 μm or more, or 1.0 μm from the viewpoint of facilitating power supply during electrolytic plating for forming metal bumps. or more, and may be 2.0 μm or more. The thickness of the electroless plated layer may be 5.0 μm or less, 2.0 μm or less, or 1.0 μm from the viewpoint of facilitating removal of the unnecessary electroless plated layer in the electroless plated layer removal step. or less, and may be 0.7 μm or less. From these points of view, the thickness of the electroless plated layer may be 0.1 to 5.0 μm.

The length (height) of the metal bump in the stacking direction of the electrode layer and the electroless plated layer may be within the following range. The length of the metal bump may be 10 μm or more, may exceed 10 μm, may be 50 μm or more, or may exceed 50 μm, from the viewpoint of easily securing a sufficient space for mounting the semiconductor element. may be 80 μm or greater, may be greater than 80 μm, may be 100 μm or greater, may be greater than 100 μm, may be 150 μm or greater, may be greater than 150 μm, may be 200 μm or greater, may be greater than 200 μm Well, it may be 250 μm or more. The length of the metal bump may be 500 μm or less, 250 μm or less, 200 μm or less, or 150 μm or less from the viewpoint of facilitating miniaturization, thinning, or high density of electronic components. It can be. From these points of view, the length of the metal bumps may be 10-500 μm. The metal bump length may be less than 40 μm.

The length (diameter) of the metal bump in the direction perpendicular to the stacking direction of the electrode layer and the electroless plated layer may be within the following range. The length of the metal bumps is 50 μm or more from the viewpoints of facilitating the formation of the metal bumps (for example, facilitating penetration of the plating solution, which will be described later, into the openings of the insulating layer) and from the viewpoint of facilitating the suppression of variations in the height of the metal bumps. may be greater than 50 μm may be 80 μm or greater may be greater than 80 μm may be 100 μm or greater may be greater than 100 μm may be 150 μm or greater may be greater than 150 μm 200 μm or more, may exceed 200 μm, or may be 250 μm or more. The length of the metal bumps may be 500 μm or less, or may be 250 μm or less, from the viewpoint of facilitating miniaturization or high density of electronic components because a plurality of metal bumps can be easily arranged at high density. It may be 200 μm or less. From these points of view, the length of the metal bumps may be 50-500 μm.

The length (thickness) of the insulating layer in the stacking direction of the electrode layer and the electroless plated layer and the length of the opening of the insulating layer may be within the following ranges. The length of the insulating layer and the opening may be 10 μm or more, may be more than 10 μm, may be 50 μm or more, or may be more than 50 μm, from the viewpoint of easily securing a sufficient space for mounting the semiconductor element. may be 80 μm or greater, may be greater than 80 μm, may be 100 μm or greater, may be greater than 100 μm, may be 150 μm or greater, may be greater than 150 μm, may be 200 μm or greater, may be 200 μm It may exceed, and may be 250 μm or more. The length of the insulating layer and the opening may be 500 μm or less, 250 μm or less, 200 μm or less, or 150 μm, from the viewpoint of facilitating miniaturization, thinning, or high density of electronic components. may be: From these points of view, the length of the insulating layer and the opening may be 10-500 μm. The length of the insulating layer and opening may be less than 40 μm.

The diameter of the opening of the insulating layer in the direction orthogonal to the stacking direction of the electrode layer and the electroless plated layer may be within the following range. The diameter of the opening may be 50 μm or more from the viewpoint of facilitating the formation of the opening (for example, facilitating infiltration of the developing solution described later) and facilitating the suppression of variations in the height of the metal bumps. may be 80 μm or greater, may be greater than 80 μm, may be 100 μm or greater, may be greater than 100 μm, may be 150 μm or greater, may be greater than 150 μm, may be 200 μm or greater, may be 200 μm It may exceed, and may be 250 μm or more. The diameter of the opening makes it easy to form the opening (easy to flatten the bottom surface of the opening), and it is easy to arrange a plurality of metal bumps at a high density, so it is easy to miniaturize or increase the density of electronic components. From a viewpoint, it may be 500 μm or less, may be 250 μm or less, or may be 200 μm or less. From these points of view, the diameter of the opening may be 50-500 μm.

Between the metal bump and the substrate, the electrode layer and the electroless plated layer do not have to be adjacent to each other in the direction perpendicular to the stacking direction of the electrode layer and the electroless plated layer. In this case, excellent adhesion between the electrode layer and the electroless plated layer is likely to be obtained. For example, in the method for manufacturing a laminate according to the present embodiment, an opening having a diameter equal to or smaller than that of the electrode layer is formed without arranging the electrode layer in the opening of the insulating layer. It can be obtained by forming an insulating layer having the insulating layer on the electrode layer. In this case, in the method for manufacturing a laminate according to the present embodiment, the first portion arranged at the formation position of the metal bump in the electroless plated layer and the position different from the formation position of the metal bump in the electroless plated layer The arranged second portions may be adjacent to each other on the electrode layer of the substrate in a direction orthogonal to the stacking direction of the electrode layer and the electroless plated layer.

Between the metal bump and the substrate, the electrode layer and the electroless plated layer may be adjacent to each other in a direction perpendicular to the stacking direction of the electrode layer and the electroless plated layer. In this case, it is easy to form an opening in the insulating layer through which the plated layer including the electroless plated layer is exposed. For example, in the method for manufacturing a laminate according to the present embodiment, the electrode layer is arranged in the opening of the insulating layer, and an insulating layer having an opening with a diameter larger than that of the electrode layer is formed on the base material. can be obtained by In this case, for example, the electrode layer and the electroless plated layer may be adjacent to each other in a direction orthogonal to the stacking direction of the electrode layer and the electroless plated layer on the surface of the base material at the positions where the metal bumps are formed. Further, for example, the first portion arranged at the formation position of the metal bump in the electroless plated layer and the second portion arranged at the position different from the formation position of the metal bump in the electroless plated layer are formed on the substrate. On the electrode layer, the electrode layer and the electroless plated layer may not be adjacent to each other in the direction perpendicular to the stacking direction.

An electronic component according to this embodiment includes the laminate according to this embodiment and a semiconductor element laminated (mounted) on the laminate. The method for manufacturing an electronic component according to this embodiment includes a semiconductor element lamination step of laminating (mounting) a semiconductor element on the laminate according to this embodiment. The semiconductor element is laminated at a position different from the formation position of the metal bumps on the substrate of the laminate. The metal bumps of the laminate in the electronic component according to this embodiment may be electrically connected to other semiconductor elements, module substrates, or electronic components.

Specific examples of the laminate, the electronic component, and the manufacturing method thereof according to the present embodiment will be described below.

1 to 4 are schematic cross-sectional views for explaining an example of a method for manufacturing a laminate. In the method for manufacturing the laminate, first, as shown in FIG. 1A, a substrate (base substrate) 10 having an electrode layer 12 on a main surface (surface) 10a is prepared in a substrate preparation step. The electrode layer 12 is, for example, a circuit pattern. The substrate 10 can be used as a substrate for obtaining a laminate for mounting a semiconductor element. As the substrate, for example, a wiring board (multilayer wiring board, etc.) can be used.

The electrode layer 12 is arranged on both surfaces (both main surfaces) of the substrate 10, but may be arranged on only one main surface. The substrate 10 has a multilayer (for example, two layers) insulating layer 14, but may have a single insulating layer. The substrate 10 has electrode layers 16 disposed between the insulating layers 14 . The electrode layer 16 is, for example, a circuit pattern. The base material 10 may have through electrodes 18 penetrating through the insulating layer 14 . Each of the two electrode layers 12 arranged at positions facing each other on both surfaces of the substrate 10 is connected to the electrode layer 16 via the through electrode 18, thereby electrically connecting these electrode layers 12 to each other. ing. Examples of materials constituting the electrode layer 12, the electrode layer 16, and the through electrode 18 include metal materials such as copper, aluminum, nickel, tin, gold, and silver. Copper can be used from the viewpoint of easily achieving high-speed signals due to its reduction. Examples of the constituent material of the insulating layer 14 include glass epoxy, glass polyimide, and the like. The thickness (total thickness) of the base material 10 is, for example, 15 to 1000 μm. The thickness of the electrode layer 12 is, for example, 3-50 μm. The thickness of the insulating layer 14 is, for example, 15-200 μm. The thickness of the electrode layer 16 is, for example, 3-50 μm.

Next, as shown in FIG. 1B, in the electroless plated layer forming step, the electrode layer 12 arranged on the main surface 10a of the substrate 10 is subjected to electroless plating (for example, electroless copper plating). An electroless plated layer 20 is formed. The electroless plated layer 20 can be used as a power supply layer when forming metal bumps 50 (see FIG. 3A), which will be described later. The electroless plated layer 20 is formed on all or part of the main surface of the base material 10 so as to function as a power supply layer when forming the metal bumps 50, and is formed on all or part of the electrode layer 12. good. The electroless plated layer 20 is formed on both surfaces of the substrate 10, but may be formed only on the main surface on which the metal bumps 50 are formed (upper side in FIG. 1(b)). The electroless plated layer 20 on the main surface on the side where the metal bumps 50 are formed is arranged at a position different from the first portion 20a arranged at the formation position of the metal bumps 50 and the formation position of the metal bumps 50. and a second portion 20b.

The electroless plated layer 20 can be obtained, for example, by immersing the base material 10 in an electroless plating solution after subjecting the base material 10 to a plating catalyst imparting treatment for adhering palladium. Examples of the constituent material of the electroless plated layer 20 include metal materials such as copper, nickel, tin, gold, and silver, and the excellent electrical conductivity reduces the connection resistance, thereby increasing the signal speed. Copper can be used from the viewpoint of easy achievement. The constituent materials of the electroless plated layer 20 and the electrode layer 12 may be the same as each other.

Next, as shown in FIG. 2, in the insulating layer forming step, an opening (through hole) is formed in the insulator 30 placed on the base material 10 to form an insulating layer 32 having an opening (through hole) 32a. obtain. Examples of methods for forming an opening in the insulator 30 include a method of exposing and developing a photosensitive (photocurable) resin composition, a method of physically removing with a laser, a drill, or the like. Polyimide etc. are mentioned as a constituent material of the photosensitive resin composition. When a photosensitive resin composition is used, the insulating layer forming step has an insulator forming step, an exposure step, and a developing step in this order.

In the insulator forming step, as shown in FIG. 2A, an insulator 30 is formed on the base material 10 . The insulator 30 is formed by transferring the insulator 30 preliminarily formed on a support (not shown) onto the substrate 10, applying and drying a photosensitive resin composition on the substrate 10, and the like. can do. The thickness of the insulator 30 may be adjusted to a desired range by transferring the insulator 30 onto the substrate 10 multiple times.

In the exposure step, the insulator 30 is exposed and cured. When a positive photosensitive resin composition is used, a portion of the insulator 30 other than the positions where the openings are formed is exposed and cured. When a negative photosensitive resin composition is used, the portion of the insulator 30 where the opening is to be formed is exposed and cured. As the exposure method, a method of curing only a desired portion by irradiating light with a mask placed on the insulator 30; a method of curing only a desired portion by irradiating patterned light (projection exposure); method, contact exposure method, direct writing exposure method, etc.). The wavelength of light is, for example, 350-450 nm. The irradiation energy of light is, for example, 50 to 3000 mJ/cm ² .

In the developing step, the exposed insulator 30 is developed to obtain an insulating layer 32 having openings 32a, as shown in FIG. 2(b). In the development step, the exposed area in the case of using a positive photosensitive resin composition or the unexposed area in the case of using a negative photosensitive resin composition is removed. Examples of the developing method include a method using a developing solution containing an alkaline aqueous solution (sodium carbonate aqueous solution, etc.) and an organic solvent (cyclopentanone, γ-butyrolactone, mesitylene, etc.).

The substrate 40 is obtained by such an insulating layer forming process. The substrate 40 includes a substrate 10 having an electrode layer 12 on its main surface 10a, an electroless plated layer 20 disposed at least on the electrode layer 12, and an electroless plated layer 20 disposed on the substrate 10. and an insulating layer 32 having an opening 32a through which (the plated layer made of the electroless plated layer 20) is exposed. The insulating layer 32 can be used as a plating resist in the bump forming process. The insulating layer 32 covers the second portion 20b arranged at a position different from the formation position of the metal bump 50 in the electroless plated layer 20. As shown in FIG. In the substrate 40 , the insulating layer 32 having openings 32 a with a diameter smaller than that of the electrode layer 12 is formed on the electrode layer 12 without placing the electrode layer 12 in the openings 32 a of the insulating layer 32 . Moreover, the first portion 20a arranged at the formation position of the metal bump 50 in the electroless plated layer 20 and the second portion 20b arranged at a position different from the formation position of the metal bump 50 in the electroless plated layer 20. are adjacent to each other on the electrode layer 12 of the substrate 40 in a direction orthogonal to the stacking direction of the electrode layer 12 and the electroless plated layer 20 .

Next, as shown in FIG. 3A, in the bump forming step, electrolytic plating (for example, electrolytic copper plating) is applied to the openings 32a of the insulating layer 32 in the substrate 40 to form metal bumps in contact with the electroless plating layer 20. (Electroplated layer, conductor post) 50 is formed in the opening 32a. As a result, a laminate 60a including the substrate 10, the electroless plated layer 20, the insulating layer 32, and the metal bumps 50 is obtained. The metal bumps 50 are filled in the openings 32a. The cross-sectional shape of the metal bumps 50 and the openings 32a perpendicular to the stacking direction of the electrode layers 12 and the electroless plated layers 20 may be circular, polygonal (for example, rectangular), or the like. Examples of materials for forming the metal bumps 50 include metal materials such as copper, nickel, tin, gold, and silver, which have excellent electrical conductivity and reduce connection resistance, thereby achieving high speed signals. Copper can be used from the viewpoint that it is easy to mount and a narrow pitch is easily achieved in flip-chip mounting. The constituent materials of the metal bumps 50 and the electroless plated layer 20 may be the same as each other. Examples of the electrolytic plating method include methods using a copper sulfate plating solution, a copper pyrophosphate plating solution, an electrolytic nickel plating solution, and the like.

After the bump forming process, the metal bumps 50 may be pressed in the length direction of the metal bumps 50 . Further, a polishing step for polishing the surface of the laminate 60a (the surface of the insulating layer 32 and the tips of the metal bumps 50) may be performed between the bump forming step and the subsequent insulating layer removing step. With these, the length of the metal bump 50 can be adjusted.

Next, as shown in FIG. 3B, the insulating layer 32 is removed in an insulating layer removing step to obtain a laminate 60b. As a result, all or part of the insulating layer 32 is removed to expose the second portions 20b arranged at positions different from the formation positions of the metal bumps 50 in the electroless plated layer 20 . Thereby, for example, the metal bumps 50 that are not in contact with the insulating layer (the entire insulating layer including the insulating layer 32) can be obtained. The insulating layer 32 can be removed, for example, with a sodium hydroxide solution. From the viewpoint of suppressing the residue of the insulating layer 32 from remaining, desmear treatment or plasma treatment may be performed after the insulating layer removing step.

Next, as shown in FIG. 4A, in the electroless plating layer removing step (plating layer removing step), the electroless plating layer 20 on the side where the metal bumps 50 are formed (upper side in FIG. 4A) is removed. By removing at least a part of the second portion 20b arranged at a position different from the formation position of the metal bump 50 in 1, a laminated body 60c is obtained. As a result, the electrode layer 12 covered with the electroless plated layer 20 is exposed. The second portion 20b of the electroless plated layer 20 can be removed by etching. From the viewpoint of removing the catalyst (for example, palladium) applied to the electrode layer 12 during the formation of the electroless plating layer 20 to improve insulation reliability, a catalyst removal treatment may be performed after the etching treatment. In the electroless plated layer removing step, the second portion 20b of the electroless plated layer 20 can be entirely or partially removed. In the electroless plated layer removing step, the electroless plated layer 20 on the side opposite to the side on which the metal bumps 50 are formed (lower side in FIG. 4A) is removed. It does not have to be removed.

Next, as shown in FIG. 4B, a protective layer (second insulating layer, resist) 70 covering at least a portion of the electrode layer 12 is formed in a protective layer forming step. As a constituent material of the protective layer 70, it is possible to use an insulating material, such as a solder resist material containing an epoxy resin as a main component. The protective layer 70 can be formed, for example, by electrostatic deposition. After the electrode layer 12 covered with the electroless plating layer 20 is exposed in the electroless plating layer removing step, the metal layer 72 may be formed on the surface of the electrode layer 12 . A metal layer 74 may be formed on the surface of the metal bump 50 after the insulating layer removing step. The metal layers 72, 74 can be formed by nickel-gold plating, for example. 60 d of laminated bodies are obtained by such a protective layer formation process.

Then, in the semiconductor element stacking step, an electronic component is obtained by stacking (for example, flip-chip mounting) a semiconductor element on the laminate 60d.

According to the method of manufacturing the laminate according to the present embodiment, the electroless plated layer 20 can be used as the power supply layer for forming the metal bumps 50 . Then, when it is necessary to remove the power supply layer from the viewpoint of suppressing noise generation after forming the metal bump 50, the second portion 20b of the electroless plated layer 20, which is a relatively thin layer, can be easily removed. Therefore, it is possible to easily obtain the laminates 60a to 60d on which semiconductor elements can be mounted. Further, according to the method of manufacturing the laminate according to the present embodiment, the laminate can be mounted with a semiconductor element without forming the power supply layer after forming the insulating layer 32 on the base material 10. It is possible to suppress complication of the manufacturing process of 60a to 60d. Furthermore, in the laminated bodies 60a to 60d obtained by the laminated body manufacturing method according to the present embodiment, semiconductor elements can be embedded (three-dimensionally mounted) at positions different from the formation positions of the metal bumps 50 on the substrate 10. In addition, since it is possible to connect to other semiconductor elements, module substrates, or electronic parts through the metal bumps 50, it is possible to achieve miniaturization, thinning, or high density of electronic parts equipped with semiconductor elements. can.

By the way, as a method of forming metal bumps on a base material, after depositing a metal layer on the base material, unnecessary portions of the metal layer are removed by etching or the like while a mask is placed on the positions where the metal bumps are to be formed. We can think of a way to do this. However, in such a method, the side portion of the metal bump is excessively etched to form a tapered portion in the metal bump, so that the diameter of the metal bump is not uniform along the length direction of the metal bump. Sometimes. On the other hand, according to the method of manufacturing the laminate according to the present embodiment, by forming the metal bumps 50 in the openings 32a of the insulating layer 32, the metal bumps 50 having the same shape as the openings 32a can be easily obtained. , and the diameter of the metal bumps 50 can be easily made uniform along the length direction of the metal bumps 50 .

Although examples of embodiments of the laminate, the electronic component, and the manufacturing method thereof have been described above, the present invention is not limited to the above-described embodiments.

For example, in the above-described embodiments, the electroless plated layer removing step is performed between the insulating layer removing step and the protective layer forming step. A protective layer forming step may be performed later. As shown in FIG. 5, in the laminated body 60e obtained in this case, the protective layer 70 is arranged on the electrode layer 12 and the electroless plated layer 20 unlike the laminated body 60d of FIG. 4(b). The protective layer 70 indirectly covers the electrode layer 12 via the electroless plated layer 20 .

Further, in the above-described embodiment, the protective layer forming step for forming the protective layer 70 is performed after the electroless plated layer forming step, but the protective layer forming step is performed before the electroless plated layer forming step. good too. In this case, first, after the base material 10 is prepared in the base material preparation step, a protective layer 70 that covers at least a portion of the electrode layer 12 is formed as shown in FIG. 6(a). The protective layer 70 covers, for example, the end portion of the electrode layer 12 (the electrode layer on the right end in FIG. 6A) arranged at the formation position of the metal bump 50 .

Next, as shown in FIG. 6B, in the electroless plated layer forming step, the electrode layer 12 and the protective layer 70 arranged on the main surface 10a of the substrate 10 are subjected to electroless plating to form electroless plating. A layer 20 is formed. Thereby, the electroless plated layer 20 covering the electrode layer 12 and the protective layer 70 is formed. The electroless plated layer 20 has a first portion 20a arranged at the formation position of the metal bump 50 and a second portion 20b arranged at a position different from the formation position of the metal bump 50. .

Next, as shown in FIG. 7A, in the insulating layer forming step, an opening is formed in the insulator placed on the substrate 10 to obtain the insulating layer 32 having the opening 32a. Thereby, the substrate 10 having the electrode layer 12 on the main surface 10a, the electroless plated layer 20 disposed at least on the electrode layer 12, and the electroless plated layer 20 ( and the insulating layer 32 having the opening 32a through which the plated layer composed of the electroless plated layer 20 is exposed.

Next, in the bump forming step, electroplating is applied inside the openings 32a of the insulating layer 32 in the substrate 40a to form the metal bumps 50 in contact with the electroless plating layer 20 inside the openings 32a. As shown, the laminate 60f is obtained by removing the insulating layer 32 in the insulating layer removing step. When a semiconductor element is laminated on the laminate 60f to obtain an electronic component, the second portion 20b of the electroless plated layer 20 may be removed in the electroless plated layer removing step, and the second portion 20b may be removed. It doesn't have to be.

Furthermore, in the above-described embodiment, the electrode layer 12 and the electroless plated layer 20 are adjacent to each other in the direction orthogonal to the stacking direction of the electrode layer 12 and the electroless plated layer 20 between the metal bump 50 and the base material 10. Although not shown, for example, the electrode layer 12 and the electroless plated layer 20 are formed between the metal bump 50 and the substrate 10, such as a laminate 60g shown in FIG. 8, which is an enlarged view of the metal bump 50 and its surroundings. The electrode layers 12 and the electroless plated layers 20 may be adjacent to each other in a direction orthogonal to the stacking direction. In the laminate 60g, the electrode layer 12 is arranged in the opening 32a of the insulating layer 32, and the insulating layer 32 having the opening 32a with a larger diameter than the electrode layer 12 is formed on the base material 10. As shown in FIG. In this case, the electrode layer 12 and the electroless plated layer 20 are adjacent to each other in the direction orthogonal to the stacking direction of the electrode layer 12 and the electroless plated layer 20 on the main surface 10a of the base material 10 at the position where the metal bumps 50 are formed. there is In addition, in the laminate 60g, the first portion 20a arranged at the formation position of the metal bump 50 on the electroless plating layer 20 and the first portion 20a arranged at a position different from the formation position of the metal bump 50 on the electroless plating layer 20 The second portions 20b are not adjacent to each other on the electrode layer 12 in the direction perpendicular to the stacking direction of the electrode layer 12 and the electroless plated layer 20 .

Further, in the above-described embodiment, the metal bumps 50 are formed in contact with the electroless plating layer 20 exposed from the openings 32a of the insulating layer 32 by using the plating layer made of the electroless plating layer 20. , an electroless plating layer, and an electroplating layer disposed on the electroless plating layer, forming a metal bump in contact with the electroplating layer (the outermost layer of the plating layer) exposed from the opening of the insulating layer. may

Also, the metal bumps may be formed on both sides of the laminate. The laminate may have a plurality of metal bumps on one or both major surfaces. The electronic component may include a plurality of semiconductor elements.

DESCRIPTION OF SYMBOLS 10... Base material 10a... Main surface (surface) 12... Electrode layer 20... Electroless plating layer 32... Insulating layer 32a... Openings 40, 40a... Substrate 50... Metal bumps 60a, 60b, 60c , 60d, 60e, 60f, 60g... laminate, 70... protective layer.

Claims (16)

A base material having an electrode layer on its surface, an electroless plated layer disposed on at least the electrode layer, and an opening exposing the plated layer including the electroless plated layer disposed on the base material. a bump forming step of electroplating a substrate having an insulating layer having a metal bump in contact with the plating layer ,
A method for manufacturing a laminate , wherein the electrode layer and the electroless plated layer are adjacent to each other in a direction perpendicular to the stacking direction of the electrode layer and the electroless plated layer between the metal bump and the base material. . 2. The method of manufacturing a laminate according to claim 1, further comprising a step of forming openings in an insulator placed on said substrate to obtain said insulating layer before said bump forming step. 3. The method of manufacturing a laminate according to claim 1, further comprising an electroless plated layer forming step of forming the electroless plated layer by applying electroless plating to the electrode layer before the bump forming step. . 4. The method of manufacturing a laminate according to claim 3, further comprising the step of forming a protective layer having openings through which the electrode layer is exposed on the substrate before the electroless plating layer forming step. 5. The method for manufacturing a laminate according to claim 1, further comprising an insulating layer removing step of removing said insulating layer after said bump forming step. 6. The method of manufacturing a laminate according to claim 5, further comprising a step of removing a portion of said electroless plated layer located at a position different from a position where said metal bump is formed, after said insulating layer removing step. 7. The method of manufacturing a laminate according to claim 5, further comprising the step of forming a protective layer covering said electrode layer after said insulating layer removing step. The method for manufacturing a laminate according to any one of claims 1 to 7, wherein the electroless plated layer is exposed from the opening of the insulating layer. The method for producing a laminate according to any one of claims 1 to 8, wherein the electrode layer is a circuit pattern. 10. The method for producing a laminate according to claim 1, wherein the metal bump has a length of 10 μm or more in the lamination direction of the electrode layer and the electroless plated layer. The method for producing a laminate according to any one of claims 1 to 9, wherein the length of the metal bump in the lamination direction of the electrode layer and the electroless plated layer exceeds 150 µm. a substrate having an electrode layer on its surface;
an electroless plated layer disposed on at least the electrode layer;
a metal bump on the electroless plating layer and in contact with the plating layer including the electroless plating layer ;
A laminate, wherein the electrode layer and the electroless plated layer are adjacent to each other in a direction orthogonal to the stacking direction of the electrode layer and the electroless plated layer between the metal bump and the substrate. 13. The laminate according to claim 12 , wherein said metal bump contacts said electroless plated layer. 14. The laminate according to claim 12 or 13 , wherein said electrode layer is a circuit pattern. The laminate according to any one of claims 12 to 14 , wherein the metal bump has a length of 10 µm or more in the lamination direction of the electrode layer and the electroless plated layer. 15. The laminate according to any one of claims 12 to 14 , wherein the length of the metal bump in the lamination direction of the electrode layer and the electroless plated layer exceeds 150 µm.

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