JP7120256B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7120256B2 JP7120256B2 JP2019567886A JP2019567886A JP7120256B2 JP 7120256 B2 JP7120256 B2 JP 7120256B2 JP 2019567886 A JP2019567886 A JP 2019567886A JP 2019567886 A JP2019567886 A JP 2019567886A JP 7120256 B2 JP7120256 B2 JP 7120256B2
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- 239000004065 semiconductor Substances 0.000 title claims description 106
- 229910052751 metal Inorganic materials 0.000 claims description 109
- 239000002184 metal Substances 0.000 claims description 109
- 239000000463 material Substances 0.000 claims description 86
- 239000003566 sealing material Substances 0.000 claims description 21
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000000470 constituent Substances 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 239000008393 encapsulating agent Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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Description
最初に本開示の技術の実施態様を列記して説明する。本開示の半導体装置は、ベース板と、ベース板上に配置される金属板と、ベース板と金属板との間に配置され、ベース板、および金属板と面で接触して金属板をベース板に接合する接合材と、金属板上に配置される絶縁板と、絶縁板と面で接触して絶縁板上に配置される回路部材と、回路部材上に搭載される半導体素子と、金属板、接合材、絶縁板、回路部材、および半導体素子を覆って、ベース板上の空間を封止する封止材とを備える。金属板の外縁に沿った金属板の底面領域は、接合材に覆われてない。ベース板には、金属板の外縁に沿って配置され上記底面領域に対向する溝形状の第一凹部と、金属板の外縁に対して内側に向かう方向を内方側としたときに第一凹部と離隔して第一凹部よりも内方側に配置される溝形状の第二凹部とが設けられている。第二凹部の少なくとも一部には、接合材が配置されている。
次に、本開示の技術の一実施形態に係る半導体装置を、以下に図面を参照しつつ説明する。なお、以下の図面において同一または相当する部分には同一の参照符号を付しその説明は繰り返さない。
図1は、一実施形態に係る半導体装置の構成を示す概略断面図である。図2は、図1に示す半導体装置に備えられるベース板をベース板の板厚方向に見た平面視における状態を示す図である。図3は、図1に示す半導体装置の一部を拡大して示す断面図である。なお、図3は、図1に示す半導体装置において、封止材等を取り除いた状態を示している。図1、および図3は、半導体装置をベース板の板厚方向に沿って切断した断面に相当する。また、図2は、ベース板の板厚方向に見た図であり、図1に示す矢印IIで示す方向から見た場合に相当する。なお、理解の容易の観点から、図2中において、金属板の外縁を一点鎖線で示している。
なお、上記の実施の形態においては、第二凹部51は、ループ状に連なって設けられていることとしたが、これに限らず、第二凹部51は、以下の構成としてもよい。図4は、他の実施形態に係る半導体装置に備えられるベース板の構成を示す図である。
12,61 ベース板
13 金属板
14,17 接合材
15 絶縁板
16 回路部材
18,19 半導体素子
20 領域
21 封止材
22,23 端子
24 外枠
25,26,27 外縁
28 領域
31,32,33,34,35,36,37,62 面
38,39 ボンディングワイヤ
41,63 第一凹部
42,43,52,53 側壁面
44,54 底壁面
45,46 端部
47 部分
51,64 第二凹部
Claims (12)
- ベース板と、
前記ベース板上に配置される金属板と、
前記ベース板と前記金属板との間に配置され、前記ベース板、および前記金属板と面で接触して前記金属板を前記ベース板に接合する接合材と、
前記金属板上に配置される絶縁板と、
前記絶縁板と面で接触して前記絶縁板上に配置される回路部材と、
前記回路部材上に搭載される半導体素子と、
前記金属板、前記接合材、前記絶縁板、前記回路部材、および前記半導体素子を覆って、前記ベース板上の空間を封止する封止材とを備え、
前記金属板の外縁に沿った前記金属板の底面領域は、前記接合材に覆われてなく、
前記ベース板には、前記金属板の前記外縁に沿って配置され前記底面領域に対向する溝形状の第一凹部と、前記金属板の前記外縁に対して内側に向かう方向を内方側としたときに前記第一凹部と離隔して前記第一凹部よりも内方側に配置される溝形状の第二凹部とが設けられており、
前記第二凹部の少なくとも一部には、前記接合材が配置されており、
前記第二凹部は、前記ベース板の板厚方向に見た平面視において前記半導体素子とは離れている、半導体装置。 - 前記第二凹部は、前記ベース板の板厚方向に見た平面視において前記半導体素子よりも前記金属板の前記外縁に近い位置に設けられている、請求項1に記載の半導体装置。
- ベース板と、
前記ベース板上に配置される金属板と、
前記ベース板と前記金属板との間に配置され、前記ベース板、および前記金属板と面で接触して前記金属板を前記ベース板に接合する接合材と、
前記金属板上に配置される絶縁板と、
前記絶縁板と面で接触して前記絶縁板上に配置される回路部材と、
前記回路部材上に搭載される半導体素子と、
前記金属板、前記接合材、前記絶縁板、前記回路部材、および前記半導体素子を覆って、前記ベース板上の空間を封止する封止材とを備え、
前記金属板の外縁に沿った前記金属板の底面領域は、前記接合材に覆われてなく、
前記ベース板には、前記金属板の前記外縁に沿って配置され前記底面領域に対向する溝形状の第一凹部と、前記金属板の前記外縁に対して内側に向かう方向を内方側としたときに前記第一凹部と離隔して前記第一凹部よりも内方側に配置される溝形状の第二凹部とが設けられており、
前記第二凹部の少なくとも一部には、前記接合材が配置されており、
前記ベース板の板厚方向に見た平面視における前記半導体素子と前記第二凹部との最短距離は、前記ベース板の板厚方向における前記回路部材の上面から前記ベース板の上面までの距離よりも大きい、半導体装置。 - 前記ベース板の上面と前記第二凹部の側壁面とは、鈍角で接続される、請求項1から請求項3のいずれか1項に記載の半導体装置。
- 前記第二凹部は、上端に近づくに従って幅が大きくなる、請求項1から請求項4のいずれか1項に記載の半導体装置。
- 前記第二凹部の凹み量は、前記接合材の厚み以下である、請求項1から請求項5のいずれか1項に記載の半導体装置。
- 前記第二凹部は、前記ベース板の板厚方向に見た平面視においてループ状に連なって設けられている、請求項1から請求項6のいずれか1項に記載の半導体装置。
- 前記第二凹部は、前記金属板の前記外縁に沿う周方向に間隔をあけて複数設けられている、請求項1から請求項6のいずれか1項に記載の半導体装置。
- 前記第一凹部は、前記ベース板の板厚方向に見た平面視においてループ状に連なって設けられている、請求項1から請求項8のいずれか1項に記載の半導体装置。
- ベース板と、
前記ベース板上に配置される金属板と、
前記ベース板と前記金属板との間に配置され、前記ベース板、および前記金属板と面で接触して前記金属板を前記ベース板に接合する接合材と、
前記金属板上に配置される絶縁板と、
前記絶縁板と面で接触して前記絶縁板上に配置される回路部材と、
前記回路部材上に搭載される半導体素子と、
前記金属板、前記接合材、前記絶縁板、前記回路部材、および前記半導体素子を覆って、前記ベース板上の空間を封止する封止材とを備え、
前記金属板の外縁に沿った前記金属板の底面領域は、前記接合材に覆われてなく、
前記ベース板には、前記金属板の前記外縁に沿って配置され前記底面領域に対向する溝形状の第一凹部と、前記金属板の前記外縁に対して内側に向かう方向を内方側としたときに前記第一凹部と離隔して前記第一凹部よりも内方側に配置される溝形状の第二凹部とが設けられており、
前記第二凹部の少なくとも一部には、前記接合材が配置されており、
前記ベース板の上面と前記第二凹部の側壁面とは、鈍角で接続され、
前記第二凹部は、上端に近づくに従って幅が大きくなり、
前記第二凹部の凹み量は、前記接合材の厚み以下であり、
前記第二凹部は、前記ベース板の板厚方向に見た平面視において前記半導体素子とは離れており、
前記第二凹部は、前記ベース板の板厚方向に見た平面視において前記半導体素子よりも前記金属板の前記外縁に近い位置に設けられており、
前記ベース板の板厚方向に見た平面視における前記半導体素子と前記第二凹部との最短距離は、前記ベース板の板厚方向における前記回路部材の上面から前記ベース板の上面までの距離よりも大きく、
前記第一凹部は、前記ベース板の板厚方向に見た平面視においてループ状に連なって設けられている、半導体装置。 - 前記第二凹部は、前記ベース板の板厚方向に見た平面視においてループ状に連なって設けられている、請求項10に記載の半導体装置。
- 前記第二凹部は、前記金属板の前記外縁に沿う周方向に間隔をあけて複数設けられている、請求項10に記載の半導体装置。
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