JP7103145B2 - Semiconductor devices, manufacturing methods for semiconductor devices, power supplies and amplifiers - Google Patents

Description

The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, a power supply device, and an amplifier.

Nitride semiconductors are being studied for application to semiconductor devices with high withstand voltage and high output by utilizing features such as high saturated electron velocity and wide band gap. For example, the bandgap of GaN, which is a nitride semiconductor, is 3.4 eV, which is larger than the bandgap of Si (1.1 eV) and the bandgap of GaAs (1.4 eV), and has a high fracture electric field strength. Therefore, nitride semiconductors such as GaN are extremely promising as materials for semiconductor devices for power supplies that obtain high voltage operation and high output.

As a semiconductor device using a nitride semiconductor, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). For example, in a GaN-based HEMT (GaN-HEMT), a HEMT made of AlGaN / GaN using GaN as an electron traveling layer and AlGaN as an electron supply layer is drawing attention. In HEMT made of AlGaN / GaN, distortion due to the difference in lattice constant between GaN and AlGaN occurs in AlGaN. A high concentration of 2DEG (Two-Dimensional Electron Gas) can be obtained by the piezo polarization and the spontaneous polarization difference of AlGaN generated thereby. Therefore, it is expected as a high-efficiency switch element, a high-voltage power device for electric vehicles, and the like.

JP-A-2002-359256 JP-A-2007-35898 Japanese Unexamined Patent Publication No. 2008-16682

In the semiconductor device using the nitride semiconductor described above, there is a demand for a semiconductor device having good high frequency characteristics and a low leakage current at the time of pinch-off.

According to one aspect of the present embodiment, the semiconductor device is formed of a first semiconductor layer formed of a nitride semiconductor on a substrate and a nitride semiconductor on the first semiconductor layer. It also has a second semiconductor layer, a gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer, and the gate electrode has an Au layer and a Ni layer. The Au layer and the Ni layer in the gate electrode are both in contact with the second semiconductor layer, and the length of the region in the gate length of the gate electrode where the Ni layer and the second semiconductor layer are in contact with each other. Is longer than the length of the region in contact with the Au layer and the second semiconductor layer .

According to the disclosed semiconductor device, in the semiconductor device using the nitride semiconductor, the high frequency characteristics are good, and the leakage current at the time of pinch-off can be lowered.

Structural diagram of semiconductor device Explanatory drawing of the semiconductor device shown in FIG. Explanatory drawing of characteristics of semiconductor device shown in FIG. Structural diagram of the semiconductor device according to the first embodiment Explanatory drawing of semiconductor device in 1st Embodiment (1) Explanatory drawing (2) of semiconductor device in 1st Embodiment Explanatory drawing (3) of semiconductor device in 1st Embodiment Structural diagram of a modified example of the semiconductor device according to the first embodiment (1) Structural diagram of a modified example of the semiconductor device according to the first embodiment (2) Process diagram of the method for manufacturing a semiconductor device according to the first embodiment (1) Process diagram of the method for manufacturing a semiconductor device according to the first embodiment (2) Process diagram of the method for manufacturing a semiconductor device according to the first embodiment (3) Process diagram (4) of the method for manufacturing a semiconductor device according to the first embodiment. Process diagram (5) of the method for manufacturing a semiconductor device according to the first embodiment. Process diagram (6) of the method for manufacturing a semiconductor device according to the first embodiment. Process diagram (7) of the method for manufacturing a semiconductor device according to the first embodiment. Process diagram (8) of the method for manufacturing a semiconductor device according to the first embodiment. Explanatory drawing of discretely packaged semiconductor device in 2nd Embodiment Circuit diagram of the power supply device according to the second embodiment Structural diagram of the high power amplifier according to the second embodiment

The embodiment for carrying out will be described below. The same members and the like are designated by the same reference numerals and the description thereof will be omitted.

[First Embodiment]
First, as a semiconductor device using a nitride semiconductor, a field effect transistor using a nitride semiconductor will be described with reference to FIG. The field-effect transistor shown in FIG. 1 is a HEMT, and a nucleation layer (not shown), a buffer layer 911, an electron traveling layer 921, and an electron supply layer 922 are laminated in this order on a substrate 910. A gate electrode 941, a source electrode 942, and a drain electrode 943 are formed on the electron supply layer 922, and an insulating film 930 serving as a protective film is formed so as to cover the exposed electron supply layer 922. There is.

In the field effect transistor which is the semiconductor device shown in FIG. 1, a SiC substrate is used for the substrate 910, and a nucleation layer (not shown) is formed of AlN or the like. The buffer layer 911 is made of AlGaN or the like. The electron traveling layer 921 is formed of GaN, and the electron supply layer 922 is formed of AlGaN, whereby the electron traveling layer 921 in the vicinity of the interface between the electron traveling layer 921 and the electron supply layer 922 is formed. 2DEG921a is produced. The insulating film 930 is formed of SiN or the like. The gate electrode 941 is formed of a metal laminated film of a lower Ni (nickel) layer 941a and an upper Au (gold) layer 941b, and the Ni layer 941a is in contact with the electron supply layer 922.

In such a field-effect transistor having the structure shown in FIG. 1, good high-frequency characteristics can be obtained by shortening the gate length Lg, which is the length of the gate electrode 941 between the source and the drain. By the way, in the field effect transistor which is the semiconductor device shown in FIG. 1, when an off gate voltage is applied to the gate electrode 941, as shown in FIG. 2, an electron supply layer is formed from the interface with the gate electrode 941. A depletion layer spreads over a part of 922 and the electron traveling layer 921. However, if the gate length Lg of the gate electrode 941 is shortened, the spread of such a depletion layer is also reduced, and the leak current flowing during pinch-off indicated by the broken line arrow is increased, which is not preferable.

FIG. 3 shows the characteristics of the field-effect transistor having the structure shown in FIG. 1 and shows the relationship between the gate length Lg of the gate electrode 941 at a gate voltage Vg of -3V and a drain voltage Vd of 20V and the leakage current at the time of pinch-off. .. As shown in FIG. 3, when the gate length Lg of the gate electrode 941 is shortened from 0.50 μm to 0.25 μm, the leakage current at the time of pinch-off increases. This is because when the gate length Lg of the gate electrode 941 is shortened, the spread of the depletion layer 925 when an off gate voltage is applied to the gate electrode 941 becomes smaller, so that the leakage current flowing around the depletion layer 925 increases. It is thought that this is to be done.

Therefore, in a semiconductor device using a nitride semiconductor, it is required that a good high frequency characteristic can be obtained and a leakage current flowing at the time of pinch-off is small.

(Semiconductor device)
Next, the semiconductor device according to the first embodiment will be described. As shown in FIG. 4, the semiconductor device according to the present embodiment is HEMT, and a nucleation layer (not shown), a buffer layer 11, an electron traveling layer 21, and an electron supply layer 22 are laminated in this order on a substrate 10. Is formed. A gate electrode 41, a source electrode 42, and a drain electrode 43 are formed on the electron supply layer 22, and an insulating film 30 serving as a protective film is formed so as to cover the exposed electron supply layer 22. There is. In the present application, the electron traveling layer 21 may be described as the first semiconductor layer, and the electron supply layer 22 may be described as the second semiconductor layer.

In the semiconductor device of the present embodiment, a SiC substrate is used as the substrate 10, and a nucleation layer (not shown) is formed of AlN or the like. The buffer layer 11 is made of AlGaN or the like. The electron traveling layer 21 is formed of GaN, and the electron supply layer 22 is formed of AlGaN, whereby the electron traveling layer 21 in the vicinity of the interface between the electron traveling layer 21 and the electron supply layer 22 is formed. 2DEG21a is generated. The insulating film 30 is formed of SiN or the like. The gate electrode 41 has an Au layer 41a formed on the drain electrode 43 side on the electron supply layer 22, and a Ni layer 41b formed on the source electrode 42 side, and further, an Au layer is formed on the Au layer 41b. 41c is formed. Therefore, the Au layer 41a of the gate electrode 41 is in contact with the drain electrode 43 side, and the Ni layer 41b is in contact with the electron supply layer 22 on the source electrode 42 side.

FIG. 5 shows the gate threshold voltage Vth in the vicinity of the gate electrode 41 and the gate electrode 41 in the semiconductor device according to the present embodiment. The gate electrode 41 and the electron supply layer 22 are Schottky connected, and the gate threshold voltage Vth changes depending on the value of the work function of the material in contact with the electron supply layer 22. Therefore, the gate threshold value Vth is −1.3 V in the region in contact with the Au layer 41a of the gate electrode 41, whereas the gate is in contact with the Ni layer 41b of the gate electrode 41. The threshold value Vth is -1.1V. The work function of Au is 4.70 eV, whereas the work function of Ni is 5.2 eV, and the gate threshold value Vth differs depending on the difference in the value of this work function.

Therefore, as shown in FIG. 6, the depletion layer 25 extends deeper on the Ni layer 41b side than on the Au layer 41a side. The region 25a shown by the broken line in FIG. 6 shows the spread of the depletion layer in the semiconductor device having the structure shown in FIG. When the voltage applied to the gate electrode is the same, the area where the depletion layer spreads is the same. Therefore, in the semiconductor device of the present embodiment, the depletion layer 25 is larger than the region 25a shown by the broken line. It spreads deeply. This makes it possible to reduce the leakage current at the time of pinch-off.

As a result, in the semiconductor device of the present embodiment, as shown in 7A of FIG. 7, even if the gate length Lg is shortened to 0.25 μm, it is possible to suppress an increase in the leakage current at the time of pinch-off. 7B and 7C in FIG. 7 show the relationship between the gate length Lg in the semiconductor device having the structure shown in FIG. 1 and the leak current at the time of pinch-off. This is the case of 0.50 μm, which is the same as that shown in FIG.

In the semiconductor device of the present embodiment, as shown in FIG. 5, the length Lga of the region of the Au layer 41a in contact with the electron supply layer 22 in the gate length Lg of the gate electrode 41 is larger than that of the Ni layer 41b. It is preferable that the length of the region Lgb is long. In the region where the electron supply layer 22 and the Au layer are in contact with each other, the leakage current is larger than in the region where the electron supply layer 22 and the Ni layer are in contact with each other. Because it can be done. In the semiconductor device of the present embodiment, the gate electrode 41 may be formed by a Pd layer instead of the Au layer 41a.

Further, in the semiconductor device of the present embodiment, as shown in FIG. 8, the gate electrode 41 may be formed by the Au layer 41a and the Ni layer 41b. Also in this case, the Au layer 41a is formed on the drain electrode 43 side, and the Ni layer 41b is formed on the source electrode 42 side. This is because the voltage on the drain electrode 43 side is high and a high electric field is likely to be applied to the drain electrode 43 side. A structure in which the positions of the Au layer 41a and the Ni layer 41b are reversed, or a structure in which the Ni layer is provided in the center of the gate electrode 41 and the Au layer is provided on both the source electrode 42 side and the drain electrode 43 side. Can also be considered.

Further, as shown in FIG. 9, the semiconductor device according to the present embodiment may have a cap layer 23 formed on the electron supply layer 22. In this case, the cap layer 23 is formed of GaN having a thickness of 5 nm, the insulating film 30 and the gate electrode 41 are formed on the cap layer 23, and the source electrode 42 and the drain electrode 43 are cap layers. 23 is formed on the removed electron supply layer 22.

Further, in the semiconductor device of the present embodiment, the electron supply layer 22 may be formed of InAlN or InAlGaN.

(Manufacturing method of semiconductor devices)
Next, the method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 10A to 13B. The nitride semiconductor layer formed on the substrate 10 is formed by epitaxial growth by MOVPE (Metal-Organic Vapor Phase Epitaxy). When the nitride semiconductor layer is grown by MOVPE, TMA (trimethylaluminum) is used as the raw material gas of Al, TMG (trimethylgallium) is used as the raw material gas of Ga, and NH is used as the raw material gas of N. ₃ (Ammonia) is used. Further, when doping Si, silane (SiH ₄ ) is supplied as a raw material gas. The nitride semiconductor layer may be formed by MBE (Molecular Beam Epitaxy).

First, as shown in FIG. 10A, a nucleation layer (not shown), a buffer layer 11, an electron traveling layer 21, and an electron supply layer 22 are sequentially formed on the substrate 10 by MOVPE. In the present embodiment, a SiC substrate is used for the substrate 10, and the nucleation layer (not shown) is formed of an AlN film having a film thickness of 1 nm to 300 nm, for example, 160 nm. The buffer layer 11 is formed of an AlGaN film having a film thickness of 1 nm to 1000 nm, for example, 600 nm. The electron traveling layer 21 is formed of an i-GaN film having a film thickness of about 3.0 μm. The electron supply layer 22 is formed of n-AlGaN having a film thickness of about 30 nm, and is doped with Si as an n-type impurity element so that the impurity concentration is 5 × 10 ¹⁸ cm ^-3 . As a result, 2DEG21a is generated in the electron traveling layer 21 in the vicinity of the interface between the electron traveling layer 21 and the electron supply layer 22. An i-AlGaN film having a film thickness of 5 nm may be formed between the electron traveling layer 21 and the electron supply layer 22 as a spacer layer (not shown).

Next, as shown in FIG. 10B, the source electrode 42 and the drain electrode 43 are formed on the electron supply layer 22. Specifically, a resist (not shown) having an opening in a region where the source electrode 42 and the drain electrode 43 are formed by applying a photoresist on the electron supply layer 22 and performing exposure and development with an exposure apparatus is performed. Form a pattern. After that, a metal laminated film is formed by forming a Ta film and an Al film in order by vacuum deposition, and then the metal laminated film on the resist pattern is removed by lift-off together with the resist pattern by immersing the metal laminated film in an organic solvent or the like. do. As a result, the source electrode 42 and the drain electrode 43 are formed by the remaining metal laminated film. The film thickness of the Ta film in the metal laminated film is, for example, 7 nm, and the film thickness of the Al film is, for example, 100 nm. After that, heat treatment is further performed at a temperature of 400 ° C. to 900 ° C., for example, 580 ° C. in a nitrogen atmosphere to establish ohmic contact in the source electrode 42 and the drain electrode 43.

Next, as shown in FIG. 11A, an insulating film 30 serving as a protective film is formed on the exposed electron supply layer 22. Specifically, the insulating film 30 is formed by forming a SiN film having a film thickness of 100 nm on the electron supply layer 22 by CVD (chemical vapor deposition).

Next, as shown in FIG. 11B, an opening 30a is formed in the region where the gate electrode 41 is formed in the insulating film 30. Specifically, a photoresist is applied onto the insulating film 30 and exposed and developed by an exposure apparatus to form a resist pattern (not shown) having an opening in a region where the opening 30a is formed. After that, the opening 30a is formed by removing the insulating film 30 in the region where the resist pattern is not formed by dry etching such as RIE (Reactive Ion Etching). The opening 30a of the insulating film 30 may be formed by wet etching, ion milling, or the like, in addition to dry etching.

Next, as shown in FIG. 12A, a resist pattern 61 is formed on the insulating film 30, the source electrode 42, and the drain electrode 43, and an Au layer 41a is further formed. The resist pattern 61 is formed by repeatedly applying a photoresist on the insulating film 30, the source electrode 42, and the drain electrode 43, and performing exposure and development with an exposure apparatus. The resist pattern 61 to be formed has an opening 61a in the region where the Au layer 41a of the gate electrode 41 is formed. After that, the Au layer 41a is formed by vacuum deposition on the electron supply layer 22 of the opening 61a of the resist pattern 61, on the insulating film 30, and on the resist pattern 61.

Next, as shown in FIG. 12B, the Au layer 41a on the resist pattern 61 is lifted off together with the resist pattern 61 by immersing it in an organic solvent or the like. The Au layer 41a remaining in this way becomes the Au layer 41a of the gate electrode 41.

Next, as shown in FIG. 13A, a resist pattern 62 is formed on the insulating film 30, the source electrode 42, and the drain electrode 43, and the Ni layer 41b and the Au layer 41c are further formed in this order. The resist pattern 62 is formed by applying a photoresist on the insulating film 30, the source electrode 42, and the drain electrode 43, and repeating exposure and development with an exposure apparatus. The resist pattern 62 to be formed has an opening 62a in the region where the Ni layer 41b and the Au layer 41c of the gate electrode 41 are formed. After that, a Ni layer 41b and an Au layer 41c are formed in this order on the Au layer 41a of the opening 62a of the resist pattern 62, on the electron supply layer 22 and on the insulating film 30, and on the resist pattern 62 by vacuum deposition. Film.

Next, as shown in FIG. 13B, the Ni layer 41b and the Au layer 41c on the resist pattern 62 are removed by lift-off together with the resist pattern 62 by immersing the resist pattern 62 in an organic solvent or the like. As a result, the gate electrode 41 is formed by the remaining Ni layer 41b, Au layer 41c, and Au layer 41a.

By the above steps, the semiconductor device according to the present embodiment can be manufactured.

[Second Embodiment]
Next, the second embodiment will be described. The present embodiment is a semiconductor device, a power supply device, and a high-power amplifier.

The semiconductor device according to the present embodiment is a discrete package of the semiconductor device according to the first embodiment, and the semiconductor device discretely packaged in this way will be described with reference to FIG. Note that FIG. 14 schematically shows the inside of the discretely packaged semiconductor device, and the arrangement of the electrodes and the like are different from those shown in the first embodiment.

First, the semiconductor device manufactured in the first embodiment is cut by dicing or the like to form a HEMT semiconductor chip 410 made of a GaN-based semiconductor material. The semiconductor chip 410 is fixed on the lead frame 420 with a die-attaching agent 430 such as solder. The semiconductor chip 410 corresponds to the semiconductor device according to the first embodiment.

Next, the gate electrode 411 is connected to the gate lead 421 by the bonding wire 431, the source electrode 421 is connected to the source lead 422 by the bonding wire 432, and the drain electrode 413 is connected to the drain lead 423 by the bonding wire 433. The bonding wires 431, 432, and 433 are made of a metal material such as Al. Further, in the present embodiment, the gate electrode 411 is a gate electrode pad and is connected to the gate electrode 41 of the semiconductor device according to the first embodiment. Further, the source electrode 412 is a source electrode pad, and is connected to the source electrode 42 of the semiconductor device according to the first embodiment. Further, the drain electrode 413 is a drain electrode pad, and is connected to the drain electrode 43 of the semiconductor device according to the first embodiment.

Next, the resin is sealed with the mold resin 440 by the transfer molding method. In this way, a discretely packaged semiconductor device of HEMT using a GaN-based semiconductor material can be manufactured.

Next, the power supply device and the high output amplifier in the present embodiment will be described. The power supply device and the high-power amplifier in the present embodiment are the power supply device and the high-power amplifier using the semiconductor device in the first embodiment.

First, the power supply device according to the present embodiment will be described with reference to FIG. The power supply device 460 in the present embodiment includes a high-voltage primary side circuit 461, a low-voltage secondary side circuit 462, and a transformer 463 arranged between the primary side circuit 461 and the secondary side circuit 462. The primary side circuit 461 includes an AC power supply 464, a so-called bridge rectifier circuit 465, a plurality of switching elements (four in the example shown in FIG. 15) 466, one switching element 467, and the like. The secondary circuit 462 includes a plurality of switching elements (three in the example shown in FIG. 15) 468. In the example shown in FIG. 15, the semiconductor device according to the first embodiment is used as the switching elements 466 and 467 of the primary circuit 461. The switching elements 466 and 467 of the primary circuit 461 are preferably normally-off semiconductor devices. Further, the switching element 468 used in the secondary side circuit 462 uses a normal MISFET (metal insulator semiconductor field effect transistor) formed of silicon.

Next, the high output amplifier according to the present embodiment will be described with reference to FIG. The high-frequency amplifier 470 in the present embodiment is a high-frequency amplifier, and may be applied to, for example, a power amplifier for a base station of a mobile phone. The high-power amplifier 470 includes a digital predistortion circuit 471, a mixer 472, a power amplifier 473, and a directional coupler 474. The digital predistortion circuit 471 compensates for the non-linear distortion of the input signal. The mixer 472 mixes the input signal and the AC signal in which the non-linear distortion is compensated. The power amplifier 473 amplifies the input signal mixed with the AC signal. In the example shown in FIG. 16, the power amplifier 473 has the semiconductor device according to the first embodiment. The directional coupler 474 monitors the input signal and the output signal. In the circuit shown in FIG. 16, for example, the output signal can be mixed with the AC signal by the mixer 472 and sent to the digital predistortion circuit 471 by switching the switch.

Although the embodiments have been described in detail above, the embodiments are not limited to the specific embodiments, and various modifications and changes can be made within the scope of the claims.

Regarding the above explanation, the following additional notes will be further disclosed.
(Appendix 1)
A first semiconductor layer formed of a nitride semiconductor on a substrate,
A second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer,
A gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer,
Have,
The gate electrode has an Au layer and a Ni layer, and has an Au layer and a Ni layer.
A semiconductor device characterized in that both the Au layer and the Ni layer in the gate electrode are in contact with the second semiconductor layer.
(Appendix 2)
The semiconductor device according to Appendix 1, wherein the Au layer is formed on the drain electrode side of the Ni layer.
(Appendix 3)
The length of the region in contact between the Ni layer and the second semiconductor layer in the gate length of the gate electrode is longer than the length of the region in contact with the Au layer and the second semiconductor layer. Or the semiconductor device according to 2.
(Appendix 4)
An insulating film having an opening is formed on the second semiconductor layer.
The semiconductor device according to any one of Supplementary note 1 to 3, wherein the Au layer and the Ni layer of the gate electrode are in contact with the second semiconductor layer at the opening.
(Appendix 5)
The semiconductor device according to any one of Supplementary note 1 to 4, wherein the gate electrode is formed of a Pd layer instead of the Au layer.
(Appendix 6)
The first semiconductor layer is formed of a material containing GaN, and is formed of a material containing GaN.
The semiconductor device according to any one of Supplementary note 1 to 5, wherein the second semiconductor layer is formed of a material containing AlGaN or InAlN.
(Appendix 7)
A process of forming a first semiconductor layer from a nitride semiconductor on a substrate, and
A step of forming a second semiconductor layer on the first semiconductor layer and
A step of forming a source electrode and a drain electrode on the second semiconductor layer, and
A step of forming an insulating film having an opening on the second semiconductor layer, and
A step of forming an Au layer of a gate electrode on the drain electrode side on the second semiconductor layer in the opening, and a step of forming the Au layer of the gate electrode.
A step of forming a Ni layer of a gate electrode on the source electrode side of the Au layer on the second semiconductor layer in the opening.
A method for manufacturing a semiconductor device.
(Appendix 8)
The first semiconductor layer is formed of a material containing GaN, and is formed of a material containing GaN.
The method for manufacturing a semiconductor device according to Appendix 7, wherein the second semiconductor layer is formed of a material containing AlGaN or InAlN.
(Appendix 9)
A power supply device comprising the semiconductor device according to any one of Appendix 1 to 6.
(Appendix 10)
An amplifier comprising the semiconductor device according to any one of Appendix 1 to 6.

10 Substrate 11 Buffer layer 21 Electronic traveling layer 21a 2DEG
22 Electron supply layer 30 Insulation film 41 Gate electrode 41a Au layer 41b Ni layer 41c Au layer 42 Source electrode 43 Drain electrode

Claims (7)

A first semiconductor layer formed of a nitride semiconductor on a substrate,
A second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer,
A gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer,
Have,
The gate electrode has an Au layer and a Ni layer, and has an Au layer and a Ni layer.
Both the Au layer and the Ni layer in the gate electrode are in contact with the second semiconductor layer .
A semiconductor device characterized in that the length of the region in contact between the Ni layer and the second semiconductor layer in the gate length of the gate electrode is longer than the length of the region in contact with the Au layer and the second semiconductor layer. .. The semiconductor device according to claim 1, wherein the Au layer is formed on the drain electrode side of the Ni layer. An insulating film having an opening is formed on the second semiconductor layer.
The semiconductor device according to claim 1 or 2 , wherein the Au layer and the Ni layer of the gate electrode are in contact with the second semiconductor layer at the opening. The first semiconductor layer is formed of a material containing GaN, and is formed of a material containing GaN.
The semiconductor device according to any one of claims 1 to 3 , wherein the second semiconductor layer is formed of a material containing AlGaN or InAlN. A process of forming a first semiconductor layer from a nitride semiconductor on a substrate, and
A step of forming a second semiconductor layer on the first semiconductor layer and
A step of forming a source electrode and a drain electrode on the second semiconductor layer, and
A step of forming an insulating film having an opening on the second semiconductor layer, and
A step of forming an Au layer of a gate electrode on the drain electrode side on the second semiconductor layer in the opening, and a step of forming the Au layer of the gate electrode.
A step of forming a Ni layer of a gate electrode on the source electrode side of the Au layer on the second semiconductor layer in the opening.
A method for manufacturing a semiconductor device. A power supply device comprising the semiconductor device according to any one of claims 1 to 4 . An amplifier comprising the semiconductor device according to any one of claims 1 to 4 .

Images