JP7038633B2 - Power converter - Google Patents

Description

The present invention relates to a configuration of a power conversion device, and more particularly to a technique applicable to a power conversion device equipped with a SiC power semiconductor module as a main circuit element of power conversion.

Power semiconductor elements for power conversion are widely used as key components of power conversion devices (hereinafter, also referred to as "power converters") such as inverters for motor drives and conversion devices for power transmission and distribution. The power semiconductor element is mounted on a power semiconductor module and incorporated in a power converter with one chip or a configuration in which a plurality of chips are connected in parallel. This power semiconductor element performs a switching operation by the control signal and performs power conversion by controlling the direction in which a current flows.

When switching and driving a power semiconductor element for power conversion, voltage vibration or current vibration generated by a parasitic capacitance of the chip or a parasitic inductor of wiring may occur at each terminal of the chip. These vibration phenomena will be referred to as "unnecessary vibration". In particular, when a plurality of chips are connected in parallel, the resonance loop due to the above-mentioned parasitic capacitance and the parasitic inductor and two or more or more that operate as an amplification element depend on the value of the voltage applied to the chip and the flowing current. Unwanted vibration is generated by the chip.

If the voltage amplitude or current amplitude of the unwanted vibration exceeds the voltage rating value between each terminal of the chip or the current rating flowing through the terminals, there is a concern that the long-term reliability of the chip may be deteriorated or destroyed. Therefore, when unnecessary vibration occurs, it is necessary to suppress the voltage vibration amplitude and the current vibration amplitude to the rated values or less of each terminal in the chip temperature range allowed for the chip.

As a background technology in this technical field, for example, there is a technology such as Patent Document 1. Patent Document 1 shows that when a plurality of semiconductor elements are arranged in parallel and driven for switching, resonance occurs due to the input capacitance or feedback capacitance of the element and the wiring inductance, and this resonance causes the semiconductor element. A circuit configuration is disclosed that increases the resistance value of a resistor arranged in a path for driving a gate of a semiconductor element when it is determined that an overcurrent flows through the semiconductor device.

Further, Patent Document 2 shows that the generation of unnecessary vibration depends on the temperature of the element itself in addition to the value of the voltage applied to the element and the flowing current, and the loss of the wide gap semiconductor element. As a drive circuit for reducing the temperature dependence of the above, a circuit configuration is disclosed in which the temperature of a power semiconductor switching element is detected and the gate drive voltage or the gate drive resistance is changed based on the detected value.

Japanese Unexamined Patent Publication No. 2016-149632 Japanese Unexamined Patent Publication No. 2007-259576

It is an issue to prevent the reliability deterioration or destruction of the power semiconductor element by suppressing the amplitude of the voltage vibration or the current vibration with respect to the unnecessary vibration generated in the plurality of power semiconductor elements incorporated in the power conversion device.

In particular, among power semiconductor devices, in the case of MOSFET type devices, the voltage rating between the gate terminal and the source terminal is smaller than the voltage rating between other terminals, so there is a high possibility that it will be destroyed by unnecessary vibration. It is necessary to keep the voltage amplitude of unnecessary vibration generated in the gate-source voltage (VGS) small. Further, in the case of an IGBT type element, it is necessary to keep the voltage amplitude of unnecessary vibration generated in the voltage between the gate terminal and the emitter terminal (VGE) small.

≪Characteristics and problems of SiC elements≫
In recent years, in order to improve the performance of a power converter, a silicon carbide (SiC: Silicon Carbide) element having a feature of low loss has been used as a power semiconductor element for power conversion. SiC devices have a wide band gap and have a breakdown breakdown resistance that is about 10 times higher than that of silicon (Si: Silicon) devices. Since the thickness of the channel semiconductor layer that serves as the current path can be made thinner than that of Si devices, insulation is achieved. When the breakdown voltage is designed to be equal, a thin channel semiconductor layer is formed, so that a very small on-resistance value at the time of conduction can be obtained.

Further, at the time of switching, there is an advantage that the switching loss is small as compared with the conventional Si IGBT (Insulated Gate Bipolar Transistor) element. When the IGBT element switches, a tail current generated when the current is cut off and a recovery current due to the accumulated charge of the Si PN diode used together with the Si-IGBT element are generated, and a switching loss occurs. On the other hand, in a SiC- MOSFET type power semiconductor device that has no tail current and can suppress the recovery current to a small value, the voltage waveform and the current waveform can be brought close to the ideal waveform.

On the other hand, the feedback capacitance (gate-collector capacitance CGC for IGBT-type power semiconductor devices, gate-drain capacitance CGD for SiC- MOSFET type power semiconductor devices) that is parasitically generated in power semiconductor devices is determined. The feedback capacitance of the SiC- MOSFET type power semiconductor element is significantly larger. Of the time required for switching by a power semiconductor element, the time Tv for changing the drain-source voltage VDS or the collector-emitter voltage VCE depends on the magnitude Ig of the drive current flowing in and out of the drive circuit and the feedback capacitance CGD or CGC. It will be decided.

When the drive current Ig is equal, the Tv of the SiC- MOSFET type power semiconductor element becomes longer than that of the Si-IGBT type power semiconductor element. The time Tsw required for switching by a power semiconductor device can be divided into the time Tv at which the voltage changes and the time Ti at which the current changes. Compared to Si-IGBT type power semiconductor devices, semiconductor devices can realize ideal waveforms by suppressing the generation of unnecessary current during switching, but the voltage change time Tv is large due to the large feedback capacitance. It has the characteristic of becoming longer.

Therefore, in order to construct a power converter having a small switching loss Esw by using a SiC- MOSFET type power semiconductor element, it is necessary to set a large gate drive current Ig to shorten Tv. There are two means for increasing Ig: (1) a means for increasing the gate drive voltage and (2) a means for decreasing the gate drive resistance.

The increase in the gate drive voltage in (1) is not effective because the rated voltage between the gate and source of the SiC- MOSFET type power semiconductor element is likely to be limited. Therefore, setting the gate drive resistance of (2) to a small value to drive the SiC- MOSFET type power semiconductor element is to operate the power conversion device using the SiC- MOSFET type power semiconductor element with low loss. It will be an important technology.

In order to configure a power conversion device using a power semiconductor device, it is necessary to suppress unnecessary vibration during switching described above, ensure long-term reliability of the device, and prevent destruction. Unwanted vibration is generated by a parasitic capacitance generated in a circuit component of a power conversion device, a resonance loop by a parasitic inductor, and two or more power semiconductor elements operating as amplification elements. In order to reduce the voltage amplitude and the current amplitude of the unwanted vibration, it is necessary to reduce the sharpness of the resonance of this resonance loop or to reduce the amplification degree of the amplification element.

To reduce the amplification degree of the amplification element, there is a method of inserting a resistor or inductance in series with the source terminal or emitter terminal to increase the impedance, but in the case of a power converter, it is adopted because it increases the loss. Can not. Therefore, among the resonance loops, it is effective to insert a resistor into the gate drive circuit having a small current value, that is, to increase the gate drive resistance at the time of switching to reduce the sharpness of the resonance of the resonance loop.

However, in order to realize the characteristics of low switching loss by using the SiC- MOSFET type power semiconductor element in the power conversion device, as described above, the gate drive resistance is increased as compared with the Si-IGBT type power semiconductor element at the time of switching. Needs to be reduced.

The present invention is for simultaneously overcoming the two problems of realizing low switching loss, ensuring long-term reliability of the switching element, and preventing destruction when the SiC- MOSFET type power semiconductor element is used in the power conversion device. Is.

In the circuit configuration described in Patent Document 1, it is necessary to provide an individual resistance circuit having a variable resistance value connected in series to the gate of each switching element, and when the number of parallel switching elements is large, the individual resistance value is variable. There is a drawback that the wiring of control vibration increases and the circuit scale becomes large. Further, when the individual resistance value is changed with reference to the temperature information of the element, wiring with the temperature sensitive diode is also required.

It is an event trigger type circuit configuration that changes the resistance value of the individual resistance circuit when an overcurrent determined by a predetermined current threshold value occurs. Unnecessary vibration may cause element destruction immediately when the gate-source voltage is exceeded due to its occurrence, and if there is a high risk of unwanted vibration, a circuit configuration that prevents it without waiting for its occurrence. Need to be taken.

<< Issues of prior art >>
From Patent Document 1 and Patent Document 2 described above, in order to suppress an overcurrent when an overcurrent is generated in any of the power semiconductor elements by the resonance circuit when switching a plurality of power semiconductor elements, (1). ) Equipped with means for detecting overcurrent and reducing overcurrent by varying the value of the individual resistance connected to the gate of each power semiconductor element, (2) Equipped with means for detecting the element temperature of the power semiconductor element, the element It can be said that it has been conventionally known to change the control of the value of the individual resistance according to the temperature.

However, when switching a plurality of power semiconductor devices, it is not only when the value of the emitter current or the source current becomes excessive that the long-term reliability of the device is deteriorated and the possibility of destruction is increased. In particular, since the maximum and minimum ratings of the gate voltage of the power semiconductor element are about several tens of volts (for example, maximum + 20V and minimum -10V), they are liable to be deteriorated by applying an excessive voltage. There are multiple cases where an excessive voltage is applied to the gate-source voltage during switching (hereinafter, the terminal name of the MOSFET type power semiconductor element is used, but it can be replaced with the terminal name of the IGBT type power semiconductor element). be.

One example is a case where a large voltage change (for example, several kV) of the collector potential or the drain potential generated in switching is applied to the gate terminal coupled by the feedback capacitance of the power semiconductor element. The following example is a case where unnecessary vibration is generated in which the present invention is effective. Unnecessary vibration is likely to occur in the gate potential at the timing when the main voltage (collector potential or drain potential) generated during the switching period is high and the main current (emitter current or source current) is large at the same time, and the upper and lower limits of the vibration voltage are set. , The element deteriorates by exceeding the rated value of the gate voltage.

Therefore, there is a need for a means for suppressing unnecessary vibration generated when switching a plurality of power semiconductor elements so that the voltage vibration amplitude generated in the above-mentioned gate-source voltage does not exceed the gate voltage rating. In particular, in the SiC- MOSFET type power semiconductor device, it is necessary to set the value of the gate drive resistance smaller than that of the Si-IGBT type power semiconductor device in order to realize low switching loss, and the sharpness of the resonance of the resonance loop is sharp. Since it is large, it can be said that unnecessary vibration is likely to occur. In addition, unwanted vibration may cause element destruction immediately when the gate-source voltage exceeds the rated voltage due to its occurrence, and avoid it when the risk of unwanted vibration is high. It is necessary to adopt a circuit configuration.

Therefore, an object of the present invention is to provide a highly reliable power conversion device capable of suppressing unnecessary vibration of the gate-source voltage (VGS) in a power conversion device equipped with a SiC power semiconductor module as a main circuit element of power conversion. To provide.

In order to solve the above problems, the present invention relates to a plurality of power semiconductor modules connected in parallel, and drain-source voltage Vds, gate-source voltage Vgs, source or drain of each of the plurality of power semiconductor modules. A detection circuit that acquires a first physical quantity, a second physical quantity, and a third physical quantity based on each of the currents Is from the plurality of power semiconductor modules, the first physical quantity, the second physical quantity, and the third physical quantity. A determination circuit that generates a detection determination signal based on a physical quantity, a detection determination circuit that is composed of the detection circuit and the determination circuit and outputs the detection determination signal, and the plurality of power semiconductor modules based on the detection determination signal. The gate drive circuit comprises a gate drive circuit that generates a control signal of the above, and the gate drive circuit has a common gate resistor configured so that the resistance value is variably controlled, and each of the plurality of power semiconductor modules has a common gate resistance. The detection determination circuit has an individual gate resistance configured so that the resistance value is variably controlled, and the detection determination circuit is a quasi-short circuit in which both the drain-source voltage Vds and the source or drain current Is are larger than a predetermined threshold value. Along with extracting the period, the module element temperature corresponding to the combination of the gate-source voltage Vgs and the source or drain current Is is extracted, and the module element temperature is within a predetermined range within the quasi-short circuit period. When is, it is characterized in that the resistance value of at least one of the common gate resistance and the individual gate resistance is changed.

According to the present invention, in a power conversion device equipped with a SiC power semiconductor module as a main circuit element of power conversion, a highly reliable power conversion device capable of suppressing unnecessary vibration of a gate-source voltage (VGS) is realized. be able to.

This makes it possible to reduce malfunctions and failures of the power conversion device.

Issues, configurations and effects other than those described above will be clarified by the description of the following embodiments.

It is a circuit block diagram which shows the structure of the power conversion apparatus which concerns on 1st Embodiment of this invention. It is a figure which shows the transient response waveform at the time of switching of the power conversion apparatus shown in FIG. (Control of the present invention) It is a figure which shows the transient response waveform at the time of switching of the power conversion apparatus shown in FIG. (When the control of the present invention is not carried out) It is a figure which shows the transient response waveform at the time of switching of the power conversion apparatus shown in FIG. (When the control of the present invention is not carried out) It is a figure which shows the transient response waveform at the time of switching of the power conversion apparatus shown in FIG. (When the control of the present invention is not carried out) It is a figure which shows the principle of suppressing an unnecessary vibration phenomenon by the power conversion apparatus shown in FIG. It is a figure which shows the temperature dependence of the gate plateau voltage VGP by the power conversion apparatus shown in FIG. It is a figure which shows the temperature dependence of the gate plateau voltage VGP by the power conversion apparatus shown in FIG. It is a figure which shows the temperature dependence of the gate plateau voltage VGP by the power conversion apparatus shown in FIG. It is a figure which shows the transient response waveform at the time of switching of the conventional power conversion apparatus. It is a figure which shows the transient response waveform at the time of switching of the power conversion apparatus shown in FIG. It is a figure which shows the structure of the detection determination circuit of the power conversion apparatus which concerns on 2nd Embodiment of this invention. It is a figure which shows the structure of the detection circuit of the power conversion apparatus which concerns on 3rd Embodiment of this invention. It is a circuit block diagram which shows the structure of the power conversion apparatus which concerns on 4th Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the same components are designated by the same reference numerals, and the detailed description of the overlapping portions will be omitted.

The power converter of the present invention is a first physical quantity, a second, based on the gate-source voltage, drain-source voltage, and source or drain current of each of a plurality of power semiconductor modules connected in parallel. A detection determination circuit that acquires a physical quantity and a third physical quantity and generates a signal for controlling the values of the common gate resistance and the individual gate resistance of a plurality of power modules is provided. The detection determination circuit extracts a quasi-short circuit period in which both the drain-source voltage and the source current are larger than a predetermined threshold value, and the module element corresponding to the combination of the gate-source voltage and the source current. The temperature is extracted and the value of the gate resistance is changed when the module element temperature is in a predetermined temperature range within the quasi-short circuit period. At least one of the operation of reducing the resistance value of the common gate resistance and the operation of increasing the resistance value of the individual gate resistance is executed.

≪Example of overall circuit configuration≫
The power conversion device according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 5B. FIG. 1 shows a circuit configuration for one phase of the power conversion device of this embodiment.

As shown in FIG. 1, the power conversion device according to the present embodiment has a plurality of power semiconductor modules 8a, 8b, 9a, 9b, and a common gate drive resistor 51, which has a gate terminal and a source sense terminal of the plurality of power semiconductor modules. The gate drive circuits 5a and 5b driven by 52, the drain-source sense voltage Vds of the power semiconductor module, the gate-source sense voltage Vgs, and the source current value Is are detected to form the gate drive circuits 5a and 5b. It is composed of common gate drive resistors 51 and 52 and detection and determination circuits 10a and 10b that control to increase or decrease the value of individual gate resistors included in the plurality of power semiconductor modules 8a, 8b, 9a and 9b.

Note that FIG. 1 shows the load of the power conversion device (inductive load 6) and the power supply (main voltage source 7).

The detection determination circuits 10a and 10b detect the Vds detection circuits 1a and 1b that detect the drain-source voltage Vds of the power semiconductor module and generate the first physical quantity, and the gate-source voltage Vgs of the power semiconductor module. The Vgs detection circuits 2a and 2b that generate a second physical quantity, and the Is detection circuits 3a and 3b that detect a voltage or current that reflects the source or drain current value Is of the power semiconductor module and generate a third physical quantity. , The first to third physical quantities are input, and the gate drive circuits 5a and 5b and the determination circuits 4a and 4b that generate control signals for increasing or decreasing the resistance values of the plurality of power semiconductor modules 8a, 8b, 9a and 9b are configured. To.

The configuration of the plurality of power semiconductor modules 8a, 8b, 9a, 9b has two forms, all of which are included in the scope of the present invention. That is, FIG. 1 shows a mode in which the power semiconductor modules 8a and 9a for the upper arm and the power semiconductor modules 8b and 9b for the lower arm of the power conversion device are configured by 1-in-1 modules in separate housings. However, even in the form of a 2-in-1 module in which the power semiconductor modules 8a and 9a for the upper arm and the power semiconductor modules 8b and 9b for the lower arm are housed in the same module housing, respectively, the following There is no change in the effect of the present invention described.

The power semiconductor modules 8a and 9a of the upper arm and the power semiconductor modules 8b and 9b of the lower arm form a half-bridge circuit, which is a circuit for one phase of the power conversion device.

The drain terminals D1 of the power semiconductor modules 8a and 9a of the upper arm are high potential terminals. The source terminals S1 of the power semiconductor modules 8a and 9a of the upper arm and the drain terminals D2 of the power semiconductor modules 8b and 9b of the lower arm are commonly connected to the intermediate potential terminal D2S1 and connected to the inductive load 6. The source terminals S2 of the power semiconductor modules 8b and 9b of the lower arm are low potential terminals.

The connection between the gate drive circuit 5 (5a, 5b), the detection / determination circuit 10 (10a, 10b), and the power semiconductor modules 8, 9 (8a, 8b, 9a, 9b) will be described by taking the upper arm as an example. The gate terminals of the two power semiconductor modules 8a and 9a exemplified are connected in common, and are connected to the output terminal nGOa of the gate drive circuit 5 (5a) (the subscript of a is added to the upper arm). The paired source sense terminals are also commonly connected and connected to the output terminal nSsOa.

The source main terminal D2S1 of the power semiconductor modules 8a and 9a is connected to one input terminal of the Is detection circuit 3a, and the source sense terminal nSsOa is connected to the other input terminal of the Is detection circuit 3a. One input terminal of the Vgs detection circuit 2a is connected to the gate terminal nGOa, and the other input terminal is connected to the source sense terminal nSsOa. One input terminal of the Vds detection circuit 1a is connected to the drain sense main terminal nSi1a of the power semiconductor modules 8a and 9a, and the other input terminal is connected to the source sense terminal nSsOa.

The outputs of the Vds detection circuit 1a, the Vgs detection circuit 2a, and the Is detection circuit 3a are input to the determination circuit 4a with reference to the potential of the source sense terminal nSsOa. Although not shown in the Vds detection circuit 1a, the Vgs detection circuit 2a, and the Is detection circuit 3a, the Vds detection circuit 1a, the Vgs detection circuit 2a, and the Is detection circuit 3a are provided with a threshold voltage generation circuit for a potential difference between each of the two input terminals, and the plurality of detection circuits 1a, 2a, and 3a are provided. It is used to determine each output value. The threshold voltage can be set independently of each other in each detection circuit.

The determination circuit 4a includes three voltage output terminals nDo1a to nDo3a, and is arranged in parallel with the switch 54 arranged in parallel with the common gate drive resistance 51 of the gate drive circuit 5a and the common gate drive resistance 52 of the gate drive circuit 5a. The switch 56, the individual gate resistance variable switch 84 arranged in parallel with the individual gate resistance 82 of the power semiconductor module 8a, and the individual gate resistance variable switch 94 arranged in parallel with the individual gate resistance 92 of the power semiconductor module 9a. Outputs an open or closed control signal.

In the gate drive circuit 5a, the gate drive circuit 5a is positive by connecting a series circuit composed of the switch 54 and the common gate drive resistor 53 in parallel to the common gate drive resistor 51 connected to the positive potential terminal nGDHa. The value of the side common gate resistance value (Rg1ON) is made variable. Due to the control signal output from the output terminal nDo1a of the detection determination circuit 10 (10a), the value R51 of the common gate drive resistance 51 becomes Rg1ON when the switch 54 is open, and the value of the common gate drive resistance 51 when the switch 54 is closed. The parallel combined resistance value R51'of R51 and the value R53 of the common gate drive resistance 53 becomes Rg1ON.

Similarly, on the negative side, a series circuit composed of the switch 56, which is a common gate variable switch, and the common gate drive resistance 55 is connected in parallel to the common gate drive resistance 52 connected to the negative potential terminal nGDLa. , The value of the negative side common gate resistance (Rg1OFF) of the gate drive circuit 5a is made variable. Due to the control signal output from the output terminal nDo2a of the detection determination circuit 10 (10a), the value R52 of the common gate drive resistance 52 becomes Rg1OFF when the switch 56 is open, and the value of the common gate drive resistance 52 when the switch 56 is closed. The parallel combined resistance value R52'of R52 and the value R55 of the common gate drive resistance 55 becomes Rg1OFF.

In the power semiconductor module 8a, the value of the individual gate resistance is set by connecting a series circuit composed of the individual gate resistance variable switch 84 and the individual gate resistance 83 in parallel to the individual gate resistance 82 connected to the gate terminal. Make it variable. According to the control signal output from the output terminal nDo3a of the detection determination circuit 10a, the value R82 of the individual gate resistance 82 becomes the gate individual resistance value when the individual gate resistance variable switch 84 is open, and the individual gate resistance variable switch 84 becomes the gate individual resistance value when the individual gate resistance variable switch 84 is closed. The parallel combined resistance value of the value R82 of the individual gate resistance 82 and the value R83 of the individual gate resistance 83 is the gate individual resistance value. In the power semiconductor module 9a as well, the value of the gate individual resistance is controlled in the same manner as in the power semiconductor module 8a.

≪Operation explanation using timing chart≫
The operation of the circuit configuration of this embodiment shown in FIG. 1 will be described with reference to the timing charts shown in FIGS. 2A to 2D. First, the temperature dependence of the gate plateau voltage will be described in advance.

When switching to an inductive load, when the gate potential of the power semiconductor module takes a flat value due to the Miller effect, this is defined as the gate plateau voltage VGP. VGP is expressed by the following equation.

VGP ≒ Vth + Is / gm ... (Equation 1)
Here, Vth is the gate threshold voltage of the switching chip mounted on the power semiconductor module, and Is is the current value flowing through the source during switching, which is equal to the load current Iload. gm indicates the mutual conductance of the switching chips, and Vth and gm each have temperature dependence. Currently, in the characteristics of the SiC- MOSFET mounted on the power semiconductor module, Vth is most dependent on the temperature change in Equation 1, and if the chip temperature is low, the VGP value corresponds to Vth. If the temperature is high and the temperature is low, the Vth value is lowered and the VGP value is low.

2A to 2D are schematic representations of the waveforms of each part of the power semiconductor modules 8a, 8b, 9a, and 9b, with time on the horizontal axis. In the following description, the upper arm (the subscript of the terminal name is a) will be described as an example.

FIG. 2A schematically shows a waveform when a turn-on operation is performed following a turn-off operation by a gate drive signal output from the output terminal nGOa of the gate drive circuit 5a of the upper arm. FIG. 2A is an example in which the control of the present invention is carried out. On the other hand, FIG. 2B shows a waveform in which a turn-on operation is performed following a turn-off operation as in FIG. 2A, but the control of the present invention is not carried out. The waveforms of FIGS. 2A to 2D show waveforms of each part constituting the drive arm controlled by the gate drive signal.

The waveform corresponding to the operation shown in FIG. 2A will be described. The voltage signal VSIG of the control terminal SIG of the gate drive circuit is shown in the first stage from the top. It is a gate drive control signal applied to the positive potential terminal nGDHa shown in FIG. 1. When the gate is controlled in the OFF state, the level is Low (L), and when the gate is controlled in the ON state, the level is High (H).

The second stage shows the response waveform of the gate-source sense terminal voltage VGS of the power semiconductor module that changes according to the signal VSIG. The voltage range changes transiently from the maximum potential VGDH on the positive side to the minimum potential VGDL, but the voltage range needs to be controlled so as not to deviate from the gate rated voltage range of the SiC- MOSFET mounted on the power semiconductor module. A plateau voltage (indicated as VGP in FIG. 2A), which is a substantially flat voltage, is generated in the VGS waveform, and the time period thereof is referred to as a plateau period. This plateau period is a period during which the drain-source voltage VDS of the power semiconductor module changes.

The response waveform of VDS is shown in the third stage. During the plateau period, the VDS transitions between the main voltage Vcc and 0V.

The transient response waveform of the source current Is of the power semiconductor module is shown in the fourth stage. The value of the source current of the power semiconductor modules 8a and 9a is converted into a potential difference appearing between both terminals of the source current detection resistor (shunt resistor) 85 and 95 provided inside the power semiconductor module or at the source terminal of the module. Is input as a potential difference between the input terminals of the Is detection circuit 3a. As shown in FIG. 2A, the current change of Is occurs after the voltage change of VDS at the turn-off time, and the voltage change of VDS occurs after the current change of Is at the turn-on time.

The waveforms in the 5th to 10th stages are the internal waveforms of the detection determination circuit 10 (10a). VGSOUT indicates the output potential of the VGS detection circuit 2a, VDSOUT indicates the output potential of the VDS detection circuit 1a, and ISOUT indicates the output potential of the Is detection circuit 3a.

The VGSOUT outputs a High signal when the VGS waveform is equal to or higher than the threshold value VGPth, and outputs a Low signal when the VGS waveform is less than the threshold value VGPth.

The VDSOUT outputs a High signal if the VDS waveform is equal to or higher than the threshold value VDSth, and outputs a Low signal if the VDS waveform is less than the threshold value VGPth.

IsOUT outputs a High signal when the value of the Is waveform is equal to or more than the threshold value Isth, and outputs a Low signal when the value is less than the threshold value Isth.

The internal waveform A indicates the logical product of VDSOUT and IsOUT, and outputs a High signal during a period in which both the VDS waveform and the Is waveform are equal to or greater than the respective determination threshold values, and outputs a Low signal when the VDS waveform and the Is waveform are both equal to or greater than the respective determination threshold values. That is, the period during which the internal waveform A outputs the High signal indicates that the power semiconductor module is in the quasi-short-circuited state.

The internal waveform B is an output in which VGSOUT is latched by a rising trigger of VDSOUT. The rise timing of VDSOUT (time T1 in FIG. 2A) occurs during the period in which the waveform VGSOUT determines the magnitude of the voltage VGS (that is, VGP) in the plateau period with respect to the threshold value VGPth. Therefore, the internal waveform B is an output signal for determining the magnitude of the VGP value at the time of turn-off. As will be described later, for example, if the temperature of the switching element inside the power semiconductor module is low, the value of VGP increases. Therefore, if the internal waveform B is a High signal, it can be determined that the temperature of the switching element is low.

The internal waveform C is a logical product of the internal waveforms A and B. That is, if the War semiconductor module is in a quasi-short-circuited state and the temperature of the switching element inside the power semiconductor module is low, a High signal is output. That is, during the period in which the internal waveform C outputs the High signal, there is a high possibility that unnecessary vibration will occur in the gate drive path of the power converter using the plurality of power semiconductor modules.

In the control of the gate drive resistance of the present invention, when the internal waveform C is a High signal, a closing signal is given to the switches (common gate variable switch) 54 and 56 that change the common gate resistance. As a result, the turn-on resistance is reduced from R51 to the parallel combined resistance value R51'of the value R51 of the common gate drive resistance 51 and the value R53 of the common gate drive resistance 53, and the turn-off resistance is reduced from R52 to the common gate drive resistance 52. The parallel combined resistance value R52'of the value R52 of and the value R55 of the common gate drive resistance 55 is reduced.

However, since the gate drive ON / OFF changeover switch 58 is closed and the gate drive ON / OFF changeover switch 57 is open at the time of turn-off, the common gate resistances affecting the switching operation are R52 and R52'. Further, since the gate drive ON / OFF changeover switch 57 is closed and the gate drive ON / OFF changeover switch 58 is open at the time of turn-on, the common gate resistances affecting the switching operation are R51 and R51'.

At the same time, when the internal waveform C is a High signal, it is controlled so as to increase the individual gate resistance of the power semiconductor module. The logical inversion value of the internal waveform C is given to the individual gate resistance variable switch 84 and the individual gate resistance variable switch 94 of the gate drive resistance of the power semiconductor modules 8a and 9a, the switch is opened, and the individual gate resistance value is set to the individual gate resistance. The parallel combined resistance value R82'of the value R82 of 82 and the value R83 of the individual gate resistance 83 is increased to the value R82 of the individual gate resistance 82, and similarly, the value R92 of the individual gate resistance 92 and the value of the individual gate resistance 93. The combined resistance value R92'in parallel with R93 is increased to the value R92 of the individual gate resistance 92.

As described above, the control of the gate resistance of the present invention reduces the common gate resistance when the power semiconductor module is in a quasi-short circuit state and the temperature of the switching element inside the power semiconductor module is low, and the individual modules are individually controlled. Is to increase resistance. In the above case, the effect of the present invention can be obtained even when only one of the reduction of the common gate resistance and the increase of the individual gate resistance is carried out.

≪Effect of increase / decrease control of gate resistance value≫
Here, the effect of increasing / decreasing the gate resistance will be described with reference to FIG. FIG. 3 is a simplification of the equivalent circuit of the gate drive path for the two power semiconductor modules 8a and 9a connected in parallel. As the equivalent circuit of the gate drive circuit, the circuit at the time of turn-on is described as an example. The unnecessary vibration generated in the gate drive path is an oscillation phenomenon generated between the resonance loop composed of the gate terminal and the source sense terminal of the two power semiconductor modules 8a and 9a.

The conditions under which unnecessary vibration occurs are described. When the chip temperature is low, the mutual conductance of the semiconductor chips becomes large, and the rate of change of the source current with respect to the change of the gate voltage including noise becomes large. The transconductance also depends on the absolute value of the source current, and when the source current is large, the rate of change of the drain current and the source current with respect to the change in the gate voltage becomes larger.

When switching to an inductive load, the value of the source current Is of the power semiconductor module changes at any time, so that a period in which the chip temperature is low and the source current Is is large occurs at the same time. During this period, the rate of change of the source current with respect to the gate voltage of the power semiconductor module is the highest, and the possibility of unnecessary vibration occurring in the gate drive loop is high.

FIG. 3 shows the path of the loop current Iring at the time of oscillation. The current Iring that oscillates at the resonance frequency flows around the resonance loop. In order to suppress oscillation, it is necessary to reduce the value of this oscillation current. There are two ways to do this: (1) insert a resonant damping resistor in the loop path to reduce the value of the oscillation current, and (2) insert a current detour circuit in parallel with the loop path to reduce the value of the oscillation current. Is. Here, the current flowing through the current detour path configured by the gate drive circuit 5 (5a) is defined as Igd.

The means for realizing the above (1) is to increase the individual gate resistance of the power semiconductor module to reduce Iring. Therefore, under the condition that unnecessary vibration is generated, the individual gate resistance variable switch 84 is opened to change the individual gate resistance from R82'to R82. At the same time, the individual gate resistance variable switch 94 is opened to change the individual gate resistance from R92'to R92. Here, the relationship is R82'<R82, R92'<R92, R82'= R82 // R83, R92'= R92 // R93.

By this realization means, the amplitude of the vibration current Iring can be reduced, and the unnecessary vibration voltage amplitude of the waveform VGS determined by the product of the Iring and the gate-source impedance of the power semiconductor module can be suppressed to a small value. (See FIGS. 5A and 5B)
The means for realizing the above (2) is to reduce the common gate resistance of the power semiconductor module. By closing the switch (common gate variable switch) 54 under the condition that the risk of unnecessary vibration is high, the common gate resistance is changed from the value of R51 at the time of turn-on and the value of R52 at the time of turn-off to R51'or R52'. Here, the relationship is R51'<R51, R52'<R52, R51'= R51 // R53, R52'= R52 // R56. Since the vibration current Igd drawn into the gate drive path can be increased by this realization means, the amplitude of the vibration current Iring flowing through the power semiconductor module can be reduced. As a result, the unnecessary vibration voltage amplitude of the waveform VGS determined by the product of the impedance between the gate and the source of the power semiconductor module can be suppressed to be small.

That is, by carrying out the above means (1) and means (2) individually or simultaneously, the phenomenon of unnecessary vibration can be suppressed.

That is, the detection determination circuit 10 (10a, 10b) includes the gate terminals of the power semiconductor modules 8a and 9a, the source sense terminals of the power semiconductor modules 8a and 9a, and the gate drive circuit 5 (5a and 5b). , The parasitic inductance generated by those connection wirings and the parasitic capacitance generated in each of the power semiconductor modules 8a and 9a form a resonance loop circuit of the gate drive path, and the common gate resistances 51, 52, 53, 55. By reducing the value of, a bypass circuit of the vibration current generated in the resonance loop circuit is generated to reduce the vibration current, and by increasing the value of the individual gate resistances 82, 83, 92, 93, a loss is caused in the resonance loop circuit. Give to reduce the vibration current.

In the timing chart of FIG. 2B, it is assumed that the chip temperature of the power semiconductor module is high, and the waveform is schematically shown. The waveform VGS shown in the second stage is a case where the value VGP of the gate plateau period is less than the threshold value VGPth. Therefore, the VGSOUT output with reference to the VGP at the time of turn-off and the threshold value VGPth holds the Low signal. On the other hand, since the maximum value of the source current Is is equal to or higher than the threshold value Isth, IsOUT changes and a High signal and a Low signal are output.

Since the internal waveform A is the logical product of VDSOUT and IsOUT, it indicates that the period of the high signal is a quasi-short circuit state in which both the voltage VDS and the current Is are large. On the other hand, since VGSOUT holds the Low level, the internal waveform B becomes a Low signal. The internal waveform C that controls the change in the gate resistance value is a Low signal because the internal waveform B is a Low signal.

That is, in the case of FIG. 2B, the control does not change the gate resistance (common gate resistance and individual gate resistance).

When the chip temperature is high, the mutual conductance of the power semiconductor module is lowered and the generation of unnecessary vibration is suppressed as described above, so that the control is performed without changing the gate resistance.

In the timing chart of FIG. 2C, the chip temperature of the power semiconductor module is as low as that of FIG. 2A, but the waveform assuming the case where the value of the source current Is is smaller than the threshold value Is is schematically shown. Among the waveform VGS shown in the second stage, the value VGP during the gate plateau period is equal to or higher than the threshold value VGPth. The VGSOUT that is output with reference to the VGP and the threshold value VGPth at the time of turn-off outputs a High signal triggered by the VDSOUT. On the other hand, since the maximum value of the source current Is is less than the threshold value Isth, IsOUT holds the Low signal.

Since the internal waveform A is a logical product of VDSOUT and IsOUT, it becomes a Low signal, and it is shown that a quasi-short circuit state in which both the voltage VDS and the current Is are large does not occur. On the other hand, since VGSOUT outputs a High signal, the internal waveform B becomes a High signal. The internal waveform C that controls the change in the gate resistance value becomes a Low signal because the internal waveform A is a Low signal.

That is, in the case of FIG. 2C, the control does not change the gate resistance (common gate resistance and individual gate resistance). Even when the chip temperature is low and the transconductance increases, when the source current Is is small, the generation of unnecessary vibration is suppressed, so control is performed without changing the gate resistance.

In the timing chart of FIG. 2D, the chip temperature of the power semiconductor module is as high as that of FIG. 2B, but the waveform assuming the case where the value of the source current Is is smaller than the threshold value Is is schematically shown. Among the waveform VGS shown in the second stage, the value VGP during the gate plateau period is less than the threshold value VGPth. The VGSOUT output with reference to the VGP and the threshold value VGPth at the time of turn-off is triggered by the VDSOUT but holds the Low signal. Further, since the maximum value of the source current Is is less than the threshold value Isth, IsOUT also holds the Low signal.

Since the internal waveform A is a logical product of VDSOUT and IsOUT, it becomes a Low signal, and it is shown that a quasi-short circuit state in which both the voltage VDS and the current Is are large does not occur. On the other hand, since VGSOUT also outputs a Low signal, the internal waveform B is also Low. The internal waveform C that controls the change in the gate resistance value becomes a Low signal because both the internal waveform A and the internal waveform B are Low signals.

That is, in the case of FIG. 2D, the control does not change the gate resistance (common gate resistance and individual gate resistance). When the chip temperature is high, the transconductance is low, and the source current Is is small, the generation of unnecessary vibration is suppressed, so control is performed without changing the gate resistance.

From the above description of the timing chart of FIGS. 2A to 2D, the method of controlling the gate resistance value of the present invention has been clarified.

≪Temperature dependence of gate plateau voltage VGP and unnecessary vibration suppression region≫
The control of the gate resistance value is organized with reference to FIGS. 4A to 4C. The voltage waveform VDS, voltage waveform VGS, and voltage waveform proportional to the source current Is are detected in the detection determination circuit 10 (10a), and the element temperature and mutual contactance value of the SiC- MOSFET inside the power semiconductor module are determined. However, under the condition that the element temperature at which unnecessary vibration generated in the gate drive path is generated is low and the mutual contact is large (illustrated in FIG. 2A), the value of the common gate resistance is reduced and the individual gate resistance of the power semiconductor module is reduced. Control to increase the value.

This control can prevent the application of an overvoltage between the gate and source of the power semiconductor modules connected in parallel. In FIG. 4A, the horizontal axis shows the time and the vertical axis shows the waveform of the gate voltage VGS at the time of turn-off. At the VGP detection timing (time T1 in FIG. 2A), the VGP has a small value less than the threshold value VGSth when the element is high temperature, and a large value equal to or higher than VGSth when the element is low temperature. The voltage waveform VGS can be detected even at turn-on as shown in FIG. 4B.

FIG. 4C summarizes the temperature dependence of VGP with respect to the element temperature shown in FIGS. 4A and 4B. From the above equation (1), VGP also increases when the source current Is is large. As described above, unnecessary vibration occurs under the condition that Is is large because the element temperature is low and gm increases. Therefore, it is detected that the element of the power semiconductor module is located in the area shown by the filled (shaded) in FIG. 4C, and the value of the gate resistance is controlled.

≪Unnecessary vibration suppression effect by gate resistance control≫
5A and 5B schematically show the effect of the present invention. FIG. 5A shows a case where vibration suppression measures are not implemented (conventional power conversion device) under the condition that unnecessary vibration is generated while taking time on the horizontal axis, and FIG. 5B shows a case where the vibration implementation measures of the present invention are implemented. ..

In the VGS waveform of FIG. 5A, unnecessary vibration occurs during the gate plateau period, and when the amplitude exceeds the maximum value VGSmax and the minimum value VGSmin of the gate voltage rating, deterioration or failure of the element occurs. On the other hand, in FIG. 5B, control is performed in which the value of the gate resistance described above changes during the period when the unwanted vibration is generated in FIG. 5A, and even if the unwanted vibration cannot be completely suppressed in the VGS waveform, the control is performed. It is possible to reduce the amplitude and switch within the gate voltage rating.

As described above, according to the present embodiment, in a power conversion device equipped with a SiC power semiconductor module as a main circuit element of power conversion, reliability that can suppress unnecessary vibration of gate-source voltage (VGS) is achieved. A high power conversion device can be realized. This makes it possible to reduce malfunctions and failures of the power conversion device.

The threshold voltage generated by the threshold voltage generation circuit of the Vds detection circuit 1a is 50% of the voltage value of the main voltage source 7, and the threshold voltage (threshold current) generated by the threshold voltage generation circuit of the Is detection circuit 3a. Is preferably a voltage value (current value) corresponding to a current of 50% of the rated current value of the source current Is. By setting the threshold values for determination for voltage and current to 50% of the rated values, it is possible to reliably suppress the deterioration and destruction of the reliability of the power semiconductor element due to unnecessary vibration.

<< An example of the judgment circuit of the detection judgment circuit >>
A power conversion device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 6 shows a partial circuit configuration of the present embodiment. This embodiment is an example embodying the internal circuit configuration of the detection determination circuit 10 (10a, 10b) of the first embodiment, and corresponds to a modified example of the first embodiment. It differs from the first embodiment in that the internal circuit configuration of the detection determination circuit 10 (10a, 10b) is embodied, but the other points are the same as the configuration of the first embodiment.

The detection determination circuit 10 is composed of a detection circuit including a Vds detection circuit 1, a Vgs detection circuit 2, and an Is detection circuit 3, and a determination circuit 4. The determination circuit 4 includes a D flip-flop 401, a AND circuit 402, 403, a buffer circuit 404, and an inverting buffer 405. The operation of the determination circuit 4 realizes the control described with reference to FIG. 2A. The D flip-flop 401 operates using the VDSOUT output of the Vds detection circuit 1 as a clock trigger, takes in the VGSOUT output of the Vgs detection circuit 2 as an input signal, and outputs it as an internal waveform B.

The AND circuit 402 outputs the AND waveform of the logic signal of the VDSOUT output of the Vds detection circuit 1 and the ISOUT output of the Is detection circuit 3 as the internal waveform A. The AND circuit 403 generates an AND waveform of the logic signals of the internal waveforms A and B, and outputs the signal to the output terminals nDo1 and nDo2 through the buffer circuit 404. The output terminal nDo3 outputs a signal logically inverted by the inverting buffer 405.

<< Effects of this example >>
According to this embodiment, even when the power supply noise of the determination circuit is generated due to the switching operation, the function can be realized by the logic circuit having a large noise margin, so that the power supply noise immunity can be improved.

Further, since the judgment circuit operation can be realized by a relatively simple logic circuit, the operation delay is small and an expensive microcomputer circuit is not required, so that a concrete circuit can be realized at low cost.

<< Example of detection circuit of detection judgment circuit >>
A power conversion device according to a third embodiment of the present invention will be described with reference to FIG. 7. FIG. 7 shows a partial circuit configuration of the present embodiment. This embodiment is an example embodying the internal circuit configuration of the detection determination circuit 10 (10a, 10b) of the first embodiment, and corresponds to a modified example of the first embodiment or the second embodiment. The internal circuit configuration of the detection determination circuit 10 (10a, 10b) is different from that of the first embodiment or the second embodiment in that the internal circuit configuration is embodied, but the other points are the same as the configuration of the first embodiment.

The detection determination circuit 10 includes a detection circuit including a Vds detection circuit 1, a Vgs detection circuit 2, and an Is detection circuit 3. FIG. 7 shows a specific circuit commonly used for each of the detection circuits 1 (1a, 1b), 2 (2a, 2b), and 3 (3a, 3b) shown in FIG.

The detection circuits 1, 2, and 3 operate using the difference voltage of the DC voltage applied to the terminals nSUP1 and the terminal nSUP2 as the power supply voltage. The differential input amplifier circuit 101 receives the differential voltage of the analog signal input to the two input terminals nIn1 and nIn2 of the detection circuits 1, 2, and 3, and the Schmidt trigger type comparator 102 that amplifies the signal with a predetermined gain is Based on the comparison voltage output by the detection threshold generation circuit 103, the magnitude of the output voltage of the differential input amplifier circuit 101 is determined, and a binary high / low voltage signal determined by the potential of the terminal nSUP1 and the potential of the terminal nSUP2 is generated. Terminal nOUT is generated. This voltage signal becomes an input signal of the determination circuit 4 (4a, 4b) shown in FIGS. 1 and 2.

The detection threshold generation circuit 103 is a circuit that holds a predetermined detection threshold voltage. The voltage stabilization circuit 104 removes a high-frequency noise signal superimposed on the difference voltage of the DC voltage applied to the terminal nSUP1 and the terminal nSUP2, and improves the noise immunity in the amplification operation of the differential input amplifier circuit 101.

The Schmitt trigger type comparator 102 is a circuit in which the logical value of the output voltage (the high and low voltage signals of the above two values) has a hysteresis characteristic with respect to the potential difference between the two input terminals. Due to this hysteresis characteristic, it has a function of providing a noise margin so that the output signal generated in nOUT does not fluctuate due to the noise of the input signal.

<< Effects of this example >>
A simple concrete configuration of the detection circuit is shown by this embodiment. The influence of noise superimposed on the detection signal can be reduced by adopting a configuration in which the detection signal to be an analog signal is amplified by the differential input amplification circuit 101 and then determined based on the threshold value.

Further, by adopting the Schmitt trigger method for the comparator, the influence of noise superimposed on the comparator input signal and its power supply voltage can be reduced.

Further, since the detection circuit operation can be realized by a simple analog circuit, an expensive microcomputer circuit is not required, so that a concrete circuit can be realized at low cost.

<< Modification example of source current value Is extraction method >>
A power conversion device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 8 shows an example of extracting the source current value Is by a shunt transistor and a shunt resistor, and corresponds to a modified example of the first embodiment (FIG. 1).

In this embodiment, power semiconductor elements 86 and 96 with current sense terminals are provided in place of the power semiconductor elements 81 and 91 of Example 1 (FIG. 1), and are further replaced with source current detection resistors (shunt resistors) 85 and 95. It differs from the power conversion device of the first embodiment (FIG. 1) in that the source current detection resistors 87 and 97 for connecting the current sense terminal are provided. Other points are the same as the configuration of the first embodiment.

As shown in FIG. 8, the source current of the power semiconductor elements 86 and 96 is divided into the detection circuits 1, 2 and 3 and the inductive load 6, and a part of the divided source current becomes a shunt resistance (source current detection resistor). (For current sense terminal connection) The potential difference generated by circulating in 87 and 97 is generated between the source sense terminal and the terminal of the source terminal.

In this embodiment as well, it is possible to suppress unnecessary vibration of the gate-source voltage (VGS) as in the first embodiment.

In each of the above-described embodiments, the effect of the present invention has been described for the SiC- MOSFET type power semiconductor module. However, even when the power conversion device is composed of a plurality of modules or a plurality of transistors equipped with FET type semiconductor elements made of Si, GaN, or GaO, the gate plateau voltage VGP and the mutual contact between the elements depend on the temperature. Needless to say, if the properties are the same, the effect of the present invention can be obtained.

Further, the present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the described configurations. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add / delete / replace a part of the configuration of each embodiment with another configuration.

1,1a, 1b, 2,2a, 2b, 3,3a, 3b ... Detection circuit 4,4a, 4b ... Judgment circuit 5,5a, 5b ... Gate drive circuit 6 ... Inductive load 7 ... Main voltage source 8,8a , 8b, 9, 9a, 9b ... Power semiconductor module 10, 10a, 10b ... Detection judgment circuit 51, 52, 53, 55 ... Common gate (drive) resistance 54, 56 ... Switch (common gate variable switch)
57, 58 ... Gate drive ON / OFF switch 60 ... Capacitor 81, 91 ... Power semiconductor element 82, 83, 92, 93 ... Individual gate resistance 84, 94 ... Individual gate resistance variable switch 85, 95 ... Source current detection resistor ( Shunt resistance)
86, 96 ... Power semiconductor device (with current sense terminal)
87,97 ... Source current detection resistance (for current sense terminal connection)
101 ... Differential input amplifier circuit 102 ... Schmitt trigger type comparator 103 ... Detection threshold generation circuit 104 ... Voltage stabilization circuit 401 ... D flip-flop 402, 403 ... Logic product (AND) circuit 404 ... Buffer circuit 405 ... Inverted buffer

Claims (14)

With multiple power semiconductor modules connected in parallel,
The first physical quantity, the second physical quantity, and the third physical quantity based on each of the drain-source voltage Vds, the gate-source voltage Vgs, and the source or drain current Is of each of the plurality of power semiconductor modules are combined with the plurality of physical quantities. The detection circuit acquired from the power semiconductor module and
A determination circuit that generates a detection determination signal based on the first physical quantity, the second physical quantity, and the third physical quantity.
A detection determination circuit composed of the detection circuit and the determination circuit and outputting the detection determination signal, and a detection determination circuit.
A gate drive circuit that generates control signals of the plurality of power semiconductor modules based on the detection determination signal is provided.
The gate drive circuit has a common gate resistance configured so that the resistance value is variably controlled.
Each of the plurality of power semiconductor modules has an individual gate resistor configured so that the resistance value is variably controlled.
The detection determination circuit extracts a quasi-short circuit period in which both the drain-source voltage Vds and the source or drain current Is are larger than a predetermined threshold value, and the gate-source voltage Vgs and the source or drain. Extract the module element temperature corresponding to the combination of current Is,
A power conversion device comprising changing the resistance value of at least one of the common gate resistance and the individual gate resistance when the module element temperature is within a predetermined range within the quasi-short circuit period. The power conversion device according to claim 1.
It has a half-bridge circuit composed of an upper arm and a lower arm in which the plurality of power semiconductor modules are connected in parallel, respectively.
Each of the upper arm and the lower arm has the detection determination circuit and the gate drive circuit, respectively.
The gate drive circuits of the upper arm and the lower arm are
The first common gate resistance and
With the first common gate resistance value switching circuit in which the resistance value of the first common gate resistance is variable,
The second common gate resistance and
It has a second common gate resistance value switching circuit in which the resistance value of the second common gate resistance is variable.
Each of the plurality of power semiconductor modules
Individual gate resistance and
A power conversion device comprising: an individual gate resistance value switching circuit in which the resistance value of the individual gate resistance is variable. The power conversion device according to claim 1.
A power conversion device characterized in that at least one of the plurality of power semiconductor modules is a SiC- MOSFET type power semiconductor element. The power conversion device according to claim 1.
The detection circuit includes a first detection circuit that detects the drain-source voltage Vds of the plurality of power semiconductor modules and generates a first physical quantity.
A second detection circuit that detects the gate-source voltage Vgs of the plurality of power semiconductor modules and generates a second physical quantity, and
It has a third detection circuit that detects the source or drain current Is of the plurality of power semiconductor modules and generates a third physical quantity.
The determination circuit is characterized in that a control signal for controlling the resistance values of the common gate resistance and the individual gate resistance is generated based on the first physical quantity, the second physical quantity, and the third physical quantity. Power converter. The power conversion device according to claim 4.
One input terminal of the first detection circuit is connected to each drain sense terminal of the power semiconductor module, and the other input terminal is connected to a source sense terminal.
One input terminal of the second detection circuit is connected to each gate terminal of the power semiconductor module, and the other input terminal is connected to the source sense terminal.
A power conversion device, wherein one input terminal of the third detection circuit is connected to each source terminal of the power semiconductor module, and the other input terminal is connected to the source sense terminal. The power conversion device according to claim 1.
The detection circuit includes a differential input amplifier circuit that operates using the differential voltage of the DC voltage of the plurality of power semiconductor modules as a power supply voltage.
A detection threshold generation circuit that outputs a predetermined detection threshold voltage, and
A Schmitt trigger type comparator that amplifies the output of the differential input amplifier circuit with a predetermined gain and determines the magnitude of the output voltage of the differential input amplifier circuit based on the detection threshold voltage.
A voltage stabilizing circuit that removes high-frequency noise signals superimposed on the differential voltage of the DC voltage of the plurality of power semiconductor modules, and
A power conversion device characterized by having. The power conversion device according to claim 4.
Each of the first detection circuit, the second detection circuit, and the third detection circuit includes a threshold voltage generation circuit for a potential difference between the input terminals.
A power conversion device characterized in that the threshold voltage in each detection circuit can be set independently of each other. The power conversion device according to claim 7.
The threshold voltage generated by the first detection circuit is a voltage value of 50% of the main voltage source of the power conversion device.
The power conversion device, characterized in that the threshold current generated by the third detection circuit is a current value corresponding to a current of 50% of the rated current value of the source current of the power conversion device. The power conversion device according to claim 4.
The determination circuit operates with the output of the first detection circuit as a clock trigger, takes in the output of the second detection circuit as an input signal, and outputs a first internal waveform signal.
A first AND circuit that takes in the output of the first detection circuit and the output of the third detection circuit as input signals and outputs a second internal waveform signal.
A second AND circuit that takes in the first internal waveform signal and the second internal waveform signal as input signals and outputs the third internal waveform signal.
A buffer circuit that takes in the third internal waveform signal as an input signal and outputs it to each individual gate resistor of the plurality of power semiconductor modules.
An inversion buffer that takes in the third internal waveform signal as an input signal, logically inverts it, and outputs it to the common gate resistance.
A power conversion device characterized by having. The power conversion device according to claim 9.
The determination circuit holds the second physical quantity at the timing when the first physical quantity changes, and outputs the first internal waveform signal.
A voltage of the logical product of the first physical quantity and the third physical quantity is generated, and the second internal waveform signal is output.
The voltage of the logical product of the first internal waveform signal and the second internal waveform signal is generated, and the third internal waveform signal is output.
The period in which the potential of the second internal waveform signal is the high potential logic output voltage (High voltage) is extracted, and the drain-source voltage Vds and the source or drain current Is of the plurality of power semiconductor modules set their respective thresholds. Judging the exceeded quasi-short circuit period t1,
The period in which the potential of the first internal waveform signal is the high potential logic output voltage (High voltage) is extracted, the element temperature of the plurality of power semiconductor modules is lower than a predetermined threshold value, and the source or drain current Is. The period t2 in which the value of is larger than the predetermined threshold value is determined, and
The period in which the potential of the third internal waveform signal is the high potential logic output voltage (High voltage) is extracted, and the period t3 in which unnecessary vibration in which the quasi-short circuit period t1 and the period t2 are superimposed is generated is determined.
A power conversion device characterized in that when the period t3 occurs, the resistance value of at least one of the common gate resistance and the individual gate resistance is changed. The power conversion device according to claim 1.
The detection determination circuit includes the gate terminals of the plurality of power semiconductor modules and the gate terminals of the plurality of power semiconductor modules.
Each source sense terminal of the plurality of power semiconductor modules and
With the gate drive circuit
Parasitic inductance caused by connection wiring and
Parasitic capacitance generated in each of the plurality of power semiconductor modules,
Form a resonant loop circuit of the gate drive path composed of
By reducing the value of the common gate resistance, a detour circuit of the oscillating current generated in the resonance loop circuit is generated to reduce the oscillating current.
A power conversion device characterized in that the vibration current is reduced by giving a loss to the resonance loop circuit by increasing the value of the individual gate resistance. The power conversion device according to claim 1.
Each of the plurality of power semiconductor modules has a shunt resistor between the source sense terminal and the source terminal.
A power conversion device characterized in that a potential difference proportional to the source or drain current Is is generated between the source sense terminal and the terminal of the source terminal. The power conversion device according to claim 1.
Each of the plurality of power semiconductor modules has a shunt resistor between the source sense terminal and the source terminal.
The source current of each of the plurality of power semiconductor modules is diverted to the detection circuit and the load.
A power conversion device characterized in that a potential difference generated by circulating a part of the divided source current through the shunt resistance is generated between the source sense terminal and the terminal of the source terminal. The power conversion device according to claim 1.
The plurality of power semiconductor modules include the plurality of individual gate resistors.
A power conversion device having a built-in switching circuit for switching the connection of the plurality of individual gate resistors.

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