JP7078653B2 - Display device - Google Patents

Description

The present invention relates to a display device having a circuit configured by using transistors. In particular, the present invention relates to a display device using an electro-optical element such as a liquid crystal or a light emitting element as a display medium and a driving method thereof.

In recent years, display devices have been actively developed due to the increase in large display devices such as liquid crystal televisions. In particular, there is a technique for integrally forming a drive circuit (hereinafter, also referred to as an internal circuit) including a pixel circuit and a shift register by using a transistor composed of a non-crystalline semiconductor (hereinafter, also referred to as amorphous silicon) on an insulating substrate. , Is being actively developed in order to greatly contribute to low power consumption and low cost. The internal circuit formed on the insulator is connected to a controller IC or the like (hereinafter, also referred to as an external circuit) via an FPC or the like, and its operation is controlled.

Among the internal circuits shown above, a shift register using a transistor composed of a non-crystalline semiconductor (hereinafter, also referred to as an amorphous silicon transistor) has been devised.
The configuration of the flip-flop of the conventional shift register is shown in FIG. 30 (A) (Patent Document 1). The flip-flop of FIG. 30A has a transistor 11, a transistor 12, a transistor 13, a transistor 14, a transistor 15, and a transistor 17, and has a signal line 21, a signal line 22, a wiring 23, a signal line 24, and a power supply line 25. It is connected to the power line 26. A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to the signal line 21, the signal line 22, the signal line 24, the power supply line 25, and the power supply line 26, respectively.
As shown in the timing chart of FIG. 30B, the operation period of the flip-flop of FIG. 30A is divided into a set period, a selection period, a reset period, and a non-selection period, and most of the operation periods are non-operational periods. It will be a selection period.

Here, the transistor 12 and the transistor 16 are turned on during the non-selection period. Therefore, since amorphous silicon is used for the semiconductor layer of the transistor 12 and the transistor 16, the threshold voltage (Vth) fluctuates due to deterioration or the like. More specifically, the threshold voltage rises. That is, the conventional shift register cannot be turned on because the threshold voltage of the transistor 12 and the transistor 16 rises, so that VSS cannot be supplied to the node 41 and the wiring 23, causing a malfunction.

In order to solve this problem, non-patent documents 1, non-patent documents 2 and non-patent documents 3 have devised shift registers capable of suppressing the shift of the threshold voltage of the transistor 12. In Non-Patent Document 1, Non-Patent Document 2 and Non-Patent Document 3, a new transistor (referred to as the first transistor) is arranged in parallel with the transistor 12 (referred to as the second transistor), and in the non-selection period, the first transistor is arranged. By inputting inverted signals to the gate electrode of the first transistor and the gate electrode of the second transistor, the shift of the threshold voltage of the first transistor and the second transistor is suppressed.

Further, in Non-Patent Document 4, a shift register that can suppress the shift of the threshold voltage of the transistor 16 as well as the transistor 12 is devised. In Non-Patent Document 4, a new transistor (referred to as a first transistor) is arranged in parallel with a transistor 12 (referred to as a second transistor), and another new transistor (referred to as a third transistor) is a transistor. Arrange in parallel with 16 (referred to as the fourth transistor). Then, during the non-selection period, inverted signals were input to the gate electrode of the first transistor and the gate electrode of the second transistor, respectively, and inverted to the gate electrode of the third transistor and the gate electrode of the fourth transistor, respectively. By inputting a signal, the shift of the threshold voltage of the first transistor, the second transistor, the third transistor, and the fourth transistor is suppressed.

Further, in Non-Patent Document 5, the shift of the threshold voltage of the transistor 12 is suppressed by applying an AC pulse to the gate electrode of the transistor 12.

The display devices of Non-Patent Document 6 and Non-Patent Document 7 use a shift register composed of an amorphous silicon transistor as a scanning line drive circuit, and further video from one signal line to each of the R, G, and B sub-pixels. By inputting a signal, the number of signal lines is reduced to 1/3. In this way, the display devices of Non-Patent Document 6 and Non-Patent Document 7 reduce the number of connections between the display panel and the driver IC.

Japanese Unexamined Patent Publication No. 2004-157508

Soo Young Yoon, et al. , "Highly Double Integrated Gate Drive Circuit using a-Si TFT with Dual Pull-down Structure", SOCIETY FOR INFORMATION DISPLAY 200 348-351 Binn Kim, et al. , "A-Si Gate Drive Integration with Time Shared Data Driving", Proceedings of The 12th International DISPLAY Workshops in conjunction, 1073-1076 Mindoo Chun, et al. , "Integrated Gate Drive Using Highly Table a-Si TFT's", Proceedings of The 12th International Display Display Works in conjunction 200thA. 1077-1080 Chun-Ching, et al. , "Integrated Gate Drive Circuit Using a-Si TFT", Proceedings of The 12th International Display Works in conjunction with 200th Asia Display. 1023-1026 Young Ho Jang, et al. , "A-Si TFT Lntegrated Gate Drive with AC-Driven Single Pull-down Structure", SOCIETY FOR INFORMATION DISPLAY IIIX IVEN 208-211 Jin Young Choi, et al. , "A Compact and Cost-efficient TFT-LCD throttle-Gate Pixel Structure", SOCIETY FOR INFORMATION DISPLAY 274-276 Young Soon Lee, et al. , "Advanced TFT-LCD Data Line Relaytion Method", SOCIETY FOR INFOMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAX, V.M. 1083-1086

According to the prior art, the shift of the threshold voltage of the transistor is suppressed by applying an AC pulse to the gate of the transistor which is easily deteriorated. However, when amorphous silicon is used as the semiconductor layer of the transistor, naturally, the transistor constituting the circuit that generates the AC pulse also has a problem that the threshold voltage shift occurs.

Further, it has been proposed to reduce the number of signal lines to 1/3 to reduce the number of contacts between the display panel and the driver IC (Non-Patent Document 6 and Non-Patent Document 7), but the driver is practically used. It is required to further reduce the number of IC contacts.

That is, as a problem that cannot be solved by the conventional technique, a circuit technique for suppressing the fluctuation of the threshold voltage of the transistor remains as an issue. A technique for reducing the number of contacts of the driver IC mounted on the display panel remains an issue. Reducing the power consumption of display devices remains an issue. Larger or higher definition display devices remain an issue.

The invention disclosed herein is intended to provide an industrially useful technique by solving one or more of these problems.

The display device according to the present invention can suppress the shift of the threshold voltage of the transistor by alternately applying a positive power supply and a negative power supply to the gate electrode of the transistor which is easily deteriorated.

Further, the display device according to the present invention alternately supplies a high potential (whether) or a low potential (VSS) via a switch to the gate electrode of a transistor which is easily deteriorated, thereby supplying the transistor to the gate electrode. It is possible to suppress the shift of the threshold voltage of.

Specifically, the gate electrode of the easily deteriorated transistor is connected to a wiring to which a high potential is supplied via the first switching transistor and a wiring to which a low potential is supplied via the second switching transistor. By inputting a clock signal to the gate electrode of the first switching transistor and inputting an inverted clock signal to the gate electrode of the second switching transistor, high potential or low potential is alternately applied to the gate electrode of the transistor which is easily deteriorated. Supply.

The switches shown in this document (specification, claims, drawings, etc.) can be of various forms. Examples include electrical switches and mechanical switches. That is, it is not limited to a specific one as long as it can control the flow of electric current. For example, as a switch, a transistor (for example, a bipolar transistor, a MOS transistor, etc.), a diode (for example, a PN diode, a PIN diode, a Schottky diode, a MIM (MetalInsulatorMetal) diode, a MIS (M).
etalInsulatorSemiconductor) diode, diode-connected transistor, etc.), thyristor, etc. can be used. Alternatively, a logic circuit combining these can be used as a switch.

When a transistor is used as a switch, the polarity (conductive type) of the transistor is not particularly limited because the transistor operates as a mere switch. However, when it is desired to suppress the off-current, it is desirable to use a transistor having the polarity with the smaller off-current. Examples of the transistor having a small off-current include a transistor having an LDD region, a transistor having a multi-gate structure, and the like. Alternatively, when the potential of the source terminal of the transistor operated as a switch operates in a state close to the low potential side power supply (Vss, GND, 0V, etc.), it is desirable to use an N-channel transistor. On the contrary, the potential of the source terminal is
It is desirable to use a P-channel transistor when operating in a state close to a high potential side power supply (Vdd, etc.). This is because, in the N-channel transistor, when the source terminal operates near the low potential side power supply, and in the P-channel transistor, when the source terminal operates near the high potential side power supply, the absolute value of the gate-source voltage is set. Because it can be made larger, it operates more reliably as a switch. Further, since the source follower operation is rarely performed, the magnitude of the output voltage is unlikely to be small.

In addition, CMOS using both N-channel type transistor and P-channel type transistor.
A type switch may be used as a switch. In a CMOS type switch, if either a P-channel transistor or an N-channel transistor conducts, a current flows, so that the switch can easily function as a switch. For example, the voltage can be appropriately output regardless of whether the voltage of the input signal to the switch is high or low. Further, since the voltage amplitude value of the signal for turning the switch on and off can be reduced, the power consumption can be reduced.

When a transistor is used as a switch, the switch has an input terminal (one of the source terminal or the drain terminal), an output terminal (the other of the source terminal or the drain terminal), and a terminal (gate terminal) for controlling conduction. is doing. On the other hand, when a diode is used as the switch, the switch may not have a terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce the wiring for controlling the terminals.

In the present specification, when it is explicitly stated that A and B are connected, the case where A and B are electrically connected and the case where A and B are functionally connected are functionally connected. It is assumed that the case where A and B are directly connected is included. Here, it is assumed that A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, in the configuration disclosed herein, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, but also includes the connection relationship other than the connection relationship shown in the figure or text.

For example, when A and B are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, etc.) that enables an electrical connection between A and B may be used. , One or more may be arranged between A and B. Alternatively, when A and B are functionally connected, a circuit (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.)) or a signal conversion circuit that enables functional connection between A and B. (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, booster circuit, etc.)
Step-down circuit, etc.), level shifter circuit that changes the potential level of the signal, etc.), voltage source, current source,
Switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier,
A differential amplifier circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a storage circuit, a control circuit, etc.) may be arranged one or more between A and B. Alternatively, assuming that A and B are directly connected, A and B are not sandwiched between A and B with another element or another circuit.
And may be directly connected.

When it is explicitly stated that A and B are directly connected, it means that A and B are directly connected (that is, another element or another circuit between A and B). When A and B are electrically connected (that is, when they are connected without intervening) and when A and B are connected by sandwiching another element or another circuit between A and B. If there is) and.

When it is explicitly stated that A and B are electrically connected, it means that A and B are electrically connected (that is, another element between A and B). When A and B are functionally connected (that is, when they are connected by sandwiching another circuit between A and B) and when they are functionally connected by sandwiching another circuit between A and B. (When) and the case where A and B are directly connected (that is, the case where another element or another circuit is not sandwiched between A and B) is included. In other words, the case where it is explicitly stated that it is electrically connected is the same as the case where it is simply stated that it is simply connected.

The display element, the display device which is a device having a display element, the light emitting element, and the light emitting device which is a device having a light emitting element can use various forms or have various elements. For example, as a display element, a display device, a light emitting element or a light emitting device, an EL element (organic EL element, an inorganic EL element or an EL element containing an organic substance and an inorganic substance), an electron emitting element, a liquid crystal element, an electronic ink, an electrophoretic element, etc. Grating light valve (GLV), plasma display (P)
A display medium such as a DP), a digital micromirror device (DMD), a piezoelectric ceramic display, a carbon nanotube, or the like, whose contrast, brightness, reflectance, transmittance, and the like are changed by an electromagnetic action can be used. The display device using the EL element is an EL display, and the display device using an electron emitting element is a field emission display (FED) or an SED type flat display (SED: Surface-c).
Liquid crystal displays (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection type liquid crystal display), electronic ink and electrophoretic As a display device using an element, there is an electronic paper.

Various forms of transistors can be used as the transistors described in this document (specification, claims, drawings, etc.). Therefore, the type of transistor used is not limited. For example, a thin film transistor (TFT) having a non-single crystal semiconductor film represented by amorphous silicon, polycrystalline silicon, microcrystal (also referred to as microcrystal or semi-amorphous) silicon, or the like can be used. When using a TFT, there are various merits. For example, since it can be manufactured at a lower temperature than that of single crystal silicon, it is possible to reduce the manufacturing cost or increase the size of the manufacturing apparatus. Since the manufacturing equipment can be made large, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, it can be manufactured at low cost. Further, since the production temperature is low, a substrate having weak heat resistance can be used. Therefore, a transistor can be manufactured on a transparent substrate. Then, the transmission of light in the display element can be controlled by using the transistor on the transparent substrate. Alternatively, since the film thickness of the transistor is thin, a part of the film constituting the transistor can transmit light. Therefore, the aperture ratio can be improved.

By using a catalyst (nickel or the like) when producing polycrystalline silicon, it becomes possible to further improve the crystallinity and produce a transistor having good electrical characteristics. As a result, the gate driver circuit (scanning line drive circuit) and source driver circuit (signal line drive circuit)
, A signal processing circuit (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) can be integrally formed on the substrate.

By using a catalyst (nickel or the like) when producing microcrystalline silicon, it is possible to further improve the crystallinity and produce a transistor having good electrical characteristics. At this time, the crystallinity can be improved only by applying a heat treatment without using a laser. As a result, a part of the gate driver circuit (scanning line drive circuit) and the source driver circuit (analog switch, etc.) can be integrally formed on the substrate. Furthermore, when a laser is not used for crystallization, unevenness in the crystallinity of silicon can be suppressed. Therefore, a beautiful image can be displayed.

However, it is possible to produce polycrystalline silicon or microcrystalline silicon without using a catalyst (nickel or the like).

Alternatively, a transistor can be formed by using a semiconductor substrate, an SOI substrate, or the like. In that case, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor described in the present specification. As a result, it is possible to manufacture a transistor having a small variation in characteristics, size, shape, etc., a high current supply capacity, and a small size. By using these transistors, it is possible to reduce the power consumption of the circuit or to increase the integration of the circuit.

Alternatively, a transistor having a compound semiconductor or an oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, SnO, or a thin film obtained by thinning these compound semiconductors or oxide semiconductors can be used. I can. As a result, the manufacturing temperature can be lowered, and for example, a transistor can be manufactured at room temperature. As a result, the transistor can be directly formed on a substrate having low heat resistance, for example, a plastic substrate or a film substrate. In addition, these compound semiconductors or oxide semiconductors are used.
Not only can it be used for the channel portion of a transistor, but it can also be used for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistance elements, pixel electrodes, and transparent electrodes. Further, since they can be formed or formed at the same time as the transistor, the cost can be reduced.

Alternatively, a transistor formed by inkjet or a printing method can be used. These allow it to be manufactured at room temperature, at a low degree of vacuum, or on a large substrate. Further, since it can be manufactured without using a mask (reticle), the layout of the transistor can be easily changed. Further, since it is not necessary to use a resist, the material cost can be reduced and the number of processes can be reduced. Further, since the film is attached only to the necessary part, the material is not wasted and the cost can be reduced as compared with the manufacturing method in which the film is formed on the entire surface and then etched.

Alternatively, an organic semiconductor, a transistor having carbon nanotubes, or the like can be used. These make it possible to form a transistor on a bendable substrate.
Therefore, it can be strong against impact.

In addition, various transistors can be used.

Various types of substrates on which the transistor is formed can be used, and the type is not limited to a specific one. Examples of the substrate on which the transistor is formed include a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, and a cloth substrate (natural fibers (silk, cotton, linen). ), Synthetic fiber (nylon, polyurethane, polyester) or recycled fiber (including acetate, cupra, rayon, recycled polyester), leather substrate, rubber substrate, stainless steel substrate, substrate with stainless steel foil, etc. Can be used. Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as a substrate. Alternatively, a transistor may be formed on one substrate, then the transistor may be transposed on another substrate, and the transistor may be arranged on another substrate. The substrate on which the transistor is transposed includes a single crystal substrate, an SOI substrate, and the like.
Glass substrate, quartz substrate, plastic substrate, paper substrate, cellophane substrate, stone substrate, wood substrate, cloth substrate (natural fiber (silk, cotton, linen), synthetic fiber (nylon, polyurethane, polyester) or recycled fiber (acetate, acetate, (Including cupra, rayon, recycled polyester), etc.), leather substrate, rubber substrate, stainless steel substrate, substrate having stainless steel still foil, etc. can be used. Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as a substrate. By using these substrates, it is possible to form a transistor having good characteristics, to form a transistor having low power consumption, to manufacture a device that is hard to break, to impart heat resistance, or to reduce the weight.

The transistor configuration can take various forms. Not limited to a particular configuration. For example, a multi-gate structure having two or more gate electrodes may be used. In the multi-gate structure, since the channel regions are connected in series, a plurality of transistors are connected in series. The multi-gate structure can reduce off-current and improve reliability by improving the withstand voltage of the transistor. Alternatively, due to the multi-gate structure, even if the drain-source voltage changes when operating in the saturation region, the drain-source current does not change much, and the slope of the voltage / current characteristics can be made flat. can. By utilizing the characteristic that the slope of the voltage / current characteristic is flat, it is possible to realize an ideal current source circuit and an active load having a very high resistance value. As a result, it is possible to realize a differential circuit or a current mirror circuit having good characteristics. Further, the structure may be such that the gate electrodes are arranged above and below the channel. By forming the structure in which the gate electrodes are arranged above and below the channel, the channel region is increased, so that the current value can be increased or the S value can be reduced by easily forming the depletion layer. When the gate electrodes are arranged above and below the channel, the configuration is such that a plurality of transistors are connected in parallel.

Alternatively, the structure may be such that the gate electrode is arranged above the channel region, or the gate electrode may be arranged below the channel region. Alternatively, it may have a normal stagger structure or a reverse stagger structure, the channel region may be divided into a plurality of regions, the channel regions may be connected in parallel, or the channel regions may be connected in series. good. again,
The source electrode and the drain electrode may overlap the channel region (or a part thereof).
By forming the structure in which the source electrode and the drain electrode overlap the channel region (or a part thereof), it is possible to prevent the operation from becoming unstable due to the accumulation of electric charges in a part of the channel region. Further, an LDD region may be provided. By providing the LDD region, it is possible to reduce the off-current or improve the reliability by improving the withstand voltage of the transistor. Alternatively, L
By providing the DD region, even if the drain-source voltage changes when operating in the saturation region, the drain-source current does not change much, and the slope of the voltage / current characteristics is flat. Can be done.

Various types of transistors can be used in the present specification, and they can be formed on various substrates. Therefore, all of the circuits necessary for realizing a predetermined function may be formed on the same substrate. For example, all of the circuits required to realize a predetermined function may be formed on a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate, or may be formed on various substrates. .. By forming all the circuits necessary to realize a given function on the same board, the number of parts can be reduced to reduce costs, and the number of connection points with circuit parts can be reduced to improve reliability. can do. Alternatively, a part of the circuit necessary to realize a predetermined function is formed on one board, and another part of the circuit necessary to realize a predetermined function is formed on another board. May be. That is, not all of the circuits required to realize a predetermined function need to be formed on the same substrate. For example, a part of the circuit necessary to realize a predetermined function is formed by using a transistor on a glass substrate, and another part of the circuit necessary to realize a predetermined function is a single crystal substrate. An IC chip formed above and composed of transistors on a single crystal substrate may be connected to a glass substrate by COG (ChipOnGlass), and the IC chip may be arranged on the glass substrate. Alternatively, the IC chip is TAB (TapeA).
It may be connected to the glass substrate by using an inverted Bonding) or a printed circuit board. As described above, since a part of the circuit is formed on the same substrate, the number of parts can be reduced to reduce the cost, and the number of connection points with the circuit parts can be reduced to improve the reliability. Further, since the circuit of the portion having a high drive voltage or the portion having a high drive frequency consumes a large amount of power, the circuit of such a portion is not formed on the same substrate, and instead, for example, on a single crystal substrate. If a circuit of that portion is formed and an IC chip composed of the circuit is used, an increase in power consumption can be prevented.

In addition, in this specification, one pixel means one element which can control brightness. Therefore, as an example, one pixel indicates one color element, and the brightness is expressed by one of the color elements. Therefore, at that time, in the case of a color display device composed of R (red) G (green) B (blue) color elements, the minimum unit of the image is the R pixel, the G pixel, and the B pixel. It shall consist of three pixels. The color element is not limited to three colors, and three or more colors may be used, or a color other than RGB may be used. For example, white may be added to make RGBW (W is white). Further, for example, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Further, for example, a color similar to at least one color in RGB may be added to RGB. For example, it may be R, G, B1 or B2. B
Both 1 and B2 are blue, but their frequencies are slightly different. Similarly, R1 and R2
, G, B may be used. By using such a color element, it is possible to display a display closer to the real thing and reduce power consumption. Further, as another example, when the brightness of one color element is controlled by using a plurality of regions, one region may be used as one pixel. Therefore, as an example, when area gradation is performed or when sub-pixels (sub-pixels) are provided, there are a plurality of areas for controlling brightness for one color element, and the gradation is expressed as a whole. However, one pixel may be used as one area for controlling the brightness. Therefore,
In that case, one color element is composed of a plurality of pixels. Alternatively, even if there are multiple areas for controlling brightness in one color element, they are grouped together to form one color element.
It may be a pixel. Therefore, in that case, one color element is composed of one pixel. Further, when the brightness of one color element is controlled by using a plurality of areas, the size of the area contributing to the display may differ depending on the pixel. Further, in a plurality of areas for controlling brightness, which are present for one color element, the signals supplied to each may be slightly different to widen the viewing angle. That is, the potentials of the pixel electrodes of each of the plurality of regions may be different for one color element. As a result, the voltage applied to the liquid crystal molecules differs depending on each pixel electrode. Therefore, the viewing angle can be widened.

In addition, when it is explicitly described as one pixel (three colors), it is assumed that the three pixels of R, G, and B are considered as one pixel. When explicitly describing one pixel (one color), when there are a plurality of areas for one color element, it is assumed that they are collectively regarded as one pixel.

In this document (specification, claims, drawings, etc.), the pixels may be arranged (arranged) in a matrix. Here, the fact that the pixels are arranged (arranged) in the matrix includes the case where the pixels are arranged side by side on a straight line in the vertical direction or the horizontal direction, and the case where the pixels are arranged on a jagged line. Therefore, for example, three color elements (for example, R).
In the case of full-color display in GB), the case where the stripes are arranged and the case where the dots of the three color elements are arranged in a delta are also included. In addition, it also includes cases where Bayer is placed. The color element is not limited to three colors, and may be more than three colors. For example, RGBW (W is white) and RGB with one or more colors such as yellow, cyan, and magenta added.
Further, the size of the display area may be different for each dot of the color element. As a result, it is possible to reduce the power consumption or extend the life of the display element.

In this document (specification, claims, drawings, etc.), an active matrix method having an active element in a pixel or a passive matrix method having no active element in a pixel can be used.

In the active matrix method, not only a transistor but also various active elements (active element, non-linear element) can be used as the active element (active element, non-linear element). For example, MIM (MetalInsulatorMetal) and TFD (Th)
It is also possible to use inFilmDeode) or the like. Since these elements have few manufacturing processes, it is possible to reduce the manufacturing cost or improve the yield. Further, since the size of the element is small, the aperture ratio can be improved, and low power consumption and high brightness can be achieved.

In addition to the active matrix method, it is also possible to use a passive matrix type that does not use an active element (active element, non-linear element). Since no active element (active element, non-linear element) is used, the number of manufacturing processes is small, and the manufacturing cost can be reduced or the yield can be improved. Further, since an active element (active element, non-linear element) is not used, the aperture ratio can be improved, and low power consumption and high brightness can be achieved.

The transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region, and has a drain region, a channel region, and a source region. A current can be passed through and. Here, since the source and the drain change depending on the structure of the transistor, operating conditions, and the like, it is difficult to limit which is the source or the drain. Therefore, in this specification,
Areas that function as sources and drains may not be referred to as sources or drains. In that case, as an example, they may be referred to as a first terminal and a second terminal, respectively. Alternatively, they may be referred to as a first electrode and a second electrode, respectively. Alternatively, it may be referred to as a source area or a drain area.

The transistor may be an element having at least three terminals including a base, an emitter, and a collector. In this case as well, the emitter and collector are connected to the first terminal and the second.
It may be referred to as a terminal.

The gate refers to the whole including the gate electrode and the gate wiring (also referred to as a gate line, a gate signal line, a scanning line, a scanning signal line, etc.) or a part thereof. The gate electrode refers to a conductive film of a portion that overlaps with a semiconductor forming a channel region via a gate insulating film. A part of the gate electrode is LDD (Lightly Dope).
In some cases, the dDrain) region or the source region and the drain region overlap with each other via the gate insulating film. The gate wiring is a wiring for connecting between the gate electrodes of each transistor, a wiring for connecting between the gate electrodes of each pixel, or a wiring for connecting the gate electrode and another wiring. Say.

However, there are parts (regions, conductive films, wirings, etc.) that also function as gate electrodes and also function as gate wiring. Such a portion (region, conductive film, wiring, etc.) may be referred to as a gate electrode or a gate wiring. That is, there is a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when a part of the gate wiring arranged in an extended manner and a channel region overlap, that portion (region, conductive film, wiring, etc.) functions as a gate wiring, but also as a gate electrode. It will be working. Therefore, such a portion (region, conductive film, wiring, etc.) may be referred to as a gate electrode or a gate wiring.

A portion (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and formed and connected to the same island as the gate electrode may also be referred to as a gate electrode. Similarly, a portion (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and formed and connected to the same island as the gate wiring may also be referred to as a gate wiring. In a strict sense, such a portion (region, conductive film, wiring, etc.) may not overlap with the channel region or may not have a function of connecting to another gate electrode. However, due to conditions in the manufacturing process, the parts (regions, conductive films, wiring, etc.) that are formed of the same material as the gate electrode or gate wiring and form the same island as the gate electrode or gate wiring are connected. ). Therefore, such a portion (region, conductive film, wiring, etc.) may also be referred to as a gate electrode or gate wiring.

For example, in a multi-gate transistor, one gate electrode and another gate electrode are often connected by a conductive film made of the same material as the gate electrode. Since such a portion (region, conductive film, wiring, etc.) is a portion (region, conductive film, wiring, etc.) for connecting the gate electrode and the gate electrode, it may be called a gate wiring, but it may be called a multi-gate. Since the transistor of can be regarded as one transistor, it may be called a gate electrode. In other words, the part (region, conductive film, wiring, etc.) that is formed of the same material as the gate electrode or gate wiring and forms the same island as the gate electrode or gate wiring is connected to the gate electrode or gate wiring. You may call it. Further, for example, a conductive film formed of a material different from the gate electrode or the gate wiring, which is a conductive film of a portion connecting the gate electrode and the gate wiring, may also be called a gate electrode or a gate wiring. You may call it.

The gate terminal refers to a part of the gate electrode (region, conductive film, wiring, etc.) or a portion electrically connected to the gate electrode (region, conductive film, wiring, etc.). ..

When referred to as a gate wiring, a gate line, a gate signal line, a scanning line, a scanning signal line, or the like, the gate of the transistor may not be connected to the wiring. In this case, the gate wiring, gate line, gate signal line, scanning line, scanning signal line are simultaneously the wiring formed in the same layer as the gate of the transistor, the wiring formed of the same material as the gate of the transistor, or the gate of the transistor. It may mean a film-formed wiring. Examples include wiring for holding capacity, power line, and reference potential supply wiring.

The source refers to the whole including the source region, the source electrode, and the source wiring (also referred to as a source line, a source signal line, a data line, a data signal line, etc.), or a part thereof. The source region refers to a semiconductor region containing a large amount of P-type impurities (boron, gallium, etc.) and N-type impurities (phosphorus, arsenic, etc.). Therefore, the region containing a small amount of P-type impurities and N-type impurities, that is, the so-called LDD (Lightly Dropped Drain) region is not included in the source region. The source electrode refers to a conductive layer in a portion formed of a material different from the source region and electrically connected to the source region. However, the source electrode may also be referred to as a source electrode including the source region. The source wiring is a wiring for connecting between the source electrodes of each transistor, a wiring for connecting between the source electrodes of each pixel, or a wiring for connecting the source electrode and another wiring. Say.

However, there are parts (regions, conductive films, wirings, etc.) that also function as source electrodes and also as source wiring. Such a portion (region, conductive film, wiring, etc.) may be referred to as a source electrode or a source wiring. That is, there is a region where the source electrode and the source wiring cannot be clearly distinguished. For example, when a part of the stretched source wiring and the source region overlap, that portion (region, conductive film, wiring, etc.) functions as the source wiring, but as a source electrode. Will also be working. Therefore, such a portion (region, conductive film, wiring, etc.) may be referred to as a source electrode or a source wiring.

In addition, a part (region, conductive film, wiring, etc.) formed of the same material as the source electrode and formed and connected to the same island as the source electrode, and a portion (region) connecting the source electrode and the source electrode. , Conductor, wiring, etc.) may also be referred to as a source electrode. Further, the portion that overlaps with the source region may also be referred to as a source electrode. Similarly, a region formed of the same material as the source wiring and formed and connected to the same island as the source wiring may also be referred to as a source wiring. Such a portion (region, conductive film, wiring, etc.) may not have a function of connecting to another source electrode in a strict sense. However, there are portions (regions, conductive films, wirings, etc.) that are formed of the same material as the source electrode or source wiring and are connected to the source electrode or source wiring due to conditions in the manufacturing process. Therefore, such a portion (region, conductive film, wiring, etc.) may also be referred to as a source electrode or source wiring.

Note that, for example, a conductive film of a portion connecting the source electrode and the source wiring and formed of a material different from the source electrode or the source wiring may also be referred to as a source electrode or the source wiring. You may call it.

The source terminal refers to a region of the source region, a source electrode, and a portion electrically connected to the source electrode (region, conductive film, wiring, etc.).

When called source wiring, source line, source signal line, data line, data signal line, etc.
The source (drain) of the transistor may not be connected to the wiring. In this case, the source wiring, source line, source signal line, data line, and data signal line are wiring formed in the same layer as the source (drain) of the transistor, and wiring formed of the same material as the source (drain) of the transistor. Alternatively, it may mean wiring that is formed at the same time as the source (drain) of the transistor. Examples include wiring for holding capacity, power line, and reference potential supply wiring.

The drain is the same as the source.

The semiconductor device refers to a device having a circuit including a semiconductor element (transistor, diode, thyristor, etc.). Further, a device that can function by utilizing semiconductor characteristics may be referred to as a semiconductor device.

The display element includes an optical modulation element, a liquid crystal element, a light emitting element, an EL element (organic EL element, an inorganic EL element or an EL element containing an organic substance and an inorganic substance), an electron emitting element, an electrophoresis element, a discharge element, and a light reflection. It refers to an element, an optical diffusing element, a digital micromirror device (DMD), and the like. However, it is not limited to this.

The display device means a device having a display element. The display device may be a display panel main body in which a plurality of pixels including display elements or peripheral drive circuits for driving those pixels are formed on the same substrate. The display device includes peripheral drive circuits arranged on the substrate by wire bonding, bumps, etc., so-called chip-on-glass (COG) connected IC chips, or TAB-connected IC chips. You may stay. The display device may include a flexible printed circuit (FPC) to which an IC chip, a resistance element, a capacitive element, an inductor, a transistor, or the like is attached. The display device may include a printed wiring board (PWB) connected via a flexible printed circuit (FPC) or the like and to which an IC chip, a resistance element, a capacitive element, an inductor, a transistor, or the like is attached. The display device may include an optical sheet such as a polarizing plate or a retardation plate. The display device may include a lighting device, a housing, an audio input / output device, an optical sensor, and the like. Here, even if the lighting device such as the backlight unit includes a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, a cold cathode tube, etc.), a cooling device (water-cooled type, air-cooled type, etc.), etc. good.

The lighting device refers to a device having a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflective sheet, a light source (LED, a cold cathode tube, a hot cathode tube, etc.), a cooling device, and the like.

The light emitting device means a device having a light emitting element or the like.

The reflecting device means a device having a light reflecting element, a light diffracting element, a light reflecting electrode, and the like.

The liquid crystal display device means a display device having a liquid crystal element. Liquid crystal display devices include a direct-view type, a projection type, a transmissive type, a reflective type, and a semi-transmissive type.

The drive device refers to a device having a semiconductor element, an electric circuit, and an electronic circuit. For example, a transistor that controls the input of a signal from a source signal line into a pixel (sometimes called a selection transistor, a switching transistor, etc.), a transistor that supplies voltage or current to a pixel electrode, and a voltage or current to a light emitting element. The transistor and the like that supply the voltage are an example of a drive device. Furthermore, it may be called a circuit that supplies a signal to the gate signal line (sometimes called a gate driver, a gate line drive circuit, etc.) and a circuit that supplies a signal to the source signal line (a source driver, a source line drive circuit, etc.). ) Is an example of a drive device.

The display device, the semiconductor device, the lighting device, the cooling device, the light emitting device, the reflecting device, the driving device, and the like may overlap with each other. For example, the display device may include a semiconductor device and a light emitting device. Alternatively, the semiconductor device may have a display device and a drive device.

When it is explicitly stated in this document (specification, claims, drawings, etc.) that B is formed on A or B is formed on A, B on top of A
Is not limited to being formed in direct contact with each other. If you are not in direct contact, that is, A
It also includes the case where another object intervenes between B and B. Here, it is assumed that A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

Therefore, for example, when it is explicitly stated that the layer B is formed on the layer A (or on the layer A), the layer B is formed in direct contact with the layer A. It includes the case where another layer (for example, layer C or layer D) is formed in direct contact with the layer A and the layer B is formed in direct contact with the layer A. The other layer (for example, layer C or layer D) may be a single layer or a plurality of layers.

Further, the same applies to the case where it is explicitly stated that B is formed above A, and the case is not limited to the case where B is in direct contact with A, and between A and B. It also includes the case where another object intervenes. Therefore, for example, when the layer B is formed above the layer A, the case where the layer B is formed directly on the layer A and the case where the layer B is directly contacted on the layer A are different layers. It includes the case where (for example, layer C, layer D, etc.) is formed and the layer B is formed in direct contact with the layer C. The other layer (for example, layer C or layer D) may be a single layer or a plurality of layers.

In addition, when it is explicitly stated that B is formed in direct contact with A, it includes the case where B is formed in direct contact with A, and is different between A and B. If an object intervenes, it shall not be included.

The same applies to the case where B is below A or B is below A.

According to the present specification, it is possible to suppress the deterioration of the characteristics of all the transistors of the shift register. Therefore, it is possible to suppress a malfunction of a semiconductor device to which the shift register is applied, such as a liquid crystal display device.

The figure explaining the structure of the flip-flop shown in Embodiment 1. A timing chart illustrating the operation of the flip-flop shown in FIG. The figure explaining the operation of the flip-flop shown in FIG. The figure explaining the operation of the flip-flop shown in FIG. The figure explaining the structure of the flip-flop shown in Embodiment 1. A timing chart illustrating the operation of the flip-flop shown in the first embodiment. The figure explaining the structure of the flip-flop shown in Embodiment 1. The figure explaining the structure of the flip-flop shown in Embodiment 1. The figure explaining the structure of the flip-flop shown in Embodiment 1. The figure explaining the structure of the flip-flop shown in Embodiment 1. The figure explaining the structure of the shift register shown in Embodiment 1. A timing chart illustrating the operation of the shift register shown in FIG. A timing chart illustrating the operation of the shift register shown in FIG. The figure explaining the structure of the shift register shown in Embodiment 1. The figure explaining the structure of the buffer shown in FIG. The figure explaining the structure of the buffer shown in FIG. The figure explaining the structure of the display device shown in Embodiment 1. A timing chart illustrating a writing operation of the display device shown in FIG. The figure explaining the structure of the display device shown in Embodiment 1. The figure explaining the structure of the display device shown in Embodiment 1. A timing chart illustrating a writing operation of the display device shown in FIG. 20. A timing chart illustrating the operation of the flip-flop shown in the second embodiment. A timing chart illustrating the operation of the flip-flop shown in the second embodiment. The figure explaining the structure of the shift register shown in Embodiment 2. A timing chart illustrating the operation of the shift register shown in FIG. 24. A timing chart illustrating the operation of the shift register shown in FIG. 24. The figure explaining the structure of the display device shown in Embodiment 2. The figure explaining the structure of the display device shown in Embodiment 2. Top view of the flip-flop of FIG. 7 (A). The figure which shows the structure of the conventional flip-flop. The figure explaining the structure of the signal line drive circuit shown in Embodiment 5. A timing chart illustrating the operation of the signal line drive circuit shown in FIG. 31. The figure explaining the structure of the signal line drive circuit shown in Embodiment 5. A timing chart illustrating the operation of the signal line drive circuit shown in FIG. 33. The figure explaining the structure of the signal line drive circuit shown in Embodiment 5. The figure explaining the structure of the protection diode shown in Embodiment 6. The figure explaining the structure of the protection diode shown in Embodiment 6. The figure explaining the structure of the protection diode shown in Embodiment 6. The figure explaining the structure of the display device shown in Embodiment 7. The figure explaining the structure of the flip-flop shown in Embodiment 3. A timing chart illustrating the operation of the flip-flop shown in FIG. 40. The figure explaining the structure of the shift register shown in Embodiment 3. A timing chart illustrating the operation of the shift register shown in FIG. 42. The figure explaining the structure of the flip-flop shown in Embodiment 4. A timing chart illustrating the operation of the flip-flop shown in FIG. 44. An example of a pixel layout and a cross-sectional view of the semiconductor device according to the present invention. An example of a pixel layout and a cross-sectional view of the semiconductor device according to the present invention. An example of a pixel layout and a cross-sectional view of the semiconductor device according to the present invention. An example of a pixel layout and a cross-sectional view of the semiconductor device according to the present invention. An example of a pixel layout and a cross-sectional view of the semiconductor device according to the present invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Top view of the display element of the semiconductor device according to the present invention. Top view of the display element of the semiconductor device according to the present invention. Top view of the display element of the semiconductor device according to the present invention. The figure explaining the peripheral circuit composition of the semiconductor device which concerns on this invention. The figure explaining the peripheral circuit composition of the semiconductor device which concerns on this invention. The figure explaining the panel circuit structure of the semiconductor device which concerns on this invention. The figure explaining the panel circuit structure of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. The figure explaining the peripheral circuit composition of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. Sectional drawing of the semiconductor device which concerns on this invention. The figure explaining the peripheral component of the semiconductor device which concerns on this invention. The figure explaining the peripheral circuit composition of the semiconductor device which concerns on this invention. The figure explaining the peripheral component of the semiconductor device which concerns on this invention. The figure explaining the peripheral component of the semiconductor device which concerns on this invention. The figure explaining the peripheral component of the semiconductor device which concerns on this invention. The figure explaining the semiconductor device which concerns on this invention. The figure explaining one of the driving method of the semiconductor device which concerns on this invention. The figure explaining one of the driving method of the semiconductor device which concerns on this invention. The figure explaining one of the driving method of the semiconductor device which concerns on this invention. The figure explaining one of the driving method of the semiconductor device which concerns on this invention. An example of a pixel layout and a cross-sectional view of the semiconductor device according to the present invention. An example of a pixel layout and a cross-sectional view of the semiconductor device according to the present invention. An example of a pixel layout and a cross-sectional view of the semiconductor device according to the present invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. The figure explaining the apparatus which forms the display element of the semiconductor apparatus which concerns on this invention. The figure explaining the apparatus which forms the display element of the semiconductor apparatus which concerns on this invention. The figure explaining one of the driving method of the semiconductor device which concerns on this invention. The figure explaining one of the driving method of the semiconductor device which concerns on this invention. The figure explaining one of the pixel circuits of the semiconductor device which concerns on this invention. The figure explaining one of the pixel circuits of the semiconductor device which concerns on this invention. The figure explaining the process of manufacturing the semiconductor device which concerns on this invention. The figure explaining the display element of the semiconductor device which concerns on this invention. The figure explaining the display element of the semiconductor device which concerns on this invention. The figure explaining the structure of the semiconductor device which concerns on this invention. The figure explaining the structure of the semiconductor device which concerns on this invention. The figure explaining the structure of the semiconductor device which concerns on this invention. The figure explaining the structure of the semiconductor device which concerns on this invention. The figure explaining the structure of the semiconductor device which concerns on this invention. The figure explaining the structure of the semiconductor device which concerns on this invention. The figure explaining the structure of the semiconductor device which concerns on this invention. The figure explaining the structure of the semiconductor device which concerns on this invention. The figure explaining the structure of the semiconductor device which concerns on this invention. The figure explaining the structure of the semiconductor device which concerns on this invention. The figure explaining the structure of the semiconductor device which concerns on this invention. The figure explaining the electronic device using the semiconductor device which concerns on this invention. The figure explaining the electronic device using the semiconductor device which concerns on this invention. The figure explaining the electronic device using the semiconductor device which concerns on this invention. The figure explaining the electronic device using the semiconductor device which concerns on this invention. The figure explaining the electronic device using the semiconductor device which concerns on this invention. The figure explaining the electronic device using the semiconductor device which concerns on this invention. The figure explaining the electronic device using the semiconductor device which concerns on this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the present invention can be carried out in many different embodiments, and the embodiments and details can be variously changed without departing from the spirit and scope of the present invention. Will be done. Therefore, the interpretation is not limited to the description of the present embodiment.

(Embodiment 1)
In the present embodiment, the configuration and driving method of the flip-flop, the drive circuit having the flip-flop, and the display device having the drive circuit will be described.

The basic configuration of the flip-flop of the present embodiment will be described with reference to FIG. 1 (A).
The flip-flop shown in FIG. 1A is a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor 104, and a fifth transistor 1.
05, 6th transistor 106, 7th transistor 107 and 8th transistor 1
Has 08. In the present embodiment, the first transistor 101 to the eighth transistor 108 are N-channel transistors, and are in a conductive state when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth). And.

The flip-flop of the present embodiment is characterized in that the first transistor 101 to the eighth transistor 108 are all composed of N-channel type transistors. Therefore, in the flip-flop of the present embodiment, amorphous silicon can be used as the semiconductor layer of the transistor, so that the manufacturing process can be simplified, the manufacturing cost can be reduced, and the yield can be improved. .. However, as a semiconductor layer of a transistor,
The manufacturing process can also be simplified by using polysilicon or polycrystalline silicon.

The connection relationship of the flip-flops of FIG. 1A will be described. The first electrode of the first transistor 101 (one of the source electrode and the drain electrode) is connected to the fifth wiring 125, and the second electrode of the first transistor 101 (the other of the source electrode and the drain electrode) is the second. It is connected to the wiring 123 of 3. The first electrode of the second transistor 102 is the fourth wiring 1
24 connected, the second transistor 102 second electrode connected to the third wiring 123,
The gate electrode of the second transistor 102 is connected to the eighth wire 128. The first electrode of the third transistor 103 is connected to the sixth wiring 126, the second electrode of the third transistor 103 is connected to the gate electrode of the sixth transistor 106, and the third transistor 1
The gate electrode of 03 is connected to the seventh wiring 127. The first electrode of the fourth transistor 104 is connected to the tenth wiring 130, the second electrode of the fourth transistor 104 is connected to the gate electrode of the sixth transistor 106, and the gate of the fourth transistor 104 is connected. The electrode is connected to the eighth wire 128. The first electrode of the fifth transistor 105 is the ninth wiring 1
It is connected to 29, the second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101, and the gate electrode of the fifth transistor 105 is connected to the first wiring 121. The first electrode of the sixth transistor 106 is connected to the twelfth wiring 132, and the second electrode of the sixth transistor 106 is connected to the gate electrode of the first transistor 101. The first electrode of the seventh transistor 107 is connected to the thirteenth wiring 133, the second electrode of the seventh transistor 107 is connected to the gate electrode of the first transistor 101, and so on.
The gate electrode of the seventh transistor 107 is connected to the second wiring 122. The first electrode of the eighth transistor 108 is connected to the eleventh wiring 131, and the eighth transistor 108
The second electrode is connected to the gate electrode of the sixth transistor 106, and the gate electrode of the eighth transistor 108 is connected to the gate electrode of the first transistor 101.

A node 141 is a connection point between the gate electrode of the first transistor 101, the second electrode of the sixth transistor 106, the second electrode of the seventh transistor 107, and the gate electrode of the eighth transistor 108. Further, the second electrode of the third transistor 103, the fourth
A node 142 is a connection point between the second electrode of the transistor 104, the gate electrode of the sixth transistor 106, and the second electrode of the eighth transistor 108.

The first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, the seventh wiring 127, and the eighth wiring 128 are the first signal line and the second signal, respectively. It may be referred to as a line, a third signal line, a fourth signal line, a fifth signal line, or a sixth signal line. Further, the fourth wiring 124, the sixth wiring 126, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 1
31, the twelfth wiring 132 and the thirteenth wiring 133 are the first power line, the second power line, the third power line, the fourth power line, the fifth power line, and the sixth power supply, respectively. It may be called a wire, a seventh power line.

Next, the operation of the flip-flop shown in FIG. 1A will be described with reference to the timing chart of FIG. 2, FIGS. 3 and 4. Furthermore, the timing chart of FIG. 2 is set during the set period.
The description will be divided into a selection period, a reset period, a first non-selection period, and a second non-selection period. However, the set period, the reset period, the first non-selection period, and the second non-selection period may be collectively referred to as a non-selection period.

The potential of V1 is supplied to the sixth wiring 126 and the ninth wiring 129, and the fourth wiring 1
24, the tenth wiring 130, the eleventh wiring 131, the twelfth wiring 132, and the thirteenth wiring 133 are supplied with the potential of V2. Here, V1> V2.

The first wiring 121, the fifth wiring 125, the eighth wiring 128, the seventh wiring 127, and the second wiring 122 have signals 221, 225, signal 228, and signal 227 shown in FIG. 2, respectively. , Signal 222 is input. Then, from the third wiring 123, the signal 2 shown in FIG. 2 is used.
23 is output. Here, signal 221, signal 225, signal 228, signal 227, signal 2
22 and the signal 223 are digital signals having an H signal potential of V1 (hereinafter, also referred to as H level) and an L signal potential of V2 (hereinafter, also referred to as L level). Further, signal 221 and signal 2
25, signal 228, signal 227, signal 222 and signal 223, respectively, start signal,
It may be referred to as a power clock signal (PCK), a first control clock signal (CCK1), a second control clock signal (CCK2), a reset signal, and an output signal.

However, the first wiring 121, the second wiring 122, the fourth wiring 124 to the thirteenth wiring 133
Various signals, potentials and currents may be input to each.

First, in the set period shown in FIGS. 2 (A) and 3 (A), the signal 221 becomes the H level and the fifth transistor 105 turns on, and since the signal 222 is the L level, the seventh transistor 107 turns off and the signal is signaled. 228 becomes the H level, the second transistor 102 and the fourth transistor 104 turn on, the signal 227 becomes the L level, and the third transistor 103 turns off. At this time, the potential (potential 241) of the node 141 is such that the second electrode of the fifth transistor 105 serves as the source electrode, and the potential of the ninth wiring 129 to the fifth transistor 105.
Since the value is obtained by subtracting the threshold voltage of Vth 105 (Vth 105: the threshold voltage of the fifth transistor 105). Therefore, the first transistor 101 and the eighth transistor 108 are turned on, and the fifth transistor 105 is turned off. Node 1 at this time
The potential of 42 (potential 242) becomes V2, and the sixth transistor 106 is turned off. As described above, during the set period, the third wiring 123 conducts with the fifth wiring 125 to which the L signal is input and the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 is V2. Will be. Therefore, the L signal is output from the third wiring 123. Further, the node 141 is in a floating state while maintaining the potential at V1-Vth105.

As shown in FIG. 5A, the flip-flop of the present embodiment is the same as the set period described above even if the first electrode of the fifth transistor 105 is connected to the first wiring 121. Can perform various operations. Since the flip-flop of FIG. 5A does not require the ninth wiring 129, the yield can be improved. Further, the flip-flop of FIG. 5A can reduce the layout area.

As shown in FIG. 5C, the flip-flop of the present embodiment is the transistor 50.
1 may be newly arranged. In the transistor 501, the first electrode is connected to the wiring 511 to which V2 is supplied, the second electrode is connected to the node 141, and the gate electrode is the first wiring 1.
Connected to 21. In the flip-flop of FIG. 5C, the transistor 501 can shorten the time during which the potential of the node 142 drops, so that the sixth transistor 106 can be turned off quickly. Therefore, in the flip-flop of FIG. 5C, the potential of the node 141 is V1-V.
Since the time until th105 can be shortened, high-speed operation becomes possible, and it can be applied to a larger display device or a higher-definition display device.

In the selection period shown in FIGS. 2B and 3B, the signal 221 becomes the L level, the fifth transistor 105 is turned off, and the signal 222 remains at the L level, so that the seventh transistor 107
Remains off, the signal 228 becomes the L level, the second transistor 102 and the fourth transistor 104 turn off, the signal 227 becomes the H level, and the third transistor 103 turns on. At this time, the node 141 maintains the potential at V1-Vth105. Therefore, the first transistor 101 and the eighth transistor 108 remain on. At this time, the potential of the node 142 is such that the potential difference (V1-V2) between the potential (V2) of the eleventh wiring 131 and the potential (V1) of the sixth wiring 126 is the third transistor 103 and the eighth transistor 108. It is divided by and becomes V2 + β (β: any positive number). Furthermore, β <Vth
It is set to 106 (threshold voltage of the sixth transistor 106). Therefore, the sixth transistor 106 remains off. Here, since the H signal is input to the fifth wiring 125, the third wiring 125
The potential of the wiring 123 of the above begins to rise. Then, the potential of the node 141 rises from V1-Vth105 by the bootstrap operation, and V1 + Vth101 + α (Vth101:
The threshold voltage of the first transistor 101, α: an arbitrary positive number). Therefore, the potential of the third wiring 123 becomes V1 because it has the same potential as the fifth wiring 125. As described above, during the selection period, the third wiring 123 conducts with the fifth wiring 125 to which the H signal is input, so that the potential of the third wiring 123 becomes V1. Therefore, the H signal is the third wiring 1
It is output from 23.

This bootstrap operation is performed by capacitive coupling of parasitic capacitance between the gate electrode of the first transistor 101 and the second electrode. However, as shown in FIG. 1 (B), by arranging the capacitive element 151 between the gate electrode of the first transistor 101 and the second electrode, the bootstrap operation can be stably performed. The parasitic capacitance of the first transistor 101 can be reduced. Here, the capacitive element 151 may use a gate insulating film as the insulating layer and the gate electrode layer and the wiring layer as the conductive layer, or may use the gate insulating film as the insulating layer and use the gate electrode layer and impurities as the conductive layer. A semiconductor layer to which is added may be used, an interlayer film (insulating film) may be used as the insulating layer, and a wiring layer and a transparent electrode layer may be used as the conductive layer.
However, when the capacitive element 151 uses the gate electrode layer and the wiring layer as the conductive film, the gate electrode layer is connected to the gate electrode of the first transistor 101, and the wiring layer is connected to the second electrode of the first transistor 101. You should connect. More preferably, when the gate electrode layer and the wiring layer are used as the conductive film, the gate electrode layer is directly connected to the gate electrode of the first transistor 101, and the wiring layer is directly connected to the second electrode of the first transistor 101. It is good to do. because,
This is because the increase in the layout area of the flip-flop due to the arrangement of the capacitive element 151 becomes small.

Further, as shown in FIG. 1C, the transistor 152 may be used as the capacitive element 151. The transistor 152 can function as a capacitive element having a large capacitive component by connecting the gate electrode to the node 141 and connecting the first electrode and the second electrode to the third wiring 123. However, the transistor 152 can function as a capacitive element even if either the first electrode or the second electrode is suspended.

The first transistor 101 must supply the H signal to the third wiring 123. Therefore, in order to shorten the fall time and rise time of the signal 223, the W / L value of the first transistor 101 is the value of the W / L of each of the first transistor 101 to the eighth transistor 108. It is desirable to maximize it.

Further, since the fifth transistor 105 must have the potential of the node 142 (gate electrode of the first transistor 101) V1-Vth105 during the set period, the value of W / L of the fifth transistor 105 is set. It is 1/2 to 1/5 times, more preferably 1/3 to 1/4 times the value of W / L of the first transistor 101.

Since the potential of the node 142 is V2 + β, the value of the ratio W / L of the channel width W and the channel length L of the eighth transistor 108 is higher than the value of W / L of the third transistor 103. It is preferably at least 10 times or more. Therefore, the eighth transistor 10
The transistor size (W × L) of 8 becomes large. Here, the value of the channel length L of the third transistor 103 is larger than the value of the channel length L of the eighth transistor 108, and more preferably two to three times, so that the transistor of the eighth transistor 108 is used. Since the size can be reduced, the layout area can be reduced.

During the reset period shown in FIGS. 2C and 3C, the signal 221 remains at the L level, so the fifth transistor 105 remains off, the signal 222 becomes the H level, and the seventh transistor 107 turns on. Then, the signal 228 becomes the H level, the second transistor 102 and the fourth transistor 104 turn on, the signal 227 becomes the L level, and the third transistor 10
3 turns off. The potential of the node 141 at this time is V2 because the potential (V2) of the thirteenth wiring 133 is supplied via the seventh transistor 107. Therefore, the first transistor 101 and the eighth transistor 108 are turned off. The potential of the node 142 at this time is V2 because the fourth transistor 104 is turned on. Therefore, the sixth transistor 106 is turned off. As described above, during the reset period, the third wiring 123 conducts with the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 becomes V2. Therefore, the L signal is output from the third wiring 123.

By delaying the timing at which the seventh transistor 107 is turned on, the signal 223
The fall time can be shortened. This is because the L signal input to the fifth wiring 125 is W.
This is because it can be supplied to the third wiring 123 via the first transistor 101 having a large value of / L.

Alternatively, the fall time of the signal 223 can be shortened by reducing the W / L value of the seventh transistor 107 and lengthening the fall time until the potential of the node 141 becomes V2. In this case, the value of the 7th transistor W / L is set to 1/10 to 1/40 times, more preferably 1/20 to 1/30 times the W / L value of the first transistor 101.

As shown in FIG. 5B, the same operation as the set period described above can be performed without the seventh transistor 107. Since the flip-flop of FIG. 5B can reduce the number of transistors and wiring, the layout area can be reduced.

In the first non-selection period shown in FIGS. 2 (D) and 4 (D), since the signal 221 remains at the L level, the fifth transistor 105 remains off, the signal 222 becomes the L level, and the seventh Transistor 107 is turned off, signal 228 becomes L level, and second transistor 10
The second and fourth transistors 104 are turned off, the signal 227 becomes H level, and the third transistor 103 is turned on. At this time, the potential of the node 142 is obtained by subtracting the threshold voltage of the third transistor 103 from the potential (V1) of the seventh wiring 127 with the second electrode of the third transistor 103 as the source electrode. Since it is a value, it becomes V1-Vth103 (Vth103: threshold voltage of the third transistor 103). Therefore, the sixth transistor 106 is turned on. Since the sixth transistor 106 turns on the potential of the node 141 at this time,
It becomes V2. Therefore, the first transistor 101 and the eighth transistor 108 remain off. As described above, in the first non-selection period, the third wiring 123 is in a floating state and the potential is maintained at V2.

The flip-flop of the present embodiment can suppress the shift of the threshold voltage of the second transistor 102 by turning off the second transistor 102.

By setting the potential of the signal 227 to V1 or less and lowering the potential of the gate electrode of the third transistor 103, the shift of the threshold voltage of the third transistor 103 can be suppressed. Further, by setting the potential of the signal 228 to V2 or less and applying a reverse bias to the fourth transistor 104 and the second transistor 102, the threshold voltage of the fourth transistor 104 and the second transistor 102 is shifted. Can be suppressed.

As shown in FIG. 9A, V2 can be supplied to the third wiring 123 by newly arranging the transistor 901. Transistor 901 is a sixth transistor because the first electrode is connected to the fourth wire 124, the second electrode of the transistor 901 is connected to the third wire 123, and the gate electrode is connected to the node 142. On at the same timing as 106
Off is controlled. Therefore, the flip-flop of FIG. 9A can be made resistant to noise because the third wiring 123 does not float. Further, as shown in FIG. 9B, the second
Transistor 901 can also be arranged instead of the transistor 102 of.

In the second non-selection period shown in FIGS. 2 (E) and 4 (E), the fifth transistor 105 remains off because the signal 221 remains at the L level, and the signal 222 remains at the L level. The transistor 107 of 7 remains off, the signal 228 becomes H level, the second transistor 102 and the fourth transistor 104 turn on, the signal 227 becomes L level, and the third transistor 103 turns off. At this time, the potential of the node 142 becomes V2 because the fourth transistor 104 is turned on. Therefore, the sixth transistor 106 is turned off.
At this time, the node 141 is in a floating state, so the potential is maintained at V2. Therefore, the first transistor 101 and the eighth transistor 108 remain off. Thus, the second
During the non-selection period, the third wiring 123 conducts with the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 becomes V2. Therefore, the L signal is the third wiring 123.
Is output from.

The flip-flop of the present embodiment can suppress the shift of the threshold voltage of the sixth transistor 106 by turning off the sixth transistor 106.

The flip-flop of the present embodiment has a third wiring 12 in the second non-selection period.
Even if the potential of 3 fluctuates due to noise, the potential of the third wiring 123 can be set to V2. Further, in the flip-flop of the present embodiment, even if the potential of the node 141 fluctuates due to noise, the potential of the node 141 can be set to V2 in the first non-selection period.

By setting the potential of the signal 227 to V2 or less and applying a reverse bias to the third transistor 103, the shift of the threshold voltage of the third transistor 103 can be suppressed. Further, the potential of the signal 228 is set to V1 or less, and the gate electrode of the fourth transistor 104 and the second
By lowering the potential of the electrode of the transistor 102 of the fourth transistor 104 and the second
It is possible to suppress the shift of the threshold voltage of the transistor 102 of the above.

From the above, the flip-flop of the present embodiment can suppress the threshold shift of the second transistor 102 and the sixth transistor 106, so that the life of the flip-flop can be extended. Further, the flip-flop of the present embodiment can suppress the shift of the threshold voltage of all the transistors, so that the life can be extended. Further, since the flip-flop of the present embodiment is resistant to noise, reliability can be improved.

Here, the functions of the first transistor 101 to the eighth transistor 108 will be described. The first transistor 101 has a function of selecting the timing of supplying the potential of the fifth wiring 125 to the third wiring 123 and raising the potential of the node 141 by the bootstrap operation, and functions as a transistor for bootstrap. do. Second transistor 10
Reference numeral 2 has a function of selecting a timing for supplying the potential of the fourth wiring 124 to the third wiring 123, and functions as a switching transistor. The third transistor 103 is the sixth transistor.
It has a function of selecting the timing of supplying the potential of the wiring 126 to the node 142, and functions as a switching transistor. The fourth transistor 104 is the tenth wiring 130.
It has a function of selecting the timing of supplying the potential of the above to the node 124, and functions as a switching transistor. The fifth transistor 105 has a function of selecting a timing for supplying the potential of the ninth wiring 129 to the node 141, and functions as an input transistor. The sixth transistor 106 has a function of selecting a timing for supplying the potential of the twelfth wiring 132 to the node 141, and functions as a switching transistor. The seventh transistor 107 has a function of selecting a timing for supplying the potential of the thirteenth wiring 133 to the node 141, and functions as a switching transistor. Eighth transistor 10
Reference numeral 8 has a function of selecting a timing for supplying the potential of the eleventh wiring 131 to the node 142, and functions as a switching transistor.

However, the first transistor 101 to the eighth transistor 108 are not limited to the transistors as long as they have the functions described above. For example, a second transistor 102, a fourth transistor 104, a third transistor 103, a fourth transistor 104, a sixth transistor 106, and a seventh transistor 1 functioning as switching transistors.
A diode, a CMOS analog switch, various logic circuits, or the like may be applied to the 07 and the eighth transistor 108 as long as they are elements having a switching function. Further, the fifth transistor 105 that functions as an input transistor may have a function of increasing the potential of the node 141 and selecting a timing to turn it off, and a PN junction diode or a diode-connected transistor may be applied. It is also good.

The arrangement and number of each transistor are not limited to FIG. 1 as long as they operate in the same manner as in FIG. As can be seen from FIGS. 3 and 4 explaining the operation of the flip-flop of FIG. 1, in the present embodiment, the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period are set. It suffices if conduction is established as shown by the solid lines shown in FIGS. 3 (A) to 3 (C), 4 (D), and 4 (E), respectively. Therefore, if a transistor or the like can be arranged and operated so as to satisfy this, a transistor, other elements (resistor element, capacitive element, etc.), diode, switch, various logic circuits, etc. are newly arranged. May be good.

For example, the potential of the node 142 is determined by whether the third transistor 103 is turned on or the fourth transistor 104 is turned on. However, as shown in FIG. 10 (A),
Between the 7th wiring 127 and the 8th wiring 128, the resistance element 1011 and the resistance element 1012
The same operation as in FIG. 1 (A) is possible even if the above is connected. Since the flip-flop of FIG. 10A can reduce the number of transistors and the number of wirings, it is possible to reduce the layout area and improve the yield.

Further, as shown in FIG. 10B, a diode-connected transistor 1021 and a diode-connected transistor 1022 are arranged between the seventh wiring 127 and the node 142 in place of the resistance element 1011, and the eighth wiring 128 is provided. And the diode-connected transistor 1023 and the diode-connected transistor 10 instead of the resistance element 1012 between the and the node 142.
24 may be arranged. The first electrode of the transistor 1021, the gate electrode of the transistor 1021, and the first electrode of the transistor 1022 are connected to the seventh wiring 127, and the first electrode of the transistor 1023 and the transistor 1024 are connected to the eighth wiring 128. The first electrode of the transistor and the gate electrode of the transistor 1024 are connected, and the second electrode of the transistor 1021, the second electrode of the transistor 1022, the gate electrode of the transistor 1022, the second electrode of the transistor 1023, and the transistor are connected to the node 142. The gate electrode of 1023 and the second electrode of the transistor 1024 are connected. That is, the seventh wiring 127 and the node 1
Two diodes are connected in reverse and in parallel, respectively, between the 42 and the eighth wire 128 and the node 142.

The flip-flop drive timing of the present embodiment is not limited to the timing chart of FIG. 2 as long as the operation is the same as that of FIG.

For example, as shown in the timing chart of FIG. 6, the first wiring 121 and the second wiring 122
, The period for inputting the H signal to the fifth wiring 125, the seventh wiring 127, and the eighth wiring 128 may be shortened. In FIG. 6, as compared with the timing chart of FIG. 2, the timing at which the signal switches from the L level to the H level is delayed by the period Ta1, and the timing at which the signal switches from the H level to the L level is earlier by the period Ta2. Therefore, in the flip-flop to which the timing chart of FIG. 6 is applied, the instantaneous current of each wiring becomes small, so that the power can be saved.
It is possible to suppress malfunctions and improve the range of operating conditions. Further, the flip-flop to which the timing chart of FIG. 6 is applied has a third wiring 12 during the reset period.
The fall time of the signal output from 3 can be shortened. This is because the timing at which the potential of the node 141 reaches the L level is delayed by the period Ta1 + the period Ta2, so that the fifth wiring 12
This is because the L signal input to No. 5 is supplied to the third wiring 123 via the first transistor 101 having a large current capacity (large channel width). It should be noted that the common reference numerals are used for the parts common to the timing chart of FIG. 2, and the description thereof will be omitted.

The relationship between the period Ta1, the period Ta2, and the period Tb is ((Ta1 + Tb) / (Ta1 +).
Ta2 + Tb))) × 100 <10 [%] is desirable. More preferably, ((T
It is desirable that a1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 <5 [%].
Further, it is desirable that the period Ta1 ≈ the period Ta2.

The first wiring 121 to the thirteenth wiring 131 can be freely connected as long as the same operation as in FIG. 1 is performed. For example, as shown in FIG. 7A, the second transistor 1
The first electrode of 02, the first electrode of the fourth transistor 104, the sixth transistor 106
The first electrode of the seventh transistor 107, the first electrode of the seventh transistor 107, and the first electrode of the eighth transistor 108 may be connected to the seventh wiring 707. Further, the fifth transistor 105
The first electrode of the third transistor 103 and the first electrode of the third transistor 103 may be connected to the sixth wiring 706. Further, the first electrode of the first transistor 101 and the third transistor 10
The gate electrode of 3 may be connected to the 4th wiring 704. However, as shown in FIG. 7B, the first electrode of the first transistor 101 may be connected to the eighth wiring 708. Further, as shown in FIG. 8A, the first electrode of the third transistor 103 is the ninth wiring 7.
It may be connected to 09. Further, as shown in FIG. 8B, the fourth transistor 104
The first electrode of the above may be connected to the tenth wiring 710. It should be noted that the common reference numerals are used for the parts common to the configuration of FIG. 1, and the description thereof will be omitted.

Since the flip-flop of FIG. 7A can reduce the number of wirings, it is possible to improve the yield, reduce the layout area, improve the reliability, or improve the range of operating conditions. Further, the flip-flop of FIG. 7B can reduce the potential applied to the third transistor 103 and apply a reverse bias, so that the shift of the threshold voltage of the third transistor 103 can be further suppressed. Further, since the flip-flop of FIG. 8A can reduce the potential supplied to the ninth wiring 709, the shift of the threshold voltage of the seventh transistor 107 can be further suppressed. Further, since the flip-flop of FIG. 8B can prevent the current flowing through the third transistor 103 and the fourth transistor 104 from operating the other transistors, it is possible to improve the range of operating conditions. can.

FIG. 29 shows an example of a top view of the flip-flop shown in FIG. 7 (A). The conductive layer 2901 includes a portion that functions as a first electrode of the first transistor 101, and is connected to the fourth wiring 704 via the wiring 2951. The conductive layer 2902 includes a function as a second electrode of the first transistor 101, and is connected to the third wiring 703 via the wiring 2952. The conductive layer 2903 includes the gate electrode of the first transistor 101 and the eighth transistor 10.
8 includes a function as a gate electrode. The conductive layer 2904 includes a portion that functions as a second electrode of the second transistor 102, and is connected to the third wiring 703 via the wiring 2952. The conductive layer 2905 is a first electrode of the second transistor 102 and a fourth transistor 1
It includes the function as the first electrode of 04 and the first electrode of the eighth transistor 108, and is connected to the seventh wiring 707. The conductive layer 2906 includes a function as a gate electrode of the second transistor 102 and a gate electrode of the fourth transistor 104, and is connected to the fifth wiring 705 via the wiring 2953. The conductive layer 2907 is the first of the third transistor 103.
Including the function as an electrode of the above, it is connected to the sixth wiring 706 via the wiring 2954. The conductive layer 2908 includes functions as a second electrode of the third transistor 103, a second electrode of the fourth transistor 104, and a second electrode of the eighth transistor 108. Conductive layer 29
09 includes a function as a gate electrode of the third transistor 103, and is connected to the fourth wiring 704 via the wiring 2955. The conductive layer 2910 includes a function as a first electrode of the fifth transistor 105, and is connected to the sixth wiring 706 via the wiring 2956. The conductive layer 2911 includes a function as a second electrode of the fifth transistor 105 and a second electrode of the seventh transistor 107, and is connected to the conductive layer 2903 via the wiring 2957. The conductive layer 2912 includes a function as a gate electrode of the fifth transistor 105, and the wiring 29
It is connected to the first wiring 701 via 58. The conductive layer 2913 is the sixth transistor 1
It includes a function as a second electrode of 06 and is connected to the conductive layer 2903 via wiring 2595. The conductive layer 2914 includes a function as a gate electrode of the sixth transistor 106, and is connected to the conductive layer 2908 via the wiring 2954. The conductive layer 2915 includes a function as a second electrode of the seventh transistor 107 and is connected to the wiring 707. The conductive layer 2916 includes a function as a gate electrode of the seventh transistor 107, and is connected to the second wiring 702 via the wiring 2960.

The portion of the first transistor 101 that functions as the gate electrode, the first electrode, and the second electrode is a portion formed by overlapping the conductive layer including each and the semiconductor layer 2981. The portion of the second transistor 102 that functions as the gate electrode, the first electrode, and the second electrode is a portion formed by overlapping the conductive layer including each and the semiconductor layer 2982. The portion of the third transistor 103 that functions as the gate electrode, the first electrode, and the second electrode is a portion formed by overlapping the conductive layer including each and the semiconductor layer 2983. The portion of the fourth transistor 104 that functions as the gate electrode, the first electrode, and the second electrode is a portion formed by overlapping the conductive layer including each and the semiconductor layer 2984. The portion of the fifth transistor 105 that functions as the gate electrode, the first electrode, and the second electrode is a portion formed by overlapping the conductive layer including each and the semiconductor layer 2985. The portion of the sixth transistor 106 that functions as the gate electrode, the first electrode, and the second electrode is a portion formed by overlapping the conductive layer including each and the semiconductor layer 2896. The portion of the seventh transistor 107 that functions as the gate electrode, the first electrode, and the second electrode is a portion formed by overlapping the conductive layer including each and the semiconductor layer 2987. Eighth transistor 10
The portion functioning as the gate electrode, the first electrode, and the second electrode of No. 8 is a portion formed by overlapping the conductive layer including each and the semiconductor layer 2988.

Subsequently, the configuration and driving method of the shift register having the flip-flop of the present embodiment described above will be described.

The configuration of the shift register of this embodiment will be described with reference to FIG. The shift register of FIG. 11 has n flip-flops (flip-flops 1101-1 to 1101_n).

The connection relationship of the shift register of FIG. 11 will be described. In the shift register of FIG. 11, in the flip-flop 1101_i of the i-th stage (any one of the flip-flops 1101-1_1 to 1101_n), the first wiring 121 shown in FIG. 1A is the seventh wiring 1117_i-1.
The second wiring 122 shown in FIG. 1A is connected to the seventh wiring 1117_i + 1, and the third wiring 123 shown in FIG. 1A is connected to the seventh wiring 1117_i. Figure 1
The fourth wiring 124, the tenth wiring 130, the eleventh wiring 131, the twelfth wiring 132, and the thirteenth wiring 133 shown in (A) are connected to the fifth wiring 1115, and FIG. 1A is shown. The fifth wiring 125 and the seventh wiring 127 shown in the above are connected to the second wiring 1112 in the odd-stage flip flop and to the third wiring 1113 in the even-stage flip flop.
In the flip-flop in which the eighth wiring 128 shown in FIG. 1A is an odd-numbered flip-flop, the third wiring 11
It is connected to 13, and in the even-numbered flip-flop, it is connected to the second wiring 1112, and FIG.
The sixth wiring 126 and the ninth wiring 129 shown in (A) are connected to the fourth wiring 1114. However, the first wiring 12 shown in FIG. 1 (A) of the first-stage flip flip 1101_1
1 is connected to the first wiring 1111 and is shown in FIG. 1 (A) of the nth stage flip-flop 1101_n.
The second wiring 122 shown in) is connected to the sixth wiring 1116.

The first wiring 1111, the second wiring 1112, the third wiring 1113, and the sixth wiring 11
16 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Further, the fourth wiring 1114 and the fifth wiring 1115 may be referred to as a first power line and a second power line, respectively.

Next, the operation of the shift register shown in FIG. 11 will be described with reference to the timing chart of FIG. 12 and the timing chart of FIG. Here, the timing chart of FIG. 12 is divided into a scanning period and a return period. The scanning period is a period from the start of the output of the selection signal from the 7th wiring 1117_1 to the end of the output of the selection signal from the 7th wiring 1117_n. The return line period is a period from the end of the output of the selection signal from the 7th wiring 1117_n to the start of the output of the selection signal from the 7th wiring 1117_1.

The potential of V1 is supplied to the fourth wiring 1114, and the potential of V2 is supplied to the fifth wiring 1115.

The first wiring 1111, the second wiring 1112, the third wiring 1113, and the sixth wiring 11
16 is the signal 1211, the signal 1212, the signal 1213, and the signal 12 shown in FIG. 12, respectively.
16 is input. Here, signal 1211, signal 1212, signal 1213, signal 1216
Is a digital signal in which the potential of the H signal is V1 (hereinafter, also referred to as H level) and the potential of the L signal is V2 (hereinafter, also referred to as L level). Further, signal 1211, signal 1212, signal 12
13. The signal 1216 may be referred to as a start signal, a first clock signal, a second clock signal (inverted clock signal), and a reset signal, respectively.

However, various signals, potentials, and currents may be input to the first wiring 1111 to the sixth wiring 1116, respectively.

From the 7th wiring 1117_1 to the 7th wiring 1117_n, a digital signal having an H signal potential of V1 (hereinafter, also referred to as H level) and an L signal potential of V2 (hereinafter, also referred to as L level) is emitted. It is output. However, as shown in FIG. 14, signals are output from the seventh wiring 1117_1 to the seventh wiring 1117_n via the buffers 1401_1 to 1401_n, respectively, and the output signal of the shift register and the transfer signal of each flip-flop are separated. Therefore, the range of operating conditions can be increased.

Here, the buffer 1401_1 to the buffer 1401 included in the shift register shown in FIG. 14
An example of _n will be described with reference to FIGS. 15 (A) and 15 (B). In the buffer 8000 shown in FIG. 15A, the inverter 8001a, the inverter 8001b, and the inverter 8001c are connected between the wiring 8011 and the wiring 8012, so that the inverting signal of the signal input to the wiring 8011 is output from the wiring 8012. To. However, wiring 8011 and wiring 801
The number of inverters connected between 2 and 2 is not limited. For example, when an even number of inverters are connected between wiring 8011 and wiring 8012, a signal having the same polarity as the signal input to wiring 8011 is wired 8012. Is output from. Further, as shown in the buffer 8100 of FIG. 15B, the inverters 8002a, 8002b and 8002c connected in series and the inverters 8003a, 8003b and 8003c arranged in series are connected in parallel. It is also good. Since the buffer 8100 of FIG. 15B can average the variation in the characteristics of the transistor, the delay and bluntness of the signal output from the wiring 8012 can be reduced. Further, the outputs of the inverter 8002a and the inverter 8002a, and the outputs of the inverter 8002b and the inverter 8002b may be connected.

In FIG. 15A, it is preferable that the transistor W of the inverter 8001a <W of the transistor of the inverter 8001b <W of the transistor of the inverter 8001c. This is because the W of the inverter 8001a is small, so that the drive capability of the flip-flop (specifically, the value of W / L of the transistor 101 in FIG. 1) can be reduced, so that the shift register of the present invention can reduce the layout area. .. Similarly, FIG.
In 5 (B), the transistor W <inverter 800 of the inverter 8002a has.
It is preferable that W of the transistor possessed by 2b <W of the transistor possessed by the inverter 8002c. Similarly, in FIG. 15B, it is preferable that the transistor W of the inverter 8003a <W of the transistor of the inverter 8003b <W of the transistor of the inverter 8003c. Further, the transistor W of the inverter 8002a = the transistor W of the inverter 8003a, the inverter 800.
It is preferable that W of the transistor included in 2b = W of the transistor possessed by the inverter 8003b, W of the transistor possessed by the inverter 8002c = W of the transistor possessed by the inverter 8003c.

The inverters shown in FIGS. 15A and 15B are not particularly limited as long as they can invert the input signal and output the inverter. For example, as shown in FIG. 15C, the inverter may be configured by the first transistor 8201 and the second transistor 8202. Further, a signal is input to the first wiring, a signal is output from the second wiring 8212, V1 is supplied to the third wiring 8213, and V2 is supplied to the fourth wiring 8214. In the inverter of FIG. 15C, when an H signal is input to the first wiring 8211, V1-
The potential of V2 divided by the first transistor 8201 and the second transistor 8202 (first)
W / L of the transistor 8201 <W / L of the second transistor 8202) is output from the second wiring 8212. Further, in the inverter of FIG. 15C, when the L signal is input to the first wiring 8211, V1-Vth8201 (Vth8201: first transistor 82)
The threshold voltage of 01) is output from the second wiring 8212. Further, the first transistor 8201 may be a PN junction diode as long as it is an element having a resistance component, or may be simply a resistance element.

Further, as shown in FIG. 15D, the inverter may be configured by the first transistor 8301, the second transistor 8302, the third transistor 8303, and the fourth transistor 8304. Further, a signal is input to the first wiring 8311, and the second wiring 8
A signal is output from 312, V1 is supplied to the third wiring 8313 and the fifth wiring 8315, and V2 is supplied to the fourth wiring 8314 and the sixth wiring 8316. FIG. 15 (D
) Inverter inputs V2 to the second wiring 831 when the H signal is input to the first wiring 8311.
Output from 2. At this time, since the node 8341 sets the potential to the L level, the first transistor 8301 is turned off. Further, when the L signal is input to the first wiring 8311, the inverter of FIG. 15D outputs V1 from the second wiring 8312. At this time, node 834
When the potential of 1 becomes V1-Vth8303 (Vth8303: the threshold voltage of the third transistor 8303), the node 8341 becomes a floating state, and the potential of the node 8341 becomes V1 + Vth8301 (Vth8301: the first transistor 8) by the bootstrap operation.
Since it is higher than the threshold voltage of 301), the first transistor 8301 is turned on.
Further, since the first transistor 8301 functions as a bootstrap transistor, a capacitive element may be arranged between the second electrode and the gate electrode.

Further, as shown in FIG. 16A, the inverter may be configured by the first transistor 8401, the second transistor 8402, the third transistor 8403 and the fourth transistor 8404. The inverter of FIG. 16A is a two-input type inverter and can operate as a bootstrap. Further, a signal is input to the first wiring 8411, an inverted signal is input to the second wiring 8412, and a signal is output from the third wiring 8413.
V1 is supplied to the fourth wiring 8414 and the sixth wiring 8416, and V2 is supplied to the fifth wiring 8415 and the seventh wiring 8417. In the inverter of FIG. 16A, when an L signal is input to the first wiring 8411 and an H signal is input to the second wiring 8412, V2 is connected to the third wiring 841.
Output from 3. At this time, since the potential of the node 8441 becomes V2, the first transistor 8401 is turned off. Further, in the inverter of FIG. 16A, H is connected to the first wiring 8411.
When the signal and the L signal are input to the second wiring 8412, V1 is output from the third wiring 8413. At this time, when the potential of the node 8441 becomes V1-Vth8403 (Vth8403: the threshold voltage of the third transistor 8403), the node 8441 becomes a floating state, and the potential of the node 8441 becomes V1 + Vth8401 (Vth84) by the bootstrap operation.
01: Since it is higher than the threshold voltage of the first transistor 8401), the first transistor 8401 is turned on. Further, since the first transistor 8401 functions as a bootstrap transistor, a capacitive element may be arranged between the second electrode and the gate electrode. Further, in one of the first wiring 8411 and the second wiring 8412, FIG. 1 (
The third wiring 123 shown in A) may be connected, and the node 142 shown in FIG. 1A may be connected to the other.

Further, as shown in FIG. 16B, the inverter may be configured by the first transistor 8501, the second transistor 8502, and the third transistor 8503. Figure 1
The inverter of 6 (B) is a 2-input type inverter and can operate as a bootstrap. Further, a signal is input to the first wiring 8511, an inverting signal is input to the second wiring 8512, a signal is output from the third wiring 8513, and the fourth wiring 8514 and the sixth wiring are output.
V2 is supplied to the wiring 8516 of the above, and V2 is supplied to the fifth wiring 8515. FIG. 16
When the L signal is input to the first wiring 8511 and the H signal is input to the second wiring 8512, the inverter (B) outputs V2 from the third wiring 8513. At this time, since the potential of the node 8541 becomes V2, the first transistor 8501 is turned off. Further, in the inverter of FIG. 16B, when an H signal is input to the first wiring 8511 and an L signal is input to the second wiring 8512, V
1 is output from the third wiring 8513. At this time, the potential of the node 8541 is V1-Vth.
When it becomes 8503 (Vth8503: threshold voltage of the third transistor 8503), the node 8541 becomes a floating state, and the potential of the node 8541 becomes V1 + Vth8501 (Vth8501: the threshold voltage of the first transistor 8501) due to the bootstrap operation.
The first transistor 8501 is turned on because it is higher than. Further, since the first transistor 8501 functions as a bootstrap transistor, a capacitive element may be arranged between the second electrode and the gate electrode. Further, the third wiring 123 shown in FIG. 1A is connected to one of the first wiring 8511 and the second wiring 8512, and the other is shown in FIG.
The node 142 shown in (A) may be connected.

Further, as shown in FIG. 16C, the inverter may be configured by the first transistor 8601, the second transistor 8602, the third transistor 8603 and the fourth transistor 8604. The inverter shown in FIG. 16C is a two-input type inverter and can operate as a bootstrap. Further, a signal is input to the first wiring 8611, an inverted signal is input to the second wiring 8612, and a signal is output from the third wiring 8613.
V1 is supplied to the fourth wiring 8614, and V2 is supplied to the fifth wiring 8615 and the sixth wiring 8616. In the inverter of FIG. 16A, the L signal is connected to the first wiring 8611 and the second wiring is used.
When the H signal is input to the wiring 8612 of the above, V2 is output from the third wiring 8613. At this time, since the potential of the node 8641 becomes V2, the first transistor 8601 is turned off.
Further, in the inverter of FIG. 16C, the H signal is connected to the first wiring 8611 and the second wiring 861 is used.
When the L signal is input to 2, V1 is output from the third wiring 8613. At this time, node 8
When the potential of 641 becomes V1-Vth8603 (Vth8603: threshold voltage of the third transistor 8603), the node 8641 becomes a floating state, and the potential of the node 8641 becomes V1 + Vth8601 (Vth8601: the threshold voltage of the first transistor 8601) by the bootstrap operation. Since it is higher than the threshold voltage), the first transistor 8601 is turned on. Further, since the first transistor 8601 functions as a bootstrap transistor, a capacitive element may be arranged between the second electrode and the gate electrode. Furthermore, the first
In one of the wiring 8611 and the second wiring 8612, the third wiring 1 shown in FIG. 1 (A) is used.
23 may be connected, and the node 142 shown in FIG. 1 (A) may be connected to the other.

The seventh wiring 1117_i-1 is used as a start signal for the flip-flop 1101_i.
The signal output from is used, and the signal output from the seventh wiring 1117_i + 1 is used as the reset signal. Here, the start signal of the flip-flop 1101_1 is input from the first wiring 1111, and the reset signal of the flip-flop 1101_n is the sixth wiring 11.
It is input from 16. However, as the reset signal of the flip-flop 1101_n, the signal output from the seventh wiring 1117_1 may be used, or the signal output from the seventh wiring 1117_2 may be used. Alternatively, a dummy flip-flop may be newly arranged and the output signal of the dummy flip-flop may be used. By doing so, the number of wires and the number of signals can be reduced.

As shown in FIG. 13, for example, when the flip-flop 1101_i becomes the selection period, the seventh
The H signal (selection signal) is output from the wiring 1117_i of. At this time, the flip-flop 1101_i + 1 is the set period. After that, the flip-flop 1101_i becomes the reset period, and the L signal is output from the seventh wiring 1117_i. At this time, the flip-flop 1101_i + 1 is the selection period. After that, the flip-flop 1101_i becomes the first non-selection period, the seventh wiring 1117_i becomes floating, and the potential is maintained at V2. At this time, the flip-flop 1101_i + 1 is the reset period. After that, the flip-flop 1101_i becomes the second non-selection period, and the L signal is output from the seventh wiring 1117_i. At this time, the flip-flop 1101_i + 1 becomes the first non-selection period period.

In this way, the shift register of FIG. 11 sends the selection signal to the seventh wiring 1117_1 in order from the seventh wiring 1117_1.
Wiring 1117_n can be output. That is, the shift register in FIG. 11 is the seventh wiring 1.
It is possible to scan 117_1 to the seventh wiring 717_n.

Further, the shift register to which the flip-flop of the present embodiment is applied can suppress the shift of the threshold voltage of the transistor, so that the life can be extended. Further, the shift register to which the flip-flop of the present embodiment is applied can improve the reliability. Further, the shift register to which the flip-flop of the present embodiment is applied can suppress malfunction.

Further, since the shift register to which the flip-flop of the present embodiment is applied can operate at high speed, it can be applied to a higher-definition display device or a larger display device. Further, the shift register to which the flip-flop of the present embodiment is applied can simplify the process. Further, the shift register to which the flip-flop of the present embodiment is applied can reduce the manufacturing cost. Further, the shift register to which the flip-flop of the present embodiment is applied can improve the yield.

Subsequently, the structure and driving method of the display device having the shift register of the present embodiment described above will be described. However, the display device of the present embodiment may have at least the flip-flop of the present embodiment.

The configuration of the display device of this embodiment will be described with reference to FIG. The display device of FIG. 17 has a signal line drive circuit 1701, a scan line drive circuit 1702, and a pixel unit 1704, and the pixel unit 1704 has a plurality of signals extended in the column direction from the signal line drive circuit 1701. Line S
1 to Sm, a plurality of scanning lines G1 to arranged extending in the row direction from the scanning line drive circuit 1702
It has a plurality of pixels 1703 arranged in a matrix corresponding to Gn, signal lines S1 to Sm, and scanning lines G1 to Gn. Then, each pixel 1703 has a signal line Sj (signal lines S1 to S).
It is connected to any one of m) and the scanning line Gi (any one of the scanning lines G1 to Gn). Further, the scanning line drive circuit 1702 may be referred to as a drive circuit.

The shift register of the present embodiment can be applied as the scanning line drive circuit 1702. Of course, the shift register of the present embodiment may also be used for the signal line drive circuit 1701.

The scanning lines G1 to Gn are connected to the seventh wiring 1117_1 to the seventh wiring 1117_n shown in FIGS. 11 and 14.

The signal line and the scanning line may be simply referred to as wiring. Furthermore, the signal line drive circuit 1701
And the scanning line drive circuit 1702 may be referred to as a drive circuit, respectively.

The pixel 1703 has at least one switching element, one capacitive element, and a pixel electrode. However, the pixel 1703 may have a plurality of switching elements or a plurality of capacitive elements. Moreover, capacitive elements are not always necessary. In addition, pixel 1703
May further have a transistor operating in the saturation region. In addition, pixel 1703
May have a display element such as a liquid crystal element or an EL element. Here, a transistor and a PN junction diode can be used as the switching element. However, when a transistor is used as the switching element, it is desirable that the transistor operates in a linear region. Further, when the scanning line drive circuit 1702 is composed of only N-channel type transistors, it is desirable to use N-channel type transistors as switching elements. Further, when the scanning line drive circuit 1702 is composed of only P-channel type transistors, it is desirable to use P-channel type transistors as switching elements.

The scanning line drive circuit 1702 and the pixel portion 1704 are formed on the insulating substrate 1705, and the signal line driving circuit 1701 is not formed on the insulating substrate 1705. The signal line drive circuit 1701 is formed on a single crystal substrate, an SOI substrate, or an insulating substrate different from the insulating substrate 1705. Then, the signal line drive circuit 1701 is connected to the signal line S via a printed circuit board such as an FPC.
It is connected to 1 to Sm. However, the signal line drive circuit 1701 may be formed on the insulating substrate 1705, and the circuit constituting a part of the function of the signal line drive circuit 1701 may be formed on the insulating substrate 17.
It may be formed on 05.
The wiring, electrodes, conductive layer, conductive film, terminals, etc. are made of aluminum (Al) and tantalum (T).
a), Titanium (Ti), Molybdenum (Mo), Tungsten (W), Neodymium (Nd)
, Chromium (Cr), Nickel (Ni), Platinum (Pt), Gold (Au), Silver (Ag), Copper (C)
u), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn)
, Niob (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O). One or more elements selected from, or compounds, alloy materials (eg, indium tin oxide (ITO), indium zinc oxide (IZO) containing one or more elements selected from the above group. ), Indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO),
It is preferably formed of tin oxide (SnO), cadmium oxide (CTO), aluminum neodymium (Al-Nd), silver magnesium (Mg-Ag), molybdenum niobium (Mo-Nb), etc.). Alternatively, it is desirable that the wiring, the electrode, the conductive layer, the conductive film, the terminal, etc. are formed by having a substance or the like in which these compounds are combined. Alternatively, one or more elements selected from the above group and a compound of silicon (SiO) (for example, aluminum silicon, molybdenum silicon, nickel silicide, etc.), one or more elements selected from the above group and nitrogen. It is desirable to have a compound (for example, titanium nitride, tantalum nitride, molybdenum nitride, etc.).

For silicon (Si), n-type impurities (phosphorus, etc.) or p-type impurities (boron, etc.)
May include. Since silicon contains impurities, the conductivity is improved and it becomes possible to behave in the same manner as a normal conductor. Therefore, it becomes easy to use as wiring, electrodes, and the like.

Silicon is single crystal, polycrystal (polysilicon), amorphous (amorphous silicon).
, Silicon having various crystallinity such as microcrystal (microcrystal silicon) can be used. Wiring, electrodes, by using single crystal silicon or polycrystalline silicon,
The resistance of the conductive layer, the conductive film, the terminal, etc. can be reduced. By using amorphous silicon or microcrystalline silicon, wiring or the like can be formed in a simple process.

Since aluminum or silver has high conductivity, signal delay can be reduced.
Further, since it is easy to etch, it is easy to pattern and fine processing can be performed.

Since copper has high conductivity, signal delay can be reduced. When using copper,
In order to improve the adhesion, it is desirable to have a laminated structure.

It should be noted that molybdenum or titanium is desirable because it has advantages such as no defects even when it comes into contact with an oxide semiconductor (ITO, IZO, etc.) or silicon, easy etching, and high heat resistance.

Tungsten is desirable because it has advantages such as high heat resistance.

Neodymium is desirable because it has advantages such as high heat resistance. In particular, when an alloy of neodymium and aluminum is used, heat resistance is improved and aluminum is less likely to hillock.

It should be noted that silicon is desirable because it has advantages such as being able to be formed at the same time as the semiconductor layer of the transistor and having high heat resistance.

In addition, ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (S)
Since nO) and tin oxide cadmium (CTO) have translucency, they can be used for a portion through which light is transmitted. For example, it can be used as a pixel electrode or a common electrode.

IZO is desirable because it is easy to etch and process. It is unlikely that IZO will leave a residue when it is etched. Therefore, when IZO is used as the pixel electrode, it is possible to reduce the occurrence of defects (short circuit, misalignment, etc.) in the liquid crystal element and the light emitting element.

The wiring, electrodes, conductive layer, conductive film, terminals and the like may have a single-layer structure or a multi-layer structure. By adopting a single-layer structure, it is possible to simplify the manufacturing process of wiring, electrodes, conductive layers, conductive films, terminals, etc., reduce the number of process days, and reduce the cost. Alternatively, by forming a multi-layer structure, it is possible to utilize the advantages of each material, reduce the disadvantages, and form wirings, electrodes, etc. with good performance. For example, by including a low resistance material (aluminum or the like) in the multilayer structure, it is possible to reduce the resistance of the wiring. Further, by forming a laminated structure in which a low heat resistant material is sandwiched between high heat resistant materials, it is possible to increase the heat resistance of wiring, electrodes, etc. while taking advantage of the low heat resistant material. For example, it is desirable to have a laminated structure in which a layer containing aluminum is sandwiched between layers containing molybdenum, titanium, neodymium, and the like.

In addition, when wiring, electrodes, etc. are in direct contact with each other, they may adversely affect each other. For example, one wiring, electrode, etc. gets into the material such as the other wiring, electrode, etc., and changes the properties, so that the original purpose cannot be achieved, a high resistance part is formed, or it is manufactured. Occasionally, problems may occur that prevent it from being manufactured normally. In such a case
A material that easily reacts due to the laminated structure may be sandwiched or covered with a material that does not easily react. For example, when connecting ITO and aluminum, it is desirable to sandwich a titanium, molybdenum, or neodymium alloy between ITO and aluminum. When connecting silicon and aluminum, it is desirable to sandwich a titanium, molybdenum, or neodymium alloy between ITO and aluminum.

The wiring means that the conductor is arranged. It may extend linearly, or it may be arranged short without extending. Therefore, the electrodes are included in the wiring.

The wiring and electrodes described above can also be applied to other display devices, shift registers, and pixels.

The signal line drive circuit 1701 inputs a voltage or a current as a video signal to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. Further, in the video signal, the positive electrode and the negative electrode may be inverted for each frame (frame inversion drive), or the positive electrode and the negative electrode may be inverted for each row (gate line inversion drive), and for each column. Positive electrode ・
The negative electrode may be inverted (source line inversion drive), or the positive electrode / negative electrode may be inverted for each row and column (dot line inversion drive). Further, the video signal may be input to the signal lines S1 to Sm by point-sequential drive or may be input by line-sequential drive. Further, the signal line drive circuit 1701 applies not only a video signal but also a constant voltage such as a precharge voltage to the signal lines S1 to Sm.
You may enter in. It is desirable to input a constant voltage such as a precharge voltage every 1 gate selection period and every 1 frame.

The scanning line drive circuit 1702 inputs signals to the scanning lines G1 to Gn, and the scanning lines G1 to Gn.
Are selected in order from the first line (hereinafter, also referred to as scanning). Then, the scanning line drive circuit 170
2 selects a plurality of pixels 1703 connected to the selected scan line. Here, the period in which one scanning line is selected is referred to as a one-gate selection period, and the period in which the scanning line is not selected is referred to as a non-selection period. Further, the signal output by the scanning line drive circuit 1702 to the scanning line is called a scanning signal. Further, the maximum value of the scanning signal is larger than the maximum value of the video signal or the maximum voltage of the signal line, and the minimum value of the scanning signal is smaller than the minimum value of the video signal or the minimum voltage of the signal line.

When the pixel 1703 is selected, a video signal is input from the signal line drive circuit 1701 to the pixel 1703 via the signal line. Further, when the pixel 1703 is not selected, the pixel 1703 holds the video signal (potential corresponding to the video signal) input during the selection period.

Although not shown, a plurality of potentials and a plurality of signals are supplied to the signal line drive circuit 1701 and the scan line drive circuit 1702.

Next, the operation of the display device shown in FIG. 17 will be described with reference to the timing chart of FIG. Further, in FIG. 18, one frame period corresponding to a period for displaying an image for one screen is shown. However, the period of one frame is not particularly limited, but it is preferably at least 1/60 second or less so that the viewer of the image does not feel flicker.

In the timing chart of FIG. 18, the scanning lines G1 on the first line and the scanning lines Gi and i on the i-th line are shown.
The timing at which the scanning line Gi + 1 on the +1st line and the scanning line Gn on the nth line are selected is shown.

In FIG. 18, for example, the scan line Gi on the i-th line is selected, and a plurality of pixels 1703 connected to the scan line Gi are selected. Then, each of the plurality of pixels 1703 connected to the scanning line Gi inputs a video signal and holds a potential corresponding to the video signal. After that, the scan line Gi on the i-th line is deselected, the scan line Gi + 1 on the i + 1 line is selected, and a plurality of pixels 1703 connected to the scan line Gi + 1 are selected. Then, each of the plurality of pixels 1703 connected to the scanning line Gi + 1 inputs a video signal and holds a potential corresponding to the video signal. In this way, in one frame period, the scanning lines G1 to the scanning lines Gn are sequentially selected, and the pixels 1703 connected to each scanning line are also selected in order. Then, each of the plurality of pixels 1703 connected to each scanning line inputs a video signal and holds a potential corresponding to the video signal.

Further, since the display device using the shift register of the present embodiment as the scanning line drive circuit 1702 can operate at high speed, higher definition or larger size can be achieved. Further, the display device of the present embodiment can simplify the process. Further, the display device of the present embodiment can reduce the manufacturing cost. Further, the display device of the present embodiment can improve the yield.

Further, in the display device of FIG. 17, since the signal line drive circuit 1701 that requires high-speed operation and the scan line drive circuit 1702 and the pixel unit 1703 are formed on separate substrates, the scan line drive circuit 17
Amorphous silicon can be used as the semiconductor layer of the transistor included in 02 and the semiconductor layer of the transistor included in the pixel 1703. Therefore, the display device of FIG. 17 can simplify the manufacturing process. Further, the display device of FIG. 17 can reduce the manufacturing cost. Further, the display device of FIG. 17 can improve the yield. Further, the display device of FIG. 17 can be increased in size. Alternatively, the display device of FIG. 17 can simplify the manufacturing process by using polysilicon or polycrystalline silicon as the semiconductor layer of the transistor.

When the signal line drive circuit 1701 and the scan line drive circuit 1702 and the pixel 1703 are formed on the same substrate, the transistor semiconductor layer of the scan line drive circuit 1702 and the transistor semiconductor layer of the pixel 1703 are poly. Silicon or polysilicon may be used.

As shown in FIG. 17, if the pixels can be selected and the video signal can be written independently to the pixels, the number and arrangement of the drive circuits are not limited to FIG.

For example, as shown in FIG. 19, the scanning lines G1 to Gn are the first scanning line drive circuit 1902.
It may be scanned by a and the second scanning line drive circuit 1902b. The first scan line drive circuit 1902a and the second drive circuit 1902b are the scan line drive circuit 1702 shown in FIG.
It has the same configuration as the above, and scans the scanning lines G1 to Gn at the same timing. Further, the first scanning line drive circuit 1902a and the second drive circuit 1902b may be referred to as a first drive circuit and a second drive circuit, respectively.

The display device of FIG. 19 includes a first scanning line driving circuit 1902a and a second scanning line driving circuit 190.
Even if a defect occurs in one of the 2bs, the other of the scan line drive circuit 1902a and the second scan line drive circuit 1902b can scan the scan lines G1 to Gn, so that redundancy can be obtained. Further, the display device of FIG. 19 shows the load of the first scanning line drive circuit 1902a (wiring resistance of the scanning line and the parasitic capacitance of the scanning line) and the load of the second scanning line drive circuit 1902b.
Since it can be reduced to about half of that of the above, the delay and bluntness of the signals input to the scanning lines G1 to Gn (the output signals of the first scanning line drive circuit 1902a and the second driving circuit 1902b) can be reduced. Further, the display device of FIG. 19 shows the load of the first scanning line drive circuit 1902a and the second scanning line drive circuit 1902a.
Since the load of the scanning line drive circuit 1902b is reduced, the scanning lines G1 to Gn can be scanned at high speed. Further, since the scanning lines G1 to Gn can be scanned at high speed, it is possible to increase the size of the panel or increase the definition of the panel. It should be noted that the common reference numerals are used for the parts common to the configuration of FIG. 17, and the description thereof will be omitted.

As another example, FIG. 20 is a display device capable of writing a video signal to a pixel at high speed. In the display device of FIG. 20, a video signal is input to the odd-numbered row pixel 1703 from the odd-numbered column signal line, and the video signal is input to the even-numbered row pixel 1703 from the even-numbered column signal line. Further, in the display device of FIG. 20, in the scanning line G1 to the scanning line Gn, the scanning line of the odd-order stage is scanned by the first scanning line drive circuit 2002a, and the scanning line of the scanning line G1 to the scanning line Gn of the even-th stage is scanned. The scan line is scanned by the second scan line drive circuit 2002b. Further, the start signal input to the first scan line drive circuit 2002b is input with a delay of 1/4 cycle of the clock signal from the start signal input to the first scan line drive circuit 2002a.

The display device of FIG. 20 can perform dot inversion drive only by inputting a positive electrode video signal and a negative electrode video signal for each row in each signal line in one frame period. Further, the display device of FIG. 20 can drive the frame inversion by inverting the polarity of the video signal input to each signal line for each frame period.

The operation of the display device of FIG. 20 will be described with reference to the timing chart of FIG. In the timing chart of FIG. 21, the scanning lines G1 on the first line and the scanning lines Gi-1 and i on the first line are shown.
The timing at which the scanning line Gi of the line, the scanning line Gi + 1 of the i + 1 line, and the scanning line Gn of the nth line are selected is shown. Further, in the timing chart of FIG. 21, one selection period is divided into a selection period a and a selection period b. Further, in the timing chart of FIG. 21, a case where the display device of FIG. 20 performs dot inversion drive and frame inversion drive will be described.

In FIG. 21, for example, the selection period a of the scanning line Gi on the i-th line is the scanning line Gi- on the i-1th line.
It overlaps with the selection period b of 1, and the selection period Tb of the scan line Gi on the i-th line overlaps with the selection period a of the scan line Gi + 1 on the i + 1 line. Therefore, in the selection period a, the same video signal as the video signal input to the pixel 1703 in the i-1 row and j + 1 column is input to the pixel 1703 in the i row and j column. Further, in the selection period b, the same video signal as the video signal input to the pixel 1703 in the i-th row and j-th column is input to the pixel 1703 in the i + 1 row and j + 1-th column.
The video signal input to the pixel 1703 in the selection period b is the original video signal, and the video signal input to the pixel 1703 in the selection period a is the video signal for precharging the pixel 1703. Therefore, each of the pixels 1703 is precharged by the video signal input to the pixels 1703 in the i-1 row and j + 1 column in the selection period a, and then the original (i row and j column) video in the selection period b. Enter the signal.

From the above, since the display device of FIG. 20 can write a video signal to the pixel 1703 at high speed, it is possible to easily realize an increase in size or high definition. Further, in the display device of FIG. 20, since a video signal having the same polarity is input to each signal line in one frame period, charging / discharging of each signal line is small, and low power consumption can be realized. Further, in the display device of FIG. 20, since the load of the IC for inputting the video signal is significantly reduced, the heat generated by the IC and I
The power consumption of C can be reduced. Further, since the display device of FIG. 20 can reduce the drive frequencies of the first scan line drive circuit 2002a and the second scan line drive circuit 2002b to about half, power saving can be achieved.

The display device of the present embodiment can perform various driving methods depending on the configuration and driving method of the pixels 1703. For example, the scan line drive circuit may scan the scan line a plurality of times in one frame period.

In addition, the display device of FIGS. 17, 19 and 20 may add another wiring or the like depending on the configuration of the pixel 1703. For example, a power line, a capacitance line, a new scanning line, etc., which are kept at a constant potential, may be added. However, when a scan line is newly added, a scan line drive circuit to which the shift register of the present embodiment is applied may be newly added. As another example, a dummy scanning line, a signal line, a power line, or a capacitance line may be arranged in the pixel portion.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 2)
In the present embodiment, a flip-flop different from that of the first embodiment, a drive circuit having the flip-flop, and a configuration and a driving method of a display device having the drive circuit will be described. It should be noted that the same parts as those in the first embodiment are shown by using a common reference numeral, and detailed description of the same part or the part having the same function will be omitted.

As the flip-flop configuration of the present embodiment, the same flip-flop configuration as that of the first embodiment can be used. However, the timing for driving the flip-flop is the first embodiment.
Is different. Therefore, in the present embodiment, the description of the flip-flop configuration will be omitted.

A case where the drive timing of this embodiment is applied to FIG. 1A will be described.
The drive timings of this embodiment are shown in FIGS. 1 (B), 1 (C), 5 (A), 5 (B), 5 (C), 7 (A), 7 (B), and FIG. 8 (A), 8 (B), 9 (A), 9 (B)
, Can be freely combined with the flip-flops of FIGS. 10 (A) and 10 (B). Further, the drive timing of the present embodiment can be freely combined with the drive timing described in the first embodiment.

The operation of the flip-flop of the present embodiment will be described with reference to the flip-flop of FIG. 1A and the timing chart of FIG. 22. Further, the timing chart of FIG. 22 will be described by dividing it into a set period, a selection period, a reset period, a first non-selection period, and a second non-selection period. However, the set period is divided into a first set period and a second set period.
The selection period is divided into a first selection period and a second selection period.

The first wiring 121, the fifth wiring 125, the eighth wiring 128, the seventh wiring 127, and the second wiring 122 have signals 2221, signal 2225, and signal 222 shown in FIG. 22, respectively.
8. Signal 2227 and signal 2222 are input. Then, from the third wiring 123, FIG. 2
The signal 2223 shown in 2 is output. Here, signal 2221, signal 2225, signal 222
8. The signal 2227, the signal 2222, and the signal 2223 are digital signals having an H signal potential of V1 (hereinafter, also referred to as H level) and an L signal potential of V2 (hereinafter, also referred to as L level). Further, the signal 2221, the signal 2225, the signal 2228, the signal 2227, the signal 2222, and the signal 2223 are combined with the start signal, the power clock signal (PCK), the first control clock signal (CCK1), and the second control clock signal (CCK2), respectively. ), Reset signal, output signal.

The flip-flop of the present embodiment basically operates in the same manner as the flip-flop described in the first embodiment. However, the flip-flop of the present embodiment is different from the flip-flop of the first embodiment in that the timing at which the H signal is input to the first wiring 121 is delayed by 1/4 cycle of the clock signal.

The flip-flop of the present embodiment has a first set period (A1), a second set period (A2), a reset period (C), a first non-selection period (D), and a first set period (D) shown in FIG. In the second non-selection period, the second non-selection period (E), the set period (A), the reset period (C), the first non-selection period (D), and the second non-selection period (D) shown in FIG. 2, respectively. Since the operation is the same as that of the period, the description thereof will be omitted.

In the flip-flop of the present embodiment, in the first selection period shown in FIG. 22 (B1), the node 141 is operated by the bootstrap operation while the H signal is input to the first wiring 121.
The potential of is V1 + Vth101 + α, and the H signal is output from the third wiring 123.
In the flip-flop of the present embodiment, the signal input to the first wiring 121 becomes the L level in the second selection period shown in FIG. 22 (B2), but the node 141 has a potential of V.
It is maintained at 1 + Vth101 + α, and the H signal is still output from the third wiring 123.

As shown in FIG. 23, the flip-flop of the present embodiment has H in the second wiring 122.
By delaying the signal input timing by 1/4 cycle of the clock signal, the fall time of the output signal can be significantly shortened. That is, in the flip-flop of the present embodiment to which FIG. 22 is applied, an L signal is input to the fifth wiring 125 in the first reset period shown in FIG. 22 (C1), and the potential of the node 141 is approximately up to V1 + Vth101. Go down. Therefore, the first transistor 101 remains on and the L signal is the third wiring 1.
It is output from 23. Since the L signal is input to the third 123 via the first transistor 101 having a large W / L value, the time required for the potential of the third wiring 123 to change from the H level to the L level is significantly increased. Can be shortened. After that, the flip-flop of the present embodiment to which FIG. 22 is applied is the seventh transistor 107 in the second reset period shown in FIG. 22 (C2).
Turns on and the potential of node 141 becomes V2. The potential of the node 142 at this time is V1-
Since the third transistor 103 is turned on as Vth 103, the L signal is the third wiring 1.
It is output from 03.

As with the flip-flop shown in the first embodiment, the flip-flop of the present embodiment can suppress the shift of the threshold voltage of the transistor, so that the life of the flip-flop can be extended. Further, since the flip-flop of the present embodiment is resistant to noise, the reliability is improved.
Alternatively, it is possible to suppress malfunction.

Further, since the flip-flop of the present embodiment can operate at high speed, it can be applied to a higher-definition display device or a larger display device. Further, the flip-flop of the present embodiment can simplify the process. Further, the flip-flop of the present embodiment can reduce the manufacturing cost. Further, the flip-flop of the present embodiment can improve the yield.

Subsequently, the configuration and driving method of the shift register having the flip-flop of the present embodiment described above will be described.

The configuration of the shift register of this embodiment will be described with reference to FIG. 24. The shift register of FIG. 24 has n flip-flops (flip-flops 2401_1 to 2401_n).

The connection relationship of the shift register of FIG. 24 will be described. In the shift register of FIG. 24, in the flip-flop 2401_i of the i-th stage (any one of the flip-flops 2401_1 to 2401_n), the first wiring 121 shown in FIG. 1A is the tenth wiring 2420_i-.
The second wiring 122 shown in FIG. 1A is connected to the tenth wiring 2420_i + 2, and the third wiring 123 shown in FIG. 1A is connected to the tenth wiring 2420_i. The fourth wiring 124, the tenth wiring 130, the eleventh wiring 131, the twelfth wiring 132, and the thirteenth wiring 133 shown in FIG. 1A are connected to the seventh wiring 2417, and FIG. (A)
The fifth wiring 125 and the seventh wiring 127 shown in the above are connected to the second wiring 2412 in the flip-flop of the 4N-3 (N is a natural number of 1 or more) stage, and are connected to the second wiring 2412 in the flip-flop of the 4N-2 stage. It is connected to the third wiring 2413, connected to the fourth wiring 2414 in the 4N-1st stage flip-flop, and connected to the fifth wiring 2415 in the 4Nth stage flip-flop.
The eighth wiring 128 shown in FIG. 1A is connected to the fourth wiring 2414 in the 4N-3rd stage flip-flop, and is connected to the fifth wiring 2415 in the 4N-2nd stage flip-flop. The 4N-1st stage flip-flop is connected to the second wiring 2412, and the 4Nth stage flip-flop is connected to the third wiring 2413, and the sixth wiring 126 shown in FIG. 1 (A).
And the ninth wire 129 is connected to the sixth wire 2416. However, the first wiring 121 shown in FIG. 1 (A) of the first-stage flip-flop 2401_1 is connected to the first wiring 2411, and in FIG. 1 (A) of the n-1th-stage flip-flop 2401_n-1. Second wiring shown 12
2 is connected to the ninth wiring 2419, and FIG. 1 (A) of the nth stage flip-flop 2401_n.
The second wiring 122 shown in) is connected to the eighth wiring 2418.

However, when the timing chart of FIG. 23 is applied to the flip-flop of the present embodiment, the second wiring 122 shown in FIG. 1 (A) of the flip-flop 2401_i of the i-th stage is connected to the tenth wiring 2420_i + 3. Will be done. Therefore, the second wiring 122 shown in FIG. 1 (A) of the flip-flop 1801_n-3 in the n-3rd stage is connected to the newly added wiring.

The first wiring 2411, the second wiring 2412, the third wiring 2413, and the fourth wiring 19
14, the fifth wiring 2415, the eighth wiring 2424, and the ninth wiring 2419 are each the first.
Signal line, second signal line, third signal line, fourth signal line, fifth signal line, sixth signal line,
It may be called the seventh wiring. Further, the sixth wiring 2416 and the seventh wiring 2417 may be referred to as a first power line and a second power line, respectively.

Next, the operation of the shift register shown in FIG. 18 will be described with reference to the timing chart of FIG. 25 and the timing chart of FIG. 26. Here, the timing chart of FIG. 25 is divided into a scanning period and a return period.

The potential of V1 is supplied to the fourth wiring 2416, and the potential of V2 is supplied to the fifth wiring 2417.

The first wiring 2411, the second wiring 2412, the third wiring 2413, and the fourth wiring 25
14, the fifth wiring 2415, the eighth wiring 2418, and the ninth wiring 2419 have the signal 2511, the signal 2512, the signal 2513, the signal 2514, and the signal 2515 shown in FIG. 25, respectively.
The signal 2518 and the signal 2519 are input. Here, in the signal 2511, the signal 2512, the signal 2513, the signal 2514, the signal 2515, the signal 2518, and the signal 2519, the potential of the H signal is V1 (hereinafter, also referred to as H level), and the potential of the L signal is V2 (hereinafter, L). It is a digital signal (also called a level). Further, signal 2511, signal 2512, signal 2513, signal 251
4. Signal 2515, signal 2518, signal 2519 are the start signal, the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the first reset signal, and the second reset, respectively. It may be called a signal.

However, various signals, potentials and currents may be input to the first wiring 2411 to the ninth wiring 2419, respectively.

From the tenth wiring 2420_1 to the tenth wiring 2420_n, a digital signal having an H signal potential of V1 (hereinafter, also referred to as H level) and an L signal potential of V2 (hereinafter, also referred to as L level) is emitted. It is output. Further, as in the first embodiment, the tenth wiring 2420
By connecting buffers to the _1 to 10th wirings 2420_n, the range of operating conditions can be increased.

The tenth wiring 2420_i- is used as a start signal for the flip-flop 2401_i.
The signal output from 1 is used, and the signal output from the tenth wiring 2420_i + 2 is used as the reset signal. Here, the start signal of the flip-flop 2401_1 is input from the first wiring 2411, the second reset signal of the flip-flop 2401_n-1 is input from the ninth wiring 2419, and the first reset signal of the flip-flop 2401_n is. It is input from the eighth wiring 2418. However, the signal output from the tenth wiring 2420_1 is used as the second reset signal of the flip-flop 2401_n-1, and the signal output from the tenth wiring 2420_1 is used as the first reset signal of the flip-flop 2401_n. You may use it. Alternatively, the signal output from the tenth wiring 2420_2 is used as the second reset signal of the flip-flop 2401_n-1, and the signal output from the tenth wiring 2420_3 is used as the first reset signal of the flip-flop 2401_n. You may use it. Alternatively, a first dummy flip-flop and a second dummy flip-flop are newly arranged, and the output signal of the first dummy flip-flop and the output signal of the second dummy flip-flop are each first. It may be used as a reset signal of the above and a second reset signal. By doing so, the number of wires and the number of signals can be reduced.

As shown in FIG. 26, for example, when the flip-flop 2401_i is in the first selection period, an H signal (selection signal) is output from the tenth wiring 2420_i. At this time, the flip-flop 2401_i + 1 becomes the second set period. Then flip-flop 240
When 1_i becomes the second selection period, the H signal is still output from the wiring 2420_i of the wiring 10. At this time, the flip-flop 2401_i + 1 becomes the first selection period. After that, when the flip-flop 2401_i reaches the reset period, the tenth wiring 2420_
The L signal is output from i. At this time, the flip-flop 2401_i + 1 becomes the second selection period. After that, when the flip-flop 2401_i becomes the first non-selection period, the first
The wiring 2420_i of 0 is in a floating state and the potential is maintained at V2. At this time, the flip-flop 2401_i + 1 is the reset period. After that, when the flip-flop 2401_i becomes the second non-selection period, the L signal is output from the tenth wiring 2420_i. At this time, the flip-flop 2401_i + 1 becomes the second non-selection period.

In this way, the shift register of FIG. 24 can output the selection signal from the tenth wiring 2420_1 to the tenth wiring 2420_n in order. Further, in the shift register of FIG. 24, since the second selection period of the flip-flop 2401_i and the first selection period of the flip-flop 2402_i + 1 are the same period, the tenth wiring 2420_i and the tenth wiring 2420_i have the same period. The selection signal can be output from the wiring 2420_i + 1.

Further, the shift register to which the flip-flop of the present embodiment is applied can suppress the shift of the threshold voltage of the transistor, so that the life can be extended. Further, since the shift register to which the flip-flop of the present embodiment is applied is resistant to noise, reliability can be improved. Further, the shift register to which the flip-flop of the present embodiment is applied can suppress malfunction.

Further, since the shift register to which the flip-flop of the present embodiment is applied can operate at high speed, it can be applied to a higher-definition display device or a larger display device. Further, the flip-flop of the present embodiment can be simplified in the process. Further, the shift register to which the flip-flop of the present embodiment is applied can reduce the manufacturing cost.
Further, the shift register to which the flip-flop of the present embodiment is applied can improve the yield.

Subsequently, the configuration and driving method of the display device having the shift register of the present embodiment described above will be described. However, the display device of the present embodiment may have at least the flip-flop of the present embodiment.

The configuration of the display device of this embodiment will be described with reference to FIG. 27. In the display device of FIG. 27, the scanning lines G1 to Gn are scanned by the scanning line driving circuit 2702. Furthermore, FIG.
In the display device 7, the video signal is input from the signal line of the odd-numbered line to the pixel 1703 of the odd-numbered line, and the video signal is input from the signal line of the even-numbered line to the pixel 1703 of the even-numbered line. In addition, FIG.
The points common to the configuration of No. 7 are the same, and the description thereof will be omitted.

By applying the shift register of the present embodiment to the scan line drive circuit 2702, the display device of FIG. 27 can perform the same operation as the display device of FIG. 20 by one scan line drive circuit. Therefore, the display device of FIG. 27 can write a video signal to the pixels at high speed. Further, the display device of FIG. 27 can have a long life. moreover,
The display device of FIG. 27 can be increased in size. Further, the display device of FIG. 27 can be improved in definition. Further, the display device of FIG. 27 can save power. Further, the display device of FIG. 27 can suppress heat generation of the IC. Further, the display device of FIG. 27 can save power of the IC.

As shown in FIG. 28, the scanning lines G1 to Gn are the first scanning line drive circuit 2802a.
And may be scanned by the second scan line drive circuit 2802b. The first scanning line driving circuit 2802a and the second driving circuit 2802b have the same configuration as the scanning line driving circuit 2702 shown in FIG. 27, and scan the scanning lines G1 to Gn at the same timing. Furthermore, the first
The scanning line drive circuit 2802a and the second drive circuit 2802b may be referred to as a first drive circuit and a second drive circuit, respectively.

The display device of FIG. 28 includes a first scanning line driving circuit 2802a and a second scanning line driving circuit 280.
Even if a defect occurs in one of the 2bs, the other of the scan line drive circuit 2802a and the second scan line drive circuit 2802b can scan the scan lines G1 to Gn, so that redundancy can be obtained. Further, in the display device of FIG. 28, since the first scanning line driving circuit 2802a and the second scanning line driving circuit 2802b scan the scanning lines G1 to Gn, the load of the first scanning line driving circuit 2802a ( The wiring resistance of the scanning line and the parasitic capacitance of the scanning line) and the load of the second scanning line drive circuit 2802b can be halved as compared with FIG. 27. Therefore, in the display device of FIG. 28, the load of the first scanning line drive circuit 2802a and the load of the second scanning line driving circuit 2802b are reduced, so that the signals input to the scanning lines G1 to Gn (the first). It is possible to reduce the delay and bluntness of the scan line drive circuit 2802a of 1 and the output signal of the second drive circuit 2802b). Further, the display device of FIG. 28 reduces the load of the first scanning line drive circuit 2802a and the load of the second scanning line driving circuit 2802b, so that the scanning lines G1 to Gn can be scanned at high speed. can. Further, since the scanning lines G1 to Gn can be scanned at high speed, it is possible to increase the size of the panel or increase the definition of the panel. It should be noted that the common reference numerals are used for the parts common to the configuration of FIG. 17, and the description thereof will be omitted.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 3)
In the present embodiment, a flip-flop different from the first and second embodiments, a drive circuit having the flip-flop, and a configuration and a driving method of a display device having the drive circuit will be described. The flip-flop of the present embodiment is characterized in that the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. The same parts as those of the first embodiment and the second embodiment are shown by using common reference numerals, and detailed description of the same parts or parts having the same functions will be omitted.

The basic configuration of the flip-flop of the present embodiment will be described with reference to FIG. 40. Figure 4
The flip-flops shown in 0 are the first transistor 101, the second transistor 102, and the like.
Third transistor 103, fourth transistor 104, fifth transistor 105, sixth transistor 106, seventh transistor 107, eighth transistor 108, ninth transistor
It has a transistor 109 and a tenth transistor 110. In the present embodiment, the ninth transistor 109 and the tenth transistor 110 are N-channel transistors, and are in a conductive state when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth). And.

The flip-flop of FIG. 40 is the same as the flip-flop of FIG. 1A with the ninth transistor 109 and the tenth transistor 110 added. Therefore, the first transistor 101, the second transistor 102, the third transistor 103, and the fourth transistor
As the transistor 104, the fifth transistor 105, the sixth transistor 106, the transistor 107 of the sixth transistor 107, and the eighth transistor 108, the same ones as in FIG. 1 can be used.

The connection relationship of the flip-flops of FIG. 40 will be described. First transistor 1
The first electrode of 01 (one of the source electrode and the drain electrode) is connected to the fifth wire 125, and the second electrode of the first transistor 101 (the other of the source electrode and the drain electrode) is the third wire 123. Connected to. The first electrode of the second transistor 102 is the fourth wiring 1
Connected to 24, the second electrode of the second transistor 102 is connected to the third wire 123, and the gate electrode of the second transistor 102 is connected to the eighth wire 128. The first electrode of the third transistor 103 is connected to the sixth wiring 126, and the third transistor 103
The second electrode is connected to the gate electrode of the sixth transistor 106, and the gate electrode of the third transistor 103 is connected to the seventh wiring 127. The first of the fourth transistor 104
Electrode is connected to the tenth wiring 130, and the second electrode of the fourth transistor 104 is the sixth.
The gate electrode of the fourth transistor 104 is connected to the gate electrode of the transistor 106, and the gate electrode of the fourth transistor 104 is connected to the eighth wiring 128. The first electrode of the fifth transistor 105 is connected to the ninth wiring 129, and the second electrode of the fifth transistor 105 is the first transistor 101.
It is connected to the gate electrode of the fifth transistor 105, and the gate electrode of the fifth transistor 105 is connected to the first wiring 121. The first electrode of the sixth transistor 106 is connected to the twelfth wiring 132, and the first electrode is connected to the twelfth wiring 132.
The second electrode of the sixth transistor 106 is connected to the gate electrode of the first transistor 101. The first electrode of the seventh transistor 107 is connected to the thirteenth wiring 133, and the seventh is
The second electrode of the transistor 107 is connected to the gate electrode of the first transistor 101, and the gate electrode of the seventh transistor 107 is connected to the second wiring 122. The first electrode of the eighth transistor 108 is connected to the eleventh wiring 131, and the eighth transistor 10
The second electrode of 8 is connected to the gate electrode of the sixth transistor 106, and the gate electrode of the eighth transistor 108 is connected to the gate electrode of the first transistor 101. The first electrode of the ninth transistor 109 is connected to the fifteenth wiring 135, and the ninth transistor 1
The second electrode of 09 is connected to the 14th wiring 134, and the gate electrode of the ninth transistor 109 is connected to the gate electrode of the first transistor 101. Tenth transistor 11
The first electrode of 0 is connected to the sixteenth wire 136, the second electrode of the tenth transistor 110 is connected to the fourteenth wire 134, and the gate electrode of the tenth transistor 110 is the eighth.
It is connected to the wiring 128 of.

The first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, the seventh wiring 127, the eighth wiring 128, the fourteenth wiring 134, and the fifteenth wiring 135. , Called the first signal line, the second signal, the third signal line, the fourth signal line, the fifth signal line, the sixth signal line, the seventh signal line, and the eighth signal line, respectively. But it may be. Further, the fourth wiring 124 and the sixth wiring
Wiring 126, 9th wiring 129, 10th wiring 130, 11th wiring 131, 12th wiring 132, 13th wiring 133 and 16th wiring 136, respectively, the first power line and the second.
Power line, 3rd power line, 4th power line, 5th power line, 6th power line, 7th power line,
It may be called the eighth power line.

Next, the operation of the flip-flop shown in FIG. 40 will be described with reference to the timing chart of FIG. 41. Further, the timing chart of FIG. 41 will be described by dividing it into a set period, a selection period, a reset period, a first non-selection period, and a second non-selection period. However, the set period, the reset period, the first non-selection period, and the second non-selection period may be collectively referred to as a non-selection period.

The potential of V1 is supplied to the sixth wiring 126 and the ninth wiring 129, and the fourth wiring 1
24, 10th wiring 130, 11th wiring 131, 12th wiring 132, 13th wiring 1
The potential of V2 is supplied to the 33rd and the 16th wiring 136. Here, V1> V2.

The first wiring 121, the fifth wiring 125, the eighth wiring 128, the seventh wiring 127, and the second wiring 122 have signals 221, 225, signal 228, and signal 227 shown in FIG. 24, respectively. , Signal 222 is input. Further, the signal 225 shown in FIG. 24 is input to the fifteenth wiring 135. Here, as the signal 221 and the signal 225, the signal 228, the signal 227, and the signal 222, the same ones as those in FIG. 2 or FIG. 6 can be used.

However, the first wiring 121, the second wiring 122, the fourth wiring 124 to the thirteenth wiring 133
, Fifteenth wiring 135 and sixteenth wiring 136 may be input with various signals, potentials and currents, respectively.

From the third wiring 123 and the 14th wiring 134, the signal 223 and the signal 23, respectively.
4 is output. The signal 234 is a flip-flop output signal, and the signal 223 is a flip-flop transfer signal. However, the signal 223 may be used as the output signal of the flip-flop, and the signal 234 may be used as the transfer signal of the flip-flop.

Therefore, when the signal 234 is used as the output signal of the flip-flop and the signal 223 is used as the transfer signal of the flip-flop, the W / L value of the ninth transistor 109 is used as the W / L of the first transistor 101 to the tenth transistor 110. It should be the largest in L. however,
When the signal 223 is used as the output signal of the flip-flop and the signal 234 is used as the transfer signal of the flip-flop, the W / L value of the first transistor 101 is used as the value of the W / L of the first transistor 101.
It is set to the maximum among the W / L of the tenth transistor 110.

As described above, the present embodiment is characterized in that the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. That is, the flip-flop of FIG. 40 outputs a signal from the third wiring 123 by the first transistor 101 and the second transistor 102, and the ninth transistor 109.
And the signal is output from the 14th wiring 134 by the 10th transistor 110. Further, the ninth transistor 109 and the tenth transistor 110 are the first transistor 1.
Since it is connected in the same manner as the 01 and the second transistor 102, the signal (signal 234) output from the 14th wiring 134 is the signal (signal 223) output from the third wiring 123 as shown in FIG. 41. ) And the waveform is almost the same.

Since the first transistor 101 only needs to be able to supply an electric charge to the gate electrode of the fifth transistor 105 in the next stage, the W / L value of the first transistor 101 is the W / L of the fifth transistor 105. It is preferably 2 times or less of the value of L, and more preferably the value of W / L or less of the fifth transistor 105.

The ninth transistor 109 and the tenth transistor 110 have the same functions as the first transistor 101 and the second transistor 102, respectively. Further, the ninth transistor 109 and the tenth transistor 110 may be referred to as a buffer unit.

From the above, the flip-flop of FIG. 40 can prevent malfunction even if a large load is connected to the 14th wiring 134 and a delay or blunting occurs in the signal 234. This is because the flip-flop of FIG. 40 is not affected by the delay or blunting of the output signal by outputting the flip-flop output signal and the flip-flop transfer signal from different wirings by different transistors. Is.

Further, since the flip-flop of the present embodiment can operate at high speed, it can be applied to a higher-definition display device or a larger display device. Further, the flip-flop of the present embodiment can simplify the process. Further, the flip-flop of the present embodiment can reduce the manufacturing cost. Further, the flip-flop of the present embodiment can improve the yield.

The flip-flops of the present embodiment are FIG. 1 (B), FIG. 1 (C), FIG. 5 (A), and FIG.
(B), FIG. 5 (C), FIG. 7 (A), FIG. 7 (B), FIG. 8 (A), FIG. 8 (B), FIG. 9 (A),
It can be carried out in any combination with FIGS. 9 (B), 10 (A) and 10 (B). Further, the flip-flop of the present embodiment can be freely combined with the drive timing described in the first embodiment and the drive timing described in the second embodiment.

Subsequently, the configuration and driving method of the shift register having the flip-flop of the present embodiment described above will be described.

The configuration of the shift register of the present embodiment will be described with reference to FIG. 42. The shift register of FIG. 42 has n flip-flops (flip-flops 4201-1 to 4201_n).

The connection relationship of the shift register of FIG. 42 will be described. In the shift register of FIG. 42, in the flip flop 4201_i of the i-th stage (any one of the flip flops 4201_1 to 4201_n), the first wiring 121 shown in FIG. 40 is connected to the seventh wiring 4217_i-1. The second wiring 122 shown in FIG. 40 is connected to the seventh wiring 4217_i + 1, the third wiring 123 shown in FIG. 40 is connected to the seventh wiring 4217_i, and the fourth wiring 124 shown in FIG. 40 is connected. , 10th wiring 130, 11th wiring 131, 12th wiring 132, 1st
The wiring 133 and the sixth wiring 136 are connected to the fifth wiring 4215, and the fifth wiring 125, the seventh wiring 127, and the fifteenth wiring 135 shown in FIG. 40 are in an odd-stage flip flop. It is connected to the second wiring 4212, connected to the third wiring 4213 in the even-stage flip flop, and the eighth wiring 128 shown in FIG. 40 is connected to the third wiring 4213 in the odd-stage flip flop. And in the even-stage flip flop, the second wiring 4212
The sixth wiring 126 and the ninth wiring 129 shown in FIG. 40 are connected to the fourth wiring 421.
The 14th wiring 134 shown in FIG. 40 is connected to the 8th wiring 4218_i. However, the first wiring 121 shown in FIG. 40 of the first-stage flip-flop 4201_1 is connected to the first wiring 4211, and the second wiring 122 shown in FIG. 40 of the nth-stage flip-flop 4201_n is the sixth wiring. It is connected to the wiring 4216.

The first wiring 4211, the second wiring 4212, the third wiring 4213, and the sixth wiring 42
16 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Further, the fourth wiring 4214 and the fifth wiring 4215 may be referred to as a first power line and a second power line, respectively.

Next, the operation of the shift register shown in FIG. 42 will be described with reference to the timing chart of FIG. 43.

The first wiring 4211, the second wiring 4212, the third wiring 4213, and the fourth wiring 42
Signal 4311, signal 4312, signal 4313, signal 4314, signal 4315, and signal 4216 are input to the 14, fifth wiring 4215, and sixth wiring 4216. Signal 4311,
The signal 4312, the signal 4313, the signal 4314, the signal 4315 and the signal 4216 correspond to the signal 211, the signal 212, the signal 213, the signal 214, the signal 215 and the signal 216, respectively.

The 7th wiring 4217_1 to the 7th wiring 4217_n and the 8th wiring 4218_1
A digital signal having an H signal potential of V1 (hereinafter, also referred to as H level) and an L signal potential of V2 (hereinafter, also referred to as L level) is output from the eighth wiring 4218_n, respectively.

As shown in FIG. 43, for example, when the flip-flop 4201_i becomes the selection period, the seventh
The H signal (selection signal) is output from the wiring 4217_i and the eighth wiring 4218_i.
At this time, the flip-flop 4201_i + 1 is the set period. After that, the flip-flop 4201_i becomes the reset period, and the seventh wiring 4217_i and the eighth wiring 4
The L signal is output from 218_i. At this time, the flip-flop 4201_i + 1 is the selection period. After that, the flip-flop 4201_i becomes the first non-selection period, and the seventh wiring 4217_i and the eighth wiring 4218_i are in a floating state and the potential is maintained at V2. At this time, the flip-flop 4201_i + 1 is the reset period. After that, the flip-flop 4201_i becomes the second non-selection period, and the L signal is output from the seventh wiring 4217_i and the eighth wiring 4218_i. At this time, the flip-flop 4201_
i + 1 is the first non-selection period.

In this way, the shift register of FIG. 42 transfers the transfer signal to the seventh wiring 4217_1 in order from the seventh wiring 4217_1.
Wiring 4217_n can be output. Further, the shift register of FIG. 42 can output the selection signal from the eighth wiring 4218_1 to the eighth wiring 4218_n in order. That is, FIG. 42.
The shift register of can scan the eighth wiring 4218_1 to the eighth wiring 4218_n. Therefore, the shift register of FIG. 42 can sufficiently obtain a function as a shift register.

Further, the shift register of FIG. 42 has the eighth wiring 4218_1 to the eighth wiring 4218_n.
Even if a large load (resistance, capacitance, etc.) is connected to, it can operate without being affected by the load. Further, the shift register of FIG. 42 has the eighth wiring 4218_1 to the eighth wiring 42.
Even if any of 18_n is short-circuited with the power line or the signal line, normal operation can be continued. Therefore, the shift register of FIG. 42 can improve the range of operating conditions. Further, the shift register of FIG. 42 can improve reliability. moreover,
The shift register of FIG. 42 can improve the yield. This is because the shift register of FIG. 42 divides the transfer signal of each flip-flop and the output signal of each flip-flop.

Further, the shift register to which the flip-flop of the present embodiment is applied can suppress the shift of the threshold voltage of the transistor. Further, the shift register to which the flip-flop of the present embodiment is applied can have a long life. Further, the shift register to which the flip-flop of the present embodiment is applied can improve the reliability. Further, the shift register to which the flip-flop of the present embodiment is applied can suppress malfunction. Further, the shift register to which the flip-flop of the present embodiment is applied can be applied to a higher-definition display device or a larger display device. Further, the shift register to which the flip-flop of the present embodiment is applied can simplify the process. Further, the shift register to which the flip-flop of the present embodiment is applied can reduce the manufacturing cost. Further, the shift register to which the flip-flop of the present embodiment is applied can improve the yield.

As the display device of the present embodiment, the display devices of FIGS. 17, 19, 20, 27, and 28 can be used. Therefore, the display device using the shift register of the present embodiment as the scanning line drive circuit can suppress the shift of the threshold voltage of the transistor. Further, the display device of the present embodiment can have a long life. Further, the display device of the present embodiment can improve the reliability. Further, the display device of the present embodiment can suppress malfunction. Further, the display device of the present embodiment can be made higher in definition or larger in size. Further, the display device of the present embodiment can simplify the process. Further, the display device of the present embodiment can reduce the manufacturing cost. Further, the display device of the present embodiment can improve the yield. Further, the display device of the present embodiment can save power of the driver IC. Further, the display device of the present embodiment can suppress heat generation of the driver IC.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 4)
In this embodiment, a case where a P-channel transistor is applied to the transistor included in the flip-flop of the present specification will be described. Further, the configuration and driving method of the drive circuit having the flip-flop and the display device having the drive circuit will be described.

The flip-flop of the present embodiment will be described in the case where the polarity of the transistor included in the flip-flop of FIG. 1A is a P-channel type. However, FIG. 1 (B) and FIG. 1 (C)
, FIG. 5 (A), FIG. 5 (B), FIG. 5 (C), FIG. 7 (A), FIG. 7 (B), FIG. 8 (A), FIG. 8 (
The polarity of the transistor having the flip-flop shown in B), FIG. 9A, FIG. 9B, FIG. 10A, FIG. 10B, or FIG. 40 may be P-channel type. Further, the flip-flop of the present embodiment can be freely combined with the description of the first to third embodiments.

The basic configuration of the flip-flop of the present embodiment will be described with reference to FIG. 44. Figure 4
The flip-flops shown in 4 are the first transistor 4401 and the second transistor 440.
2. Third transistor 4403, fourth transistor 4404, fifth transistor 4
It has 405, a sixth transistor 4406, a seventh transistor 4407 and an eighth transistor 4408. In the present embodiment, the first transistor 4401, the second transistor 4402, the third transistor 4403, the fourth transistor 4404, and the fifth transistor.
Transistor 4405, 6th transistor 4406, 7th transistor 4407 and transistor 4408 are P-channel transistors, and the absolute value of the gate-source voltage (| Vgs |) is the absolute value of the threshold voltage (| Vth). When it exceeds (|) (Vgs is V)
It shall be in a conductive state (when it falls below th).

The flip-flop of the present embodiment is characterized in that the first transistor 4401 to the eighth transistor 4408 are all composed of P-channel type transistors. Therefore, the flip-flop of the present embodiment can simplify the manufacturing process.
Further, the flip-flop of the present embodiment can reduce the manufacturing cost. Further, the flip-flop of the present embodiment can improve the yield.

The connection relationship of the flip-flops of FIG. 44 will be described. First transistor 4
The first electrode of 401 (one of the source and drain electrodes) is connected to the fifth wire 4425, and the second electrode of the first transistor 4401 (the other of the source and drain electrodes) is the third wire 4423. Connected to. The first electrode of the second transistor 4402 is connected to the fourth wire 4424, and the second electrode of the second transistor 4402 is the third wire 44.
Connected to 23, the gate electrode of the second transistor 4402 is connected to the eighth wire 4428. The first electrode of the third transistor 4403 is connected to the sixth wire 4426, the second electrode of the third transistor 4403 is connected to the gate electrode of the sixth transistor 4406, and the gate of the third transistor 4403 is connected. The electrodes are connected to the seventh wire 4427.
The first electrode of the fourth transistor 4404 is connected to the tenth wire 4430, the second electrode of the fourth transistor 4404 is connected to the gate electrode of the sixth transistor 4406, and the gate of the fourth transistor 4404 is connected. The electrodes are connected to the eighth wire 4428. The first electrode of the fifth transistor 4405 is connected to the ninth wire 4429, the second electrode of the fifth transistor 4405 is connected to the gate electrode of the first transistor 4401, and the gate of the fifth transistor 4405. The electrodes are connected to the first wire 4421. The first electrode of the sixth transistor 4406 is connected to the twelfth wiring 4432, and the sixth transistor 44
The second electrode of 06 is connected to the gate electrode of the first transistor 4401. The first electrode of the seventh transistor 4407 is connected to the thirteenth wire 4433, the second electrode of the seventh transistor 4407 is connected to the gate electrode of the first transistor 4401, and the gate of the seventh transistor 4407. The electrodes are connected to the second wire 4422. The first electrode of the eighth transistor 4408 is connected to the eleventh wiring 4431, and the eighth transistor 440 is connected.
The second electrode of 8 is connected to the gate electrode of the sixth transistor 4406, and the gate electrode of the eighth transistor 4408 is connected to the gate electrode of the first transistor 4401.

The gate electrode of the first transistor 4401, the second electrode of the fifth transistor 4405, the second electrode of the sixth transistor 4406, the second electrode of the seventh transistor 4407, and the eighth transistor 4408. The connection point of the gate electrode is a node 4441.
Further, the second electrode of the third transistor 4403 and the second electrode of the fourth transistor 4404
The connection point of the electrode, the gate electrode of the sixth transistor 4406, and the second electrode of the eighth transistor 4408 is referred to as a node 4442.

The first wiring 4421, the second wiring 4422, the third wiring 4423, and the fifth wiring 44
25, the seventh wiring 4427 and the eighth wiring 4428 are the first signal line, the second signal, the third signal line, the fourth signal line, the fifth signal line, and the sixth signal line, respectively. You may call it. Further, the fourth wiring 4424, the sixth wiring 4426, the ninth wiring 4429, and the tenth wiring 443.
0, 11 wiring 4431, 12th wiring 4432 and 13th wiring 4433 are the first power line, the second power line, the third power line, the fourth power line, and the fifth power line, respectively. , 6th power line, 7th power line may be called.

Next, the operation of the flip-flop shown in FIG. 44 will be described with reference to the timing chart of FIG. 45. Further, the timing chart of FIG. 45 will be described by dividing it into a set period, a selection period, a reset period, a first non-selection period, and a second non-selection period. However, the set period, the reset period, the first non-selection period, and the second non-selection period may be collectively referred to as a non-selection period.

The timing chart of FIG. 45 is the same as that of the timing chart of FIG. 2 in which the H level and the L level are inverted.

The potential of V2 is supplied to the sixth wiring 4426 and the ninth wiring 4429, and the fourth wiring 4424, the tenth wiring 4430, the eleventh wiring 4431, the twelfth wiring 4432, and the thirteenth wiring The potential of V1 is supplied to 4433. Here, V1> V2.

The first wiring 4421, the fifth wiring 4425, the eighth wiring 4428, and the seventh wiring 44.
The signal 4521 and the signal 4525 shown in FIG. 45 are connected to the 27 and the second wiring 4422, respectively.
The signal 4528, the signal 4527, and the signal 4522 are input. And the third wiring 4423
Outputs the signal 4423 shown in FIG. 45. Here, signal 4421, signal 4425
, Signal 4428, Signal 4427, Signal 4422 and Signal 4423 have an H signal potential of V1.
(Hereinafter, also referred to as H level), the potential of the L signal is a digital signal of V2 (hereinafter, also referred to as L level). Further, the signal 4421, the signal 4425, the signal 4428, the signal 4427, the signal 4422 and the signal 4423 are added to the start signal and the power clock signal (PCK), respectively.
, The first control clock signal (CCK1), the second control clock signal (CCK2), the reset signal, and the output signal may be referred to.

However, various signals, potentials, and currents may be input to the first wiring 4421, the second wiring 4422, and the fourth wiring 4424 to the thirteenth wiring 4433, respectively.

First, in the set period shown in FIG. 45 (A), the signal 4521 becomes the L level, the fifth transistor 4405 is turned on, and the signal 4422 is the H level, so that the seventh transistor 440
7 is turned off, signal 4528 becomes L level, second transistor 4402 and fourth transistor 4404 are turned on, signal 4527 becomes H level, and third transistor 4403.
Turns off. At this time, the potential of the node 4441 (potential 4541) is such that the second electrode of the fifth transistor 4405 serves as the source electrode, and the potential of the ninth wiring 4429 and the threshold voltage of the fifth transistor 4405 are absolute. V2 + | Vth4405 | (V) because it is the sum of the values
th4405: Threshold voltage of the fifth transistor 4405). Therefore, the first transistor 4401 and the eighth transistor 4408 are turned on, and the fifth transistor 44 is turned on.
05 turns off. At this time, the potential of the node 4442 (potential 4542) becomes V1.
The sixth transistor 4406 is turned off. Thus, during the set period, the third wiring 44
Since 23 is electrically connected to the fifth wiring 4425 and the fourth wiring 4424 to which the H signal is input, the potential of the third wiring 4423 becomes V1. Therefore, the H signal is the third wiring 4423.
Is output from. Further, the node 4441 is in a floating state while maintaining the potential at V2 + | Vth4405 |.

In the selection period shown in FIG. 45 (B), the signal 4521 becomes the H level and the fifth transistor 4
Since 405 is off and signal 4522 remains at H level, the seventh transistor 4407 remains off, signal 4528 becomes H level, second transistor 4402 and fourth transistor 4404 are off, and signal 4527 is L. It becomes a level and the third transistor 45
03 turns on. At this time, the node 4441 maintains the potential at V1 + | Vth4405 |. Therefore, the first transistor 4401 and the eighth transistor 4408 remain on. The potential of the node 4442 at this time is the potential (V1) of the eleventh wiring 4431.
The potential difference (V1-V2) between and the potential (V2) of the sixth wiring 4426 is the third transistor 4.
The pressure is divided by the 403 and the eighth transistor 4408 to obtain V1-θ (θ: an arbitrary positive number). Further, θ << Vth4406 | (threshold voltage of the sixth transistor 4406). Therefore, the sixth transistor 4406 remains off. Here, since the L signal is input to the fifth wiring 4425, the potential of the third wiring 4423 begins to drop. Then, the potential of the node 4441 is changed to V2 + | Vth4405 by the bootstrap operation.
V2- | Vth4401 | -γ (Vth4401: 1st transistor 4)
The threshold voltage of 401, γ: an arbitrary positive number). Therefore, the potential of the third wiring 4423 becomes V2 because it has the same potential as the fifth wiring 4425. As described above, during the selection period, the third wiring 4423 is electrically connected to the fifth wiring 4425 to which the L signal is input, so that the potential of the third wiring 4423 becomes V2. Therefore, the L signal is output from the third wiring 4423.

In the reset period shown in FIG. 45 (C), since the signal 4521 remains at the H level, the fifth transistor 4405 remains off, the signal 4522 becomes the L level, the seventh transistor 4407 turns on, and the signal 4528 becomes L. At the level, the second transistor 4402 and the fourth transistor 4404 are turned on, the signal 4527 becomes the H level, and the third transistor 4403 is turned off. The potential of the node 4441 at this time is V1 because the potential (V1) of the thirteenth wiring 4433 is supplied via the seventh transistor 4407. Therefore, the first transistor 4401 and the eighth transistor 4408 are turned off. The potential of the node 4442 at this time becomes V1 because the fourth transistor 4404 is turned on. Therefore,
The sixth transistor 4406 is turned off. Thus, during the reset period, the third wiring 4
Since 423 conducts with the fourth wiring 4424 to which V1 is supplied, the third wiring 4423
The potential of is V1. Therefore, the H signal is output from the third wiring 4423.

In the first non-selection period shown in FIG. 45 (D), since the signal 4521 remains at the H level, the fifth transistor 4405 remains off, the signal 4522 becomes the H level, and the seventh transistor 4407 turns off. The signal 4528 becomes H level and the second transistor 440
The second and fourth transistors 4404 are turned off, the signal 4527 becomes L level, and the third transistor 4403 is turned on. At this time, the potential of the node 4442 is the potential (V2) of the seventh wiring 4427 and the third potential of the seventh wiring 4427, with the second electrode of the third transistor 4403 serving as the source electrode.
V2 + | Vth440 because it is the sum of the absolute value of the threshold voltage of the transistor 4403 of
3 | (Vth4403: threshold voltage of the third transistor 4403). Therefore,
The sixth transistor 4406 is turned on. At this time, the potential of the node 4441 becomes V1 because the sixth transistor 4406 is turned on. Therefore, the first transistor 4401 and the eighth transistor 4408 remain off. Thus, in the first non-selection period,
The third wiring 4423 is in a floating state and maintains the potential at V1.

The flip-flop of the present embodiment can suppress the shift of the threshold voltage of the second transistor 4402 by turning off the second transistor 4402.

In the second non-selection period shown in FIG. 45 (E), the fifth transistor 4405 remains off because the signal 4521 remains at the H level, and the seventh transistor 4407 is off because the signal 4522 remains at the H level. The signal 4528 becomes the L level, the second transistor 4402 and the fourth transistor 4404 turn on, the signal 4527 becomes the H level, and the third transistor 4403 turns off. At this time, the potential of the node 4442 becomes V1 and the sixth transistor 4406 is turned off. At this time, the node 4441 is in a floating state, so the potential is maintained at V1. Therefore, the first transistor 4401 and the eighth transistor 4408 remain off. Thus, in the second non-selection period, the third wiring 4
Since 423 conducts with the fourth wiring 4424 to which V1 is supplied, the third wiring 4423
The potential of is V1. Therefore, the H signal is output from the third wiring 4423.

The flip-flop of the present embodiment can suppress the shift of the threshold voltage of the sixth transistor 4406 by turning off the sixth transistor 4406.

From the above, the flip-flop of the present embodiment can suppress the shift of the threshold voltage of the second transistor 4402 and the sixth transistor 4406, so that the life can be extended. Further, the flip-flop of the present embodiment can suppress the shift of the threshold voltage of all the transistors, so that the life can be extended. Further, the flip-flop of the present embodiment can improve the reliability. Further, the flip-flop of the present embodiment can suppress malfunction.

The shift register of the present embodiment can be implemented by freely combining the flip-flop of the present embodiment with the shift register according to the first to third embodiments. For example, the shift register of the present embodiment shows the flip-flop of the present embodiment in FIG. 11.
, Can be freely combined with the shift registers of FIGS. 14, 24 and 42. However, the shift register of the present embodiment has the H level and the L level inverted as compared with the shift register according to the first to third embodiments.

The display device of the present embodiment can be implemented by freely combining the shift register of the present embodiment with the display device according to the first to third embodiments. For example, the display device of the present embodiment can be freely combined with the display devices of FIGS. 17, 19, 20, 27, and 28. However, the display device of the present embodiment has the H level and the L level reversed as compared with the display device according to the first to third embodiments.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 5)
In this embodiment, the signal line drive circuit included in the display device shown in the first to fourth embodiments will be described.

The signal line drive circuit of FIG. 31 will be described. The signal line drive circuit shown in FIG. 31 is the driver I.
It has C5601, switch groups 5602_1 to 5602_M, first wiring 5611, second wiring 5612, third wiring 5613 and wiring 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M has a first switch 5603a, a second switch 5603b and a third switch 5603c.

The driver IC 5601 has a first wiring 5611, a second wiring 5612, and a third wiring 5613.
And wiring 5621_1 to 5621_M. And switch group 5602_1 ~
5602_M Each is the first wiring 5611, the second wiring 5612, and the third wiring 561.
Wiring 5621_1 to 5 corresponding to 3 and switch groups 5602_1 to 5602_M, respectively.
Connected to one of 621_M. The wirings 5621_1 to 5621_M are the first switch 5603a, the second switch 5603b, and the third switch 56, respectively.
It is connected to three signal lines via 03c. For example, the wiring 5621_J in the Jth row (any one of the wiring 5621_1 to the wiring 5621_M) has the first switch 5603a, the second switch 5603b, and the third switch 5603c of the switch group 5602_J.
It is connected to the signal line Sj-1, the signal line Sj, and the signal line Sj + 1 via the above.

Signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

The driver IC5601 is preferably formed on a glass substrate using a single crystal substrate or a polycrystalline semiconductor. Further, it is desirable that the switch group 5602 is formed on the same substrate as the pixel portion shown in the first to fourth embodiments. therefore,
The driver IC5601 and the switch group 5602 may be connected via an FPC or the like.

Next, the operation of the signal line drive circuit shown in FIG. 31 will be described with reference to the timing chart of FIG. 32. The timing chart of FIG. 32 shows a timing chart when the scanning line Gi on the i-th row is selected. Further, the selection period of the scan line Gi on the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line drive circuit of FIG. 31 operates in the same manner as in FIG. 32 even when the scanning lines of other lines are selected.

In the timing chart of FIG. 32, the wiring 5621_J in the Jth column is the first switch 56.
03a, the signal line Sj via the second switch 5603b and the third switch 5603c.
-1, The case where it is connected to the signal line Sj and the signal line Sj + 1 is shown.

In the timing chart of FIG. 32, the timing at which the scanning line Gi on the i-th row is selected, the on / off timing of the first switch 5603a 5703a, and the second switch 5603 are shown.
The on / off timing 5703b of b, the on / off timing 5703c of the third switch 5603c, and the signal 5721_J input to the wiring 5621_J in the Jth row are shown.

Note that different video signals are input to the wiring 5621_1 to the wiring 5621_M in the first subselection period T1, the second subselection period T2, and the third subselection period T3. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj. And wiring 5621 in the third subselection period T3
The video signal input to _J is input to the signal line Sj + 1. Further, in the selection period T1, the second sub-selection period T2, and the third sub-selection period T3, the video signals input to the wiring 5621_J are designated as Dataj-1, Dataj, and Dataj + 1, respectively.

As shown in FIG. 32, in the first subselection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 5603c are turned off. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 via the first switch 5603a. In the second subselection period T2, the second switch 5603b is turned on and the first switch 5603a and the third switch 5603c are turned off. At this time,
The Dataj input to the wiring 5621_J is input to the signal line Sj via the second switch 5603b. In the third sub-selection period T3, the third switch 5603c is turned on and
The first switch 5603a and the second switch 5603b are turned off. At this time, wiring 5
Dataj + 1 input to 621_J is signal line S via the third switch 5603c.
It is input to j + 1.

From the above, the signal line drive circuit of FIG. 31 can input a video signal from one wiring 5621 to three signal lines during one gate selection period by dividing one gate selection period into three. can. Therefore, in the signal line drive circuit of FIG. 31, the number of connections between the board on which the driver IC5601 is formed and the board on which the pixel portion is formed can be reduced to about 1/3 of the number of signal lines. By reducing the number of connections to about 1/3, the signal line drive circuit of FIG. 31 can improve reliability, yield, and the like.

By applying the signal line drive circuit of the present embodiment to the display devices shown in the first to fourth embodiments, the number of connections between the board on which the pixel portion is formed and the external board can be further reduced. .. Therefore, the display device of the present invention can improve the reliability. Further, the display device of the present invention can increase the yield.

Next, the first switch 5603a, the second switch 5603b, and the third switch 560.
A case where an N-channel transistor is applied to 3c will be described with reference to FIG. 33.
The same parts as those in FIG. 31 are shown by using a common reference numeral, and detailed description of the same part or the part having the same function will be omitted.

The first transistor 5903a corresponds to the first switch 5603a, the second transistor 5903b corresponds to the second switch 5603b, and the third transistor 5903c corresponds to the third switch 5603c.

For example, in the case of the switch group 5602_J, in the first transistor 5903a, the first electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj-1, and the gate electrode is connected to the first wiring 5611. Will be done. In the second transistor 5903b, the first electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj, and the gate electrode is connected to the second wiring 5612. In the third transistor 5903c, the first electrode is wired 5621_.
It is connected to J, the second electrode is connected to the signal line Sj + 1, and the gate electrode is the third wiring 561.
Connected to 3.

The first transistor 5903a, the second transistor 5903b, and the third transistor 5903c each function as a switching transistor. Further, the first transistor 5903a, the second transistor 5903b, and the third transistor 5903.
c is turned on when the signal input to the gate electrode is H level, and turned off when the signal input to the gate electrode is L level.

The first switch 5603a, the second switch 5603b, and the third switch 560.
By using an N-channel transistor as 3c, amorphous silicon can be used as the semiconductor layer of the transistor, so that the manufacturing process can be simplified, the manufacturing cost can be reduced, and the yield can be improved. Because it can be done. Further, it is possible to manufacture a semiconductor device such as a large display panel. Further, the manufacturing process can be simplified by using polysilicon or polycrystalline silicon as the semiconductor layer of the transistor.

In the signal line drive circuit of FIG. 33, the first transistor 5903a and the second transistor 59
Although the case where an N-channel type transistor is used as the 03b and the third transistor 5903c has been described, the first transistor 5903a and the second transistor 5903b have been described.
A P-channel type transistor may be used as the third transistor 5903c. At this time, the transistor is turned on when the signal input to the gate electrode is L level, and turned off when the signal input to the gate electrode is H level.

As shown in FIG. 31, if one gate selection period can be divided into a plurality of sub-selection periods and a video signal can be input to each of a plurality of signal lines from one wiring in each of the plurality of sub-selection periods, a switch is used. The arrangement, number, driving method, etc. are not limited.

For example, when a video signal is input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, a switch and a wiring for controlling the switch may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes shorter. Therefore, it is desirable that the one-gate selection period be divided into two or three sub-selection periods.

As another example, as shown in the timing chart of FIG. 34, one selection period is divided into a precharge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3. You may. Further, in the timing chart of FIG. 34, the timing at which the scanning line Gi on the i-th row is selected, the on / off timing of the first switch 5603a 5803a, and the second
Switch 5603b on / off timing 5803b, 3rd switch 5603c
On / off timing 5803c and the signal 5 input to the wiring 5621_J in the Jth row.
821_J is shown. As shown in FIG. 34, the first switch 5603a, the second switch 5603b, and the third switch 5603c are turned on during the precharge period Tp. At this time, the precharge voltage Vp input to the wiring 5621_J is the first switch 56.
It is input to the signal line Sj-1, the signal line Sj, and the signal line Sj + 1, respectively, via 03a, the second switch 5603b, and the third switch 5603c. In the first sub-selection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 5 are turned on.
603c turns off. At this time, the Dataj-1 input to the wiring 5621_J is the first.
It is input to the signal line Sj-1 via the switch 5603a of. In the second subselection period T2, the second switch 5603b is turned on and the first switch 5603a and the third switch 5603c are turned off. At this time, Dataj input to the wiring 5621_J is input to the signal line Sj via the second switch 5603b. In the third subselection period T3, the third switch 5603c is turned on, and the first switch 5603a and the second switch 560 are turned on.
3b turns off. At this time, Dataj + 1 input to the wiring 5621_J is input to the signal line Sj + 1 via the third switch 5603c.

From the above, the signal line drive circuit of FIG. 31 to which the timing chart of FIG. 34 is applied can precharge the signal line by providing the precharge selection period before the sub-selection period, so that the video signal to the pixel can be obtained. Can be written at high speed. The same parts as those in FIG. 32 are shown by using a common reference numeral, and detailed description of the same part or the part having the same function will be omitted.

Also in FIG. 35, as shown in FIG. 31, one gate selection period is divided into a plurality of sub-selection periods.
A video signal can be input to each of a plurality of signal lines from one wiring in each of the plurality of subselection periods. Note that FIG. 35 shows only the switch group 6022_J in the Jth row of the signal line drive circuit. The switch group 6022_J is the first transistor 60.
It has 01, a second transistor 6002, a third transistor 6003, a fourth transistor 6004, a fifth transistor 6005, and a sixth transistor 6006. First transistor 6001, second transistor 6002, third transistor 6003
, 4th transistor 6004, 5th transistor 6005, 6th transistor 60
06 is an N-channel type transistor. The switch group 6022_J is the first wiring 60.
11, 2nd wiring 6012, 3rd wiring 6013, 4th wiring 6014, 5th wiring 60
15, 6th wiring 6016, wiring 5621_J, signal line Sj-1, signal line Sj, signal line S
Connected to j + 1.

The first electrode of the first transistor 6001 is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj-1, and the gate electrode is connected to the first wiring 6011. The first electrode of the second transistor 6002 is connected to the wiring 5621_J, and the second electrode is the signal line Sj.
It is connected to -1, and the gate electrode is connected to the second wiring 6012. Third transistor 6
The first electrode of 003 is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj, and the gate electrode is connected to the third wiring 6013. The first electrode of the fourth transistor 6004 is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj, and the gate electrode is connected to the fourth wiring 6014. The first electrode of the fifth transistor 6005 is the wiring 56.
It is connected to 21_J, the second electrode is connected to the signal line Sj + 1, and the gate electrode is connected to the fifth wiring 6015. The first electrode of the sixth transistor 6006 is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj + 1, and the gate electrode is connected to the sixth wiring 6016.

The first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 each function as a switching transistor. Further, the first transistor 6001, the second transistor 6002, the third transistor 6003, and the fourth transistor
Transistor 6004, fifth transistor 6005, and sixth transistor 6006 are turned on when the signal input to the gate electrode is H level, and turned off when the signal input to the gate electrode is L level. ..

The first wiring 6011 and the second wiring 6012 correspond to the first wiring 5911 in FIG. 33. The third wiring 6013 and the fourth wiring 6014 correspond to the second wiring 5912 in FIG. 33. The fifth wiring 6015 and the sixth wiring 6016 are the third wiring 5913 of FIG. 33.
Corresponds to. The first transistor 6001 and the second transistor 6002 correspond to the first transistor 5903a in FIG. 33. Third transistor 6003 and fourth
Transistor 6004 corresponds to the second transistor 5903b in FIG. 33. The fifth transistor 6005 and the sixth transistor 6006 correspond to the third transistor 5903c in FIG. 33.

In FIG. 35, the first transistor 600 in the first subselection period T1 shown in FIG. 32.
Either the 1st or the 2nd transistor 6002 is turned on. In the second subselection period T2, either the third transistor 6003 or the fourth transistor 6004 is turned on. In the third subselection period T3, either the fifth transistor 6005 or the sixth transistor 6006 is turned on. Further, in the precharge period Tp shown in FIG. 34, the first transistor 6001, the third transistor 6003, and the fifth transistor 60
Either 05 or the second transistor 6002, the fourth transistor 6004 and the sixth transistor 6006 are turned on.

Therefore, in FIG. 35, since the on-time of each transistor can be shortened, deterioration of the characteristics of each transistor can be suppressed. This is because, for example, in the first subselection period T1 shown in FIG. 32, the first transistor 6001 or the second transistor 60
This is because if either of 02 is turned on, the video signal can be input to the signal line Sj-1. For example, in the first subselection period T1 shown in FIG. 32, the video signal can be input to the signal line Sj-1 at high speed by turning on the first transistor 6001 and the second transistor 6002 at the same time. can.

In FIG. 35, a case where two transistors are connected in parallel between the wiring 5621 and the signal line has been described. However, the present invention is not limited to this, and three or more transistors are wired 56.
It may be connected in parallel between 21 and the signal line. By doing so, it is possible to further suppress the deterioration of the characteristics of each transistor.

In addition, although it has been described using various figures in the present embodiment, a part of the content or the content described in each figure can be applied to the content or a part of the content described in another figure. Alternatively, they can be combined. Furthermore, in the figures described so far, with respect to each part,
By combining different parts, more figures can be constructed.

Similarly, a part of the content or content described in each figure of the present embodiment can be applied to a part of the content or content described in the figure of another embodiment. Alternatively, they can be combined.
.. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

In this embodiment, the contents described in the other embodiments are embodied as an example, a slightly modified example, a partially modified example, and an improved example. An example of the case described, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be applied to the present embodiment. Alternatively, they can be combined. ..

(Embodiment 6)
In this embodiment, a configuration for preventing defects due to electrostatic breakdown of the display device shown in the first to fourth embodiments will be described.

In addition, electrostatic breakdown means that when positive or negative charges accumulated in the human body or an object come into contact with a semiconductor device, they are instantly discharged via the input / output terminals of the device, and a large current is generated inside the device. It is the destruction that occurs when it flows.

FIG. 36A shows a configuration for preventing electrostatic breakdown generated in the scanning line by the protection diode. FIG. 36A shows a configuration in which the protection diode is arranged between the wiring 6111 and the scanning line. Although not shown, a plurality of pixels are connected to the scanning line Gi on the i-th row. A transistor 6101 is used as the protection diode. The transistor 61
01 is an N-channel type transistor. However, a P-channel type transistor may be used, and the polarity of the transistor 6101 may be the same as that of the transistor of the scanning line drive circuit or the pixel.

Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, in parallel, or in series-parallel.

In the transistor 6101, the first electrode is connected to the scanning line Gi in the i-th row, the second electrode is connected to the wiring 6111, and the gate electrode is connected to the scanning line Gi in the i-th row.

The operation of FIG. 36 (A) will be described. A certain potential is input to the wiring 6111, and the potential is lower than the L level of the signal input to the scanning line Gi on the i-th row. When the positive or negative charge is not discharged to the scanning line Gi in the i-th row, the potential of the scanning line Gi in the i-th row is H level or L level, so that the transistor 6101 is turned off. On the other hand, when the negative charge is discharged to the scanning line Gi on the i-th row, the potential of the scanning line Gi on the i-th row drops momentarily. At this time, the potential of the scanning line Gi on the i-th line is from the potential of the wiring 6111 to the transistor 61.
When it becomes lower than the value obtained by subtracting the threshold voltage of 01, the transistor 6101 is turned on and a current flows through the transistor 6101 to the wiring 6111. Therefore, according to the configuration shown in FIG. 36 (A), it is possible to prevent a large current from flowing into the pixel, and thus it is possible to prevent electrostatic destruction of the pixel.

Note that FIG. 36B is a configuration for preventing electrostatic breakdown when a positive charge is discharged to the scanning line Gi on the i-th row. A transistor 6102 that functions as a protection diode is arranged between the scanning line and the wiring 6112. Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, in parallel, or in series-parallel. The transistor 6102 is an N-channel type transistor. However, a P-channel type transistor may be used, and the polarity of the transistor 6102 may be the same as that of the transistor of the scanning line drive circuit or the pixel. In the transistor 6102, the first electrode is connected to the scanning line Gi on the i-th row, the second electrode is connected to the wiring 6112, and the gate electrode is connected to the wiring 6112. A potential higher than the H level of the signal input to the scanning line Gi on the i-th line is input to the wiring 6112. Therefore, the transistor 6102 is turned off when the charge is not discharged to the scan line Gi on the i-th row. On the other hand, when the positive charge is discharged to the scanning line Gi on the i-th row, the potential of the scanning line Gi on the i-th row rises instantaneously. At this time, the scanning line G on the i-th line
When the potential of i becomes higher than the sum of the potential of the wiring 6112 and the threshold voltage of the transistor 6102, the transistor 6102 is turned on and the current is wired through the transistor 6102.
Flow to 112. Therefore, according to the configuration shown in FIG. 36 (B), it is possible to prevent a large current from flowing into the pixel, and thus it is possible to prevent electrostatic destruction of the pixel.

As shown in FIG. 36 (C), by combining FIGS. 36 (A) and 36 (B), even when a positive charge is discharged to the scanning line Gi on the i-th row. Even when a negative charge is discharged to the scanning line Gi on the i-th row, electrostatic destruction of the pixel can be prevented. In addition, FIG.
6 (A) and (B) are shown using a common reference numeral, and detailed description of the same portion or a portion having the same function will be omitted.

FIG. 37A shows a configuration in which a transistor 6201 functioning as a protection diode is connected between a scanning line and a holding capacitance line. Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, in parallel, or in series-parallel. The transistor 6201 is an N-channel type transistor. However, a P-channel type transistor may be used, and the polarity of the transistor 6201 may be the same as the polarity of the transistor of the scanning line drive circuit or the pixel. The wiring 6211 functions as a holding capacity line. Transistor 6201
The first electrode is connected to the scanning line Gi on the i-th line, and the second electrode is connected to the wiring 6211.
The gate electrode is connected to the scanning line Gi on the i-th row. A potential lower than the L level of the signal input to the scanning line Gi on the i-th line is input to the wiring 6211. Therefore, the transistor 6201 is turned off when the charge is not discharged to the scan line Gi on the i-th row. On the other hand, when the negative charge is discharged to the scanning line Gi on the i-th row, the scanning line Gi on the i-th row
The potential of is dropped momentarily. At this time, when the potential of the scanning line Gi on the i-th row becomes lower than the value obtained by subtracting the threshold voltage of the transistor 6201 from the potential of the wiring 6211, the transistor 62
01 is turned on and current flows through the transistor 6201 to the wiring 6211. Therefore, according to the configuration shown in FIG. 37 (A), it is possible to prevent a large current from flowing into the pixel, and thus it is possible to prevent electrostatic destruction of the pixel. Further, in the configuration shown in FIG. 37 (A), since the holding capacitance wire is used as the wiring for releasing the electric charge, it is not necessary to newly add the wiring.

Note that FIG. 37B is a configuration for preventing electrostatic breakdown when a positive charge is discharged to the scanning line Gi on the i-th row. Here, a potential higher than the H level of the signal input to the scanning line Gi on the i-th line is input to the wiring 6211. Therefore, the transistor 6201
Is off when the charge is not discharged to the scan line Gi on the i-th row. on the other hand,
When the positive charge is discharged to the scanning line Gi in the i-th row, the potential of the scanning line Gi in the i-th row rises instantaneously. At this time, the potential of the scanning line Gi on the i-th line is the potential of the wiring 6211 and the transistor 6
When it becomes higher than the sum of the threshold voltage of 201, the transistor 6201 is turned on and a current flows through the transistor 6201 to the wiring 6211. Therefore, according to the configuration shown in FIG. 37 (B), it is possible to prevent a large current from flowing into the pixel, and thus it is possible to prevent electrostatic destruction of the pixel. Further, in the configuration shown in FIG. 37B, since the holding capacitance line is used as the wiring for releasing the electric charge, it is not necessary to add a new wiring. In addition, FIG. 37
The same parts as in (B) are shown by using a common reference numeral, and detailed description of the same part or the part having the same function is omitted.

Next, FIG. 38 shows a configuration for preventing electrostatic breakdown generated in the signal line by the protection diode.
Shown in (A). FIG. 38A shows a configuration in which the protection diode is arranged between the wiring 6411 and the signal line. Although not shown, a plurality of pixels are connected to the signal line Sj in the jth column. A transistor 6401 is used as the protection diode. The transistor 6401 is an N-channel type transistor. However, a P-channel type transistor may be used, and the polarity of the transistor 6401 may be the same as the polarity of the transistor of the signal line drive circuit or the pixel.

Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, in parallel, or in series-parallel.

In the transistor 6401, the first electrode is connected to the signal line Sj on the jth line, the second electrode is connected to the wiring 6411, and the gate electrode is connected to the signal line Sj on the jth line.

The operation of FIG. 38 (A) will be described. A certain potential is input to the wiring 6411, and the potential is a potential at which the minimum value of the video signal input to the signal line Sj on the jth line is also low. When the positive or negative charge is not discharged to the signal line Sj on the jth line, the potential of the signal line Sj on the jth line is the same potential as the video signal, so that the transistor 6401 is turned off. On the other hand, when the negative charge is discharged to the signal line Sj on the jth line, the potential of the signal line Sj on the jth line drops momentarily.
At this time, when the potential of the signal line Sj on the jth line becomes lower than the value obtained by subtracting the threshold voltage of the transistor 6401 from the potential of the wiring 6411, the transistor 6401 is turned on and the current is wired 6411 via the transistor 6401. Flow to. Therefore, according to the configuration shown in FIG. 38 (A), it is possible to prevent a large current from flowing into the pixel, and thus it is possible to prevent electrostatic destruction of the pixel.

Note that FIG. 38B is a configuration for preventing electrostatic breakdown when a positive charge is discharged to the signal line Sj on the jth line. A transistor 6402 functioning as a protection diode is arranged between the scan line and the wiring 6412. Although only one protection diode is arranged, a plurality of protection diodes may be arranged in series, in parallel, or in series-parallel. The transistor 6402 is an N-channel type transistor. However, a P-channel type transistor may be used, and the polarity of the transistor 6402 may be the same as that of the transistor of the scanning line drive circuit or the pixel. In the transistor 6402, the first electrode is connected to the signal line Sj on the jth line, the second electrode is connected to the wiring 6412, and the gate electrode is connected to the wiring 6412. A potential higher than the maximum value of the video signal input to the signal line Sj on the jth line is input to the wiring 6412. Therefore, the transistor 6402 is turned off when the electric charge is not discharged to the signal line Sj on the jth line. On the other hand, when the positive charge is discharged to the signal line Sj on the jth line, the potential of the signal line Sj on the jth line rises instantaneously. At this time, when the potential of the signal line Sj on the jth line becomes higher than the sum of the potential of the wiring 6412 and the threshold voltage of the transistor 6402, the transistor 6402 is turned on and the current is connected to the wiring 6412 via the transistor 6402. It flows. Therefore, according to the configuration shown in FIG. 38 (B), it is possible to prevent a large current from flowing into the pixel, and thus it is possible to prevent electrostatic destruction of the pixel.

As shown in FIG. 38 (C), by combining FIGS. 38 (A) and 38 (B), even when a positive charge is discharged to the signal line Sj on the jth line. Even when a negative charge is discharged to the signal line Sj on the jth line, electrostatic destruction of the pixel can be prevented. In addition, FIG.
8 (A) and (B) are shown using a common reference numeral, and detailed description of the same portion or a portion having the same function will be omitted.

In the present embodiment, a configuration for preventing electrostatic destruction of pixels connected to the scanning line and the signal line has been described. However, the configuration of this embodiment is not applied only to prevent electrostatic destruction of pixels connected to scanning lines and signal lines. For example, when the present embodiment is applied to the wiring to which the signal or potential connected to the scan line drive circuit and the signal line drive circuit shown in the first to fourth embodiments is input, the scan line drive circuit And electrostatic destruction of the signal line drive circuit can be prevented.

In addition, although it has been described using various figures in the present embodiment, a part of the content or the content described in each figure can be applied to the content or a part of the content described in another figure. Alternatively, they can be combined. Furthermore, in the figures described so far, with respect to each part,
By combining different parts, more figures can be constructed.

Similarly, a part of the content or content described in each figure of the present embodiment can be applied to a part of the content or content described in the figure of another embodiment. Alternatively, they can be combined.
Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

In this embodiment, the contents described in the other embodiments are embodied as an example, a slightly modified example, a partially modified example, and an improved example. An example of the case described, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be applied to the present embodiment. Alternatively, they can be combined.

(Embodiment 7)
In the present embodiment, a new configuration of the display device applicable to the display devices shown in the first to fourth embodiments will be described.

FIG. 39A is a configuration in which a diode-connected transistor is arranged between one scanning line and another scanning line. In FIG. 39 (A), a transistor 6301a connected by a diode is arranged between the scanning line Gi-1 on the i-1st line and the scanning line Gi on the i-th row, and the scanning line Gi and the i + 1 row on the i-th row are arranged. Transistor 63 diode-connected to the eye scanning line Gi + 1.
The configuration when 01b is arranged is shown. The transistor 6301a and the transistor 6301b are N-channel type transistors. However, a P-channel type transistor may be used, and the polarity of the transistor 6301a and the transistor 6301b may be the same as the polarity of the transistor of the scanning line drive circuit or the pixel.

In FIG. 39 (A), the scanning line Gi-1 on the i-1st line, the scanning line Gi on the i-th line, and the scanning line Gi + 1 on the i + 1th line are shown as representatives, but other scanning lines are also shown. Similarly, a diode-connected transistor is arranged.

The first electrode of the transistor 6301a is connected to the scanning line Gi on the i-th row, and the second electrode is i.
It is connected to the scanning line Gi-1 on the first line, and the gate electrode is connected to the scanning line Gi-1 on the Gi-1 line. The first electrode of the transistor 6301b is connected to the scan line Gi + 1 in the i + 1 row, the second electrode is connected to the scan line Gi in the i row, and the gate electrode is connected to the scan line Gi in the i row.

The operation of FIG. 39 (A) will be described. In the scan line drive circuit shown in the first to fourth embodiments, the scan line Gi-1 on the i-1 line, the scan line Gi on the i line, and the scan line Gi + 1 on the i + 1 line during the non-selection period. Maintains the L level. Therefore, the transistor 6301a and the transistor 6301b are turned off. However, when the potential of the scanning line Gi on the i-th row rises due to noise or the like, the scanning line Gi on the i-th row selects a pixel, and an invalid video signal is written to the pixel. Therefore, by arranging a diode-connected transistor between the scanning lines as shown in FIG. 39 (A), it is possible to prevent an invalid video signal from being written to the pixel. This is because when the potential of the scanning line Gi in the i-th row rises above the sum of the potential of the scanning line Gi-1 in the i-1th row and the threshold voltage of the transistor 6301a, the transistor 6301a is turned on and the i-row is turned on. The potential of the scanning line Gi of the eye drops. Therefore, the pixel is not selected by the scanning line Gi on the i-th row.

The configuration of FIG. 39A is particularly advantageous when the scanning line drive circuit and the pixel portion are integrally formed on the same substrate. This is because, in a scanning line drive circuit composed of only N-channel type transistors or P-channel type transistors, the scanning lines may be in a floating state, and noise is likely to occur in the scanning lines.

Note that FIG. 39B is a configuration in which the directions of the diode-connected transistors arranged between the scanning lines are reversed. The transistor 6302a and the transistor 6302b
Is an N-channel type transistor. However, a P-channel type transistor may be used, and the polarity of the transistor 6302a and the transistor 6302b may be the same as the polarity of the transistor of the scanning line drive circuit or the pixel. In FIG. 39B, the first electrode of the transistor 6302a is connected to the scanning line Gi of the i-th row, the second electrode is connected to the scanning line Gi-1 of the i-1st row, and the gate electrode is i. It is connected to the scanning line Gi on the line. The first electrode of the transistor 6302b is connected to the scan line Gi + 1 in the i + 1 row, the second electrode is connected to the scan line Gi + 1 in the i row, and the gate electrode is connected to the scan line Gi + 1 in the i + 1 row. In FIG. 39 (B), similarly to FIG. 38 (A), the potential of the scanning line Gi on the i-th row is equal to or higher than the sum of the potential of the scanning line Gi + 1 on the i-1th row and the threshold voltage of the transistor 6302b. When it rises,
The transistor 6302b is turned on, and the potential of the scanning line Gi on the i-th row is lowered. therefore,
The pixel is not selected by the scanning line Gi on the i-th line, and it is possible to prevent an invalid video signal from being written to the pixel.

As shown in FIG. 39 (C), by combining FIGS. 39 (A) and 39 (B), even if the potential of the scanning line Gi on the i-th row rises, the transistor 6301a And since the transistor 6302b is turned on, the potential of the scanning line Gi on the i-th row is lowered. In addition, FIG. 39
In (C), since the current flows through the two transistors, it is possible to remove larger noise. The same parts as those in FIGS. 39 (A) and 39 (B) are shown by using a common reference numeral, and detailed description of the same part or the part having the same function will be omitted.

As shown in FIGS. 37 (A) and 37 (B), even if a diode-connected transistor is arranged between the scanning line and the holding capacitance line, it is the same as in FIGS. 39 (A), (B), and (C). The effect of can be obtained.

In addition, although it has been described using various figures in the present embodiment, a part of the content or the content described in each figure can be applied to the content or a part of the content described in another figure. Alternatively, they can be combined. Furthermore, in the figures described so far, for each part,
By combining different parts, more figures can be constructed.

Similarly, a part of the content or content described in each figure of the present embodiment can be applied to a part of the content or content described in the figure of another embodiment. Alternatively, they can be combined.
Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

In this embodiment, the contents described in the other embodiments are embodied as an example, a slightly modified example, a partially modified example, and an improved example. An example of the case described, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be applied to the present embodiment. Alternatively, they can be combined.

(Embodiment 8)
In this embodiment, the pixel structure of the display device will be described. In particular, the pixel structure of the liquid crystal display device will be described.

FIG. 46 is a cross-sectional view and a top view of pixels when a thin film transistor (TFT) is combined with a pixel structure of a liquid crystal display device, which is called a TN method. FIG. 46 (A) is a cross-sectional view of a pixel, and FIG. 46 (B) is a top view of the pixel. Further, the cross-sectional view of the pixel shown in FIG. 46A corresponds to the line segment aa'in the top view of the pixel shown in FIG. 46B. By applying the display device of the present embodiment to the liquid crystal display device having a pixel structure shown in FIG. 46, the liquid crystal display device can be manufactured at low cost.

The pixel structure of the TN type liquid crystal display device will be described with reference to FIG. 46 (A). The liquid crystal display device has a core portion for displaying an image, which is called a liquid crystal panel. The LCD panel is
It is produced by laminating two processed substrates with a gap of several μm and injecting a liquid crystal material between the two substrates. In FIG. 46 (A), the two substrates are the first substrate 10101 and the second substrate 10116. A TFT and a pixel electrode are formed on the first substrate, and a light-shielding film 10114, a color filter 10115, a fourth conductive layer 10113, a spacer 10117, and a second alignment film 10112 are formed on the second substrate. You may.

The display device of this embodiment can be implemented without forming a TFT on the first substrate 10101. When the TFT is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when manufacturing a TFT, a larger display device can be obtained.

The TFT shown in FIG. 46 is a bottom gate type TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost by using a large-area substrate. However, the display device of the present embodiment is not limited to this. The structure of the TFT that can be used includes a channel etch type and a channel protection type for the bottom gate type TFT. Moreover, the top gate type may be used. Further, not only amorphous semiconductors but also polycrystalline semiconductors can be used.

The display device of this embodiment can be implemented without forming a light-shielding film 10114 on the second substrate 10116. If the light-shielding film 10114 is not manufactured, the number of steps is reduced, so that
The manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light-shielding film 10114 is manufactured, it is possible to obtain a display device having less light leakage when displaying black.

The display device of the present embodiment can be implemented without manufacturing the color filter 10115 on the second substrate 10116. When the color filter 10115 is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. However, even if the color filter 10115 is not manufactured, it is possible to obtain a display device capable of color display by field sequential drive. On the other hand, when the color filter 10115 is manufactured, it is possible to obtain a display device capable of displaying colors.

The display device of the present embodiment can also be implemented by spraying a spherical spacer without forming the spacer 10117 on the second substrate 10116. When the spherical spacer is sprayed, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the spacer 10117 is manufactured, the position of the spacer does not vary, so that the distance between the two substrates can be made uniform.
A display device with less display unevenness can be obtained.

Next, the processing performed on the first substrate 10101 will be described. The first substrate 10101 is preferably a transparent substrate, and may be, for example, a quartz substrate, a glass substrate, or a plastic substrate. The first substrate 10101 may be a light-shielding substrate, and may be a semiconductor substrate or SOI (S).
It may be an insulator) substrate.

First, the first insulating film 10102 may be formed on the first substrate 10101. The first insulating film 10102 is a silicon oxide film, a silicon nitride film or a silicon nitride film (SiOxN).
It may be an insulating film such as y). Alternatively, as the first insulating film 10102, an insulating film having a laminated structure in which two or more films such as a silicon oxide film, a silicon nitride film, and a silicon oxide film (SiOxNy) are combined may be used. When the first insulating film 10102 is formed, it is possible to prevent impurities from the substrate from affecting the semiconductor layer and changing the properties of the TFT. Further, since the change in the properties of the TFT can be suppressed, a highly reliable display device can be obtained. If the first insulating film 10102 is not formed, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved.

Next, on the first substrate 10101 or the first insulating film 10102, the first conductive layer 1010
Form 3. The first conductive layer 10103 may be formed by processing its shape. The process of processing the shape is preferably as follows. First, the first conductive layer 101
03 is formed on the entire surface. At this time, the first conductive layer 10103 is a sputtering device or C.
The film may be formed using a film forming apparatus such as a VD apparatus. Next, a photosensitive resist material is formed on the entire surface of the first conductive layer formed on the entire surface. Next, the resist material is exposed to light according to the shape to be formed by a photolithography method, a laser direct drawing method, or the like. Next, by removing either the exposed resist material or the non-exposed resist material by etching, a mask for shaping the first conductive layer 10103 can be obtained. Then, according to the formed mask pattern, the first conductive layer 10103
Is removed by etching, so that the first conductive layer 10103 can be shaped into a desired pattern. There are two methods for etching the first conductive layer 10103: a chemical method (wet etching) and a physical method (dry etching). The material of the first conductive layer 10103 and the first method are used. It is appropriately selected in consideration of the properties of the material under the conductive layer 10103. The materials used for the first conductive layer 10103 are Mo, Ti, and Al.
, Nd, Cr and the like are suitable. Alternatively, it may have a laminated structure in which two or more of Mo, Ti, Al, Nd, Cr and the like are combined.

Next, the second insulating film 10104 is formed. At this time, the second insulating film 10104 may be formed by using a film forming apparatus such as a sputtering apparatus or a CVD apparatus. The material used for the second insulating film 10104 is preferably a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon nitride film, or the like. Alternatively, it may have a laminated structure in which two or more of a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon nitride film, and the like are combined.
It is particularly preferable that the second insulating film 10104 in the portion in contact with the first semiconductor layer 10105 is a silicon oxide film. This is because the semiconductor layer 10 is made of a silicon oxide film.
This is because the trap level at the interface with 105 is reduced. The first conductive layer 10
When the 103 is formed of Mo, the second insulating film 1 in the portion in contact with the first conductive layer 10103 is formed.
0104 is preferably a silicon nitride film. This is because the silicon nitride film does not oxidize Mo.

Next, the first semiconductor layer 10105 is formed. After that, it is preferable to continuously form the second semiconductor layer 10106. The first semiconductor layer 10105 and the second semiconductor layer 1
0106 may be formed by processing the shape. It is preferable that the step of processing the shape is a method such as the above-mentioned photolithography method. The material used for the first semiconductor layer 10105 is preferably silicon or silicon germanium (SiGe). Further, as the material used for the second semiconductor layer 10106, silicon or the like containing phosphorus or the like is suitable.

Next, the second conductive layer 10107 is formed. At this time, it is preferable to use a sputtering method or a printing method as a method for forming the second conductive layer 10107. The second conductive layer 10
The material used in 107 may be transparent or reflective. If it has transparency, for example, indium tin oxide (IT), which is a mixture of indium oxide and tin oxide.
O) film, indium tin oxide (ITSO) film in which silicon oxide is mixed with indium tin oxide (ITO), indium zinc oxide (IZO) film in which zinc oxide is mixed with indium oxide, zinc oxide film or tin oxide. A membrane can be used. In addition, IZO is 2 to ITO.
A transparent conductive material formed by sputtering using a target mixed with 20 wt% zinc oxide (ZnO). On the other hand, if it has reflectivity, Ti, Mo, Ta, Cr
, W, Al and the like can be used. Further, a two-layer structure in which Ti, Mo, Ta, Cr, W and Al are laminated, or a three-layer laminated structure in which Al is sandwiched between metals such as Ti, Mo, Ta, Cr and W may be used. The second conductive layer 10107 may be formed by processing the shape. It is preferable that the method for processing the shape is a method such as the above-mentioned photolithography method. The etching method is preferably dry etching. Dry etching is performed by ECR (Electron Cyclotron Response) or ICP (In).
It may be performed by a dry etching apparatus using a high-density plasma source such as ductive Coupled Plasma).

Next, the channel region of the TFT is formed. At this time, as the mask for etching the second semiconductor layer 10106, the second conductive layer 10107 may be used, or the mask (resist) for etching the second conductive layer 10107 may be used. good. By doing so, the number of masks can be reduced, so that the manufacturing cost can be reduced. By etching the second semiconductor layer 10106 having conductivity, the removed portion is a TFT.
It becomes the channel area of. In addition, after forming the first semiconductor layer 10105 without forming the first semiconductor layer 10105 and the second semiconductor layer 10106 continuously, a film serving as a stopper is formed on the portion to be the channel region of the TFT. After pattern processing, the second semiconductor layer 10
106 may be formed. The first semiconductor layer 10105 and the second semiconductor layer 10106
Is etched using the same mask when the shape of the second conductive layer 10107 is processed by a method such as the photolithography method described above. By doing so, the second conductive layer 1010
Since the channel region of the TFT can be formed without using 7 as a mask, there is an advantage that the degree of freedom of the layout pattern is increased. Further, since the first semiconductor layer 10105 is not etched at the time of etching the second semiconductor layer 10106, there is an advantage that the channel region of the TFT can be reliably formed without causing an etching defect.

Next, the third insulating film 10108 is formed. It is preferable that the third insulating film has transparency. The material used for the third insulating film 10108 is an inorganic material (silicon oxide,
Silicon nitride, silicon oxide, etc.) or organic compound materials with low dielectric constant (photosensitive or non-photosensitive organic resin materials) are suitable. Further, a material containing siloxane may be used. Siloxane is a material whose skeletal structure is composed of bonds between silicon (Si) and oxygen (O). As the substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. Alternatively, a fluoro group may be used as the substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as the substituent. A contact hole is selectively formed in the third insulating film 10108 by etching. Further, the contact hole is formed on at least the second conductive layer 10107. note that,
By etching the third insulating film 10108 and the second insulating film 10104 at the same time, it is possible to form a contact hole not only with the second conductive layer 10107 but also with the first conductive layer 10103. The surface of the third insulating film 10108 is preferably as flat as possible. This is because the orientation of the liquid crystal molecules is affected by the unevenness of the surface in contact with the liquid crystal.

Next, the third conductive layer 10109 is formed. At this time, it is preferable to use a sputtering method or a printing method as a method for forming the third conductive layer 10109. The third conductive layer 10
The material used for 109 may have transparency or reflectivity as in the second conductive layer 10107. The material that can be used as the third conductive layer 10109 is the second.
It may be the same as the conductive layer 10107 of. Further, the third conductive layer 10109 may be formed by processing the shape. The method of processing the shape may be the same as that of the second conductive layer 10107.

Next, the first alignment film 10110 is formed. A polymer film such as polyimide can be used for the alignment film 10110. After forming the first alignment film 10110, rubbing may be performed in order to control the orientation of the liquid crystal molecules. Rubbing is a process of forming streaks on the alignment film by rubbing the alignment film with a cloth. By performing rubbing, the alignment film can be made oriented.

The first substrate 10101 manufactured as described above, the light-shielding film 10114, and the color filter 10
115, the fourth conductive layer 10113, the spacer 10117, and the second substrate 10116 on which the second alignment film 10112 is formed are bonded to each other with a gap of several μm by a sealing material. Then, a liquid crystal panel can be manufactured by injecting a liquid crystal material between the two substrates. In the TN type liquid crystal panel as shown in FIG. 46, the fourth conductive layer 101
13 may be manufactured on the entire surface of the second substrate 10116.

Next, the characteristics of the pixel structure of the TN type liquid crystal panel shown in FIG. 46 will be described. FIG. 46
The liquid crystal molecule 10118 shown in (A) is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecule 10118, in FIG. 46 (A), it is expressed by its length. That is, it is assumed that the orientation of the long axis of the long-expressed liquid crystal molecule 10118 is parallel to the paper surface, and the shorter the expressed liquid crystal molecule 10118 is, the closer the orientation of the long axis is to the normal direction of the paper surface. .. That is, the liquid crystal molecule 10118 shown in FIG. 46 (A) has a major axis orientation of 9 between the one close to the first substrate 10101 and the one close to the second substrate 10116.
They differ by 0 degrees, and the orientation of the long axis of the liquid crystal molecules 10118 located in the middle of these is such that they are smoothly connected. That is, the liquid crystal molecule 101 shown in FIG. 46 (A).
Reference numeral 18 is oriented so as to be twisted by 90 degrees between the first substrate 10101 and the second substrate 10116.

Next, an example of the pixel layout when the display device of the present embodiment is applied to the TN type liquid crystal display device will be described with reference to FIG. 46 (B). The pixels of the TN type liquid crystal display device to which the display device of the present embodiment is applied are the scanning line 10121 and the video signal line 10122.
, Capacity line 10123, TFT 10124, pixel electrode 10125, and pixel capacity 101.
26 and may be provided.

Since the scanning line 10121 is electrically connected to the gate electrode of the TFT 10124, it is preferably composed of the first conductive layer 10103.

Since the video signal line 10122 is electrically connected to the source electrode or drain electrode of the TFT 10124, it is preferably composed of the second conductive layer 10107. Further, since the scanning lines 10121 and the video signal lines 10122 are arranged in a matrix, at least,
It is preferably formed of different conductive layers.

The capacitance line 10123 is arranged in parallel with the pixel electrode 10125 to have a pixel capacitance of 1012.
6 is a wiring for forming, and it is preferable that the wiring is composed of the first conductive layer 10103. As shown in FIG. 46B, the capacitance line 10123 may be extended along the video signal line 10122 so as to surround the video signal line 10122. By doing so, it is possible to reduce the phenomenon that the potential of the electrode that should hold the potential changes with the potential change of the video signal line 10122, that is, so-called crosstalk. In addition, in order to reduce the cross capacitance with the video signal line 10122, as shown in FIG. 46 (B), the first semiconductor layer 10105
May be provided in the intersection region of the capacitance line 10123 and the video signal line 10122.

The TFT 10124 operates as a switch for conducting the video signal line 10122 and the pixel electrode 10125. As shown in FIG. 46B, either the source region or the drain region of the TFT 10124 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained in a small area, and the switching capacity can be increased. As shown in FIG. 46 (B), the TFT
The gate electrode of 10124 may be arranged so as to surround the first semiconductor layer 10105.

The pixel electrode 10125 is electrically connected to either the source electrode or the drain electrode of the TFT 10124. The pixel electrode 10125 is an electrode for applying a signal voltage transmitted by the video signal line 10122 to the liquid crystal element. In addition, by arranging the capacity line 10123,
The pixel capacity 10126 may be formed. By doing so, the pixel electrode 10125 can easily hold the signal voltage transmitted by the video signal line 10122. The pixel electrode 101
25 may be rectangular, as shown in FIG. 46 (B). By doing so, the aperture ratio of the pixels can be increased, so that the efficiency of the liquid crystal display device is improved. Also, the pixel electrode 1
When 0125 is made of a transparent material, a transmissive liquid crystal display device can be obtained. The transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. Further, when the pixel electrode 10125 is made of a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors, and does not require a backlight, so that power consumption can be extremely reduced. When the pixel electrode 10125 is made of both a transparent material and a reflective material, a semi-transmissive liquid crystal display device having the advantages of both can be obtained. When the pixel electrode 10125 is made of a reflective material, the surface of the pixel electrode 10125 may have irregularities. Alternatively, the pixel electrode 10125 can be made uneven by making the surface of the third insulating film 10108 uneven. By doing so, since the reflected light is diffusely reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light becomes small. That is, it is possible to obtain a reflective liquid crystal display device having a constant brightness regardless of the angle.

Next, a case where the display device of the present embodiment is applied to the liquid crystal display device in the VA (Vertical Alignment) mode will be described with reference to FIG. 47. FIG. 47 shows a so-called MVA (Multi-domai) in which the liquid crystal molecules are controlled to have various orientations and the viewing angle is increased by using the alignment control protrusions in the pixel structure of the liquid crystal display device in the VA mode.
It is a cross-sectional view and a top view of a pixel when the display device of this embodiment is applied to the n (Vertical Alignment) method. FIG. 47 (A) is a cross-sectional view of a pixel, which is FIG.
(B) of 7 is a top view of a pixel. Further, the cross-sectional view of the pixel shown in FIG. 47 (A) is shown in FIG.
It corresponds to the line segment aa'in the top view of the pixel shown in (B) of 7. By applying the display device of the present embodiment to the liquid crystal display device having a pixel structure shown in FIG. 47, it is possible to obtain a liquid crystal display device having a large viewing angle, a high response speed, and a high contrast.

The pixel structure of the MVA type liquid crystal display device will be described with reference to FIG. 47 (A). The liquid crystal display device has a core portion for displaying an image, which is called a liquid crystal panel. The liquid crystal panel is manufactured by laminating two processed substrates with a gap of several μm and injecting a liquid crystal material between the two substrates. In FIG. 47 (A), the two substrates are the first substrate 10201 and the second substrate 10216. A TFT and a pixel electrode are formed on the first substrate, and a light-shielding film 10214, a color filter 10215, a fourth conductive layer 10213, a spacer 10217, a second alignment film 10212, and an orientation control are formed on the second substrate. The projection 10219 may be manufactured.

The display device of this embodiment can be implemented without forming a TFT on the first substrate 10201. When the TFT is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when manufacturing a TFT, a larger display device can be obtained.

The TFT shown in FIG. 47 is a bottom gate type TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost by using a large-area substrate. However, the display device of the present embodiment is not limited to this. The structure of the TFT that can be used includes a channel etch type and a channel protection type for the bottom gate type TFT. Moreover, the top gate type may be used. Further, not only amorphous semiconductors but also polycrystalline semiconductors can be used.

The display device of this embodiment can be implemented without forming a light-shielding film 10214 on the second substrate 10216. If the light-shielding film 10214 is not manufactured, the number of steps is reduced, so that
The manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light-shielding film 10214 is manufactured, it is possible to obtain a display device having less light leakage when displaying black.

The display device of the present embodiment can be implemented without forming the color filter 10215 on the second substrate 10216. When the color filter 10215 is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. However, even if the color filter 10215 is not manufactured, it is possible to obtain a display device capable of color display by field sequential drive. On the other hand, when the color filter 10215 is manufactured, it is possible to obtain a display device capable of displaying colors.

The display device of the present embodiment can also be implemented by spraying a spherical spacer without forming the spacer 10217 on the second substrate 10216. When the spherical spacer is sprayed, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the spacer 10217 is manufactured, the position of the spacer does not vary, so that the distance between the two substrates can be made uniform.
A display device with less display unevenness can be obtained.

Next, the processing performed on the first substrate 10201 may be omitted because the method described with reference to FIG. 46 may be used. Here, the first substrate 10201, the first insulating film 10202, the first conductive layer 10203, the second insulating film 10204, the first semiconductor layer 10205, the second semiconductor layer 10206, and the second conductive layer 10207. , Third insulating film 10208, third conductive layer 1020
9. The first alignment film 10210 is the first substrate 10101 and the first in FIG. 46, respectively.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
It corresponds to 108, the third conductive layer 10109, and the first alignment film 10110. Although not shown, an orientation control protrusion may be provided on the first substrate side as well. By doing so, the orientation of the liquid crystal molecules can be controlled more reliably. In addition, the first alignment film 10210 and the second alignment film 10210.
The alignment film 10212 may be a vertical alignment film. By doing so, the liquid crystal molecule 10218 can be vertically oriented.

The first substrate 10201 manufactured as described above, the light-shielding film 10214, and the color filter 10
215, 4th conductive layer 10213, spacer 10217, and 2nd alignment film 10212
A liquid crystal panel can be manufactured by laminating the second substrate 10216 on which the above is prepared with a gap of several μm by a sealing material and injecting a liquid crystal material between the two substrates. In the MVA type liquid crystal panel as shown in FIG. 47, the fourth conductive layer 10213 is the second.
It may be manufactured on the entire surface of the substrate 10216 of the above. Further, the orientation control protrusion 10219 may be formed in contact with the fourth conductive layer 10213. The shape of the orientation control protrusion 10219 is not limited, but it is preferably a shape having a smooth curved surface. By doing this,
Since the orientations of the adjacent liquid crystal molecules 10218 are very close to each other, poor orientation is reduced. Further, it is possible to reduce the defect of the alignment film due to the second alignment film 10212 being cut off by the alignment control projection 10219.

Next, the characteristics of the pixel structure of the MVA type liquid crystal panel shown in FIG. 47 will be described. Figure 4
The liquid crystal molecule 10218 shown in (A) of No. 7 is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecule 10218, in FIG. 47 (A), it is expressed by its length. That is, it is assumed that the orientation of the long axis of the long-expressed liquid crystal molecule 10218 is parallel to the paper surface, and the shorter the expressed liquid crystal molecule 10218 is, the closer the orientation of the long axis is to the normal direction of the paper surface. .. That is, the liquid crystal molecule 10218 shown in FIG. 47 (A) is oriented so that the direction of the long axis thereof faces the normal direction of the alignment film. Therefore, the protrusion 1021 for orientation control
The liquid crystal molecule 10218 in a certain portion of 9 is oriented radially around the orientation control protrusion 10219. In this state, a liquid crystal display device having a large viewing angle can be obtained.

Next, an example of the pixel layout when the display device of the present embodiment is applied to the MVA type liquid crystal display device will be described with reference to FIG. 47 (B). The pixels of the MVA type liquid crystal display device to which the display device of the present embodiment is applied are the scanning line 10221 and the video signal line 102.
22, the capacitance line 10223, the TFT 10224, the pixel electrode 10225, and the pixel capacitance 1.
0226 and an orientation control protrusion 10219 may be provided.

Since the scanning line 10221 is electrically connected to the gate electrode of the TFT 10224, it is preferably composed of the first conductive layer 10203.

Since the video signal line 10222 is electrically connected to the source electrode or drain electrode of the TFT 10224, it is preferably composed of the second conductive layer 10207. Further, since the scanning lines 10221 and the video signal lines 10222 are arranged in a matrix, at least,
It is preferably formed of different conductive layers.

By arranging the capacitance line 10223 in parallel with the pixel electrode 10225, the pixel capacitance 1022
6 is a wiring for forming, and it is preferable that the wiring is composed of the first conductive layer 10203. As shown in FIG. 47 (B), the capacitance line 10223 may be extended along the video signal line 10222 so as to surround the video signal line 10222. By doing so, it is possible to reduce the phenomenon that the potential of the electrode that should hold the potential changes with the potential change of the video signal line 10222, that is, so-called crosstalk. In addition, in order to reduce the cross capacitance with the video signal line 10222, as shown in FIG. 47 (B), the first semiconductor layer 10205
May be provided in the intersection region of the capacitance line 10223 and the video signal line 10222.

The TFT 10224 operates as a switch for conducting the video signal line 10222 and the pixel electrode 10225. As shown in FIG. 47 (B), either the source region or the drain region of the TFT 10224 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained in a small area, and the switching capacity can be increased. As shown in FIG. 47 (B), the TFT is
The gate electrode of 10224 may be arranged so as to surround the first semiconductor layer 10205.

The pixel electrode 10225 is electrically connected to either the source electrode or the drain electrode of the TFT 10224. The pixel electrode 10225 is an electrode for applying a signal voltage transmitted by the video signal line 10222 to the liquid crystal element. In addition, by arranging the capacitance line 10223,
The pixel capacity 10226 may be formed. By doing so, the pixel electrode 10225 can easily hold the signal voltage transmitted by the video signal line 10222. The pixel electrode 102
25 may be rectangular, as shown in FIG. 47 (B). By doing so, the aperture ratio of the pixels can be increased, so that the efficiency of the liquid crystal display device is improved. Also, the pixel electrode 1
When 0225 is made of a transparent material, a transmissive liquid crystal display device can be obtained. The transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. Further, when the pixel electrode 10225 is made of a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors, and does not require a backlight, so that power consumption can be extremely reduced. When the pixel electrode 10225 is made of both a transparent material and a reflective material, a semi-transmissive liquid crystal display device having the advantages of both can be obtained. When the pixel electrode 10225 is made of a reflective material, the surface of the pixel electrode 10225 may have irregularities. Alternatively, the pixel electrode 10225 can be made uneven by making the surface of the third insulating film 10208 uneven. By doing so, since the reflected light is diffusely reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light becomes small. That is, it is possible to obtain a reflective liquid crystal display device having a constant brightness regardless of the angle.

Next, another example will be described when the display device of the present embodiment is applied to the liquid crystal display device in the VA (Vertical Alignment) mode with reference to FIG. 48. FIG. 48 shows
Of the pixel structure of the VA mode liquid crystal display device, the fourth conductive layer 10313 is patterned to control the liquid crystal molecules to have various orientations and increase the viewing angle, so-called PVA (Paterned Vertical). It is a cross-sectional view and a top view of a pixel when the display device of this embodiment is applied to the (Asignment) method. (A) of FIG. 48 is a cross-sectional view of a pixel, and (B) of FIG. 48 is a top view of the pixel. Further, the cross-sectional view of the pixel shown in FIG. 48A corresponds to the line segment aa'in the top view of the pixel shown in FIG. 48B. By applying the display device of the present embodiment to the liquid crystal display device having a pixel structure shown in FIG. 48, it is possible to obtain a liquid crystal display device having a large viewing angle, a high response speed, and a high contrast.

The pixel structure of the PVA type liquid crystal display device will be described with reference to FIG. 48 (A). The liquid crystal display device has a core portion for displaying an image, which is called a liquid crystal panel. The liquid crystal panel is manufactured by laminating two processed substrates with a gap of several μm and injecting a liquid crystal material between the two substrates. In FIG. 48A, the two substrates are the first substrate 10301 and the second substrate 10316. A TFT and pixel electrodes are manufactured on the first substrate, and a light-shielding film 10314 and a color filter 10315 are formed on the second substrate.
, The fourth conductive layer 10313, the spacer 10317, and the second alignment film 10312 may be produced.

The display device of this embodiment can be implemented without forming a TFT on the first substrate 10301. When the TFT is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when manufacturing a TFT, a larger display device can be obtained.

The TFT shown in FIG. 48 is a bottom gate type TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost by using a large-area substrate. However, the display device of the present embodiment is not limited to this. The structure of the TFT that can be used includes a channel etch type and a channel protection type for the bottom gate type TFT. Moreover, the top gate type may be used. Further, not only amorphous semiconductors but also polycrystalline semiconductors can be used.

The display device of the present embodiment can be implemented without forming a light-shielding film 10314 on the second substrate 10316. If the light-shielding film 10314 is not manufactured, the number of steps is reduced, so that
The manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light-shielding film 10314 is manufactured, it is possible to obtain a display device having less light leakage when displaying black.

The display device of the present embodiment can be implemented without manufacturing the color filter 10315 on the second substrate 10316. If the color filter 10315 is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Also, because the structure is simple,
Yield can be improved. However, even if the color filter 10315 is not manufactured, it is possible to obtain a display device capable of color display by field sequential drive. On the other hand, when the color filter 10315 is manufactured, a display device capable of displaying colors can be obtained.

The display device of the present embodiment can also be implemented by spraying a spherical spacer without forming the spacer 10317 on the second substrate 10316. When the spherical spacer is sprayed, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the spacer 10317 is manufactured, the positions of the spacers do not vary, so that the distance between the two substrates can be made uniform.
A display device with less display unevenness can be obtained.

Next, the processing performed on the first substrate 10301 may be omitted because the method described with reference to FIG. 46 may be used. Here, the first substrate 10301, the first insulating film 10302, the first conductive layer 10303, the second insulating film 10304, the first semiconductor layer 10305, the second semiconductor layer 10306, and the second conductive layer 10307. , Third insulating film 10308, third conductive layer 1030
9. The first alignment film 10310 is the first substrate 10101 and the first in FIG. 46, respectively.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
It corresponds to 108, the third conductive layer 10109, and the first alignment film 10110. The electrode notch may be provided in the third conductive layer 10309 on the first substrate 10301 side. By doing so, the orientation of the liquid crystal molecules can be controlled more reliably. Further, the first alignment film 10
The 310 and the second alignment film 10312 may be a vertical alignment film. By doing so, the liquid crystal molecule 10318 can be vertically oriented.

The first substrate 10301 produced as described above, the light-shielding film 10314, and the color filter 10
315, 4th conductive layer 10313, spacer 10317, and 2nd alignment film 10312
A liquid crystal panel can be manufactured by laminating the second substrate 10316 on which the above is prepared with a gap of several μm by a sealing material and injecting a liquid crystal material between the two substrates. In the PVA type liquid crystal panel as shown in FIG. 48, the fourth conductive layer 10313 may be patterned to form an electrode cutout portion 10319. The shape of the electrode cutout portion 10319 is not limited, but a shape in which a plurality of rectangles having different orientations are combined is preferable. By doing so, since a plurality of regions having different orientations can be formed, a liquid crystal display device having a large viewing angle can be obtained. Further, it is preferable that the shape of the fourth conductive layer 10313 at the boundary between the electrode cutout portion 10319 and the fourth conductive layer 10313 is a smooth curve. By doing so, the orientation of the adjacent liquid crystal molecules 10318 becomes very close, so that the orientation defect is reduced. Further, the second alignment film 10312 has an electrode notch portion 10.
It is also possible to reduce the defect of the alignment film due to the step break caused by 319.

Next, the characteristics of the pixel structure of the PVA type liquid crystal panel shown in FIG. 48 will be described. Figure 4
The liquid crystal molecule 10318 shown in (A) of No. 8 is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecule 10318, in FIG. 48 (A), it is expressed by its length. That is, it is assumed that the orientation of the long axis of the long-represented liquid crystal molecule 10318 is parallel to the paper surface, and the shorter the representation of the liquid crystal molecule 10318, the closer the orientation of the long axis is to the normal direction of the paper surface. .. That is, the liquid crystal molecule 10318 shown in FIG. 48 (A) is oriented so that the direction of its long axis faces the normal direction of the alignment film. Therefore, the electrode notch portion 1031
The liquid crystal molecule 10318 in a portion of 9 has an electrode notch 10319 and a fourth conductive layer 103.
It is oriented radially around the boundary of 13. In this state, a liquid crystal display device having a large viewing angle can be obtained.

Next, an example of the pixel layout when the display device of the present embodiment is applied to the PVA type liquid crystal display device will be described with reference to FIG. 48 (B). The pixels of the PVA type liquid crystal display device to which the display device of the present embodiment is applied are the scanning line 10321 and the video signal line 103.
22, the capacitance line 10323, the TFT 10324, the pixel electrode 10325, and the pixel capacitance 1.
0326 and an electrode notch 10319 may be provided.

Since the scanning line 10321 is electrically connected to the gate electrode of the TFT 10324, it is preferably composed of the first conductive layer 10303.

Since the video signal line 10322 is electrically connected to the source electrode or drain electrode of the TFT 10324, it is preferably composed of the second conductive layer 10307. Further, since the scanning lines 10321 and the video signal lines 10322 are arranged in a matrix, at least,
It is preferably formed of different conductive layers.

The capacitance line 10323 is arranged in parallel with the pixel electrode 10325 to have a pixel capacitance of 1032.
6 is a wiring for forming, and it is preferable that the wiring is composed of the first conductive layer 10303. As shown in FIG. 48 (B), the capacitance line 10323 may be extended along the video signal line 10322 so as to surround the video signal line 10322. By doing so, it is possible to reduce the phenomenon that the potential of the electrode that should hold the potential changes with the potential change of the video signal line 10322, that is, so-called crosstalk. In addition, in order to reduce the cross capacitance with the video signal line 10322, as shown in FIG. 48 (B), the first semiconductor layer 10305
May be provided in the intersection region of the capacitance line 10323 and the video signal line 10322.

The TFT 10324 operates as a switch for conducting the video signal line 10322 and the pixel electrode 10325. As shown in FIG. 48 (B), either the source region or the drain region of the TFT 10324 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained in a small area, and the switching capacity can be increased. As shown in FIG. 48 (B), the TFT is
The gate electrode of 10324 may be arranged so as to surround the first semiconductor layer 10305.

The pixel electrode 10325 is electrically connected to either the source electrode or the drain electrode of the TFT 10324. The pixel electrode 10325 is an electrode for applying a signal voltage transmitted by the video signal line 10322 to the liquid crystal element. In addition, by arranging the capacity line 10323,
The pixel capacity 10326 may be formed. By doing so, the pixel electrode 10325 can easily hold the signal voltage transmitted by the video signal line 10322. The pixel electrode 103
As shown in FIG. 48B, 25 is a pixel electrode 103 in a portion without the electrode cutout portion 10319 according to the shape of the electrode cutout portion 10319 provided in the fourth conductive layer 10313.
It is preferable to form a notched portion of 25. By doing this, the liquid crystal molecule 10318
Since it is possible to form a plurality of regions having different orientations, it is possible to obtain a liquid crystal display device having a large viewing angle. When the pixel electrode 10325 is made of a transparent material,
A transmissive liquid crystal display device can be obtained. The transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. Further, when the pixel electrode 10325 is made of a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors, and does not require a backlight, so that power consumption can be extremely reduced. When the pixel electrode 10325 is made of both a transparent material and a reflective material, a semi-transmissive liquid crystal display device having the advantages of both can be obtained. When the pixel electrode 10325 is made of a reflective material, the surface of the pixel electrode 10325 may have irregularities. Alternatively, the pixel electrode 10325 can be made uneven by making the surface of the third insulating film 10308 uneven. By doing so, since the reflected light is diffusely reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light becomes small. That is, it is possible to obtain a reflective liquid crystal display device having a constant brightness regardless of the angle.

Next, a case where the display device of the present embodiment is applied to the horizontal electric field type liquid crystal display device will be described with reference to FIG. 49. FIG. 49 shows the pixel electrode 10425 and the common electrode 10423 in the pixel structure of the liquid crystal display device in which an electric field is applied in the lateral direction in order to perform switching so that the orientation of the liquid crystal molecules is always horizontal to the substrate. Cross-sectional view and top surface of pixels when the display device of this embodiment is applied to the so-called IPS (In-Plane-Switching) method, which applies an electric field in the lateral direction by applying a comb-shaped pattern. It is a figure. (A) of FIG. 49 is a cross-sectional view of a pixel, and (B) of FIG. 49 is a top view of the pixel. In addition, FIG. 49
The cross-sectional view of the pixel shown in (A) of FIG. 49 is a line segment aa in the top view of the pixel shown in (B) of FIG.
It corresponds to'. By applying the display device of the present embodiment to the liquid crystal display device having a pixel structure shown in FIG. 49, it is possible to obtain a liquid crystal display device having a large viewing angle and a small gradation dependence of the response speed in principle.

The pixel structure of the IPS type liquid crystal display device will be described with reference to FIG. 49 (A). The liquid crystal display device has a core portion for displaying an image, which is called a liquid crystal panel. The liquid crystal panel is manufactured by laminating two processed substrates with a gap of several μm and injecting a liquid crystal material between the two substrates. In (A) of FIG. 49, the two substrates are the first substrate 10401 and the second substrate 10416. A TFT and pixel electrodes are manufactured on the first substrate, and a light-shielding film 10414 and a color filter 10415 are formed on the second substrate.
, Spacer 10417, and second alignment film 10412 may be made.

The display device of this embodiment can be implemented without forming a TFT on the first substrate 10401. When the TFT is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when manufacturing a TFT, a larger display device can be obtained.

The TFT shown in FIG. 49 is a bottom gate type TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost by using a large-area substrate. However, the display device of the present embodiment is not limited to this. The structure of the TFT that can be used includes a channel etch type and a channel protection type for the bottom gate type TFT. Moreover, the top gate type may be used. Further, not only amorphous semiconductors but also polycrystalline semiconductors can be used.

The display device of the present embodiment can be implemented without forming a light-shielding film 10414 on the second substrate 10416. If the light-shielding film 10414 is not manufactured, the number of steps is reduced, so that
The manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light-shielding film 10414 is manufactured, it is possible to obtain a display device having less light leakage when displaying black.

The display device of the present embodiment can be implemented without forming the color filter 10415 on the second substrate 10416. When the color filter 10415 is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. However, the color filter 1041
Even when 5 is not manufactured, it is possible to obtain a display device capable of color display by field sequential drive. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the color filter 10415 is manufactured, a display device capable of displaying colors can be obtained.

The display device of the present embodiment can also be implemented by spraying a spherical spacer without forming the spacer 10417 on the second substrate 10416. When the spherical spacer is sprayed, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the spacer 10417 is manufactured, the positions of the spacers do not vary, so that the distance between the two substrates can be made uniform.
A display device with less display unevenness can be obtained.

Next, the processing performed on the first substrate 10401 may be omitted because the method described with reference to FIG. 46 may be used. Here, the first substrate 10401, the first insulating film 10402, the first conductive layer 10403, the second insulating film 10404, the first semiconductor layer 10405, the second semiconductor layer 10406, and the second conductive layer 10407. , Third insulating film 10408, third conductive layer 1040
9. The first alignment film 10410 is the first substrate 10101 and the first in FIG. 46, respectively.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
It corresponds to 108, the third conductive layer 10109, and the first alignment film 10110. The third conductive layer 10409 on the side of the first substrate 10401 was patterned and meshed with each other.
It may be formed in the shape of two comb teeth. Further, one comb-shaped electrode may be electrically connected to one of the source electrode or the drain electrode of the TFT 10424, and the other comb-shaped electrode may be electrically connected to the common electrode 10423. By doing this, the liquid crystal molecule 10418
A lateral electric field can be effectively applied to.

The first substrate 10401, the light-shielding film 10414, and the color filter 10 produced as described above.
The second substrate 10 on which the 415, the spacer 10417, and the second alignment film 10412 were prepared.
A liquid crystal panel can be manufactured by laminating 416 with a gap of several μm by a sealing material and injecting a liquid crystal material between two substrates. Although not shown, the second substrate 1
A conductive layer may be formed on the 0416 side. By forming the conductive layer on the side of the second substrate 10416, it is possible to reduce the influence of electromagnetic wave noise from the outside.

Next, the characteristics of the pixel structure of the IPS liquid crystal panel shown in FIG. 49 will be described. Figure 4
The liquid crystal molecule 10418 shown in (A) of 9 is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecule 10418, in FIG. 49 (A), it is expressed by its length. That is, it is assumed that the orientation of the long axis of the long-expressed liquid crystal molecule 10418 is parallel to the paper surface, and the shorter the expressed liquid crystal molecule 10418 is, the closer the orientation of the long axis is to the normal direction of the paper surface. .. That is, the liquid crystal molecule 10418 shown in FIG. 49 (A) is oriented so that its long axis always faces the horizontal direction with respect to the substrate. In (A) of FIG. 49,
It represents the orientation in the absence of an electric field, but when an electric field is applied to the liquid crystal molecule 10418, it rotates in a horizontal plane while always maintaining the direction of its major axis horizontal to the substrate. In this state, a liquid crystal display device having a large viewing angle can be obtained.

Next, an example of the pixel layout when the display device of the present embodiment is applied to the IPS type liquid crystal display device will be described with reference to FIG. 49 (B). The pixels of the IPS type liquid crystal display device to which the display device of the present embodiment is applied are the scanning line 10421 and the video signal line 104.
22, a common electrode 10423, a TFT 10424, and a pixel electrode 10425 may be provided.

Since the scanning line 10421 is electrically connected to the gate electrode of the TFT 10424, it is preferably composed of the first conductive layer 10403.

Since the video signal line 10422 is electrically connected to the source electrode or drain electrode of the TFT 10424, it is preferably composed of the second conductive layer 10407. Further, since the scanning lines 10421 and the video signal lines 10422 are arranged in a matrix, at least,
It is preferably formed of different conductive layers. As shown in FIG. 49B, the video signal line 10422 may be formed so as to be bent in the pixel so as to match the shapes of the pixel electrode 10425 and the common electrode 10423. By doing so, the aperture ratio of the pixels can be increased, so that the efficiency of the liquid crystal display device can be improved.

The common electrode 10423 is an electrode for generating an electric field in the lateral direction by being arranged in parallel with the pixel electrode 10425, and is composed of a first conductive layer 10403 and a third conductive layer 10409. Suitable. As shown in FIG. 49 (B), the common electrode 1042
3 may be extended along the video signal line 10422 so as to surround the video signal line 10422. By doing so, it is possible to reduce the phenomenon that the potential of the electrode that should hold the potential changes with the potential change of the video signal line 10422, that is, so-called crosstalk.
In order to reduce the cross capacitance with the video signal line 10422, the first semiconductor layer 10405 may be provided in the crossing region between the common electrode 10423 and the video signal line 10422, as shown in FIG. 49 (B).

The TFT 10424 operates as a switch for conducting the video signal line 10422 and the pixel electrode 10425. As shown in FIG. 49 (B), either the source region or the drain region of the TFT 10424 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained in a small area, and the switching capacity can be increased. As shown in FIG. 49 (B), the TFT
The gate electrode of 10424 may be arranged so as to surround the first semiconductor layer 10405.

The pixel electrode 10425 is electrically connected to either the source electrode or the drain electrode of the TFT 10424. The pixel electrode 10425 is an electrode for applying a signal voltage transmitted by the video signal line 10422 to the liquid crystal element. Further, the pixel capacitance may be formed by arranging the common electrode 10423. By doing so, the pixel electrode 10325 becomes the video signal line 10.
It becomes easy to hold the signal voltage transmitted by 422. The pixel electrode 10425 and the comb-shaped common electrode 10423 are preferably formed in a bent comb-shaped shape as shown in FIG. 49 (B). By doing so, it is possible to form a plurality of regions in which the orientations of the liquid crystal molecules 10418 are different, so that a liquid crystal display device having a large viewing angle can be obtained. Further, when the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of a transparent material, a transmissive liquid crystal display device can be obtained. The transmissive liquid crystal display device is
It has high color reproducibility and can display images with high image quality. Further, in the transmissive liquid crystal display device, the pixels have a high aperture ratio, and the light efficiency can be improved. However, even when the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of a material that does not have transparency and does not have reflection, a transmissive liquid crystal display device can be obtained. Since the transmissive liquid crystal display device transmits light only through the liquid crystal molecules 10418 in the portion where the lateral electric field exists, it is possible to display an image having high color reproducibility and high image quality. When the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of a reflective material,
A semi-transmissive liquid crystal display device can be obtained. The semi-transmissive liquid crystal display device has high visibility in a bright environment such as outdoors, and can greatly reduce power consumption. moreover,
The semi-transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. However, even when the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of both a transparent material and a reflective material, a transflective liquid crystal display device can be obtained. When the pixel electrode 10425 and the comb-shaped common electrode 10423 are made of a reflective material, the pixel electrode 10425 and the comb-shaped common electrode 10 are used.
The surface of the 423 may be uneven. Alternatively, the pixel electrode 10425 and the comb-shaped common electrode 10423 can be made uneven by making the surface of the third insulating film 10408 uneven. By doing so, since the reflected light is diffusely reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light becomes small. That is, it is possible to obtain a reflective liquid crystal display device having a constant brightness regardless of the angle.

It is said that the comb-shaped pixel electrode 10425 and the comb-shaped common electrode 10423 are both formed of the third conductive layer 10409, but the pixel configuration to which the display device of the present embodiment can be applied is this. It is not limited to, and can be appropriately selected. For example, comb-shaped pixel electrode 1042
5 and the comb-shaped common electrode 10423 may both be formed by the second conductive layer 10407, both may be formed by the first conductive layer 10403, or either one may be formed by the third conductive layer. Layer 1
It may be formed of 0409 and the other may be formed of a second conductive layer 10407, or one may be formed of a third conductive layer 10409 and the other may be formed of a first conductive layer 10407. ,
Either one may be formed of the second conductive layer 10409 and the other may be formed of the first conductive layer 10407.

Next, a case where the display device of the present embodiment is applied to another horizontal electric field type liquid crystal display device will be described with reference to FIG. 50. FIG. 50 is a diagram showing another pixel structure of a liquid crystal display device of a type in which an electric field is applied in the lateral direction in order to perform switching so that the orientation of the liquid crystal molecules is always horizontal with respect to the substrate. More specifically, one of the pixel electrode 10525 and the common electrode 10523 is subjected to comb-shaped pattern processing, and the other is formed by uniformly forming an electrode in a region overlapping the comb-shaped shape. A method of applying an electric field in the direction, so-called FFS (Fringe Fi)
It is a cross-sectional view and a top view of a pixel when the display device of this embodiment is applied to the eld switching) method. (A) of FIG. 50 is a cross-sectional view of a pixel, and (B) of FIG. 50 is a sectional view of a pixel.
It is a top view of a pixel. Further, the cross-sectional view of the pixel shown in FIG. 50A corresponds to the line segment aa'in the top view of the pixel shown in FIG. 50B. By applying the display device of the present embodiment to the liquid crystal display device having a pixel structure shown in FIG. 50, it is possible to obtain a liquid crystal display device having a large viewing angle and a small gradation dependence of the response speed in principle.

The pixel structure of the FFS type liquid crystal display device will be described with reference to FIG. 50 (A). The liquid crystal display device has a core portion for displaying an image, which is called a liquid crystal panel. The liquid crystal panel is manufactured by laminating two processed substrates with a gap of several μm and injecting a liquid crystal material between the two substrates. In FIG. 50A, the two substrates are the first substrate 10501 and the second substrate 10516. A TFT and a pixel electrode may be formed on the first substrate, and a light-shielding film 10514, a color filter 10515, a spacer 10517, and a second alignment film 10512 may be formed on the second substrate.

The display device of this embodiment can be implemented without manufacturing a TFT on the first substrate 10501. When the TFT is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when manufacturing a TFT, a larger display device can be obtained.

The TFT shown in FIG. 50 is a bottom gate type TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost by using a large-area substrate. However, the display device of the present embodiment is not limited to this. The structure of the TFT that can be used includes a channel etch type and a channel protection type for the bottom gate type TFT. Moreover, the top gate type may be used. Further, not only amorphous semiconductors but also polycrystalline semiconductors can be used.

The display device of the present embodiment can be implemented without forming a light-shielding film 10514 on the second substrate 10516. If the light-shielding film 10514 is not manufactured, the number of steps is reduced, so that
The manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the light-shielding film 10514 is manufactured, it is possible to obtain a display device having less light leakage when displaying black.

The display device of the present embodiment can be implemented without manufacturing the color filter 10515 on the second substrate 10516. When the color filter 10515 is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. However, even if the color filter 10515 is not manufactured, it is possible to obtain a display device capable of color display by field sequential drive. On the other hand, when the color filter 10515 is manufactured, it is possible to obtain a display device capable of displaying colors.

The display device of the present embodiment can also be implemented by spraying a spherical spacer without forming the spacer 10517 on the second substrate 10516. When the spherical spacer is sprayed, the number of steps is reduced, so that the manufacturing cost can be reduced. Moreover, since the structure is simple, the yield can be improved. On the other hand, when the spacer 10517 is manufactured and used as the display device of the present embodiment, the position of the spacer does not vary, so that the distance between the two substrates can be made uniform, and a display device with less display unevenness can be obtained. be able to.

Next, the processing performed on the first substrate 10501 may be omitted because the method described with reference to FIG. 46 may be used. Here, the first substrate 10501, the first insulating film 10502, the first conductive layer 10503, the second insulating film 10504, the first semiconductor layer 10505, the second semiconductor layer 10506, and the second conductive layer 10507. , Third insulating film 10508, third conductive layer 1050
9. The first alignment film 10510 is the first substrate 10101 and the first in FIG. 46, respectively.
Insulating film 10102, first conductive layer 10103, second insulating film 10104, first semiconductor layer 10105, second semiconductor layer 10106, second conductive layer 10107, third insulating film 10
It corresponds to 108, the third conductive layer 10109, and the first alignment film 10110.

However, the difference from FIG. 46 is that the fourth insulating film 10519 and the fourth conductive layer 10513 may be formed on the first substrate 10501 side. More specifically, after pattern processing is applied to the third conductive layer 10509, a fourth insulating film 10519 is formed, and after pattern processing is performed to form a contact hole, a fourth conductive layer 10513 is formed. The first alignment film 10510 may be formed after the film is formed and the pattern is processed in the same manner. As the materials and processing methods that can be used for the fourth insulating film 10519 and the fourth conductive layer 10513, the same materials and processing methods as those used for the third insulating film 10508 and the third conductive layer 10509 can be used. Further, one comb-shaped electrode may be electrically connected to one of the source electrode or the drain electrode of the TFT 10524, and the other uniform electrode may be electrically connected to the common electrode 10523. By doing so, a lateral electric field can be effectively applied to the liquid crystal molecule 10518.

The first substrate 10501 manufactured as described above, the light-shielding film 10514, and the color filter 10
The second substrate 10 on which the 515, the spacer 10517, and the second alignment film 10512 were prepared.
A liquid crystal panel can be manufactured by laminating 516 with a sealing material having a gap of several μm and injecting a liquid crystal material between two substrates. Although not shown, the second substrate 1
A conductive layer may be formed on the 0516 side. By forming the conductive layer on the side of the second substrate 10516, it is possible to reduce the influence of electromagnetic wave noise from the outside.

Next, the characteristics of the pixel structure of the FFS type liquid crystal panel shown in FIG. 50 will be described. Figure 5
The liquid crystal molecule 10518 shown in (A) of 0 is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecule 10518, in FIG. 50 (A), it is expressed by its length. That is, it is assumed that the orientation of the long axis of the long-represented liquid crystal molecule 10518 is parallel to the paper surface, and the shorter the representation of the liquid crystal molecule 10518, the closer the orientation of the long axis is to the normal direction of the paper surface. .. That is, the liquid crystal molecule 10518 shown in FIG. 50 (A) is oriented so that its long axis always faces the horizontal direction with respect to the substrate. In (A) of FIG. 50,
Although it represents the orientation in the absence of an electric field, when an electric field is applied to the liquid crystal molecules 10518, the liquid crystal molecules rotate in a horizontal plane while always maintaining the horizontal direction with the substrate. In this state, a liquid crystal display device having a large viewing angle can be obtained.

Next, an example of the pixel layout when the display device of the present embodiment is applied to the FFS type liquid crystal display device will be described with reference to FIG. 50 (B). The pixels of the FFS type liquid crystal display device to which the display device of the present embodiment is applied are the scanning line 10521 and the video signal line 105.
22, a common electrode 10523, a TFT 10524, and a pixel electrode 10525 may be provided.

Since the scanning line 10521 is electrically connected to the gate electrode of the TFT 10524, it is preferably composed of the first conductive layer 10503.

Since the video signal line 10522 is electrically connected to the source electrode or drain electrode of the TFT 10524, it is preferably composed of the second conductive layer 10507. Further, since the scanning lines 10521 and the video signal lines 10522 are arranged in a matrix, at least,
It is preferably formed of different conductive layers. As shown in FIG. 50B, the video signal line 10522 may be formed so as to be bent in the pixel so as to match the shape of the pixel electrode 10525. By doing this, the aperture ratio of the pixels can be increased, so
The efficiency of the liquid crystal display device can be improved.

The common electrode 10523 is preferably composed of a first conductive layer 10503 and a third conductive layer 10509. In addition, in order to reduce the cross capacitance with the video signal line 10522,
As shown in FIG. 50B, the first semiconductor layer 10505 may be provided at the intersection region of the common electrode 10523 and the video signal line 10522.

The TFT 10524 operates as a switch for conducting the video signal line 10522 and the pixel electrode 10525. As shown in FIG. 50B, either the source region or the drain region of the TFT 10524 may be arranged so as to surround the other of the source region and the drain region. By doing so, a large channel width can be obtained in a small area, and the switching capacity can be increased. As shown in FIG. 50 (B), the TFT is
The gate electrode of 10524 may be arranged so as to surround the first semiconductor layer 10505.

The pixel electrode 10525 is electrically connected to either the source electrode or the drain electrode of the TFT 10524. The pixel electrode 10525 is an electrode for applying a signal voltage transmitted by the video signal line 10522 to the liquid crystal element. Further, the pixel capacitance may be formed by arranging the common electrode 10523. By doing so, the pixel electrode 10525 becomes the video signal line 10.
It becomes easy to hold the signal voltage transmitted by 522. The pixel electrode 10525 is
As shown in FIG. 50 (B), it is preferable to form it as a bent comb-shaped shape. By doing so, it is possible to form a plurality of regions in which the orientations of the liquid crystal molecules 10518 are different, so that a liquid crystal display device having a large viewing angle can be obtained. In addition, the comb-shaped pixel electrode 1052
When the 5 and the common electrode 10523 are made of a transparent material, a transmissive liquid crystal display device can be obtained. However, even when the comb-shaped pixel electrode 10525 is made of a non-reflective material and the common electrode 10523 is made of a transparent material, a transmissive liquid crystal display device can be obtained. The transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. Further, when the comb-shaped pixel electrode 10525 and the common electrode 10523 are made of a reflective material, a reflective liquid crystal display device can be obtained. However, if at least the common electrode 10523 is made of a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors, and does not require a backlight, so that power consumption can be extremely reduced. When the comb-shaped pixel electrode 10525 and the common electrode 10523 are made of both a transparent material and a reflective material, a semi-transmissive liquid crystal display device having the advantages of both is provided. Obtainable. However, the comb-shaped pixel electrode 1
Even when the 0525 is made of a reflective material and the pixel electrode 10525 is made of a transparent material, a semi-transmissive liquid crystal display device can be obtained. When the pixel electrode 10525 and the comb-shaped common electrode 10523 are made of a reflective material, the surfaces of the comb-shaped pixel electrode 10525 and the common electrode 10523 may have irregularities. Alternatively, the comb-shaped pixel electrode 10525 and the common electrode 10523 can be made uneven by making the surface of the third insulating film 10508 uneven. By doing so, since the reflected light is diffusely reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light becomes small. That is, it is possible to obtain a reflective liquid crystal display device having a constant brightness regardless of the angle.

Although the comb-shaped pixel electrode 10525 is formed by the fourth conductive layer 10513 and the uniform common electrode 10523 is formed by the third conductive layer 10509, the display device of the present embodiment is described. The pixel configuration to which is applicable is not limited to this, and can be appropriately selected as long as certain conditions are satisfied. More specifically, the comb-shaped electrode may be located closer to the liquid crystal display than the uniform electrode when viewed from the first substrate 10501. This is because the lateral electric field is always generated in the opposite direction to the uniform electrode when viewed from the comb-shaped electrode. That is, in order to apply a lateral electric field to the liquid crystal, the comb-shaped electrode must be located closer to the liquid crystal than the uniform electrode.

To satisfy this condition, for example, a comb-shaped electrode may be formed by a fourth conductive layer 10513, a uniform electrode may be formed by a third conductive layer 10509, or a comb-shaped electrode may be formed. Fourth conductive layer 1
The uniform electrode may be formed by the second conductive layer 10507, or the comb-shaped electrode may be formed by the fourth conductive layer 10513, and the uniform electrode may be formed by the first conductive layer. The comb-shaped electrode may be formed of 10503, the comb-shaped electrode may be formed of the third conductive layer 10509, and the uniform electrode may be formed of the second conductive layer 10507, or the comb-shaped electrode may be formed of the second conductive layer 10507. The third conductive layer 10509 may be formed and a uniform electrode may be formed by the first conductive layer 10503, or the comb-shaped electrode may be formed by the second conductive layer 1.
It may be formed of 0507 and a uniform electrode may be formed of the first conductive layer 10503. The comb-shaped electrode is electrically connected to either the source region or the drain region of the TFT 10524, and the uniform electrode is electrically connected to the common electrode 10523, but this connection is reversed. But it may be. In that case, uniform electrodes may be formed independently for each pixel.

Subsequently, various liquid crystal modes applicable to the liquid crystal display device of the present embodiment will be described.

First, FIGS. 51 (A1) and 51 (A2) show a schematic diagram of a TN mode liquid crystal display device.

Similar to the above embodiment, the liquid crystal layer 10600 is sandwiched between the first substrate 10601 and the second substrate 10602 arranged so as to face each other. And the first substrate 106
A layer 10603 containing a first polarizing element is laminated on the 01 side, and a layer 10604 containing a second polarizing element is arranged on the second substrate 10602 side. The layer 10 containing the first polarizing element
The 603 and the layer 10604 containing the second polarizing element are arranged so as to form a cross Nicol.

Although not shown, the backlight or the like is arranged outside the layer containing the second polarizing element. The first electrode 10605 is placed on the first substrate 10601 and the second substrate 10602, respectively.
, A second electrode 10606 is provided. The first electrode 10605, which is an electrode on the opposite side of the backlight, that is, on the visual recognition side, is formed so as to have at least translucency.

In the liquid crystal display device having the configuration as shown in FIGS. 51 (A1) and 51 (A2), in the normal white mode, a voltage is applied to the first electrode 10605 and the second electrode 10606 (referred to as a longitudinal electric field method). As shown in FIG. 51 (A1), a black display is performed. At this time, the liquid crystal molecules are arranged vertically. Then, the light from the backlight cannot pass through the substrate and is displayed in black.

Then, as shown in FIG. 51 (A2), the first electrode 10605 and the second electrode 10606
When no voltage is applied between, the display is white. At this time, the liquid crystal molecules are lined up side by side,
It will be in a state of rotating in a plane. As a result, the light from the backlight passes through a layer containing a pair of polarizing elements arranged so as to form a cross Nicol (layer 10603 containing the first polarizing element and layer 10604 containing the second polarizing element). And the predetermined video display is performed.

The liquid crystal display device having the configuration as shown in FIGS. 51 (A1) and 51 (A2) can perform full-color display by providing a color filter. The color filter is the first substrate 10
It can be provided on either the 601 side or the second substrate 10602 side. However, FIG. 5
A liquid crystal display device having a configuration as shown in 1 (A1) and (A2) can perform full-color display by field sequential drive if the light from the backlight changes with time without providing a color filter.

As the liquid crystal material used in the TN mode, a known one may be used.

FIG. 51 (B1) shows a schematic diagram of a liquid crystal display device in VA mode. The VA mode is a mode in which the liquid crystal molecules are oriented so as to be perpendicular to the substrate when there is no electric field.

Similar to FIGS. 51 (A1) and 51 (A2), a first electrode 10605 and a second electrode 10606 are provided on the first substrate 10601 and the second substrate 10602, respectively. The first electrode 10605, which is an electrode on the opposite side of the backlight, that is, on the visual recognition side, is formed so as to have at least translucency. Then, a layer 10603 containing a first polarizing element is laminated on the first substrate 10601 side, and a layer 1 containing a second polarizing element is laminated on the second substrate 10602 side.
0604 is arranged. The layer 10603 containing the first polarizing element and the layer 10604 containing the second polarizing element are arranged so as to form a cross Nicol.

In the liquid crystal display device having the configuration as shown in FIGS. 51 (A1) and 51 (A2), the first electrode 106
When a voltage is applied to 05 and the second electrode 10606 (longitudinal electric field method), FIG. 51 (B1).
As shown in, the white display is performed and the on state is set. At this time, the liquid crystal molecules are arranged side by side. Then, the light from the backlight is a layer containing a pair of substituents arranged so as to form a cross Nicol (a layer 10603 containing a first polarizing element and a layer 10604 containing a second polarizing element).
) Can be passed, and a predetermined video display is performed. At this time, by providing a color filter, full-color display can be performed. The color filter is the first substrate 10
It can be provided on either the 601 side or the second substrate 10602 side.

Then, as shown in FIG. 51 (B2), the first electrode 10605 and the second electrode 10606
When no voltage is applied during, it is displayed in black, that is, it is turned off. At this time, the liquid crystal molecules are arranged vertically. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

In the off state, the liquid crystal molecules stand up perpendicular to the substrate and display in black, and in the on state, the liquid crystal molecules fall horizontally with respect to the substrate and display in white. Since the liquid crystal molecules stand up in the off state, the light from the polarized backlight passes through the cell without being affected by the birefringence of the liquid crystal molecules and is blocked by the layer containing the polarizing element on the opposite substrate side. be able to.

Here, FIGS. 51 (C1) and 51 (C2) show an example of applying a layer containing a laminated polarizing element of the display device of the present embodiment to the MVA mode in which the orientation of the liquid crystal is divided. The MVA mode is a method of compensating each other for the viewing angle dependence of each part. As shown in FIG. 51 (C1), M
In the VA mode, protrusions 10607 and 10608 having a triangular cross section are provided on the first electrode 10605 and the second electrode 10606 for orientation control. First electrode 10605
When a voltage is applied to the second electrode 10606 (longitudinal electric field method), a white display is performed as shown in FIG. 51 (C1), and the on state is set. At this time, the liquid crystal molecules are in a state of being tilted and lined up with respect to the protrusions 10607 and 10608. Then, the light from the backlight is a layer containing a pair of polarizing elements arranged so as to form a cross Nicol (layer 1060 containing a first polarizing element).
It can pass through the layer 10604) containing the third and the second polarizing element, and a predetermined image display is performed. The liquid crystal display device having the configuration shown in FIGS. 51 (C1) and 51 (C2) can perform full-color display by providing a color filter. The color filter is
It can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, the liquid crystal display device having the configuration shown in FIGS. 51 (C1) and 51 (C2) can perform full-color display by field sequential drive without providing a color filter.

Then, as shown in FIG. 51 (C2), the first electrode 10605 and the second electrode 1060
When no voltage is applied during 6, the black display, that is, the off state is set. At this time, the liquid crystal molecules are arranged vertically. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

A top view and a cross-sectional view of another example of the MVA mode are shown in FIG. 54. As shown in FIG. 54 (A), the second electrodes 10606a, 10606b, and 10606c may be formed in a bent pattern like a dogleg. Further, the insulating layers 10901 and 10902 are formed in the vicinity of the liquid crystal layer 10600. The insulating layers 10901 and 10902 may be alignment films. As shown in FIG. 54 (B), the protrusion 1 is located close to the first electrode 10605.
0607 may be formed corresponding to the second electrode 10606a, 10606b, 10606c. The protrusion 10607 is attached to the second electrode 10606a, 10606b, 10606c.
By forming in correspondence with, the second electrode 10606a, 10606b, 10606
The opening of c functions like a protrusion and can effectively orient the liquid crystal molecules. The order in which the first electrode 10605 and the protrusion 10607 are formed may be reversed from that in FIG. 54 (B).

FIGS. 52 (A1) and 52 (A2) show a schematic diagram of an OCB mode liquid crystal display device. In the OCB mode, the arrangement of liquid crystal molecules in the liquid crystal layer optically forms a compensating state, which is called bend orientation.

Similar to FIG. 51, a first electrode 10605 and a second electrode 10606 are provided on the first substrate 10601 and the second substrate 10602, respectively. Further, although not shown, the backlight or the like is arranged outside the layer 10604 containing the second polarizing element. The first electrode 10605, which is an electrode on the opposite side of the backlight, that is, on the visual recognition side, is formed so as to have at least translucency. Then, on the side of the first substrate 10601, the layer 1 containing the first polarizing element 1 is formed.
0603 is laminated, and a layer 10604 containing a second polarizing element is arranged on the second substrate 10602 side. The layer 10603 containing the first polarizing element and the layer 10 containing the second polarizing element.
604 is arranged so as to be a cross Nicol.

In the liquid crystal display device having the configuration as shown in FIGS. 52 (A1) and 52 (A2), the first electrode 106
When a constant on-voltage is applied to 05 and the second electrode 10606 (longitudinal electric field method), FIG. 5
As shown in 2 (A1), black display is performed. At this time, the liquid crystal molecules are arranged vertically. Then, the light from the backlight cannot pass through the substrate and is displayed in black.

Then, as shown in FIG. 52 (A2), the first electrode 10605 and the second electrode 1060
When a constant off voltage is applied during 6, the display is white. At this time, the liquid crystal molecules are in a bend-oriented state. As a result, the light from the backlight passes through a layer containing a pair of polarizing elements arranged so as to form a cross Nicol (layer 10603 containing the first polarizing element and layer 10604 containing the second polarizing element). And the predetermined video display is performed. In addition, FIG. 52 (
A liquid crystal display device having a configuration as described in A1) and (A2) can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, FIG. 52 (A)
1) The liquid crystal display device having the configuration as shown in (A2) can perform full-color display by field sequential drive without providing a color filter.

In the OCB mode as shown in FIGS. 52 (A1) and 52 (A2), the arrangement of the liquid crystal molecules can be optically compensated in the liquid crystal layer, so that the viewing angle is less dependent on the viewing angle. The ratio can be increased.

FIGS. 52 (B1) and 52 (B2) show schematic views of the liquid crystal display in the FLC mode and the AFLC mode.

Similar to FIG. 51, a first electrode 10605 and a second electrode 10606 are provided on the first substrate 10601 and the second substrate 10602, respectively. The first electrode 10605, which is an electrode on the opposite side of the backlight, that is, on the visual recognition side, is formed so as to have at least translucency. Then, on the side of the first substrate 10601, a layer 10603 containing the first polarizing element is formed.
Is laminated, and a layer 10604 containing a second polarizing element is arranged on the side of the second substrate 10602. The layer 10603 containing the first polarizing element and the layer 10604 containing the second polarizing element are arranged so as to form a cross Nicol.

In the liquid crystal display device having the configuration as shown in FIGS. 52 (B1) and 52 (B2), the first electrode 106
When a voltage is applied to 05 and the second electrode 10606 (referred to as a longitudinal electric field method), FIG. 52 (B)
As shown in 1), the display is white. At this time, the liquid crystal molecules are arranged side by side in a direction deviated from the rubbing direction. Thus, the light from the backlight passes through a layer containing a pair of polarizing elements arranged so as to form a cross Nicol (layer 10603 containing the first polarizing element and layer 10604 containing the second polarizing element). It is possible to display a predetermined image.

Then, as shown in FIG. 52 (B2), the first electrode 10605 and the second electrode 1060
When no voltage is applied during 6, black display is performed. At this time, the liquid crystal molecules are arranged side by side along the rubbing direction. Then, the light from the backlight cannot pass through the substrate and is displayed in black.

The liquid crystal display device having the configuration shown in FIGS. 52 (B1) and 52 (B2) can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, the liquid crystal display device having the configuration shown in FIGS. 52 (B1) and 52 (B2) can perform full-color display by field sequential drive without providing a color filter.

As the liquid crystal material used in the FLC mode and the AFLC mode, known ones may be used.

FIGS. 53 (A1) and 53 (A2) show a schematic diagram of an IPS mode liquid crystal display device. The IPS mode is a mode in which the liquid crystal molecules are always rotated in a plane with respect to the substrate, and the electrodes adopt a transverse electric field method provided only on one substrate side.

The IPS mode is characterized in that the liquid crystal is controlled by a pair of electrodes provided on one of the substrates. Therefore, paired electrodes 10801 and 10802 are provided on the second substrate 10602. The paired electrodes 10801 and 10802 may have light-shielding properties, respectively. A layer 10603 containing a first polarizing element is laminated on the first substrate 10601 side, and a layer 10604 containing a second polarizing element is arranged on the second substrate 10602 side. The layer 10603 containing the first polarizing element and the layer 10604 containing the second polarizing element may be arranged so as to form a cross Nicol.

In a liquid crystal display device having a configuration as shown in FIGS. 53 (A1) and 53 (A2), a pair of electrodes 10
When a voltage is applied to 801 and 10802, as shown in FIG. 53 (A1), the liquid crystal molecules are oriented along the electric lines of force deviated from the rubbing direction, and a white display is performed. Then, the light from the backlight passes through a layer containing a pair of substituents arranged so as to form a cross Nicol (a layer 10603 containing the first polarizing element and a layer 10604 containing the second polarizing element). It is possible to display a predetermined image.

The liquid crystal display device having the configuration shown in FIGS. 53 (A1) and 53 (A2) can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, the liquid crystal display device having the configuration shown in FIGS. 53 (A1) and 53 (A2) can perform full-color display by field sequential drive without providing a color filter.

Then, as shown in FIG. 53 (A2), when no voltage is applied between the pair of electrodes 10604 and 10602, the display is black, that is, the state is turned off. At this time, the liquid crystal molecules are arranged side by side along the rubbing direction. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

FIG. 55 shows an example of a pair of electrodes 10801 and 10802 that can be used in the IPS mode. In FIGS. 55 (A) to 55 (D), the electrode 10801 is the electrode 10801a and the electrode 10.
Corresponds to 801b, electrode 10801c and electrode 10801d. Also, the electrode 10802
Corresponds to the electrode 10802a, the electrode 10802b, the electrode 10802c and the electrode 10802d. In FIG. 55 (A), the electrode 10801a and the electrode 10802a have a wavy shape having undulations, and in FIG. 55 (B), the electrode 10801b and the electrode 10802b have a shape having concentric openings, and FIG. 55 (C) shows. Then, the electrode 10801c and the electrode 10802c
Is a comb field shape and has a partially overlapping shape. In FIG. 55 (D), the electrodes 10801d and 10802d have a comb field shape and are shaped so that the electrodes mesh with each other.

In addition to the IPS mode, the FFS mode can also be used. In the IPS mode, the paired electrodes are formed on the same insulating film, whereas in the FFS mode, FIGS. 53 (B1) and (B).
As shown in 2), the paired electrodes 10803 and 10804 may be formed on different layers of insulating films.

In a liquid crystal display device having a configuration as shown in FIGS. 53 (B1) and 53 (B2), when a voltage is applied to the paired electrodes 10803 and 10804, white display is performed as shown in FIG. 53 (B1). Turns on. Then, the light from the backlight passes through a layer containing a pair of substituents arranged so as to form a cross Nicol (a layer 10603 containing the first polarizing element and a layer 10604 containing the second polarizing element). It is possible to display a predetermined image.

The liquid crystal display device having the configurations shown in FIGS. 53 (B1) and 53 (B2) can perform full-color display by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Of course, the liquid crystal display device having the configurations shown in FIGS. 53 (B1) and 53 (B2) can perform full-color display by field sequential drive without providing a color filter.

Then, as shown in FIG. 53 (B2), when no voltage is applied between the paired electrodes 10803 and 10804, a black display, that is, an off state is set. At this time, the liquid crystal molecules are arranged side by side and are in a state of being rotated in a plane. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

FIG. 56 shows an example of a pair of electrodes 10803 and 10804 that can be used in the FFS mode. In FIGS. 56A to 56D, the electrode 10803 has an electrode 10803a and an electrode 10
Corresponds to 803b, electrode 10803c and electrode 10803d. Also, the electrode 10804
Corresponds to the electrode 10804a, the electrode 10804b, the electrode 10804c and the electrode 10804d. In FIG. 56 (A), the electrode 10803a has a bent dogleg shape, and the electrode 1080.
4a does not have to be patterned in the pixel region. In FIG. 56B, the electrode 108
03b has a concentric shape, and the electrode 10804b does not have to be patterned in the pixel region. In FIG. 56 (C), the electrode 10803c has a comb-like shape so that the electrodes mesh with each other, and the electrode 10804c does not have to be patterned in the pixel region.
In FIG. 56D, the electrode 10803d has a comb-like shape, and the electrode 10804d does not have to be patterned in the pixel region.

The electrodes 10803 (10803a, 10803b, 10803c, 10803d) and the electrodes 10804 (10804a, 10804b, 10804c, 10804d) are
It may have translucency. By having translucency, it is possible to obtain a transmissive display device having a large aperture ratio.

The electrodes 10803 (10803a, 10803b, 10803c, 10803d) and the electrodes 10804 (10804a, 10804b, 10804c, 10804d) are
It may have light-shielding property or reflective property. By having a light-shielding property or a reflective property, it is possible to obtain a reflective display device that does not require a backlight and consumes less power.

The electrodes 10803 (10803a, 10803b, 10803c, 10803d) and the electrodes 10804 (10804a, 10804b, 10804c, 10804d) are
It may have both a light-transmitting region and a light-shielding or reflective region. By having both areas, a transmissive display with high display quality is performed in a dark environment such as indoors, and a reflective display with low power consumption is performed in a bright environment such as outdoors without a backlight. , A translucent display device can be obtained.

As the liquid crystal material used in the IPS mode and the FFS mode, known ones may be used.

As a liquid crystal mode applicable to the liquid crystal display device of the present embodiment, in addition to the liquid crystal mode described above, ASM (Axially Symmetrically named Micro-
cell) mode, PDLC (Polymer Dispersed Liquid C)
There is a rystal) mode and so on.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 9)
In this embodiment, a display panel configuration and a peripheral configuration of the display device will be described.
In particular, a display panel (also referred to as a liquid crystal panel) configuration and a peripheral configuration of the liquid crystal display device will be described.

First, a simple configuration of the liquid crystal panel will be described with reference to FIG. 57 (A). In addition, FIG.
7 (A) is a top view of the liquid crystal panel.

In the liquid crystal panel shown in FIG. 57A, a pixel portion 20101, a scanning line side input terminal 20103, and a signal line side input terminal 20104 are formed on the substrate 20100. A scanning line extends in the row direction from the scanning line side input terminal 20103 and is formed on the substrate 20100, and a signal line extends in the column direction from the signal line input terminal 20104 and is formed on the substrate 20100. Further, in the pixel unit 20101, the pixel 20102 is arranged on the matrix at the intersection of the scanning line and the signal line. Further, a switching element and a pixel electrode layer are arranged in the pixel 20102.

As shown in the liquid crystal panel of FIG. 57 (A), the scanning line side input terminal 20103 is the substrate 2010.
It is formed on both sides in the row direction of 0. The signal line input terminal 20103 is formed in one of the row directions of the substrate 20100. Further, the scanning lines extending from one scanning line side input terminal 20103 and the scanning lines extending from the other scanning line side input terminal 20103 are alternately formed.

Further, in each of the pixels 20102 of the pixel unit 20101, the first terminal of the switching element is connected to the signal line, and the second terminal is connected to the pixel electrode layer, whereby the individual pixels 201 are connected.
02 can be controlled independently by a signal input from the outside. The on / off of the switching element is controlled by the signal supplied to the scanning line.

By arranging the scan line side input terminals 20103 in both of the row directions of the substrate 20100, the pixels 20102 can be arranged at a high density. In addition, the signal line side input terminal 2010
By arranging the 3 in one of the row directions of the substrate 20100, it is possible to narrow the frame of the liquid crystal panel or expand the area of the pixel 20101.

As described above, the substrate 20100 includes a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a stainless steel substrate, and a stainless steel still foil. A substrate or the like can be used.

As already described, a transistor, a diode (for example, a PN diode, a PIN diode, a shotkey diode, a diode-connected transistor, etc.), a thyristor, a logic circuit combining them, or the like can be used as the switching element. ..

When a TFT is used as the switching element, the gate of the TFT is connected to the scanning line, the first terminal is connected to the signal line, and the second terminal is connected to the pixel electrode layer, so that each pixel 20102 is connected. Can be controlled independently by a signal input from the outside.

The scanning line side input terminal 20103 may be arranged in one of the row directions of the substrate 20100. By arranging the scanning line side input terminal 20103 in one of the row directions of the substrate 20100, it is possible to narrow the frame of the liquid crystal panel and expand the area of the pixel 20101.

The scanning line extending from one scanning line side input terminal 20103 and the scanning line extending from the other scanning line side input terminal 20103 may be common.

The signal line side input terminals 20103 may be arranged in both of the row directions of the substrate 20100. By arranging the signal line side input terminals 20103 in both of the column directions of the substrate 20100, the pixels 20102 can be arranged at a high density.

A capacitive element may be further formed in the pixel 20102. When the capacitive element is provided in the pixel 20102, the capacitive line may be formed on the substrate 20100. When forming a capacitance line on the substrate 20100, the first electrode of the capacitance element is connected to the capacitance line, and the second terminal is connected to the pixel electrode layer. When the capacitance line is not formed on the substrate 20100, the first electrode of the capacitance element is connected to a scanning line different from the pixel 20102 in which the capacitance element is arranged, and the second terminal is connected to the pixel electrode layer. To do.

Here, the liquid crystal panel shown in FIG. 57 (A) shows a configuration in which the signals supplied to the scanning line and the signal line are controlled by an external drive circuit, but as shown in FIG. 58 (A), COG (
The driver IC 20101 may be mounted on the substrate 20100 by the Chip on Glass) method. Further, as another configuration, as shown in FIG. 58 (B), TAB (Tape)
The driver IC20201 is FPC (FPC) by the Automated Bonding method.
It may be implemented on a Flexible Printed Circuit) 20200.
Further, in FIG. 58, the driver IC20201 is connected to the FPC20200.

The driver IC20201 may be formed on a single crystal semiconductor substrate or may have a circuit formed by a TFT on a glass substrate.

In the liquid crystal panel shown in FIG. 57 (A), the scanning line drive circuit 20105 may be formed on the substrate 20100 as shown in FIG. 57 (B). Further, as shown in FIG. 57 (C), the scanning line driving circuit 20105 and the signal line driving circuit 20106 may be formed on the substrate 20100.

The scanning line driving circuit 20105 and the scanning line driving circuit 20106 are composed of a large number of N-channel type transistors and a large number of P-channel type transistors. However, it may be composed of only a large number of N-channel type transistors, or may be composed of only a large number of P-channel type transistors.

Subsequently, the details of the pixel 20102 will be described with reference to the circuit diagrams of FIGS. 59 and 60.

The pixel 20102 in FIG. 59 (A) has a transistor 20131, a liquid crystal element 20302, and a capacitive element 20303. The gate of the transistor 20301 is connected to the wiring 20305, and the first terminal is connected to the wiring 20304. The first electrode of the liquid crystal element 20302 is connected to the counter electrode 20307, and the second electrode is connected to the second terminal of the transistor 20131. The first electrode of the capacitive element 20303 is connected to the wiring 20306, and the second electrode is connected to the second terminal of the transistor 20301.

The wiring 20304 is a signal line, the wiring 20305 is a scanning line, and the wiring 20306.
Is a capacitance line. Further, the transistor 20131 is a switching transistor and is a switching transistor.
It may be a P-channel type transistor or an N-channel type transistor. Further, the liquid crystal element 20
307 is an operation mode such as TN (Twisted Nematic) mode and IPS (IPS).
In-Plane-Switching mode, FFS (Fringe Field)
Switching) mode, MVA (Multi-domain Vertical)
Alginment) mode, PVA (Patterned Vertical Ali)
gnment), ASM (Axially Symmetrically named Mi)
Cro-cell) mode, OCB (Optical Contracted Bir)
Efringence) mode, FLC (Ferroelectric Liquid)
Crystal) mode, AFLC (AntiFerolectric Liquii)
d Crystal) and the like can be used.

A video signal and a scanning signal are input to the wiring 20304 and the wiring 20305, respectively. The video signal is an analog voltage signal and the scanning signal is an H-level or L-level digital voltage signal. However, the video signal may be a current signal or a digital signal. Further, the H level and the L level of the scanning signal may be any potential as long as they can control the on / off of the transistor 20131.

A constant power supply voltage is supplied to the capacitance line 20306. However, a pulsed signal may be supplied.

The operation of the pixel 20102 in FIG. 59 (A) will be described. First, when the wiring 20305 reaches the H level, the transistor 20301 is turned on, and the video signal is turned on from the wiring 20304 via the transistor 20301, and the second electrode and the capacitive element 2030 of the liquid crystal element 20302 are turned on.
It is supplied to the second electrode of 3. Then, the capacitive element 20303 holds the potential difference between the potential of the wiring 203076 and the potential of the video signal.

Next, when the wiring 20305 reaches the L level, the transistor 20301 is turned off and the wiring 20 is turned off.
The 304 and the second electrode of the liquid crystal element 20302 and the second electrode of the capacitive element 20303 are electrically cut off. However, since the capacitive element 20303 holds the potential difference between the potential of the wiring 203076 and the potential of the video signal, the potential of the second electrode of the capacitive element 20302 can maintain the same potential as the video signal.

In this way, the pixel 20102 in FIG. 59A can maintain the potential of the second electrode of the liquid crystal element 20302 at the same potential as the video signal, and can maintain the liquid crystal element 20302 at the transmittance corresponding to the video signal.

Although not shown, the capacitive element 20303 is not always necessary as long as the liquid crystal element 20302 has a capacitive component capable of holding a video signal.

As shown in FIG. 59B, the first electrode of the liquid crystal element 20302 may be connected to the wiring 20306. For example, when the liquid crystal mode of the liquid crystal element 20132 is the FFS mode, the liquid crystal element 20302 uses the configuration shown in FIG. 59 (B).

As shown in FIG. 60, the first electrode of the capacitive element 20303 may be connected to the wiring 20305a in the previous row. When the wiring 20305a is the scanning line of the nth line (n is a positive integer), the wiring 20305b is the scanning line of the n + 1th line. Similarly, the transistor 20131a
, When the pixel 20102a and the capacitive element 20303a are the elements on the nth row, the transistor 2
0301b, pixel 20102b, and capacitive element 20303b are elements on the n + 1th line. In this way, by connecting the first electrode of the capacitive element 20303b to the wiring 20305a in the front row, the wiring can be reduced. Therefore, the pixels 20102a and 20102 in FIG. 60
b can increase the aperture ratio.

Next, a more detailed configuration of the liquid crystal panel than the configuration of the liquid crystal panel described with reference to FIGS. 57 and 58 will be described with reference to FIG. 61. Specifically, the TFT substrate, the facing substrate, and
A configuration of a liquid crystal panel having a liquid crystal layer sandwiched between the facing substrate and the TFT substrate will be described. Further, FIG. 61A is a top view of the liquid crystal panel. FIG. 61 (B) is shown in FIG. 61 (B).
It is sectional drawing in line CD of A). Note that FIG. 61B is a cross-sectional view when a top gate type transistor is formed on the substrate 20100 when a crystalline semiconductor film (polysilicon film) is used as the semiconductor film.

In the liquid crystal panel shown in FIG. 61A, a pixel portion 20101, a scanning line driving circuit 20105a, a scanning line driving circuit 20105b, and a signal line driving circuit 20106 are formed on a substrate 20100. Pixel unit 20101, scanning line drive circuit 20105a, scanning line drive circuit 20105
b and the signal line drive circuit 20106 are sealed between the substrate 20100 and the facing substrate 20515 by the sealing material 20516. Also, by the TAB method, FPC2051
8 and the IC chip 20530 are arranged on the substrate 20100.

The cross-sectional structure in line CD of FIG. 61 (A) will be described with reference to FIG. 61 (B).
On the substrate 20100, the pixel unit 20101 and its peripheral drive circuit unit (scanning line circuit 20105).
a and the scanning line circuit 20105b and the signal line driving circuit 20106) are formed, but here, the driving circuit region 20525 (scanning line driving circuit 20105a and the scanning line driving circuit 20) are formed.
105b) and the pixel area 20526 (pixel unit 20101) are shown.

First, an insulating film 20501 is formed on the substrate 20100 as a base film. The insulating film 20501 is a silicon oxide film, a silicon nitride film, or a silicon oxide film (Si).
A single layer of an insulating film such as OxNy) or a laminated structure having at least two films of these films may be used.

It is better to use a silicon oxide film in the portion in contact with the semiconductor. As a result, it is possible to suppress electron traps in the base film and hysteresis of transistor characteristics. again,
It is desirable to arrange at least one film containing a large amount of nitrogen as the base film. Thereby, impurities from the glass can be reduced.

Next, the semiconductor film 20502 is formed on the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like.

Next, the insulating film 2 is used as a gate insulating film on the insulating film 20501 and the semiconductor film 20502.
0503 is formed.

As the insulating film 20503, a single-layer or laminated structure such as a thermal oxide film, a silicon oxide film, a silicon nitride film, or a silicon oxide film can be used. Semiconductor film 20503
The insulating film 20503 in contact with the insulating film 20503 is preferably a silicon oxide film. This is because the silicon oxide film reduces the trap level at the interface with the semiconductor film 20503. When the gate electrode is formed of Mo, a silicon nitride film is preferable as the gate insulating film in contact with the gate electrode. This is because the silicon nitride film does not oxidize Mo. Here, the insulating film 20503
As a result, a silicon oxide film having a thickness of 115 nm by the plasma CVD method (composition ratio Si = 3).
2%, O = 59%, N = 7%, H = 2%).

Next, a conductive film 20504 is formed on the insulating film 20503 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like.

The conductive film 20504 includes Ti, Mo, Ta, Cr, W, Al, Nd, Cu, and A.
There are g, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge and the like, alloys of these elements and the like. Alternatively, it may be composed of a laminate of these elements or alloys of these elements. Here, the gate electrode is formed by Mo. Mo is suitable because it is easy to etch and is resistant to heat.

In the semiconductor film 20502, an impurity element is doped in the semiconductor film 20502 with the conductive film 20504 or a resist as a mask, and a channel forming region and an impurity region serving as a source region and a drain region are formed.

The impurity region may be formed into a high concentration region and a low concentration region by controlling the impurity concentration.

The conductive film 20504 of the transistor 20521 has a dual gate structure.
Transistor 20531 has a dual gate structure so that transistor 20531 can be used.
Off current can be reduced. The dual gate structure is a structure having two gate electrodes. However, a plurality of gate electrodes may be provided on the channel region of the transistor.

Next, the insulating film 20505 is used as an interlayer film on the insulating film 20503 and the conductive film 20504.
Is formed.

As the insulating film 20505, an organic material, an inorganic material, or a laminated structure thereof can be used. For example, silicon oxide, silicon nitride, silicon oxide, silicon oxide, aluminum nitride, aluminum oxide, aluminum oxide or aluminum oxide having a nitrogen content higher than the oxygen content, diamond dry carbon (DLC), polysilazane, nitrogen content. It can be formed of a material selected from materials including carbon (CN), PSG (phosphorus glass), BPSG (phosphorus glass), alumina and other inorganic insulating materials. Further, an organic insulating material may be used, and the organic material may be either photosensitive or non-photosensitive, and polyimide, acrylic, polyamide, polyimideamide, resist or benzocyclobutene, siloxane resin and the like can be used. .. The siloxane resin is Si-
Corresponds to a resin containing an O—Si bond. The skeleton structure of siloxane is composed of the bonds between silicon (Si) and oxygen (O). As the substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as the substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as the substituent.

Contact holes are selectively formed in the insulating film 20503 and the insulating film 20505. For example, the contact hole is formed on the upper surface of the impurity region of each transistor.

Next, a conductive film 20506 is formed on the insulating film 20505 as a drain electrode, a source electrode, and wiring by a photolithography method, an inkjet method, a printing method, or the like.

The conductive film 20506 is made of Ti, Mo, Ta, Cr, W, Al, N as a material.
There are d, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge and the like, alloys of these elements and the like. Alternatively, a laminated structure of these elements or alloys of these elements can be used.

In the portion where the contact holes of the insulating film 20503 and the insulating film 20504 are formed, the conductive film 20506 and the impurity region of the semiconductor film 20502 of the transistor are connected.

Next, an insulating film 20507 is formed as a flattening film on the insulating film 20505 and the conductive film 20506 formed on the insulating film 20505.

Since it is desirable that the insulating film 20507 has good flatness and covering property, it is often formed by using an organic material. The insulating film 20507 may have a multi-layer structure, or an organic material may be formed on an inorganic material (silicon oxide, silicon nitride, silicon oxide).

A contact hole is selectively formed in the insulating film 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521.

Next, a conductive film 20508 is formed on the insulating film 20507 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like.

As the conductive film 20508, a transparent electrode that transmits light and a reflective electrode that reflects light can be used.

In the case of transparent electrodes, for example, indium tin oxide, which is a mixture of indium oxide and tin oxide (
ITO) film, indium tin oxide (ITSO) film made by mixing indium tin oxide (ITO) with silicon oxide, indium zinc oxide (IZO) made by mixing indium oxide with zinc oxide.
) Membrane, zinc oxide film, tin oxide film and the like can be used. IZO is I
It is a transparent conductive material formed by sputtering using a target in which 2 to 20 wt% zinc oxide (ZnO) is mixed with TO, but is not limited thereto.

In the case of a reflective electrode, for example, Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, A
u, Pt, Nb, Si, Zn, Fe, Ba, Ge and the like, alloys thereof and the like can be used. Further, a two-layer structure in which Ti, Mo, Ta, Cr, W and Al are laminated, and Al is Ti,
It may be a three-layer laminated structure sandwiched between metals such as Mo, Ta, Cr, and W.

Next, on the insulating film 20507 and the conductive film 20508 formed on the insulating film 20507,
An insulating film 20509 is formed as the alignment film.

Next, the sealing material 20516 is formed on the peripheral portion of the pixel portion 20101 or the peripheral portion of the peripheral portion of the pixel portion 20101 and the peripheral portion of the peripheral drive circuit portion thereof by an inkjet method or the like.

Next, the substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, etc. are formed and the substrate 20100 are bonded to each other via the spacer 20531, and the liquid crystal layer 20510 is arranged in the gap. Has been done.

The substrate 2015 may function as a facing substrate. Further, the insulating film 20514 is provided with the insulating film 20514.
It may function as a black matrix (light-shielding film). Further, the insulating film 20513 may function as a color filter. Further, the spacer 20531 may be provided by spraying particles of several μm, or may be formed by forming a resin film on the entire surface of the substrate and then etching the resin film. Further, the conductive film 20512 may function as a counter electrode. As the conductive film 20512, the same one as that of the conductive film 20508 can be used.
Further, the insulating film 20511 may function as an alignment film.

An insulating film 20532 may be formed as a flattening film between the insulating film 20513 and the insulating film 20514 and the conductive film 20512. However, in FIG. 61, the insulating film 20532 is not shown.

A known liquid crystal can be freely used as the liquid crystal layer 20510. For example, a ferroelectric liquid crystal may be used as the liquid crystal 20510, or an antiferroelectric liquid crystal may be used.
The liquid crystal drive system is TN (Twisted Nematic) mode, IPS (I).
n-Plane-Switching) mode, FFS (Fringe Field S)
(witching) mode, MVA (Multi-domain Vertical A)
lignment) mode, PVA (Patterned Vertical Alig)
nment), ASM (Axially Symmetrically aligned Mic)
ro-cell) mode, OCB (Optical Compensated Bire)
fringence) mode, FLC (Ferroelectric Liquid C)
rystal) mode, AFLC (AntiFerolectric Liquid)
Crystal) and the like can be freely used.

Next, the conductive film 205 electrically connected to the pixel unit 20101 and its peripheral drive circuit unit.
The FPC 20200 is arranged on the 31 via the anisotropic conductor layer 20517. Further, an IC chip is arranged on the FPC20200 via the anisotropic conductor layer 20517. That is, the FPC 20200, the conductive film 20531, and the IC chip 20530 are electrically connected.

The conductive film 20531 has a function of transmitting signals and potentials input from the FPC 20200 to pixels and peripheral circuits. As the conductive film 20531, the same one as the conductive film 20506 may be used, the same one as the conductive film 20504 may be used, or the same one as the impurity region of the semiconductor film 20502 may be used. , A combination of at least two or more layers may be used.

The IC chip 20530 can effectively utilize the board area by forming a functional circuit (memory or buffer).

The liquid crystal panels of FIGS. 61A and 61B have a scanning line drive circuit 20105a and a scanning line drive circuit 2
The configuration when 0105b and the signal line drive circuit 20106 are formed on the substrate 20100 has been described. However, as shown in the liquid crystal panel of FIG. 62 (A), a drive circuit corresponding to the signal line drive circuit 20106 is formed on the driver IC 20601. Then, it may be mounted on the liquid crystal panel by the COG method or the like. By forming the signal line drive circuit 20106 in the driver IC 20601, power saving can be achieved. Further, by using the driver IC 20601 as a semiconductor chip such as a silicon wafer, the liquid crystal panel of FIG. 62 (A) can achieve higher speed and lower power consumption.

Similarly, as shown in the liquid crystal panel of FIG. 62 (B), the drive circuits corresponding to the scan line drive circuit 20105a, the scan line drive circuit 20105b, and the signal line drive circuit 20106 are provided in the driver IC 20602a, the driver IC 20602b, and the driver IC 20601, respectively. It may be formed and mounted on a liquid crystal panel by a COG method or the like. Further, by forming the drive circuits corresponding to the scan line drive circuit 20105a, the scan line drive circuit 20105b, and the signal line drive circuit 20106 in the driver IC 20602a, the driver IC 20602b, and the driver IC 20601, respectively, cost reduction can be achieved.

Although the transistor 20521 has a dual gate structure, the pixel portion 2052 in FIG. 63
As shown in 6, the transistor 20521 may have a single gate structure. however,
FIG. 63 shows only the pixel portion 20526.

Next, a cross-sectional view when a bottom gate type transistor is formed on the substrate 20100 will be described with reference to FIG. 64. However, FIG. 64 shows only the pixel region 20526.

First, an insulating film 20501 is formed on the substrate 20100 as a base film. next,
A conductive film 20504 is formed on the insulating film 20501 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like. The transistor 2052
The conductive film 20504 of No. 1 has a dual gate structure. This is because, as already mentioned, the transistor 20521 has a dual gate structure so that the transistor 2052 can be used.
The off current of 1 can be reduced. Next, an insulating film 20503 is formed as a gate insulating film on the insulating film 20501 and the conductive film 20504. Next, on the insulating film 20503,
The semiconductor film 20502 is formed by a photolithography method, an inkjet method, a printing method, or the like. The semiconductor film 20502 has a semiconductor film 20 using a resist as a mask.
Impurity elements are doped in 502, and a channel forming region and an impurity region serving as a source region and a drain region are formed. The impurity region may be formed into a high concentration region and a low concentration region by controlling the impurity concentration. Next, an insulating film 20505 is formed as an interlayer film on the insulating film 20503 and the semiconductor layer 20502. A contact hole is selectively formed in the insulating film 20505. For example, the contact hole is formed on the upper surface of the impurity region of each transistor. Next, the insulating film 2050
A conductive film 20506 is formed on the drain electrode, the source electrode, and the wiring by a photolithography method, an inkjet method, a printing method, or the like. The insulating film 205
In the portion where the contact hole of 05 is formed, the conductive film 20506 and the impurity region of the semiconductor film 20502 of the transistor are connected. Next, an insulating film 20507 is formed as a flattening film on the insulating film 20505 and the conductive film 20506. A contact hole is selectively formed in the insulating film 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive film 20508 is formed on the insulating film 20507 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20509 is formed as an alignment film on the insulating film 20507 and the conductive film 20508. Next, the insulating film 2
The liquid crystal layer 20510 is arranged in the gap between the substrate 20515 on which the 0514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed, and the substrate 20100.

In FIG. 64, the transistor 20521 has a dual gate structure. However, FIG. 6
As shown in the pixel portion 20526 of 5, the transistor 20521 may have a single gate structure.

Next, a cross-sectional view when a double-gate type transistor is formed on the substrate 20100 will be described with reference to FIG. 66. However, FIG. 66 shows only the pixel region 20526.

The double gate type transistor means a structure in which gate electrodes are arranged above and below the semiconductor film. Further, the double gate type transistor doubles the flowing current if it has the same size and the same applied voltage as the top gate type transistor and the bottom gate type transistor. That is, a double-gate transistor can carry a larger current with a smaller transistor size.

First, an insulating film 20501 is formed on the substrate 20100 as a base film. next,
A conductive film 20504a is formed on the insulating film 20501 as a first gate electrode by a photolithography method, an inkjet method, a printing method, or the like. The conductive film 205
As 04a, those having the same material and structure as the conductive film 20504 can be used. next,
The insulating film 2 is used as the first gate insulating film on the insulating film 20501 and the conductive film 20504a.
0503a is formed. As the insulating film 20503a, the same material and structure as the insulating film 20503 can be used. Next, the semiconductor film 20502 is formed on the insulating film 20503a by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20503b is formed on the insulating film 20503a and the semiconductor film 20502 as a second gate insulating film. The conductive film 20503b is the conductive film 20.
Materials and structures similar to those of 503 can be used. Next, a conductive film 20504b is formed on the insulating film 20504b as a second gate electrode by a photolithography method, an inkjet method, a printing method, or the like. The conductive film 20504b is the conductive film 2
Materials and structures similar to 0504 can be used. The semiconductor film 20502
The semiconductor film 20502 is doped with an impurity element using the conductive film 20504b or a resist as a mask, and a channel forming region and an impurity region serving as a source region and a drain region are formed. The impurity region may be formed into a high concentration region and a low concentration region by controlling the impurity concentration. The semiconductor film 20502 has an insulating film 20503.
Before the b and the conductive film 20504b are formed, the semiconductor film 2050 using the resist as a mask is used.
Impurity elements may be doped into 2 to form a channel forming region and an impurity region serving as a source region and a drain region. Next, on the insulating film 20503b and the conductive film 20
An insulating film 20505 is formed on the 504b as an interlayer film. The insulating film 205
Contact holes are selectively formed in the 03b and the insulating film 20505. For example, the contact hole is formed on the upper surface of the impurity region of each transistor. Next, a conductive film 20506 is formed on the insulating film 20505 as a drain electrode, a source electrode, and wiring by a photolithography method, an inkjet method, a printing method, or the like. note that,
In the portion where the contact holes of the insulating film 20503 and the insulating film 20504 are formed,
The conductive film 20506 and the impurity region of the semiconductor film 20502 of the transistor are connected. Next, as a flattening film, the insulating film 205 is placed on the insulating film 20505 and the conductive film 20506.
07 is formed. A contact hole is selectively formed in the insulating film 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive film 20508 is formed on the insulating film 20507 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20509 is formed as an alignment film on the insulating film 20507 and the conductive film 20508. Next, the liquid crystal layer 20510 is arranged in the gap between the substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed, and the substrate 20100.

In addition, in FIG. 61 and FIGS. 63 to 66, the cross-sectional view in the case where the insulating film 20507 is formed as a flat film on the insulating film 20505 and the conductive film 20506 formed on the insulating film 20505 has been described. .. However, the insulating film 20507 is not always necessary, as shown in FIG. 67.

The cross-sectional view shown in FIG. 67 shows the case of a top gate type transistor, but the same applies to the case of a bottom gate type transistor and a double gate type transistor.

Next, on the substrate 20100, a non-crystalline semiconductor film (amorphous silicon film) is used as a semiconductor film.
A cross-sectional view in the case of forming a transistor using the above will be described with reference to FIG. 68. The cross-sectional view shown in FIG. 68 is a cross-sectional view of a transistor having an inverted stagger type channel etch structure.

First, an insulating film 20501 is formed on the substrate 20100 as a base film. next,
A conductive film 20504 is formed on the insulating film 20501 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20503 is formed as a gate insulating film on the insulating film 20501 and the conductive film 20504. Next, the semiconductor film 20502 is formed on the insulating film 20503 by a photolithography method, an inkjet method, a printing method, or the like. The semiconductor film 20502 has a first semiconductor film and a second semiconductor film, and a second semiconductor film is formed on the first semiconductor film. Further, the first semiconductor film and the second semiconductor film may be continuously formed and simultaneously patterned by a photolithography method. Further, the second semiconductor film contains an impurity element. Next, the conductive film 20506 is formed on the insulating film 20503 and the semiconductor film 20502 by a photolithography method, an inkjet method, a printing method, or the like. note that,
The semiconductor film 20502 is etched with the conductive film 20506 as a mask to form a channel forming region and an impurity region serving as a source region and a drain region. That is, in the channel region, the second semiconductor film containing the impurity element is removed. However, the semiconductor film 20502 may be etched by using a resist for etching the conductive film 20506 as a mask. Next, the insulating film 20507 is formed as a flattening film on the insulating film 20503, the semiconductor film 20502, and the conductive film 20506. A contact hole is selectively formed in the insulating film 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive film 20508 is formed on the insulating film 20507 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20509 is formed as an alignment film on the insulating film 20507 and the conductive film 20508. Next, the insulating film 2
The liquid crystal layer 20510 is arranged in the gap between the substrate 20515 on which the 0514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed, and the substrate 20100.

Although the transistor having a channel etch structure has been described, the insulating film 21301 may be provided on the semiconductor film 20502 as shown in FIG. 69. The insulating film 21301 is formed between the first semiconductor film and the second semiconductor film. Further, the semiconductor film 20502 is a conductive film 20.
When forming the 506, it is etched at the same time.

The transistor 20521 in FIG. 68 is referred to as a channel etch structure, and the transistor 20521 in FIG. 69 is referred to as a channel protection structure.

Next, a cross-sectional view of a case where a top gate type transistor using an amorphous semiconductor film as a semiconductor film is formed on the substrate 20100 will be described with reference to FIG. 70.

First, an insulating film 20501 is formed on the substrate 20100 as a base film. next,
A conductive film 20506 is formed on the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like. Next, the semiconductor film 20502a is formed on the conductive film 20506 by a photolithography method, an inkjet method, a printing method, or the like. As the semiconductor film 20502a, those having the same material and structure as the semiconductor film 20502 can be used. Further, the semiconductor film 20502a contains an impurity element. Next, the semiconductor film 20502b is formed on the insulating film 20501 and the semiconductor film 20502a by a photolithography method, an inkjet method, a printing method, or the like. The semiconductor film 2
As 0502b, those having the same material and structure as the semiconductor film 20502 can be used.
Next, an insulating film 20503 is formed as a gate insulating film on the insulating film 20501, the semiconductor film 20502b, and the conductive film 20506. Next, a conductive film 20504 is formed on the insulating film 20503 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, the insulating film 20507 is formed as a flattening film on the insulating film 20503 and the conductive film 20504 formed on the insulating film 20503. A contact hole is selectively formed in the insulating film 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive film 20508 is formed on the insulating film 20507 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20509 is formed as an alignment film on the insulating film 20507 and the conductive film 20508. Next, the liquid crystal layer 20510 is arranged in the gap between the substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed, and the substrate 20100.

In addition, in FIGS. 69 and 70, the cross-sectional view in the case where the insulating film 20507 is formed as a flat film on the insulating film 20505 and the conductive film 20506 formed on the insulating film 20505 has been described. However, the insulating film 20507 is not always necessary, as shown in FIG. 71.

The cross-sectional view shown in FIG. 71 shows the case of a transistor having an inverted stagger type channel etch structure, but the same applies to the case of a transistor having an inverted stagger type channel protection structure. Further, in FIG. 71, the case of an inverted stagger type transistor is shown.
It may be a top gate type transistor. A cross-sectional view of a top gate transistor in the case of a transistor is shown in FIGS. 72 and 73.

In the case of the cross-sectional view shown in FIG. 72, the conductive film 2 is used as a pixel electrode on the insulating film 20501 and the conductive film 20506 by a photolithography method, an inkjet method, a printing method, or the like.
0508 is formed. Further, the conductive film 20508 is formed from the formation of the conductive film 20506 to the formation of the insulating film 20503.

In the case of the cross-sectional view shown in FIG. 73, the conductive film 20508 is formed on the insulating film 20501 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Further, the conductive film 20508 is formed after the insulating film 20501 is formed.

Next, a cross-sectional view of the transflective liquid crystal panel will be described with reference to FIG. 74.

The cross-sectional view of FIG. 74 is a cross-sectional view of the liquid crystal panel when the transistor uses a polycrystalline semiconductor as the semiconductor film. However, the transistor may be a bottom gate type or a double gate type. Further, the gate electrode of the transistor may have a single gate structure or may be used.
A dual gate structure may be used.

Note that FIG. 74 is the same as in FIG. 63 until the conductive film 20506 is formed. Therefore, the process and structure after the conductive film 20506 is formed will be described.

First, as a film for reducing the thickness (so-called cell gap) of the liquid crystal layer 20510 on the insulating film 20505 and the conductive film 20506 formed on the insulating film 20505, a photolithography method, an inkjet method, a printing method, etc. Therefore, the insulating film 21801 is formed. Since it is desirable that the insulating film 21801 has good flatness and covering property, it is often formed by using an organic material. An organic material may be formed on the inorganic material (silicon oxide, silicon nitride, silicon oxide) to form a multi-layer structure. A contact hole is selectively formed in the insulating film 21801. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, the conductive film 20508a is formed on the insulating film 20505 and the insulating film 20507 as the first pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. As the conductive film 20508a, a transparent electrode that transmits the same light as the conductive film 20508 can be used. Next, the conductive film 20508b is formed on the conductive film 20508a as a second pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. As the conductive film 20508b, a reflective electrode that reflects light similar to that of the conductive film 20508 can be used. The region where the conductive film 20508b is formed is referred to as a reflection region. Further, among the regions where the conductive film 20508a is formed, the region where the conductive film 20508b is not formed on the conductive film 20508a is referred to as a transmission region. Next, an insulating film 20509 is formed as an alignment film on the insulating film 21801, the conductive film 20508a and the conductive film 20508b. Next, the liquid crystal layer 20510 is arranged in the gap between the substrate 20515 on which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed, and the substrate 20100.

In FIG. 74, the conductive film 20508b is formed after the conductive film 20508a is formed, but as shown in FIG. 75, the conductive film 20508 is formed after the conductive film 20508b is formed.
a may be formed.

In FIGS. 74 and 75, an insulating film for adjusting the liquid crystal layer 20510 (cell gap) is formed under the conductive film 20508a and under the conductive film 20508b. but,
As shown in FIG. 76, the insulating film 22001 may be formed on the substrate 20515 side. Insulating film 2
2001 is an insulating film for adjusting the liquid crystal layer 20510 (cell gap), similarly to the insulating film 21801.

Although the case where the insulating film 20507 is formed as the flattening film is described in FIG. 76, the insulating film 20507 may not be formed as shown in FIG. 77. In the case of FIG. 77, the conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

The insulating film 22001 may be formed between the conductive film 20512 and the insulating film 20511, or may be formed between the insulating film 20511 and the liquid crystal layer 20510.

Next, FIG. 78 shows a cross-sectional view of the liquid crystal panel in the case where a polycrystalline semiconductor is used as the semiconductor film of the transistor in the transflective liquid crystal panel.

The cross-sectional view of FIG. 78 is a cross-sectional view of a liquid crystal panel having a transistor using an inverted stagger type channel etch structure. However, the transistor may be a top gate type or an inverted stagger type channel protection structure.

Note that FIG. 78 is the same as in FIG. 78 until the conductive film 20506 is formed. Therefore, the process and structure after the conductive film 20506 is formed will be described.

First, the liquid crystal layer 20 is placed on the semiconductor film 20502, the insulating film 20503, and the conductive film 20506.
As a layer for reducing the thickness of 510 (so-called cell gap), an insulating film 22201 is formed by a photolithography method, an inkjet method, a printing method, or the like. Since it is desirable that the insulating film 22201 has good flatness and covering property, it is often formed by using an organic material. An organic material may be formed on the inorganic material (silicon oxide, silicon nitride, silicon nitride) to form a multi-layer structure. The insulating film 22
A contact hole is selectively formed in 201. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, the insulating film 205
A conductive film 20508a is formed on the 03 and the insulating film 22201 as the first pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, the conductive film 20508b is formed on the conductive film 20508a as a second pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. The conductive film 20508 should be noted.
The region where b is formed is called a reflection region. Further, among the regions where the conductive film 20508a is formed, the region where the conductive film 20508b is not formed on the conductive film 20508a is referred to as a transmission region. Next, on the insulating film 22201, on the conductive film 20508a and the conductive film 20508b,
An insulating film 20509 is formed as the alignment film. Next, the insulating film 20514 and the insulating film 2
A substrate 20515 on which 0513, a conductive film 20512, an insulating film 20511, etc. are formed, and
The liquid crystal layer 20510 is arranged in the gap between the substrate and the substrate 20100.

In FIG. 78, the conductive film 20508b is formed after the conductive film 20508a is formed, but as shown in FIG. 79, the conductive film 20508 is formed after the conductive film 20508b is formed.
a may be formed.

In FIGS. 78 and 79, an insulating film for adjusting the liquid crystal layer 20510 (cell gap) is formed under the conductive film 20508a and under the conductive film 20508b. but,
As shown in FIG. 80, the insulating film 22001 may be formed on the substrate 20515 side. Insulating film 2
2001 is an insulating film for adjusting the liquid crystal layer 20510 (cell gap), similarly to the insulating film 22201.

Although the case where the insulating film 20507 is formed as the flattening film is described in FIGS. 79 and 80, the insulating film 20507 may not be formed as shown in FIG. 81. In the case of FIG. 81, the conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

In addition, in FIG. 61 and FIGS. 63 to 81, a pair of electrodes (which apply a voltage to the liquid crystal layer 20510).
An example in which the conductive film 20508 and the conductive film 20512) are formed on different substrates is shown. However, the conductive film 20512 may be provided on the substrate 20100. In this way, the IPS (In-Plane-Switching) mode can be used as the driving method of the liquid crystal display. Further, depending on the liquid crystal layer 20510, the structure may be such that one or both of the two alignment films (insulating film 20509 and insulating film 20511) are not present.

In FIGS. 61 and 63 to 81, the conductive film 20508 (conductive film 20508b) is formed as the reflective pixel electrode, but it is desirable that the shape of the conductive film 20508 is uneven. This is because the reflective pixel electrode reflects external light for display. This is because the external light that has entered the reflective electrode can be efficiently utilized and diffusely reflected by the reflective electrode in order to increase the display brightness. The film under the conductive film 20508 (insulating film 20).
By making the shape of the insulating film 20507, the insulating film 21801, the insulating film 22201, etc.) uneven, the shape of the conductive film 20508 becomes uneven.

Subsequently, the liquid crystal display device having the liquid crystal panel described with reference to FIGS. 61 to 81 will be described with reference to FIG. 82.

First, the liquid crystal display device shown in FIG. 82 is provided with a backlight unit 22601, a liquid crystal panel 22607, a layer 22608 containing a first polarizing element, and a layer 22609 containing a second polarizing element.

The liquid crystal panel 22607 can be the same as that described in this embodiment. Further, although the liquid crystal panel of the present embodiment has described an active type structure in which a switching element is provided for each pixel, the liquid crystal panel of FIG. 82 may have a passive type structure.

The structure of the backlight unit 22601 will be described. Backlight unit 226
01 is a diffuser plate 22602, a light guide plate 22603, a reflector plate 22604, and a lamp reflector 2.
2605, configured to have a light source 22606. As the light source 22606, a cold cathode tube, a hot cathode tube, a light emitting diode, an inorganic EL, an organic EL, or the like is used, and the light source 2260 is used.
6 has a function of emitting light as needed. The lamp reflector 22605 is a light source 2260.
It has a function of efficiently guiding the fluorescence from 6 to the light guide plate 22603. The light guide plate 22603 has a function of totally reflecting fluorescence and guiding light over the entire surface. The diffuser plate 22602 has a function of reducing unevenness in brightness. The reflector 22604 is downward from the light guide plate 22603 (liquid crystal panel 2).
It has a function of reflecting and reusing the light leaked in the direction opposite to 2607).

By arranging a prism sheet between the diffuser plate 22602 and the layer 22609 including the second polarizing element, the liquid crystal display device of the present embodiment can improve the brightness of the screen of the liquid crystal panel.

A control circuit for adjusting the brightness of the light source 22606 is connected to the backlight unit 22601. The brightness of the light source 22606 can be adjusted by supplying a signal from the control circuit.

A layer 22609 containing a second polarizing element is provided between the liquid crystal panel 22607 and the backlight unit 22601, and the liquid crystal panel 22 in the direction opposite to the backlight unit 22601 is provided.
607 is also provided with a layer 22608 containing a first substituent.

The layer 22608 containing the first polarizing element and the layer 22609 containing the second polarizing element are arranged so as to form a cross Nicole when the liquid crystal element of the liquid crystal panel 22607 is driven in the TN mode. Further, the layer 22608 containing the first polarizing element and the layer 22609 containing the second polarizing element are arranged so as to form a cross Nicole when the liquid crystal element of the liquid crystal panel 22607 is driven in the VA mode. Further, the layer 22608 containing the first polarizing element and the layer 226 containing the second polarizing element.
09 means that when the liquid crystal element of the liquid crystal panel 22607 is driven in the IPS mode and the FFS mode, it may be arranged so as to be a cross Nicole or a parallel Nicole.

A retardation plate may be provided between the liquid crystal panel 22607 and both or one of the layer 22608 containing the first polarizing element and the layer 22609 containing the second polarizing element.

As shown in FIG. 85, the layer 22609 containing the second polarizing element and the backlight unit 2
By arranging the slit (lattice) 22610 between the 2601 and the liquid crystal display device of the present embodiment, the liquid crystal display device of the present embodiment can perform three-dimensional display.

The slit 22610 having an opening arranged on the backlight unit side transmits the light incident from the light source in a striped shape and causes the light to be incident on the display device. This slit 2261
By 0, parallax can be created in both eyes of the viewer on the viewing side, and the viewer sees only the pixel for the right eye with the right eye and only the pixel for the left eye with the left eye at the same time. Therefore, the viewer can see the three-dimensional display. That is, the light given a specific viewing angle by the slit 22610 passes through the pixels corresponding to the right-eye image and the left-eye image, respectively.
The image for the right eye and the image for the left eye are separated into different viewing angles, and three-dimensional display is performed.

If an electronic device such as a television device or a mobile phone is manufactured using the liquid crystal display device of FIG. 85, it is possible to provide a high-performance and high-quality electronic device capable of performing three-dimensional display.

Subsequently, a detailed configuration of the backlight will be described with reference to FIG. 84. The backlight is provided in the liquid crystal display device as a backlight unit having a light source, and the light source is surrounded by a reflector in order to efficiently scatter the light.

As shown in FIG. 84 (A), the backlight unit 22852 has a cold cathode tube 2 as a light source.
2801 can be used. Further, in order to efficiently reflect the light from the cold cathode tube 22801, a lamp reflector 22832 can be provided. The cold-cathode tube 22801 is often used for a large display device. This is due to the intensity of the brightness from the cold cathode fluorescent lamp. Therefore, a backlight unit having a cold cathode fluorescent lamp can be used for a display of a personal computer.

As shown in FIG. 84 (B), the backlight unit 22852 can use a light emitting diode (LED) 22802 as a light source. For example, light emitting diodes (W) 22802 that emit white light are arranged at predetermined intervals. Further, in order to efficiently reflect the light from the light emitting diode (W) 22802, a lamp reflector 22832 can be provided.

Further, as shown in FIG. 84 (C), the backlight unit 22852 has each color R as a light source.
GB light emitting diodes (LEDs) 22803, 22804, 22805 can be used. By using the light emitting diodes (LEDs) 22803, 22804, and 22805 of each color RGB, the color reproducibility can be improved as compared with only the light emitting diode (W) 22802 that emits white. Also, in order to efficiently reflect the light from the light emitting diode,
A lamp reflector 22832 can be provided.

Further, as shown in FIG. 84 (D), a light emitting diode (LED) of each color RGB is used as a light source.
) 22803, 22804, 22805 need not be the same in number and arrangement. For example, a plurality of colors having low emission intensity (for example, green) may be arranged.

Furthermore, a light emitting diode 22802 that emits white and a light emitting diode (LED) of each color RGB
) 22803, 22804, 22805 may be used in combination.

In the case of having an RGB light emitting diode, if the field sequential mode is applied, color display can be performed by sequentially lighting the RGB light emitting diodes according to the time.

When a light emitting diode is used, the brightness is high, so that it is suitable for a large display device. Further, since the color purity of each RGB color is good, the color reproducibility is excellent as compared with the cold cathode fluorescent lamp, and the arrangement area can be reduced. Therefore, when adapted to a small display device, the frame can be narrowed.

Further, the light source does not necessarily have to be arranged as the backlight unit shown in FIG. 84. For example, when a backlight having a light emitting diode is mounted on a large display device, the light emitting diode can be arranged on the back surface of the substrate. At this time, the light emitting diodes can maintain a predetermined interval, and the light emitting diodes of each color can be arranged in order. Color reproducibility can be improved by arranging the light emitting diodes.

Subsequently, an example of a layer containing a polarizing element (also referred to as a polarizing plate or a polarizing film) will be described with reference to FIG. 86.

The layer 23000 containing the polarizing element in FIG. 86 includes a protective film 23001 and a substrate film 2300.
2. It is configured to have a PVA polarizing film 23003, a substrate film 23004, an adhesive layer 23005, and a release film 23006.

The PVA polarizing film 23003 has a function of producing light (linearly polarized light) only in a certain vibration direction. Specifically, the PVA polarizing film 23003 contains molecules (polarizers) whose electron densities differ greatly between the vertical and horizontal directions. The PVA polarizing film 23003 can produce linear polarization by aligning the directions of molecules in which the electron densities differ greatly in the vertical and horizontal directions.

As an example, the PVA polarizing film 23003 is a polyvinyl alcohol (Poly V).
By doping a polymer film of inyl Alcohol) with an iodine compound and pulling the PVA film in a certain direction, a film in which iodine molecules are arranged in a certain direction can be obtained. Then, the light parallel to the major axis of the iodine molecule is absorbed by the iodine molecule. Further, for high durability use and high heat resistance use, a dichroic dye may be used instead of iodine. It is desirable that the dye be used in a liquid crystal display device such as an in-vehicle LCD or a projector LCD, which is required to have durability and heat resistance.

The PVA polarizing film 23003 is a film whose base material is both sides (substrate film 23002).
And by sandwiching it between the substrate film 3604), the reliability can be increased. Further, the PVA polarizing film 23003 may be sandwiched between highly transparent and highly durable triacetylrose (TAC) films. The substrate film and the TAC film function as a protective layer for the polarizing element of the PVA polarizing film 23003.

On one of the substrate films (substrate film 23004), an adhesive layer 23005 for attaching to the glass substrate of the liquid crystal panel is attached. The pressure-sensitive adhesive layer 23005 is formed by applying the pressure-sensitive adhesive to the substrate film (substrate film 23004) on one side. Further, the pressure-sensitive adhesive layer 23005 is provided with a release film 23005 (separate film).

The other substrate film (substrate film 23002) is provided with a protective film.

A hard-coated scattering layer (anti-glare layer) may be provided on the surface of the polarizing film 23000. Since the hard-coated scattering layer has fine irregularities formed on its surface by the AG treatment and has an antiglare function of scattering external light, it is possible to prevent reflection of external light and surface reflection on the liquid crystal panel.

Further, a plurality of optical thin film layers having different refractive indexes may be multilayered (also referred to as anti-reflection treatment or AR treatment) on the surface of the polarizing film 23000. The optical thin film layer having a plurality of layers having different refractive indexes can reduce the reflectance of the surface due to the interference effect of light.

Subsequently, the operation of each circuit included in the liquid crystal display device will be described with reference to FIG. 83.

FIG. 83 shows a system block diagram of the pixel unit 22705 and the drive circuit unit 22708 of the display device.

The pixel unit 22705 has a plurality of pixels, and the signal line 22712 and the scanning line 22 are each pixel.
A switching element is provided in the intersection region with the 710. The application of a voltage for controlling the inclination of the liquid crystal molecule can be controlled by the switching element. A structure in which a switching element is provided in each intersecting region in this way is called an active type. The pixel portion of the display device of the present embodiment is not limited to such an active type, and may have a passive type configuration. Since the passive type does not have a switching element in each pixel, the process is simple.

The drive circuit unit 22708 includes a control circuit 22702, a signal line drive circuit 22703, and a scanning line drive circuit 22704. The control circuit 22702 to which the video signal 22701 is input has a function of performing gradation control according to the display content of the pixel unit 22705. Therefore, the control circuit 2
The 2702 uses the generated signal as a signal line drive circuit 22703 and a scan line drive circuit 22704.
Enter in. Then, when the switching element is selected via the scanning line 22710 based on the scanning line drive circuit 22704, a voltage is applied to the pixel electrodes in the selected intersection region. The value of this voltage is determined based on the signal input from the signal line drive circuit 22703 via the signal line.

Further, the control circuit 22702 generates a signal for controlling the electric power supplied to the lighting means 22706, and the signal is input to the power supply 22707 of the lighting means 22706. As the lighting means, the backlight unit shown in the above embodiment can be used. In addition to the backlight, there is also a front light as the lighting means. The front light is a plate-shaped light unit attached to the front side of the pixel portion and composed of a light emitting body and a light guide body that illuminate the whole. With such a lighting means, it is possible to evenly illuminate the pixel portion with low power consumption.

As shown in FIG. 83 (B), the scan line drive circuit 22704 has a circuit that functions as a shift register 22741, a level shifter 22742, and a buffer 22743. Signals such as a gate start pulse (GSP) and a gate clock signal (GCK) are input to the shift register 22741. The scanning line drive circuit of the display device of the present embodiment is not limited to the configuration shown in FIG. 83 (B).

Further, as shown in FIG. 83 (C), the signal line drive circuit 22703 has a shift register 22731.
, A first latch 22732, a second latch 22733, a level shifter 22734, and a circuit that functions as a buffer 22735. The circuit that functions as the buffer 22735 is a circuit that has a function of amplifying a weak signal, and has an operational amplifier or the like. A signal such as a start pulse (SSP) is input to the level shifter 22734, and data (DATA) such as a video signal is input to the first latch 22732. The second latch 22733 has a latch (L).
AT) The signal can be temporarily held and input to the pixel unit 22705 all at once. This is called line sequential drive. Therefore, if it is a pixel that performs point-sequential drive instead of line-sequential drive, the second
Latch can be eliminated. As described above, the signal line drive circuit of the display device of the present embodiment is not limited to the configuration shown in FIG. 83 (C).

Such a signal line drive circuit 22703, a scan line drive circuit 22704, and a pixel unit 22705 can be formed by semiconductor elements provided on the same substrate. The semiconductor element can be formed by using a thin film transistor provided on a glass substrate. In this case, a crystalline semiconductor film may be applied to the semiconductor element. Since the crystalline semiconductor film has high electrical characteristics, particularly high mobility, it is possible to form a circuit included in the drive circuit unit. Further, the signal line drive circuit 2
The 2703 and the scanning line drive circuit 22704 are IC (Integrated Circuit).
) It can also be mounted on a substrate using a chip. In this case, an amorphous semiconductor film can be applied to the semiconductor element of the pixel portion.

Here, the liquid crystal display module of this embodiment will be described with reference to FIGS. 87 (A) and 87 (B).

FIG. 87 (A) is an example of a liquid crystal display module, in which the TFT substrate 23100 and the facing substrate 23 are shown.
101 is fixed by the sealing material 23102, and the pixel portion 23103 including the TFT and the like is in between.
And the liquid crystal layer 23104 is provided to form a display area. The colored layer 23105 is necessary for color display, and in the case of the RGB method, a colored layer corresponding to each of the red, green, and blue colors is provided corresponding to each pixel. On the outside of the TFT substrate 23100 and the facing substrate 23101, a layer 23106 containing a first polarizing element, a layer 23107 containing a second polarizing element, and a diffuser plate 23113
Are arranged. The light source is composed of a cold cathode tube 23110 and a reflector 23111, and the circuit board 23112 is connected to the TFT board 23100 by a flexible wiring board 23109, and an external circuit such as a control circuit and a power supply circuit is incorporated.

Layer 2310 containing a second polarizing element between the TFT substrate 23100 and the backlight which is a light source.
7 is laminated and provided, and the facing substrate 23101 is also provided with a layer 23106 containing a first polarizing element in a laminated manner. On the other hand, the absorption axis of the layer 23107 containing the second polarizing element and the absorption axis of the layer 23106 including the first polarizing element provided on the viewing side are arranged so as to form a cross Nicole.

Layer 23107 containing the laminated second polarizing element and layer 2310 containing the laminated first polarizing element.
6 is adhered to the TFT substrate 23100 and the facing substrate 23101. Further, the layer containing the laminated polarizing element may be laminated with a retardation plate between the substrate and the layer. Further, if necessary, the layer 23106 containing the first polarizing element on the visual recognition side may be subjected to antireflection treatment.

The liquid crystal display module has a TN (Twisted Nematic) mode and an IPS (I).
n-Plane-Switching) mode, FFS (Fringe Field S)
(witching) mode, MVA (Multi-domain Vertical A)
lignment) mode, PVA (Patterned Vertical Alig)
nment), ASM (Axially Symmetrically aligned Mic)
ro-cell) mode, OCB (Optical Compensated Bire)
fringence) mode, FLC (Ferroelectric Liquid C)
rystal) mode, AFLC (AntiFerolectric Liquid)
Crystal), PDLC (Polymer Dispersed Liquid)
Crystal) mode and the like can be used.

FIG. 87 (B) is an example in which the OCB mode is applied to the liquid crystal display module of FIG. 87 (A), and is an FS-LCD (Field sequential-LCD). FS-L
The CD emits red light, green light, and blue light in one frame period, respectively, and it is possible to synthesize images and display them in color by using time division. Further, since each light emission is performed by a light emitting diode, a cold cathode tube, or the like, a color filter is not required. Therefore, it is not necessary to arrange the color filters of the three primary colors and limit the display area of each color, and all three colors can be displayed in any area. On the other hand, since three colors are emitted in one frame period, a high-speed response of the liquid crystal display is required. By applying the FLC mode and OCB mode using the FS method to the display device of the present embodiment, it is possible to complete a high-performance, high-quality display device and a liquid crystal television device.

The liquid crystal layer in OCB mode has a so-called π cell structure. The π-cell structure is a structure in which the pretilt angle of the liquid crystal molecules is oriented in a plane-symmetrical relationship with respect to the central plane between the active matrix substrate and the opposite substrate. The orientation state of the π cell structure is spray orientation when no voltage is applied between the substrates, and shifts to bend orientation when voltage is applied. This bend orientation is displayed in white. When a voltage is further applied, the bend-oriented liquid crystal molecules are oriented perpendicular to both substrates, and light is not transmitted. In the OCB mode, high-speed response that is about 10 times faster than the conventional TN mode can be realized.

In addition, as a mode corresponding to the FS method, a ferroelectric liquid crystal display (FLC: Fe) capable of high-speed operation is possible.
HV (Half V) using rotary Liquid Crystal)
) -FLC, SS (Surface Managed) -FLC and the like can also be used.

Further, by narrowing the cell gap of the liquid crystal display module, the optical response speed of the liquid crystal display module can be increased. In addition, the speed can be increased by lowering the viscosity of the liquid crystal material. The high speed is more effective when the pixel pitch of the pixel region of the liquid crystal display module in the TN mode is 30 μm or less. Further, the speed may be increased by using an overdrive in which the applied voltage applied to the liquid crystal layer is momentarily higher (or lower) than the original voltage.

The liquid crystal display module of FIG. 87B shows a transmissive liquid crystal display module, and is provided with a red light source 23190a, a green light source 23190b, and a blue light source 23190c as light sources. As the light source, a control unit 23199 is installed to control the on / off of each of the red light source 23190a, the green light source 23190b, and the blue light source 23190c. Control unit 2319
The emission of each color is controlled by 9, the light is incident on the liquid crystal display, the image is synthesized by using the time division, and the color display is performed.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 10)
In this embodiment, a method of driving the display device will be described. In particular, a method of driving the liquid crystal display device will be described.

First, the overdrive drive will be described with reference to FIG. 88. (A) of FIG. 88 is
It represents the time change of the output luminance of the display element with respect to the input voltage. The time change of the output luminance of the display element with respect to the input voltage 30121 represented by the broken line is as shown by the output luminance 30123 also represented by the broken line. That is, the voltage for obtaining the target output luminance Low is Vi, but when Vi is input as it is as the input voltage, it takes time corresponding to the response speed of the element until the target output luminance Low is reached. It ends up.

Overdrive drive is a technique for increasing this response speed. Specifically, first,
This is a method in which the response speed of the output luminance is increased by applying Vo, which is a voltage higher than Vi, to the element for a certain period of time, and after approaching the target output luminance Low, the input voltage is returned to Vi. The input voltage at this time is represented by the input voltage 30122, and the output luminance is represented by the output luminance 30124. In the graph of the output luminance 30124, the time required to reach the target luminance Low is shorter than that of the graph of the output luminance 30123.

In addition, in FIG. 88A, the case where the output luminance changes positively with respect to the input voltage is described, but the present embodiment also includes the case where the output luminance changes negatively with respect to the input voltage. I'm out.

A circuit for realizing such a drive will be described with reference to FIG. 88 (B) and FIG. 88 (C). First, with reference to FIG. 88B, a case where the input video signal 30131 is a signal having an analog value (may be a discrete value) and the output video signal 30132 is also a signal having an analog value will be described. The overdrive circuit shown in FIG. 88 (B) includes a coding circuit 30101, a frame memory 30102, a correction circuit 30103, and a DA conversion circuit 30.
104.

The input video signal 30131 is first input to the coding circuit 30101 and encoded. That is, the analog signal is converted into a digital signal having an appropriate number of bits. After that, the converted digital signal is input to the frame memory 30102 and the correction circuit 30103, respectively. The video signal of the previous frame held in the frame memory 30102 is also input to the correction circuit 30103 at the same time. Then, in the correction circuit 30103, the corrected video signal is output from the video signal of the frame and the video signal of the previous frame according to the numerical table prepared in advance. At this time, the output switching signal 30133 may be input to the correction circuit 30103 so that the corrected video signal and the video signal of the frame can be switched and output. Next, the corrected video signal or the video signal of the frame is input to the DA conversion circuit 30104. Then, the output video signal 30132, which is an analog signal having a value according to the corrected video signal or the video signal of the frame, is output. In this way, overdrive drive can be realized.

Next, a case where the input video signal 30131 is a signal having a digital value and the output video signal 30132 is also a signal having a digital value will be described with reference to FIG. 88 (C). FIG. 8
The overdrive circuit shown in (C) of 8 is a frame memory 30112 and a correction circuit 301.
13.

The input video signal 30131 is a digital signal, and first, the frame memory 30112 and
It is input to the correction circuit 30113 and, respectively. The video signal of the previous frame held in the frame memory 30112 is also input to the correction circuit 30113 at the same time. Then, in the correction circuit 30113, the corrected video signal is output from the video signal of the frame and the video signal of the previous frame according to the numerical table prepared in advance. At this time, the output switching signal 30133 may be input to the correction circuit 30113 so that the corrected video signal and the video signal of the frame can be switched and output. In this way, overdrive drive can be realized.

The overdrive circuit in the present embodiment also includes a case where the input video signal 30131 is an analog signal and the output video signal 30132 is a digital signal. At this time,
The DA conversion circuit 30104 may be omitted from the circuit shown in FIG. 88 (B). Further, the overdrive circuit in the present embodiment includes a case where the input video signal 30131 is a digital signal and the output video signal 30132 is an analog signal. At this time, the coding circuit 30101 may be omitted from the circuit shown in FIG. 88 (B).

Next, the drive for manipulating the potential of the common line will be described with reference to FIG. 89. Of FIG. 89
A) represents a plurality of pixel circuits when one common line is arranged for one scanning line in a display device using a display element having a capacitive property such as a liquid crystal element. It is a figure. The pixel circuit shown in FIG. 89A includes a transistor 30201, an auxiliary capacity 30202, a display element 30203, a video signal line 30204, a scanning line 30205, and a common line 30206.

The gate electrode of the transistor 30201 is electrically connected to the scanning line 30205, one of the source or drain electrodes of the transistor 30201 is electrically connected to the video signal line 30204, and the other of the source or drain electrodes of the transistor 30201. Is electrically connected to one electrode of the auxiliary capacity 30202 and one electrode of the display element 30203.
Further, the other electrode of the auxiliary capacity 30202 is electrically connected to the common wire 30206.

First, since the transistor 30201 is turned on for the pixel selected by the scanning line 30205, a voltage corresponding to the video signal is applied to the display element 30203 and the auxiliary capacity 30202, respectively, via the video signal line 30204. At this time, the video signal is the common line 3
If the lowest gradation is displayed for all the pixels connected to 0206, or the highest gradation is displayed for all the pixels connected to the common line 30206, the pixel. It is not necessary to write a video signal to each of the video signals via the video signal line 30204.
Instead of writing the video signal via the video signal line 30204, the voltage applied to the display element 30203 can be changed by moving the potential of the common line 30206.

Next, FIG. 89 (B) shows a display device using a display element having a capacitive property such as a liquid crystal element, in which two common lines are arranged for one scanning line. It is a figure showing a plurality of pixel circuits. The pixel circuit shown in FIG. 89 (B) includes a transistor 30211, an auxiliary capacity 30212, a display element 30213, a video signal line 30214, a scanning line 30215, a first common line 30216, and a second common line 30217. ..

The gate electrode of transistor 30211 is electrically connected to the scanning line 30215, one of the source or drain electrodes of transistor 30211 is electrically connected to the video signal line 30214, and the other of the source or drain electrode of transistor 30211. Is electrically connected to one electrode of the auxiliary capacity 30212 and one electrode of the display element 30213.
Further, the other electrode of the auxiliary capacity 30212 is electrically connected to the first common wire 30216.
Further, in the pixel adjacent to the pixel, the other electrode of the auxiliary capacitance 30212 is electrically connected to the second common wire 30217.

Since the pixel circuit shown in FIG. 89 (B) has few pixels electrically connected to one common line, the first common line 30216 is used instead of writing a video signal via the video signal line 30214. Alternatively, by moving the potential of the second common line 30217, the display element 30213
The frequency with which the voltage applied to can be changed is significantly increased. In addition, source inversion drive or dot inversion drive becomes possible. By the source inversion drive or the dot inversion drive, flicker can be suppressed while improving the reliability of the element.

Next, the scanning backlight will be described with reference to FIG. 90. FIG. 90A is a diagram showing a scanning backlight in which cold cathode fluorescent lamps are juxtaposed. The scanning backlight shown in FIG. 90 (A) includes a diffuser plate 30301 and N cold-cathode tubes 30302-1 to 30302-N. By juxtaposing N cold-cathode tubes 30302-1 to 30302-N behind the diffuser plate 30301, the N cold-cathode tubes 30302-1 to 30302-N can be scanned by changing their brightness. Can be done.

The change in the brightness of each cold-cathode tube during scanning will be described with reference to FIG. 90 (C). First, the brightness of the cold cathode fluorescent lamp 30302-1 is changed for a certain period of time. Then, after that, the cold cathode fluorescent lamp 30
The brightness of the cold cathode fluorescent lamp 30302-2 arranged next to the 302-1 is changed by the same time. In this way, the brightness is sequentially changed from the cold cathode fluorescent lamp 30302-1 to 30302-N. In (C) of FIG. 90, the brightness changed for a certain period of time is smaller than the original brightness, but may be larger than the original brightness. In addition, cold cathode tubes 30302-1 to 3030
Although it is assumed that scanning is performed up to 2-N, the cold-cathode tubes 30302-N to 30302-1 may be scanned in the opposite direction.

By driving as shown in FIG. 90, the average brightness of the backlight can be reduced. Therefore, it is possible to reduce the power consumption of the backlight, which occupies most of the power consumption of the liquid crystal display device.

An LED may be used as the light source of the scanning backlight. The scanning backlight in that case is as shown in FIG. 90 (B). The scanning backlight shown in FIG. 90 (B) includes a diffuser plate 30311 and light sources 30312-1 to 30312-N in which LEDs are juxtaposed. When an LED is used as the light source of the scanning backlight, the backlight is made thin.
It has the advantage of being lighter. In addition, there is an advantage that the color reproduction range can be expanded. Further, LEs arranged side by side in each of the light sources 30312-1 to 30312-N in which LEDs are arranged side by side.
Since D can also be scanned in the same manner, it can also be a point scanning type backlight.
If the point scanning type is used, the image quality of the moving image can be further improved.

Even when an LED is used as the light source of the backlight, it can be driven by changing the brightness as shown in FIG. 90 (C).

Next, the high frequency drive will be described with reference to FIG. 91. FIG. 91 (A) is a diagram when one image and one intermediate image are displayed in one frame period 30400. 3040
1 is an image of the frame, 30402 is an intermediate image of the frame, 30403 is an image of the next frame, and 30404 is an intermediate image of the next frame.

The intermediate image 30402 of the frame may be an image created based on the video signals of the frame and the next frame. Further, the intermediate image 30402 of the frame may be an image created from the image 30401 of the frame. Further, the intermediate image 30402 of the frame may be a black image. By doing so, the image quality of the moving image of the hold type display device can be improved. Further, when displaying one image and one intermediate image in one frame period 30400, there is an advantage that the frame rate of the video signal is easily matched and the image processing circuit is not complicated.

FIG. 91 (B) is a diagram when one image and two intermediate images are displayed in a period (two frame periods) in which one frame period 30400 is two consecutive periods. 30411 is the image of the frame, 30412 is the intermediate image of the frame, 30413 is the intermediate image of the next frame, 3.
0414 is an image of frames one after another.

The intermediate image 30412 of the frame and the intermediate image 30413 of the next frame may be images created based on the video signals of the frame, the next frame, and the next frame. Further, the intermediate image 30412 of the frame and the intermediate image 30413 of the next frame are
It may be a black image. When displaying one image and two intermediate images in a two-frame period, there is an advantage that the image quality of the moving image can be effectively improved without increasing the operating frequency of the peripheral drive circuit so much.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 11)
In this embodiment, the pixel structure of the display device will be described. In particular, the pixel structure of the display device using the organic EL element will be described.

FIG. 92A shows a layout example of a pixel element having two TFTs in one pixel.
Further, in FIG. 92 (A), a cross-sectional view of a portion indicated by XX'is shown in FIG. 92 (B).

As shown in FIG. 92 (A), the pixel in this embodiment is the first TFT 60105,
First wiring 60106, second wiring 60107, second TFT 60108, third wiring 6
0111, counter electrode 60112, capacitor 60113, pixel electrode 60115, partition wall 60
It may have 116, an organic conductor film 60117, an organic thin film 60118, and a substrate 60119. The first TFT 60105 is a switching TFT, and the first wiring 601 is used.
06 is a gate signal line, the second wiring 60107 is a source signal line, and a second TFT.
It is preferable that 60108 is used as a driving TFT and the third wiring 60111 is used as a current supply line.

As shown in FIG. 92 (A), the gate electrode of the first TFT 60105 is the first wiring 60.
Electrically connected to 106, one of the source or drain electrodes of the first TFT 60105 is electrically connected to the second wiring 60107, and the other of the source or drain electrodes of the first TFT 60105 is the second. It is preferable that the gate electrode of the TFT 60108 and one electrode of the capacitor 60113 are electrically connected. The first TFT
As shown in FIG. 92 (A), the gate electrode of 60105 may be composed of a plurality of gate electrodes. By doing so, the leakage current in the off state of the first TFT 60105 can be reduced.

Further, one of the source electrode and the drain electrode of the second TFT 60108 is a third wiring 6
It is preferably electrically connected to 0111 and the other of the source or drain electrodes of the second TFT 60108 is electrically connected to the pixel electrode 60115. By doing so, the current flowing through the pixel electrode 60115 can be controlled by the second TFT 60108.

An organic conductor film 60117 may be provided on the pixel electrode 60115, and an organic thin film (organic compound layer) 60118 may be further provided. A counter electrode 60112 may be provided on the organic thin film (organic compound layer) 60118. The counter electrode 60112 may be formed in a solid shape so as to be connected in common to all the pixels, or may be patterned by using a shadow mask or the like.

The light emitted from the organic thin film (organic compound layer) 60118 is emitted through either the pixel electrode 60115 or the counter electrode 60112. At this time, in FIG. 92B, the case where light is emitted to the pixel electrode side, that is, the side where the TFT or the like is formed is referred to as bottom surface emission, and the case where light is emitted to the counter electrode side is referred to as top surface emission.

In the case of bottom surface injection, it is preferable that the pixel electrode 60115 is formed of a transparent conductive film. On the contrary, in the case of top surface injection, it is preferable that the counter electrode 60112 is formed of a transparent conductive film.

Further, in the color display light emitting device, the EL elements having the respective emission colors of R, G, and B may be painted separately, or the single color EL elements may be painted in a solid form, and the R, G, and B may be painted by a color filter. The light emission of B may be obtained.

The configuration shown in FIG. 92 is merely an example, and various configurations other than those shown in FIG. 92 can be taken with respect to the pixel layout, the cross-sectional configuration, the stacking order of the electrodes of the EL element, and the like. Further, as the light emitting layer, in addition to the element composed of the organic thin film shown in the figure, various elements such as a crystalline element such as an LED and an element composed of an inorganic thin film can be used.

Next, with reference to FIG. 93 (A), a layout example of a pixel element having three TFTs in one pixel will be described. Further, in FIG. 93 (A), a cross-sectional view of a portion indicated by XX'is shown in FIG. 93 (B).

As shown in FIG. 93 (A), the pixels in the present embodiment include the substrate 60200, the first wiring 60201, the second wiring 60202, the third wiring 60203, and the fourth wiring 60204.
It may have a first TFT 60205, a second TFT 60206, a third TFT 60207, a pixel electrode 60208, a partition wall 60211, an organic conductor film 60212, an organic thin film 60213, and a counter electrode 60214. The first wiring 60201 is used as a source signal line.
The second wiring 60202 is used as a writing gate signal line, the third wiring 60203 is used as an erasing gate signal line, the fourth wiring 60204 is used as a current supply line, and the first TFT 60205 is used as a switching TFT. TFT 60206 is a third T as an erasing TFT.
The FT60207 is preferably used as a driving TFT, respectively.

As shown in FIG. 93 (A), the gate electrode of the first TFT 60205 is the second wiring 60.
Electrically connected to 202, one of the source or drain electrodes of the first TFT 60205 is electrically connected to the first wiring 60201, and the other of the source or drain electrodes of the first TFT 60205 is the third. It is preferable that it is electrically connected to the gate electrode of TFT 60207. The gate electrode of the first TFT 60205 is shown in FIG. 93 (A).
As shown in, it may be composed of a plurality of gate electrodes. By doing this, the first
The leakage current in the OFF state of the TFT 60205 can be reduced.

Further, the gate electrode of the second TFT 60206 is electrically connected to the third wiring 60203, and one of the source electrode and the drain electrode of the second TFT 60206 is the fourth wiring 6
It is preferred that it is electrically connected to 0204 and the other of the source or drain electrodes of the second TFT 60206 is electrically connected to the gate electrode of the third TFT 60207. As shown in FIG. 93 (A), the gate electrode of the second TFT 60206 may be composed of a plurality of gate electrodes. By doing so, the leakage current in the off state of the second TFT 60206 can be reduced.

Further, one of the source electrode and the drain electrode of the third TFT 60207 is the fourth wiring 6
It is preferred that it is electrically connected to 0204 and the other of the source or drain electrodes of the third TFT 60207 is electrically connected to the pixel electrode 60208. By doing so, the current flowing through the pixel electrode 60208 can be controlled by the third TFT 60207.

An organic conductor film 60212 may be provided on the pixel electrode 60208, and an organic thin film (organic compound layer) 60213 may be further provided. A counter electrode 60214 may be provided on the organic thin film (organic compound layer) 60213. The counter electrode 60214 may be formed in a solid shape so as to be connected in common to all the pixels, or may be patterned by using a shadow mask or the like.

The light emitted from the organic thin film (organic compound layer) 60213 is emitted through either the pixel electrode 60208 or the counter electrode 60214. At this time, in FIG. 93B, the case where light is emitted to the pixel electrode side, that is, the side where the TFT or the like is formed is referred to as bottom surface emission, and the case where light is emitted to the counter electrode side is referred to as top surface emission.

In the case of bottom surface injection, the pixel electrode 60208 is preferably formed of a transparent conductive film. On the contrary, in the case of top surface injection, it is preferable that the counter electrode 60214 is formed of a transparent conductive film.

Further, in the color display light emitting device, the EL elements having the respective emission colors of R, G, and B may be painted separately, or the single color EL elements may be painted in a solid form, and the R, G, and B may be painted by a color filter. The light emission of B may be obtained.

The configuration shown in FIG. 93 is merely an example, and various configurations other than those shown in FIG. 93 can be taken with respect to the pixel layout, the cross-sectional configuration, the stacking order of the electrodes of the EL element, and the like. Further, as the light emitting layer, in addition to the element composed of the organic thin film shown in the figure, various elements such as a crystalline element such as an LED and an element composed of an inorganic thin film can be used.

Next, with reference to FIG. 94 (A), a layout example of a pixel element having four TFTs in one pixel will be described. Further, in FIG. 94 (A), a cross-sectional view of a portion indicated by XX'is shown in FIG. 94 (B).

As shown in FIG. 94 (A), the pixels in the present embodiment include the substrate 60300, the first wiring 60301, the second wiring 60302, the third wiring 60303, and the fourth wiring 60304.
1st TFT60305, 2nd TFT60306, 3rd TFT60307, 4th T
FT60308, pixel electrode 60309, fifth wiring 60311, sixth wiring 60312,
Partition wall 60321, organic conductor film 60322, organic thin film 60323, counter electrode 60324,
May have. The first wiring 60301 is used as a source signal line, and the second wiring 6 is used.
0302 is a writing gate signal line, the third wiring 60303 is an erasing gate signal line, the fourth wiring 60304 is a reverse bias signal line, and the first TFT 60305 is a switching TFT. The TFT 60306 is a third T as an erasing TFT.
The FT60307 is a driving TFT, and the fourth TFT 60308 is a reverse bias TF.
As T, it is preferable that the fifth wiring 60311 is used as a current supply line and the sixth wiring 60312 is used as a power supply line for reverse bias.

As shown in FIG. 94 (A), the gate electrode of the first TFT 60305 is the second wiring 60.
Electrically connected to 302, one of the source or drain electrodes of the first TFT 60305 is electrically connected to the first wiring 60301, and the other of the source or drain electrodes of the first TFT 60305 is the third. It is preferable that it is electrically connected to the gate electrode of the TFT 60307. The gate electrode of the first TFT 60305 is shown in FIG. 94 (A).
As shown in, it may be composed of a plurality of gate electrodes. By doing this, the first
The leakage current in the OFF state of the TFT 60305 can be reduced.

Further, the gate electrode of the second TFT 60306 is electrically connected to the third wiring 60303, and one of the source electrode and the drain electrode of the second TFT 60306 is the fifth wiring 6
It is preferred that it is electrically connected to 0311 and the other of the source or drain electrodes of the second TFT 60306 is electrically connected to the gate electrode of the third TFT 60307. As shown in FIG. 94A, the gate electrode of the second TFT 60306 may be composed of a plurality of gate electrodes. By doing so, the leakage current in the off state of the second TFT 60306 can be reduced.

Further, one of the source electrode and the drain electrode of the third TFT 60307 is the fifth wiring 6
It is preferable that the other of the source electrode or the drain electrode of the third TFT 60307 is electrically connected to the pixel electrode 60309. By doing so, the current flowing through the pixel electrode 60309 can be controlled by the third TFT 60307.

Further, the gate electrode of the fourth TFT 60308 is electrically connected to the fourth wiring 60304, and one of the source electrode and the drain electrode of the fourth TFT 60308 is the sixth wiring 60.
It is preferred that it is electrically connected to 312 and the other of the source or drain electrodes of the fourth TFT 60308 is electrically connected to the pixel electrode 60309. By doing so, the potential of the pixel electrode 60309 can be controlled by the fourth TFT 60308, so that the bias in the opposite direction can be applied to the organic conductor film 60322 and the organic thin film 60323. By applying a bias in the opposite direction to the light emitting element composed of the organic conductor film 60322 and the organic thin film 60323, the reliability of the light emitting element can be greatly improved.

For example, an AC voltage (forward bias: 3.7V, reverse bias: 1.7V, duty 50%,) of a light emitting element having a brightness half time of about 400 hours when driven by a DC voltage (3.65V). It is known that when driven at an AC frequency of 60 Hz), the brightness half-time is 700 hours or more.

Next, an organic conductor film 60322 may be provided on the pixel electrode 60309, and an organic thin film (organic compound layer) 60323 may be further provided. Organic thin film (organic compound layer) 603
A counter electrode 60324 may be provided on the 23. The counter electrode 60324 may be formed in a solid shape so as to be connected in common to all the pixels, or may be patterned by using a shadow mask or the like.

The light emitted from the organic thin film (organic compound layer) 60323 is emitted through either the pixel electrode 60309 or the counter electrode 60324. At this time, in FIG. 94B, the case where light is emitted to the pixel electrode side, that is, the side where the TFT or the like is formed is referred to as bottom surface emission, and the case where light is emitted to the counter electrode side is referred to as top surface emission.

In the case of bottom surface injection, it is preferable that the pixel electrode 60309 is formed of a transparent conductive film. On the contrary, in the case of top surface injection, it is preferable that the counter electrode 60324 is formed of a transparent conductive film.

Further, in the color display light emitting device, the EL elements having the respective emission colors of R, G, and B may be painted separately, or the single color EL elements may be painted in a solid form, and the R, G, and B may be painted by a color filter. The light emission of B may be obtained.

The configuration shown in FIG. 94 is merely an example, and various configurations other than those shown in FIG. 94 can be taken with respect to the pixel layout, the cross-sectional configuration, the stacking order of the electrodes of the EL element, and the like. Further, as the light emitting layer, in addition to the element composed of the organic thin film shown in the figure, various elements such as a crystalline element such as an LED and an element composed of an inorganic thin film can be used.

Next, the structure of the EL element applicable to the present invention will be described.

The EL element applicable to the present invention includes a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light emitting layer made of a light emitting material, an electron transport layer made of an electron transport material, and an electron injection material. The electron injection layer and the like are not a laminated structure that can be clearly distinguished, but a plurality of materials among the materials such as hole injection material, hole transport material, light emitting material, electron transport material, and electron injection material are used. A configuration having a mixed layer (mixed layer) (hereinafter, referred to as a mixed bonding type EL element) may be used.

A schematic diagram showing the structure of the mixed bonding type EL element is shown in FIG. 95. In FIG. 95, 604
01 is the anode of the EL element. Reference numeral 60402 is a cathode of the EL element. The layer sandwiched between the anode 60401 and the cathode 60402 corresponds to the EL layer.

In FIG. 95 (A), the EL layer has a hole transport region 60403 made of a hole transport material and a hole transport region 60403.
The hole transport region 60403 includes an electron transport region 60404 made of an electron transport material, the hole transport region 60403 is located on the anode side of the electron transport region 60404, and the hole transport region 60403 is located.
A mixed region 60405 containing both the hole transporting material and the electron transporting material may be provided between the electron transporting region 60404 and the hole transporting material.

At this time, in the direction from the anode 60401 to the cathode 60402, the mixing region 6040
It may be characterized in that the concentration of the hole transporting material in 5 decreases and the concentration of the electron transporting material in the mixed region 60405 increases.

In the above configuration, the hole transport region 60403 composed only of the hole transport material does not exist, and the concentration ratio of each functional material changes inside the mixed region 60405 containing both the hole transport material and the electron transport material. It may be configured (having a concentration gradient). Further, the hole transport region 60403 composed only of the hole transport material and the electron transport region 6040 composed only of the electron transport material.
4 may be absent and the composition may be such that the ratio of the concentration of each functional material changes (has a concentration gradient) inside the mixed region 60405 containing both the hole transporting material and the electron transporting material. Further, the ratio of the concentration may be configured to change depending on the distance from the anode or the cathode. Furthermore, the change in the proportion of the concentration may be continuous. The method of setting the concentration gradient can be freely set.

Within the mixed region 60405, there is a region 60406 to which the light emitting material is added. The emission color of the EL element can be controlled by the light emitting material. In addition, the light emitting material can trap the carrier. As the light emitting material, various fluorescent dyes can be used in addition to a metal complex containing a quinoline skeleton, a metal complex containing a benzoxador skeleton, a metal complex containing a benzothiazol skeleton, and the like. By adding these light emitting materials, the light emitting color of the EL element can be controlled.

As the anode 60401, it is preferable to use an electrode material having a large work function in order to efficiently inject holes. For example, transparent electrodes such as tin-doped indium oxide (ITO), zinc-doped indium oxide (IZO), ZnO, SnO ₂ , and In ₂ O ₃ can be used. Further, the anode 60401 may be an opaque metal material if it is not necessary to have translucency.

Further, as the hole transport material, an aromatic amine-based compound or the like can be used.

Further, as the electron transport material, a quinoline derivative, 8-quinolinol or a metal complex having a derivative thereof as a ligand (particularly, tris (8-quinolinolite) aluminum (Alq ₃ )).
) Etc. can be used.

As the cathode 60402, it is preferable to use an electrode material having a small work function in order to efficiently inject electrons. Metals such as aluminum, indium, magnesium, silver, calcium, barium and lithium can be used alone. Further, it may be an alloy of these metals, or an alloy of these metals with another metal.

FIG. 95 (B) shows a schematic diagram of an EL element having a configuration different from that of FIG. 95 (A). In addition, FIG. 95
The same parts as in (A) are shown using the same reference numerals, and the description thereof will be omitted.

In FIG. 95 (B), there is no region to which the light emitting material is added. However, the electron transport region 60
As the material to be added to 404, a material having both electron transporting property and light emitting property (electron transporting light emitting material), for example, tris (8-quinolinolite) aluminum (Alq ₃ ) can be used for light emission.

Alternatively, as the material to be added to the hole transport region 60403, a material having both hole transport property and luminescence (hole transport luminescent material) may be used.

FIG. 95 (C) shows a schematic diagram of an EL element having a configuration different from that of FIGS. 95 (A) and 95 (B). The same parts as those in FIGS. 95 (A) and 95 (B) are shown using the same reference numerals, and the description thereof will be omitted.

In FIG. 95 (C), the hole blocking material having a large energy difference between the highest occupied molecular orbital and the lowest occupied molecular orbital as compared with the hole transporting material has a region 60407 added in the mixed region 60405. .. By arranging the region 60407 to which the hole blocking material is added on the cathode 60402 side of the region 60406 to which the light emitting material is added in the mixed region 60405, the carrier recombination rate can be increased and the luminous efficiency can be increased. can. The above-mentioned configuration in which the region 60407 to which the hole blocking material is added is particularly effective in an EL device that utilizes light emission (phosphorescence) by a triple photoexciter.

FIG. 95 (D) shows a schematic diagram of an EL element having a configuration different from that of FIGS. 95 (A), 95 (B) and 95 (C). The same parts as those in FIGS. 95 (A), 95 (B) and 95 (C) are shown using the same reference numerals, and the description thereof will be omitted.

In FIG. 95 (D), the electron blocking material having a larger energy difference between the highest occupied molecular orbital and the lowest occupied molecular orbital than the electron transporting material has a region 60408 added in the mixed region 60405. By arranging the region 60408 to which the electron blocking material is added closer to the anode 60401 than the region 60406 to which the light emitting material is added in the mixed region 60405, the carrier recombination rate can be increased and the luminous efficiency can be increased. .. The above-mentioned configuration in which the region 60408 to which the electron blocking material is added is provided is particularly effective in an EL device that utilizes light emission (phosphorescence) by a triple photoexciter.

FIG. 95 (E) is a schematic diagram showing the configuration of a mixed-junction type EL element different from FIGS. 95 (A), 95 (B), 95 (C) and 95 (D). FIG. 95 (E) shows an example of a configuration having a region 60409 to which a metal material is added in a portion of the EL layer in contact with the electrode of the EL element. In FIG. 95 (E), the same parts as those in FIGS. 95 (A) to 95 (D) are shown by using the same reference numerals, and the description thereof will be omitted. The configuration shown in FIG. 95 (E) is, for example, Mg as the cathode 60401.
Cathode 60 in region 60404 to which electron transport material was added using Ag (Mg—Ag alloy)
It may be configured to have a region 60409 in which an Al (aluminum) alloy is added to a region in contact with 402. With the above configuration, it is possible to prevent oxidation of the cathode and increase the efficiency of electron injection from the cathode. In this way, the life of the mixed bonding type EL element can be extended. In addition, the drive voltage can be lowered.

As a method for producing the mixed bonding type EL element, a co-deposited method or the like can be used.

In the mixed bonding type EL element as shown in FIGS. 95 (A) to 95 (E), the interface of a clear layer does not exist, and the charge accumulation can be reduced. In this way, the life can be extended. In addition, the drive voltage can be lowered.

The configurations shown in FIGS. 95 (A) to 95 (E) can be freely combined and implemented.

The configuration of the mixed bonding type EL element is not limited to this. A known configuration can be freely used.

The organic material constituting the EL layer of the EL element may be a small molecule material or a polymer material. Moreover, you may use both of these materials. When a small molecule material is used as the organic compound material, a film can be formed by a vapor deposition method. On the other hand, when a polymer material is used as the EL layer, the polymer material can be dissolved in a solvent to form a film by a spin coating method or an inkjet method.

Further, the EL layer may be made of a medium molecular weight material. In the present specification, the medium-molecular-weight organic light-emitting material means an organic light-emitting material having no sublimation property and having a degree of polymerization of about 20 or less. When a medium molecular weight material is used as the EL layer, a film can be formed by an inkjet method or the like.

A small molecule material, a polymer material, and a medium molecule material may be used in combination.

Further, the EL element may be either one that utilizes light emission (fluorescence) from a singlet exciton or one that utilizes light emission (phosphorescence) from a triplet exciton.

Next, a vapor deposition apparatus for manufacturing a display device applicable to the present invention will be described with reference to the drawings.

The display device applicable to the present invention may be manufactured by forming an EL layer. The EL layer is formed by containing at least a part of a material that expresses electroluminescence. The EL layer may be composed of a plurality of layers having different functions. In that case, the EL layer is a hole injection transport layer, a light emitting layer,
Layers having different functions, which are also called electron injection transport layers, may be combined and configured.

FIG. 9 shows the configuration of a thin-film deposition apparatus for forming an EL layer on an element substrate on which a transistor is formed.
Shown in 6. In this thin-film deposition apparatus, a plurality of processing chambers are connected to the transport chambers 60560 and 60561. The processing chamber includes a load chamber 60562 for supplying the substrate and an unload chamber 60 for collecting the substrate.
563, heat treatment chamber 60568, plasma treatment chamber 60572, film formation treatment chambers 60569 to 60575 for depositing EL material, film formation to form a conductive film containing aluminum or aluminum as a main component as one electrode of the EL element. It includes a processing chamber 60576.
Further, gate valves 60577a to 60577m are provided between the transport chamber and each treatment chamber, and the pressure in each treatment chamber can be controlled independently to prevent mutual contamination between the treatment chambers.

The substrate introduced from the load chamber 60562 to the transport chamber 60560 is carried into a predetermined processing chamber by the rotatably provided arm-type transport means 60566. Further, the substrate is conveyed from one processing chamber to another by the conveying means 60566. The transport chamber 60560 and the transport chamber 60561 are connected by a film forming processing chamber 60570, where the substrate is delivered by the transport means 60566 and the transport means 60567.

Each processing chamber connected to the transport chamber 60560 and the transport chamber 60561 is maintained in a reduced pressure state. Therefore, in this thin-film deposition apparatus, the film formation process of the EL layer is continuously performed without the substrate coming into contact with the atmosphere. Since the display panel after the film formation process of the EL layer may be deteriorated by water vapor or the like, in this vapor deposition apparatus, a sealing process is performed to perform a sealing process before the film is exposed to the atmosphere in order to maintain the quality. The chamber 60565 is connected to the transport chamber 60561. Sealing chamber 60
Since the 565 is placed under atmospheric pressure or a reduced pressure close to that of the atmospheric pressure, an intermediate processing chamber 60564 is also provided between the transport chamber 60561 and the sealing processing chamber 60565. Intermediate processing room 6056
Reference numeral 4 is provided for passing the substrate and cushioning the pressure between the chambers.

The load chamber, the unload chamber, the transport chamber, and the film forming processing chamber are provided with exhaust means for keeping the chamber under reduced pressure. As the exhaust means, various vacuum pumps such as a dry pump, a turbo molecular pump, and a diffusion pump can be used.

In the thin-film deposition apparatus of FIG. 96, the number and configurations of the processing chambers connected to the transport chamber 60560 and the transport chamber 60561 can be appropriately combined according to the laminated structure of the EL elements. An example of the combination is shown below.

The heat treatment chamber 60568 first heats a substrate on which a lower electrode, an insulating partition wall, and the like are formed to perform degassing treatment. In the plasma processing chamber 60572, the surface of the base electrode is treated with a rare gas or oxygen plasma. This plasma treatment is performed to clean the surface, stabilize the surface state, and stabilize the physical or chemical state of the surface (for example, work function).

The film forming processing chamber 60569 is a processing chamber for forming an electrode buffer layer in contact with one electrode of the EL element. The electrode buffer layer has carrier injection properties (hole injection or electron injection).
This layer suppresses the occurrence of short circuits and dark spot defects in EL elements. Typically, the electrode buffer layer is
It is an organic-inorganic mixed material, has a resistivity of 5 × 104 to 1 × 106 Ωcm, and has a resistance of 30 to 30.
It is formed to a thickness of 0 nm. Further, the film forming chamber 60571 is a processing chamber for forming a hole transport layer.

The light emitting layer in the EL element has a different configuration depending on whether it emits monochromatic light or white light. It is preferable that the film forming processing chamber is also arranged accordingly in the vapor deposition apparatus. For example, when forming three types of EL elements having different emission colors on a display panel, it is necessary to form a light emitting layer corresponding to each emission color. In this case, the film forming processing chamber 60570 is used for forming a film of the first light emitting layer, and the film forming processing chamber 60573 is used for forming a film of the second light emitting layer.
Can be used for film formation of the third light emitting layer. By separating the film forming processing chamber for each light emitting layer, mutual contamination by different light emitting materials can be prevented, and the throughput of the film forming processing can be improved.

Further, three types of EL materials having different emission colors may be sequentially vapor-deposited in the film-forming processing chamber 60570, the film-forming processing chamber 60573, and the film-forming processing chamber 60574. In this case, a shadow mask is used, and the mask is shifted according to the area to be vapor-deposited to perform the vapor deposition.

When forming an EL element that emits white light, light emitting layers having different emission colors are vertically stacked. Even in that case, the element substrate can sequentially move in the film forming processing chamber to form a film for each light emitting layer. Further, different light emitting layers can be continuously formed in the same film forming processing chamber.

In the film forming processing chamber 60576, an electrode is formed on the EL layer. Although an electron beam vapor deposition method or a sputtering method can be applied to the formation of the electrodes, it is preferable to use a resistance heating vapor deposition method.

The element substrate, which has been formed up to the electrode, passes through the intermediate processing chamber 60564 and then the sealing processing chamber 6056.
It is carried in to 5. The sealing processing chamber 60565 is filled with an inert gas such as helium, argon, neon, or nitrogen, and a sealing plate is attached to the side where the EL layer of the element substrate is formed in the atmosphere. Stop. In the sealed state, the element substrate and the sealing plate may be filled with an inert gas or may be filled with a resin material. The sealing processing chamber 60565 is provided with a dispenser for drawing a sealing material, mechanical elements such as a fixed stage and an arm for fixing the sealing plate facing the element substrate, a dispenser for filling a resin material, a spin coater, and the like. Has been done.

FIG. 97 shows the internal configuration of the film forming processing chamber. The film formation processing chamber is kept under reduced pressure, and FIG. 97
The inside of the room sandwiched between the top plate 60691 and the bottom plate 60692 is the room, which indicates the room kept in a decompressed state.

The treatment chamber is provided with one or more evaporation sources. This is because it is preferable to provide a plurality of evaporation sources when forming a plurality of layers having different compositions or when co-depositing different materials. In FIG. 97, the evaporation sources 60681a, 60681b, and 60681c are attached to the evaporation source holder 60680. The evaporation source holder 60680 is held by an articulated arm 60683. The articulated arm 60683 has an evaporation source holder 6 due to the expansion and contraction of the joints.
The position of 0680 can be freely moved within the movable range. In addition, the evaporation source holder 60
A distance sensor 60682 is provided on the 680, and the evaporation sources 60681a to 60681c and the substrate 60 are provided.
The interval from 689 may be monitored to control the optimum interval during vapor deposition. In that case, the articulated arm may be displaced in the vertical direction (Z direction) to the articulated arm.

The board stage 60686 and the board chuck 60687 are paired to fix the board 60689. The substrate stage 60686 may be configured to have a built-in heater so that the substrate 60689 can be heated. The substrate 60689 is fixed to the substrate stage 60686 and carried in and out by locking the substrate chuck 60687. At the time of vapor deposition, a shadow mask 60690 having an opening corresponding to the pattern to be vapor-deposited can also be used, if necessary. In that case, the shadow mask 60690 is the substrate 60689 and the evaporation sources 60681a-60681.
It should be placed between c. Shadow mask 60690 is mask chuck 60688
Therefore, it is in close contact with the substrate 60689 or fixed at a certain interval. When alignment of the shadow mask 60690 is required, a camera is placed in the processing chamber, and the mask chuck 60688 is provided with a positioning means for fine movement in the XY-θ direction to perform the alignment.

The evaporation source 60681 is provided with a vapor deposition material supply means for continuously supplying the vapor deposition material to the evaporation source. The thin-film deposition material supply means is a thin-film deposition material supply source 60685a, 60685b, 60685c arranged at a position distant from the evaporation source 60681, and a material supply pipe 6 connecting the two.
Has 0684. Typically, material sources 60685a, 60685b, 6068
5c is provided corresponding to the evaporation source 60681. In the case of FIG. 97, the material supply source 606
85a and 606 evaporation source 81a correspond. Material source 60685b and evaporation source 6068
The same applies to 1b, the material supply source 60685c and the evaporation source 60681c.

An air flow transfer method, an aerosol method, or the like can be applied to the supply method of the vapor-filmed material. In the air flow transfer method, fine powder of the vapor-film deposition material is carried on the air flow, and is carried to the evaporation source 60681 using an inert gas or the like. The aerosol method is a vapor deposition performed while transporting a raw material liquid in which a vapor-deposited material is dissolved or dispersed in a solvent, atomizing it with a sprayer, and vaporizing the solvent in the aerosol. In either case, the evaporation source 60681 is provided with a heating means, and the conveyed vapor deposition material is evaporated to form a film on the substrate 60689. In the case of FIG. 97, the material supply pipe 6068
Reference numeral 4 is composed of a thin tube that can be flexibly bent and has a rigidity that does not deform even under a reduced pressure state.

When the air flow transfer method or the aerosol method is applied, the film formation may be performed in the film formation processing chamber at atmospheric pressure or lower, preferably under a reduced pressure of 133 Pa to 13300 Pa.
The film forming chamber can be filled with an inert gas such as helium, argon, neon, krypton, xenon, or nitrogen, or the pressure can be adjusted while supplying (simultaneously exhausting) the gas. Further, in the film forming treatment chamber where the oxide film is formed, a gas such as oxygen or nitrous oxide may be introduced to create an oxidizing atmosphere. Further, a gas such as hydrogen may be introduced into the film forming processing chamber where the organic material is vapor-deposited to create a reducing atmosphere.

As another method of supplying the vapor-deposited material, a screw may be provided in the material supply pipe 60684 to continuously extrude the vapor-deposited material toward the evaporation source.

According to this thin-film deposition apparatus, even a large-screen display panel can be continuously formed with good uniformity. Further, since it is not necessary to replenish the vapor-deposited material each time the vapor-deposited material runs out in the evaporation source, the throughput can be improved.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 12)
In this embodiment, the pixel circuit of the display device and the driving method will be described.

First, a digital time gradation drive applicable to the present invention will be described. First, a driving method when the signal writing period (address period) and the light emitting period (sustaining period) to the pixels are separated will be described with reference to FIG. 98 (A). Here, a case of 4-bit digital time gradation will be described as an example.

The period for completely displaying the image for one display area is called one frame period. One frame period has a plurality of subframe periods, and one subframe period has an address period and a sustain period. The address periods Ta1 to Ta4 indicate the time required to write the signal to the pixels for all rows, and the periods Tb1 to Tb4 indicate the time required to write the signal to the pixels (or one pixel) for one row. Further, the sustain periods Ts1 to Ts4 indicate the time for maintaining the lighting or non-lighting state according to the video signal written to the pixel, and the ratio of the lengths is Ts1: Ts2: Ts3: Ts4 = 23: 22: 21 :. 20 = 8: 4: 2: 1. The gradation is expressed by which sustain period the light is emitted.

The operation will be described. First, in the address period Ta1, the pixel selection signal is input to the scanning line in order from the first line, and the pixel is selected. Then, when the pixel is selected, a video signal is input from the signal line to the pixel. Then, when a video signal is written to the pixel, the pixel holds the signal until the signal is input again. The written video signal controls lighting and non-lighting of each pixel during the sustain period Ts1. Similarly, a video signal is input to the pixels in the address periods Ta2, Ta3, and Ta4, and the lighting and non-lighting of each pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signal. Then, in each subframe period, the pixel is not lit during the address period, the sustain period starts after the address period ends, and the pixel in which the signal for lighting is written is lit.

Here, with reference to FIG. 98 (B), the pixel row on the i-th row will be described. First, in the address period Ta1, pixel selection signals are input to the scanning lines in order from the first line, and the address period T
In the period Tb1 (i) of a1, the pixel in the i-th row is selected. Then, when the pixel on the i-th row is selected, a video signal is input from the signal line to the pixel on the i-th row. and,
When a video signal is written to the pixel on the i-th row, the pixel on the i-th row holds the signal until the signal is input again. The written video signal controls the lighting and non-lighting of the pixel in the i-th row in the sustain period Ts1. Similarly, the address periods Ta2, Ta3, T
In a4, a video signal is input to the pixel in the i-th row, and the video signal controls lighting and non-lighting of the pixel in the i-th row in the sustain periods Ts2, Ts3, and Ts4. Then, in each subframe period, the pixel is not lit during the address period, the sustain period starts after the address period ends, and the pixel in which the signal for lighting is written is lit.

Although the case of expressing the 4-bit gradation has been described here, the number of bits and the number of gradations are not limited to this. Further, the order of lighting does not have to be Ts1, Ts2, Ts3, and Ts4, and may be random or may be divided into a plurality of pieces to emit light. Also, Ts1 and Ts2
, Ts3 and Ts4 need not be set to a power of 2, but may be set to the same length of lighting time, or may be slightly shifted from the power of 2.

Subsequently, a driving method when the signal writing period (address period) and the light emitting period (sustaining period) to the pixels are not separated will be described. That is, the pixel in the row in which the video signal writing operation is completed holds the signal until the next writing (or erasing) of the signal to the pixel. The period from the writing operation to the next writing of the signal to this pixel is called the data retention time. Then, during this data holding time, the pixels are turned on or off according to the video signal written to the pixels. The same operation is performed until the last line, and the address period ends. Then, the signal writing operation for the next subframe period is started in order from the line at which the data retention time ends.

In this way, in the case of a driving method in which the pixel is turned on or off according to the video signal written to the pixel immediately after the signal writing operation is completed and the data holding time is reached, the data holding time is attempted to be shorter than the address period. However, since signals cannot be input to two lines at the same time, the address periods must not overlap, so that the data retention time cannot be shortened. Therefore, as a result, it becomes difficult to perform high gradation display.

Therefore, by providing an erasure period, a data retention time shorter than the address period is set. A driving method in the case of setting an erasure period and setting a data retention time shorter than the address period will be described with reference to FIG. 99 (A).

First, in the address period Ta1, pixel scanning signals are input to the scanning lines in order from the first line.
Pixels are selected. Then, when the pixel is selected, a video signal is input from the signal line to the pixel. Then, when a video signal is written to the pixel, the pixel holds the signal until the signal is input again. Sustain period Ts1 by this written video signal
The lighting and non-lighting of each pixel in the above are controlled. In the line where the video signal writing operation is completed, the pixels are turned on or off according to the immediately written video signal. The same operation is performed up to the last line, and the address period Ta1 ends. Then, the signal writing operation for the next subframe period is started in order from the line at which the data retention time ends. Similarly, a video signal is input to the pixels in the address periods Ta2, Ta3, and Ta4, and the lighting and non-lighting of each pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signal. Then, the sustain period TS4 is set at the end by starting the erasing operation. This is because when the signal written to the pixel is erased at the erase time Te of each line, it is forced regardless of the video signal written to the pixel during the address period until the signal is written to the next pixel. This is because it is not lit. That is, the data holding time ends from the pixel in the row where the erasing time Te starts.

Here, with reference to FIG. 99B, the description will be made focusing on the pixel row of the i-th row. In the pixel row of the i-th row, in the address period Ta1, the pixel scanning signal is input to the scanning line in order from the first row, and the pixel is selected. Then, when the pixel in the i-th row is selected in the period Tb1 (i), the video signal is input to the pixel in the i-th row. Then, when the video signal is written to the pixel on the i-th row, the pixel on the i-th row holds the signal until the signal is input again. The written video signal controls lighting and non-lighting of the pixel on the i-th row in the sustain period Ts1 (i). That is, when the video signal writing operation is completed on the i-th line,
According to the video signal written immediately, the pixel on the i-th row is turned on or off. Similarly, a video signal is input to the pixel on the i-th row in the address periods Ta2, Ta3, and Ta4, and the video signal controls lighting and non-lighting of the pixel on the i-th row in the sustain periods Ts2, Ts3, and Ts4. Then, the sustain period Ts4 (i) is set by the start of the erasing operation at the end of the sustain period Ts4 (i). This is because the lighting is forcibly turned off regardless of the video signal written in the pixel of the i-th row at the erasing time Ts (i) of the i-th row. That is, when the erasing time Te (i) starts, the data holding time of the pixel in the i-th row ends.

Therefore, it is possible to provide a display device having a high gradation shorter than the address period and a high duty ratio (ratio of the lighting period in one frame period) without separating the address period and the sustain period. Further, since the instantaneous brightness can be lowered, the reliability of the display element can be improved.

Although the case of expressing the 4-bit gradation has been described here, the number of bits and the number of gradations are not limited to this. Further, the order of lighting does not have to be Ts1, Ts2, Ts3, and Ts4, and may be random or may be divided into a plurality of lights to emit light. Also, Ts1, Ts2,
The lighting time of Ts3 and Ts4 does not have to be a power of 2, but may be a lighting time of the same length, or may be slightly shifted from the power of 2.

Here, FIGS. 100 (A), (B), (C), (D) and (E) are shown with respect to the pixel configurations capable of digital time gradation drive described with reference to FIGS. 98 (A) and 99 (A). It will be explained with reference to. The display elements shown in FIGS. 100 (A), (B), (C), (D) and (E) are EL.
Elements (organic EL elements, inorganic EL elements or EL elements containing organic and inorganic substances), electron emitting elements, liquid crystal elements, electronic inks, grating light valves (GLV), digital micromirror devices (DMD), carbon nanotubes, etc. A display medium whose contrast changes due to magnetic action can be adapted. In addition, FIGS. 100 (A), (B), (
As the pixels shown in C), (D) and (E), self-luminous elements such as EL elements are suitable as display elements. Although FIGS. 100 (A), (B), (C), (D) and (E) show only one pixel, the pixel portion of the display device is formed in a matrix in the row direction and the column direction. Multiple pixels are arranged.

The pixel shown in FIG. 100A has a switching transistor 80301a, a driving transistor 80302a, and a capacitive element 80304a. In the switching transistor 80301a, the gate terminal is connected to the scanning line 80312a, the first terminal (source terminal or drain terminal) is connected to the signal line 80311a, and the second terminal (source terminal or drain terminal) is the driving transistor 80302a. It is connected to the gate terminal. Further, the second terminal of the switching transistor 80301a is a power line 8 via the capacitive element 80304a.
It is connected to 0313a. Further, the drive transistor 80302a has a first terminal connected to a power supply line 80313a and a second terminal connected to a first electrode of the display element 80320a. A low power supply potential is set in the second electrode 80321a of the display element 80320a. The low power potential is a potential that satisfies the low power potential <high power potential with reference to the high power potential set in the power line 80313a, and the low power potential is set to, for example, GND or 0V. Is also good. Display element 80320 shows the potential difference between this high power supply potential and low power supply potential.
Since the current is applied to the display element 80320a to cause the display element 80320a to emit light, the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80320a. Set the potential. The capacitive element 80304a can be omitted by substituting the gate capacitance of the driving transistor 80302a. Regarding the gate capacitance of the drive transistor 80302a, the capacitance may be formed in a region where the gate electrode overlaps with the source region, drain region, LDD region, etc., or the channel region and the gate electrode may be formed. A capacitance may be formed between the and.

When the pixel is selected by the scanning line 80312a, that is, the switching transistor 8
When 0301a is on, a video signal is input to the pixels from the signal line 80311a. Then, the electric charge corresponding to the voltage corresponding to the video signal is accumulated in the capacitive element 80304a, and the electric charge is accumulated in the capacitive element 80304a.
The capacitive element 80304a holds the voltage. This voltage is the drive transistor 80302
It is the voltage between the gate terminal and the first terminal of a, and corresponds to the gate-source voltage Vgs of the driving transistor 80302a.

In general, the operating region of a transistor can be divided into a linear region and a saturated region. The boundary is when (Vgs-Vth) = Vds, where Vds is the voltage between the drain and source, Vgs is the voltage between the gate and source, and Vth is the threshold voltage. (Vgs-Vth)> Vds
In the case of, it is a linear region, and the current value is determined by the magnitudes of Vds and Vgs. on the other hand,(
When Vgs-Vth) <Vds, it becomes a saturated region, and ideally, even if Vds changes,
The current value is almost the same. That is, the current value is determined only by the magnitude of Vgs.

Here, in the case of the voltage input voltage drive method, a video signal is input to the gate terminal of the drive transistor 80302a so that the drive transistor 80302a is sufficiently turned on or off. .. That is, the driving transistor 80302a is operated in the linear region.

Therefore, when the drive transistor 80302a is a video signal to be turned on, ideally, the power potential Vdd set in the power line 80313a is displayed as it is in the display element 80320.
It is set to the first electrode of a.

That is, ideally, the voltage applied to the display element 80320a is made constant, and the display element 8032 is used.
Make the brightness obtained from 0a constant. Then, a plurality of subframe periods are provided within one frame period, a video signal is written to the pixels for each subframe period, lighting or non-lighting of the pixels is controlled for each subframe period, and the lighting is performed. The gradation is expressed by the total of the subframe periods.

Next, the pixel configuration of FIG. 100 (B) will be described. The pixels shown in FIG. 100B are a switching transistor 80301a, a driving transistor 80302a, and a rectifying element 803.
It has 06a, a capacitance element 80304a, and a display element 80320b. In the switching transistor 80301b, the gate terminal is connected to the first scanning line 80312b, the first terminal (source terminal or drain terminal) is connected to the signal line 80311b, and the second terminal (source terminal or drain terminal) is for driving. It is connected to the gate terminal of the transistor 80302b. Further, the gate terminal of the driving transistor 80302 is connected to the second scanning line 80313b via the rectifying element 80306a. Further, the switching transistor 80
The second terminal of 301b is connected to the power supply line 80313b via the capacitive element 80304b. Further, the drive transistor 80302b has a first terminal connected to a power supply line 80313b and a second terminal connected to a first electrode of the display element 80320b. Display element 8032
A low power supply potential is set in the second electrode 80321b of 0b. The low power potential is a potential that satisfies the low power potential <high power potential with reference to the high power potential set in the power line 80313b, and the low power potential is set to, for example, GND or 0V. Is also good.
The potential difference between the high power supply potential and the low power supply potential is applied to the display element 80320b, and the display element 8 is used.
In order to cause the display element 80320b to emit light by passing a current through 0320b, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80320b. The capacitive element 80304b can be omitted by substituting the gate capacitance of the driving transistor 80302b. Regarding the gate capacitance of the drive transistor 80302b, the capacitance may be formed in a region where the gate electrode overlaps with the source region, drain region, LDD region, etc., or the channel region and the gate electrode may be formed. A capacitance may be formed between the and.

In this pixel configuration, the pixel of FIG. 100 (A) has a rectifying element 80306a and a second scanning line 8031.
3b is added. Therefore, the switching transistor 80301b, the driving transistor 80302b, the capacitive element 80304b, the signal line 80311b, the first scanning line 80312b, and the power supply line 80313b are each switching transistor 80301.
a, it corresponds to the driving transistor 80302a, the capacitive element 80304a, the signal line 80311a, the scanning line 80312a, and the power supply line 80313a, and the writing operation and the light emitting operation are the same, so the description thereof is omitted here.

The erasing operation will be described. At the time of erasing operation, an H level signal is input to the second scanning line 80313b. Then, a current flows through the rectifying element 80306a, and the gate potential of the driving transistor 80302b held by the capacitive element 80304b can be set to a certain potential. That is, the potential of the gate terminal of the drive transistor 80302b is set to a certain potential, and the drive transistor 80302 is set regardless of the video signal written to the pixel.
b can be forcibly turned off.

The L-level signal input to the second scanning line 80313b has a potential such that no current flows through the rectifying element 80306a when a video signal that is not lit is written in the pixel. Further, the H level signal input to the second scanning line 80313b is a potential at which the potential at which the driving transistor 80302b is turned off can be set at the gate terminal regardless of the video signal written in the pixel. And.

A diode-connected transistor can be used for the rectifying element 80306a. Further, in addition to the diode-connected transistor, a PN-junction or PIN-junction diode, a Schottky-type diode, a diode formed of carbon nanotubes, or the like may be used. FIG. 100 (C) shows a case where an N-channel transistor connected by a diode is applied. The first terminal (source terminal or drain terminal) of the diode connection transistor 80303c is connected to the gate terminal of the drive transistor 80302c. again,
The second terminal (source terminal or drain terminal) of the diode connection transistor 80303c is connected to the gate terminal and is connected to the second scanning line 80313c. Then, when the second scanning line 80313c is at the L level, the diode connection transistor 80303c is connected to the gate terminal and the source terminal, so that no current flows, but the second scanning line 80313
When an H level signal is input to c, the second terminal of the diode connection transistor 80303c becomes a drain terminal, so that a current flows through the diode connection transistor 80303c.
Therefore, the diode connection transistor 80303c exerts a rectifying action.

The switching transistor 80301c, the driving transistor 80302c, the capacitive element 80304c, the signal line 80311c, the first scanning line 80312c, and the power supply line 8031.
3c is a switching transistor 80301a, a driving transistor 80302a, a capacitive element 80304a, a signal line 80311a, and a scanning line 8031, respectively, of FIG. 100A.
2a corresponds to the power line 80313a. Further, the second scanning line 80312c is shown in FIG. 100 (
It corresponds to the second scanning line 80312d of B).

Further, when a diode-connected P-channel transistor is applied, it is shown in FIG. 100 (D). The first terminal (source terminal or drain terminal) of the diode connection transistor 80303d is connected to the second scanning line 80313d. Also, the diode connection transistor 803
The second terminal (source terminal or drain terminal) of 03d is connected to the gate terminal, and is also connected to the gate terminal of the driving transistor 80302d. Then, the second scanning line 8031
When 3d is L level, current does not flow in the diode connection transistor 80303d because the gate terminal and the source terminal are connected, but when an H level signal is input to the second scanning line 80313d, the diode connection transistor 80303d becomes the first. Since the two terminals are drain terminals, a current flows through the diode connection transistor 80303d. Therefore, the diode connection transistor 80303d exerts a rectifying action.

The switching transistor 80301d, the driving transistor 80302d, the capacitive element 80304d, the signal line 80311d, the first scanning line 80312d, and the power supply line 8031.
3d is a switching transistor 80301a, a driving transistor 80302a, a capacitive element 80304a, a signal line 80311a, and a scanning line 8031, respectively, of FIG. 100A.
2a corresponds to the power line 80313a. Further, the second scanning line 80312d is shown in FIG. 100 (
It corresponds to the second scanning line 80312d of B).

Further, an erasing transistor may be provided to erase the signal written to the pixel.
The pixel shown in FIG. 100 (E) is the pixel of FIG. 100 (A) and the erasing transistor 80303e.
And a second scanning line 80312e are added. Therefore, the switching transistor 80301e, the driving transistor 80302e, the capacitive element 80304e, and the signal line 80
311e, the first scanning line 80312e, and the power supply line 80313e are shown in FIG. 100 (A), respectively.
Corresponds to the switching transistor 80301a, the driving transistor 80302a, the capacitive element 80304a, the signal line 80311a, the scanning line 80312a, and the power supply line 80313a, and the writing operation and the light emitting operation are the same, and thus the description thereof will be omitted here.

The erasing operation will be described. At the time of erasing operation, an H level signal is input to the second scanning line 80312e. Then, the erasing transistor 80303e is turned on, and the gate terminal and the first terminal of the driving transistor 80302e can be set to the same potential. That is, the voltage between the gate and the source of the drive transistor 80302e can be set to 0V. It is desirable that the H level potential of the second scanning line 80312e is higher than the potential of the power supply line 80313e by the threshold voltage Vth or more of the erasing transistor 80303e. In this way, the driving transistor 80302e can be forcibly turned off.

Subsequently, an example of the threshold voltage correction type pixel circuit and the driving method applicable to the present invention will be described with reference to FIG. 101 (A).

The pixels shown in FIG. 101 (A) are a driving transistor 80400 and a first switch 8040.
1. Second switch 80402, third switch 80403, first capacitive element 80404
, A second capacitive element 80405 and a display element 80420. In the drive transistor 80400, the gate terminal is connected to the signal line 80411 via the first capacitive element 80404 and the first switch 80401 in order, the first terminal is connected to the power supply line 80412, and the second terminal is connected.
The terminal is connected to the first electrode of the display element 80420 via the third switch 80403. Further, the gate terminal of the drive transistor 80400 is a second capacitive element 80405.
It is connected to the power line 80412 via. Further, the gate terminal of the drive transistor 80400 is connected to the second terminal of the drive transistor 80400 via the second switch 80402. Further, a low power supply potential is set on the second electrode 80421 of the display element 80420. The low power supply potential is a potential that satisfies the low power supply potential <high power supply potential with reference to the high power supply potential set in the power supply line 80412, and the low power supply potential is, for example, GND.
, 0V and the like may be set. Since the potential difference between the high power supply potential and the low power supply potential is applied to the display element 80420 and a current is passed through the display element 80420 to cause the display element 80420 to emit light, the potential difference between the high power supply potential and the low power supply potential is the display element 80420. Set each potential so that it is equal to or higher than the forward threshold voltage of. The second capacitive element 80405 can be omitted by substituting the gate capacitance of the driving transistor 80400. Regarding the gate capacitance of the drive transistor 80400, the capacitance may be formed in a region where the gate electrode overlaps with the source region, drain region, LDD region, etc., or the channel region and the gate electrode may be formed. A capacitance may be formed between the and. The first switch 80401, the second switch 80402, and the third switch 80403 are turned on and off by the first scanning line 80413, the second scanning line 80414, and the third scanning line 80414, respectively. ..

The pixel driving method shown in FIG. 101 (A) can be divided into an initialization period, a data writing period, a threshold value acquisition period, and a light emitting period.

During the initialization period, the second switch 80402 and the third switch 80403 are turned on.
The potential of the gate terminal of the drive transistor 80400 is at least lower than the potential of the power line 80412. At this time, the first switch 80401 may be turned on or off. The initialization period is not always necessary.

During the threshold acquisition period, pixels are selected by the first scan line 80413. That is, the first switch 80401 is turned on, and a certain constant voltage is input from the signal line 80411. At this time, the second switch 80402 is turned on, and the driving transistor 80400 is diode-connected. Also, the third switch 80403 is off. Therefore, the potential of the gate terminal of the drive transistor 80400 is a value obtained by subtracting the threshold voltage of the drive transistor 80400 from the potential of the power supply line 80412. The threshold voltage of the driving transistor 80400 is held in the first capacitive element 80404. Further, the second capacitive element 8
In 0405, the potential difference between the potential of the gate terminal of the driving transistor 80400 and the constant voltage input from the signal line 80411 is maintained.

During the data writing period, a video signal (voltage) is input from the signal line 80411. At this time, the first switch 80401 remains on, the second switch 80402 turns off, and the second switch 80402 remains off. In addition, the driving transistor 8040
The gate terminal of 0 is in a floating state. Therefore, the potential of the gate terminal of the drive transistor 80400 changes according to the potential difference between the constant voltage input to the signal line 80411 during the threshold acquisition period and the video signal input to the signal line 80411 during the data writing period. .. For example, if the capacitance value of the first capacitance element 80404 << the capacitance value of the second capacitance element 80405, the potential of the gate terminal of the drive transistor 80400 during the data writing period is the signal line 80411 during the threshold acquisition period. The potential difference between the input constant voltage and the video signal input to the signal line 80411 during the data writing period is set to the power supply line 804.
It is approximately equal to the value obtained by adding the value obtained by subtracting the threshold voltage of the drive transistor 80400 from the potential of 12. That is, the potential of the gate terminal of the drive transistor 80400 is a potential corrected for the threshold voltage of the drive transistor 80400.

During the light emission period, a current corresponding to the potential difference (Vgs) between the potential of the gate terminal of the driving transistor 80400 and the power supply line 80412 flows through the display element 80420. At this time, the first switch 80401 is turned off, the second switch 80402 remains off, and the third switch 80403 is turned on. The current flowing through the display element 80420 is constant regardless of the threshold voltage of the driving transistor 80400.

The pixel configuration shown in FIG. 101 (A) is not limited to FIG. 101 (A). For example, FIG.
A switch, a resistance element, a capacitive element, a transistor, a logic circuit, or the like may be newly added to the pixel shown in 01 (A). Further, for example, the second switch 80402 is composed of a P-channel transistor or an N-channel transistor, the third switch 80403 is composed of a transistor having a polarity different from that of the second switch 80402, and the second switch 80402 is configured. And the third switch 80403 may be controlled by the same scanning line.

Subsequently, FIG. 10 shows an example of a current input type pixel circuit and a driving method applicable to the present invention.
This will be described with reference to 1 (B).

The pixels shown in FIG. 101B are the driving transistor 80430 and the first switch 8043.
1. It has a second switch 80432, a third switch 80433, a capacitance element 80434, and a display element 80450. In the drive transistor 80430, the gate terminal is connected to the signal line 80441 via the second switch 80432 and the first switch 80431 in order, the first terminal is connected to the power supply line 80442, and the second terminal is the third. It is connected to the first electrode of the display element 80450 via the switch 80433. Further, the gate terminal of the drive transistor 80430 is connected to the power line 80442 via the capacitive element 80434. Further, the gate terminal of the drive transistor 80430 is connected to the second terminal of the drive transistor 80430 via the second switch 80432. In addition, the display element 804
A low power potential is set in the second electrode 80451 of 50. The low power potential is
The low power potential <the potential satisfying the high power potential with reference to the high power potential set in the power line 80442, and the low power potential may be set to, for example, GND, 0V or the like. The potential difference between the high power supply potential and the low power supply potential is applied to the display element 80450 to display the display element 8045.
In order to make the display element 80450 emit light by passing a current through 0, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is equal to or higher than the forward threshold voltage of the display element 80450. The capacitive element 80434 can be omitted by substituting the gate capacitance of the driving transistor 80430. Regarding the gate capacitance of the drive transistor 80430,
The capacitance may be formed in a region where the gate electrode overlaps and overlaps with the source region, drain region, LDD region, etc., or the capacitance is formed between the channel region and the gate electrode. May be good. The first switch 80431 and the second switch 804
32, the third switch 80433 has the first scanning line 80443 and the second scanning line 8, respectively.
On / off is controlled by 0444 and the third scanning line 80454.

The pixel driving method shown in FIG. 101B can be divided into a data writing period and a light emitting period.

During the data writing period, pixels are selected by the first scan line 80443. in short,
The first switch 80431 is turned on, and a current is input as a video signal from the signal line 80431. At this time, the second switch 80432 is turned on and the third switch 80433 is turned off. Therefore, the potential of the gate terminal of the driving transistor 80430 becomes the potential corresponding to the video signal. That is, the capacitive element 80434 has a drive transistor 80430.
The gate-source voltage of the drive transistor 80430 is maintained so that the same current as the video signal is passed.

Next, during the light emission period, the first switch 80431 and the second switch 80432 are turned off, and the third switch 80433 is turned on. Therefore, a current having the same value as the video signal flows through the display element 80450.

The pixel configuration shown in FIG. 101 (B) is not limited to FIG. 101 (B). For example, FIG.
A switch, a resistance element, a capacitive element, a transistor, a logic circuit, or the like may be newly added to the pixel shown in 01 (B). Further, for example, the first switch 80431 is composed of a P-channel transistor or an N-channel transistor, the second switch 80432 is composed of a transistor having the same polarity as the first switch 80431, and the first switch 80431 and the first switch 80431 are configured. Switch 80432 of 2 may be controlled by the same scanning line. Also, the second switch 8043
2 may be arranged between the gate terminal of the drive transistor 80430 and the signal line 80431.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 13)
In the present embodiment, a method for manufacturing a semiconductor device when the semiconductor device to which the present invention can be applied has a thin film transistor (TFT) as an element will be described with reference to the drawings.

FIG. 102 is a diagram showing an example of a TFT structure and manufacturing process that a semiconductor device to which the present invention can be applied can have. FIG. 102 (A) is a diagram showing an example of a TFT structure that a semiconductor device to which the present invention can be applied can have. Further, FIGS. 102 (B) to 102 (G) are views showing an example of a TFT manufacturing process that can be possessed by a semiconductor device to which the present invention can be applied.

The structure and manufacturing process of the TFT that can be possessed by the semiconductor device to which the present invention can be applied are not limited to those shown in FIG. 102, and various structures and manufacturing processes can be used.

First, referring to FIG. 102 (A), a T that can be possessed by a semiconductor device to which the present invention can be applied.
An example of the structure of the FT will be described. FIG. 102 (A) is a cross-sectional view of a TFT having a plurality of different structures. Here, in FIG. 102 (A), TFTs having a plurality of different structures are shown side by side, which can be possessed by a semiconductor device to which the invention can be applied.
It is an expression for explaining the structure of T, and the TFTs that the semiconductor device to which the invention can be applied do not need to be juxtaposed as shown in FIG. 102 (A), and are made separately as needed. be able to.

Next, the features of each layer constituting the TFT that can be possessed by the semiconductor device to which the present invention can be applied will be described.

As the substrate 110111, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, a ceramic substrate, a metal substrate containing stainless steel, or the like can be used. In addition, polyethylene terephthalate (PET) and polyethylene naphthalate (P)
It is also possible to use a substrate made of a flexible synthetic resin such as plastic or acrylic represented by EN) and polyether sulfone (PES). By using a flexible substrate, it becomes possible to manufacture a semiconductor device that can be bent. Further, as long as the substrate has flexibility, there are no major restrictions on the area of the substrate and the shape of the substrate. Therefore, as the substrate 110111, for example, a substrate having a side of 1 meter or more and having a rectangular shape may be used. , Productivity can be significantly improved. Such an advantage is a great advantage as compared with the case of using a circular silicon substrate.

The insulating film 110112 functions as a base film. It is provided from the substrate 110111 in order to prevent an alkali metal such as Na or an alkaline earth metal from adversely affecting the characteristics of the semiconductor element. The insulating film 110112 includes an insulating film having oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide (SiOxNy) (x> y), silicon nitride (SiNxOy) (x> y). It can be provided with a single-layer structure or a laminated structure thereof.
For example, when the insulating film 110112 is provided in a two-layer structure, it is preferable to provide a silicon nitride film as the first insulating film and a silicon oxide film as the second insulating film. In addition, the insulating film 110
When the 112 is provided in a three-layer structure, a silicon oxide film is provided as the first insulating film, a silicon nitride film is provided as the second insulating film, and a silicon oxide film is provided as the third insulating film. It is good.

The semiconductor films 110113, 110114, 110115 can be formed of an amorphous semiconductor or a semi-amorphous semiconductor (SAS). Alternatively, a polycrystalline semiconductor film may be used. SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state stable in free energy, and has short-range order and a lattice. It contains a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the region in the film, and when silicon is the main component, the Raman spectrum shifts to the lower wavenumber side than 520 cm ^-1 . There is. In X-ray diffraction, diffraction peaks (111) and (220), which are said to be derived from the silicon crystal lattice, are observed. Unbonded hands (
The end of the dangling bond) contains at least 1 atomic% or more of hydrogen or halogen. SAS is formed by glow discharge decomposition (plasma CVD) of a gas containing silicified wood. Gases containing silicification include SiH ₄ , Si ₂ H ₆ and SiH ₂ Cl ₂ .
, SiHCl ₃ , _{SiC4, SiF 4 ,} and the like can be used. Or Ge
_F4 may be mixed. The gas containing this silicification is H ₂ , or H ₂ and He, Ar, Kr.
, Ne may be diluted with one or more rare gas elements selected from Ne. Dilution rate is 2 to 10
00 times range. The pressure is approximately in the range of 0.1 Pa to 133 Pa, and the power frequency is 1 MHz to 12
0 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature may be 300 ° C. or lower. Impurities of atmospheric components such as oxygen, nitrogen, ^and carbon as impurity elements in the membrane are 1 x 10 ²⁰ cm-
It is preferably ¹ or less, and in particular, the oxygen concentration is 5 × 10 ¹⁹ / cm ³ or less, preferably 1 × 10 ¹⁹ / cm ³ or less. Here, known means (spatter method, LPCVD method,
A material containing silicon (Si) as a main component (for example, SixGe) using a plasma CVD method or the like).
An amorphous semiconductor film is formed by 1-x, etc.), and the amorphous semiconductor film is subjected to a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, and a thermal crystal using a metal element that promotes crystallization. Crystallize by a known crystallization method such as a crystallization method.

The insulating film 110116 includes silicon oxide (SiOx), silicon nitride (SiNx), and silicon nitride (silicon oxide).
It can be provided by a single-layer structure of an insulating film having oxygen or nitrogen such as SiOxNy) (x> y) and silicon nitride (SiNxOy) (x> y), or a laminated structure thereof.

The gate electrode 110117 may have a single-layer conductive film or a laminated structure of two-layer or three-layer conductive film. A known conductive film can be used as the material of the gate electrode 110117. For example, a single film of an element such as tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si), or a nitrided film of the element (typically). Tantalum nitride film, tungsten nitride film, titanium nitride film), alloy film combining the above elements (typically Mo-W alloy, Mo-Ta alloy), or silicide film of the element (typically). Tungsten silicide film, titanium silicide film) and the like can be used. The above-mentioned single film, nitride film, alloy film, silicide film and the like may be used as a single layer or may be used in a laminated manner.

The insulating film 110118 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide (SiOxNy) (x> y), by a known means (spatter method, plasma CVD method, etc.).
An insulating film having oxygen or nitrogen such as silicon nitride (SiNxOy) (x> y) or DLC (
It can be provided by a single-layer structure of a carbon-containing film such as diamond-like carbon) or a laminated structure thereof.

The insulating film 110119 is made of a siloxane resin, silicon oxide (SiOx), or silicon nitride (S).
iNx), Silicon Nitride (SiOxNy) (x> y), Silicon Nitride (SiNxOy) (
An insulating film having oxygen or nitrogen such as x> y), a film containing carbon such as DLC (diamond-like carbon), or an epoxy, polyimide, polyamide, polyvinylphenol,
It can be provided in a single layer or laminated structure made of an organic material such as benzocyclobutene or acrylic. The siloxane resin corresponds to a resin containing a Si—O—Si bond. The skeleton structure of siloxane is composed of the bonds between silicon (Si) and oxygen (O). As the substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as the substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as the substituent. In the semiconductor device applicable to the present invention, it is also possible to directly provide the insulating film 110119 so as to cover the gate electrode 110117 without providing the insulating film 110118.

The conductive film 110123 has Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, and M.
A simple substance film of an element such as n, a nitride film of the element, an alloy film in which the elements are combined, a silicide film of the element, or the like can be used. For example, as the alloy containing a plurality of the elements, an Al alloy containing C and Ti, an Al alloy containing Ni, an Al alloy containing C and Ni, an Al alloy containing C and Mn, and the like can be used. Further, when the structure is provided in a laminated structure, the structure may be such that Al is sandwiched between Mo or Ti. By doing so, the resistance of Al to heat and chemical reaction can be improved.

Next, with reference to the cross-sectional view of the TFT having a plurality of different structures shown in FIG. 102 (A).
The features of each structure will be described.

Since 110101 is a single-drain TFT and can be manufactured by a simple method, it has the advantages of low manufacturing cost and high yield. Here, the semiconductor film 110113, 1
In 10115, the concentration of impurities is different, and the semiconductor film 110113 is in the channel region.
The semiconductor film 110115 is used as a source region and a drain region. By controlling the amount of impurities in this way, the resistivity of the semiconductor film can be controlled. Further, the semiconductor film and the conductive film 11
The electrical connection with 0123 can be brought closer to ohmic connection. As a method for producing semiconductor films having different amounts of impurities, a method of doping the semiconductor film with impurities using the gate electrode 110117 as a mask can be used.

The 110102 is a TFT having a taper angle of a certain value or more on the gate electrode 110117, and can be manufactured by a simple method, so that there are advantages that the manufacturing cost is low and the yield can be high. Here, the semiconductor films 110113, 110114, and 110115 have different impurity concentrations, the semiconductor film 110113 is a channel region, the semiconductor film 110114 is a low concentration drain (LDD) region, and the semiconductor film 110115.
Is used as the source area and drain area. By controlling the amount of impurities in this way, the resistivity of the semiconductor film can be controlled. Further, the electrical connection state between the semiconductor film and the conductive film 110123 can be brought close to that of ohmic connection. In addition, because it has an LDD area,
It is difficult for a high electric field to be applied to the inside of the TFT, and deterioration of the element due to hot carriers can be suppressed. As a method for forming semiconductor films having different amounts of impurities, the gate electrode 11 is used.
A method of doping impurities in the semiconductor film using 0117 as a mask can be used.
In 110102, since the gate electrode 110117 has a taper angle of a certain value or more, it is possible to give a gradient to the concentration of impurities that pass through the gate electrode 110117 and are doped into the semiconductor film, and the LDD region can be easily formed. Can be formed.

Reference numeral 110103 is a TFT in which the gate electrode 110117 is composed of at least two layers, and the lower gate electrode has a shape longer than that of the upper gate electrode. Since the shape of the gate electrode 110117 is composed of two layers and the lower gate electrode has a longer shape than the upper gate electrode, the LDD region can be formed without adding a photomask. A structure in which the LDD region overlaps with the gate electrode 110117, such as 110103, is used.
In particular, it is called a GOLD structure (Gate Overlapped LDD). As a method in which the shape of the gate electrode 110117 is composed of two layers and the shape of the lower gate electrode is longer than that of the upper gate electrode, the following method may be used.

First, when patterning the gate electrode 110117, the lower gate electrode and the upper gate electrode are etched by dry etching to form a shape having an inclination (taper) on the side surface. Subsequently, it is processed by anisotropic etching so that the inclination of the upper gate electrode becomes close to vertical. As a result, a gate electrode having a cross-sectional shape in which the lower gate electrode is longer than the upper gate electrode is formed. Then, by doping the impurity element twice, the semiconductor film 110113 used as the channel region and the semiconductor film 1 used as the LDD region are used.
A semiconductor film 110115 used as 10114, a source electrode and a drain electrode is formed.

The LDD region overlapping the gate electrode 110117 is the Lov region, and the gate electrode 11
The LDD region that does not overlap with 0117 is referred to as a Loff region. Here, Lof
The f region has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field near the drain to prevent deterioration of the on-current value due to hot carriers. On the other hand, the Lov region relaxes the electric field in the vicinity of the drain and is effective in preventing deterioration of the on-current value, but the effect of suppressing the off-current value is low. Therefore, it is preferable to manufacture a TFT having a structure according to the required characteristics for each of various circuits. For example, when a semiconductor device applicable to the present invention is used as a display device, it is preferable to use a TFT having a Loff region as the pixel TFT in order to suppress the off-current value.
On the other hand, as the TFT in the peripheral circuit, it is preferable to use a TFT having a Lov region in order to relax the electric field in the vicinity of the drain and prevent deterioration of the on-current value.

The 110104 is in contact with the side surface of the gate electrode 110117, and the sidewall 110121 is in contact with the side surface.
It is a TFT having. By having the sidewall 110121, the region overlapping the sidewall 110121 can be set as the LDD region.

In 110105, LDD (Lof) is obtained by doping a semiconductor film with a mask.
f) A TFT that forms a region. By doing so, the LDD region can be reliably formed, and the off-current value of the TFT can be reduced.

110106 is LDD (Lov) by doping the semiconductor film with a mask.
) It is a TFT that forms a region. By doing so, the LDD region can be reliably formed, the electric field in the vicinity of the drain of the TFT can be relaxed, and the deterioration of the on-current value can be reduced.

Next, with reference to FIGS. 102 (B) to (G), an example of a TFT manufacturing process that can be possessed by a semiconductor device to which the present invention can be applied will be described.
The structure and manufacturing process of the TFT that can be possessed by the semiconductor device to which the present invention can be applied are not limited to those shown in FIG. 102, and various structures and manufacturing processes can be used.

In the present embodiment, the insulating film 1 is on the surface of the substrate 110111, on the surface of the insulating film 110112, on the surface of the semiconductor film 110113, on the surface of 110114, and on the surface of 110115.
The semiconductor film or insulating film can be oxidized or nitrided by oxidizing or nitriding the surface of 10116, the surface of the insulating film 110118, or the surface of the insulating film 110119 using plasma treatment. In this way, the surface of the semiconductor film or the insulating film is modified by oxidizing or nitriding the semiconductor film or the insulating film using plasma treatment, and C.
Since a denser insulating film can be formed as compared with the insulating film formed by the VD method or the sputtering method, it is possible to suppress defects such as pinholes and improve the characteristics of the semiconductor device.

First, the surface of the substrate 110111 is washed with hydrofluoric acid (HF), alkali or pure water. As the substrate 110111, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, a ceramic substrate, a metal substrate containing stainless steel, or the like can be used. In addition, polyethylene terephthalate (PET) and polyethylene naphthalate (
It is also possible to use a substrate made of a plastic typified by PEN), a polyether sulfone (PES), or a synthetic resin having flexibility such as acrylic. Here, a case where a glass substrate is used as the substrate 110111 is shown.

Here, an oxide film or a nitride film may be formed on the surface of the substrate 110111 by oxidizing or nitriding the surface of the substrate 110111 by performing plasma treatment on the surface of the substrate 110111 (FIG. 102 (B)). .. An insulating film such as an oxide film or a nitride film formed by subjecting the surface to plasma treatment is also referred to as a plasma treatment insulating film below. In FIG. 102 (B), the insulating film 131 is a plasma-treated insulating film. Generally, when a semiconductor element such as a thin film film is provided on a substrate such as glass or plastic, an impurity element such as an alkali metal or an alkaline earth metal such as Na contained in glass or plastic is mixed in the semiconductor element. Contamination may affect the characteristics of the semiconductor element. However, by nitriding the surface of a substrate made of glass, plastic, or the like, it is possible to prevent impurity elements such as alkali metal or alkaline earth metal contained in the substrate from being mixed into the semiconductor element.

When the surface is oxidized by plasma treatment, it is under an oxygen atmosphere (for example, oxygen (O ₂ ).
) And noble gas (including at least one of He, Ne, Ar, Kr, Xe), oxygen and hydrogen (H ₂ ) and noble gas atmosphere, or dinitrogen monoxide and noble gas atmosphere. ) Performs plasma processing. On the other hand, when the semiconductor film is nitrided by plasma treatment, it is under a nitrogen atmosphere (for example, a nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, Xe) atmosphere) or. Perform plasma treatment in a nitrogen, hydrogen, and noble gas atmosphere, or in an _NH3 and noble gas atmosphere). As the noble gas, for example, Ar can be used. Alternatively, a gas in which Ar and Kr are mixed may be used. Therefore, the plasma-treated insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment. For example, when Ar is used, Ar is contained in the plasma-treated insulating film.

In the plasma treatment, the electron density is 1 × 10 ¹¹ cm ^-3 in the atmosphere of the gas.
It is 1 × 10 ¹³ cm ^-3 or less, and the electron temperature of plasma is 0.5 ev or more and 1.5 ev.
It is preferable to carry out the following. Since the electron density of the plasma is high and the electron temperature in the vicinity of the object to be processed is low, damage to the object to be processed by the plasma can be prevented. Further, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ^-3 or more, the oxide or nitride film formed by oxidizing or nitriding the irradiated object by using plasma treatment is C.
Compared with the film formed by the VD method, the sputtering method, or the like, the film thickness and the like are excellent in uniformity, and a dense film can be formed. Alternatively, since the electron temperature of the plasma is as low as 1 eV or less, the oxidation or nitriding treatment can be performed at a lower temperature as compared with the conventional plasma treatment or thermal oxidation method. For example, even if the plasma treatment is performed at a temperature 100 degrees or more lower than the strain point temperature of the glass substrate, the oxidation or nitriding treatment can be sufficiently performed. As the frequency for forming the plasma, a high frequency such as a microwave (2.45 GHz) can be used. Unless otherwise specified below, the plasma treatment shall be performed using the above conditions.

Although FIG. 102 (B) shows a case where a plasma-treated insulating film is formed by plasma-treating the surface of the substrate 110111, the present embodiment shows the case where the substrate 1101 is formed.
The case where the plasma-treated insulating film is not formed on the surface of No. 11 is also included.

Although the plasma-treated insulating film formed by plasma-treating the surface of the object to be treated is not shown in FIGS. 102 (C) to 102 (G), in the present embodiment, the substrate 1 is not shown.
10111, insulating film 110112, semiconductor film 110113, 110114, 110115
, The case where a plasma-treated insulating film formed by performing plasma treatment is present on the surface of the insulating film 110116, the insulating film 110118, or the insulating film 110119 is also included.

Next, the insulating film 110112 is formed on the substrate 110111 by using known means (sputtering method, LPCVD method, plasma CVD method, etc.) (FIG. 102 (C)). As the insulating film 110112, silicon oxide (SiOx) or silicon nitride (SiOxNy) (x> y) can be used.

Here, the plasma-treated insulating film may be formed on the surface of the insulating film 110112 by subjecting the surface of the insulating film 110112 to plasma treatment and oxidizing or nitriding the insulating film 110112. By oxidizing the surface of the insulating film 110112, the surface of the insulating film 110112 can be modified to obtain a dense film having few defects such as pinholes. In addition, the insulating film 110
By oxidizing the surface of 112, a plasma-treated insulating film having a low N atom content can be formed. Therefore, when a semiconductor film is provided in the plasma-treated insulating film, the interface characteristics between the plasma-treated insulating film and the semiconductor film are improved. improves. Further, the plasma-treated insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment. note that,
The plasma treatment can be carried out in the same manner under the above-mentioned conditions.

Next, the island-shaped semiconductor films 110113 and 110114 are formed on the insulating film 110112 (.
FIG. 102 (D). The island-shaped semiconductor films 110113 and 110114 have an insulating film 110112.
Silicon (sputtering method, LPCVD method, plasma CVD method, etc.) using the above known means (sputtering method, LPCVD method, plasma CVD method, etc.)
An amorphous semiconductor film is formed using a material containing Si) as a main component (for example, Si _x Ge _1-x , etc.), the amorphous semiconductor film is crystallized, and the semiconductor film is selectively etched. It can be provided by. The crystallization of the amorphous semiconductor film includes a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or a method in which these methods are combined. It can be carried out by the known crystallization method of. Here, the end portion of the island-shaped semiconductor film is provided in a shape close to a right angle (θ = 85 to 100 °).
Alternatively, the semiconductor film 110114, which is a low-concentration drain region, may be formed by doping impurities with a mask.

Here, the surfaces of the semiconductor films 110113 and 110114 are subjected to plasma treatment, and the semiconductor film 1 is subjected to plasma treatment.
By oxidizing or nitriding the surface of 10113, 110114, the semiconductor film 1101
A plasma-treated insulating film may be formed on the surface of 13, 110114. For example, semiconductor film 1
When Si is used as the 10113 and 110114, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the plasma-treated insulating film. Alternatively, the semiconductor films 110113 and 110114 may be oxidized by plasma treatment and then nitrided by plasma treatment again. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor films 110113 and 110114, and silicon nitride (SiNxOy) (SiNxOy) is formed on the surface of the silicon oxide.
x> y) is formed. When the semiconductor film is oxidized by plasma treatment, it is under an oxygen atmosphere (for example, an oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere) or. Plasma treatment is performed with oxygen and hydrogen (H ₂ ) and a noble gas atmosphere or dinitrogen monoxide and a noble gas atmosphere). On the other hand, when the semiconductor film is nitrided by plasma treatment, it is in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (He, Ne, Ar, Kr).
Plasma treatment is performed in an atmosphere (including at least one of Xe), or in an atmosphere of nitrogen, hydrogen, and a rare gas, or in an atmosphere of _NH3 and a rare gas). As the noble gas, for example, Ar can be used. Further, a gas in which Ar and Kr are mixed may be used. Therefore, the plasma-treated insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment. For example, when Ar is used, the plasma-treated insulating film is A.
r is included.

Next, the insulating film 110116 is formed (FIG. 102 (E)). The insulating film 110116 uses a known means (sputtering method, LPCVD method, plasma CVD method, etc.) to form silicon oxide (SiO).
Single-layer structure of insulating film having oxygen or nitrogen such as x), silicon nitride (SiNx), silicon oxide (SiOxNy) (x> y), silicon nitride (SiNxOy) (x> y), or a laminate thereof. It can be provided by the structure. When the plasma-treated insulating film is formed on the surface of the semiconductor films 110113 and 110114 by plasma-treating the surfaces of the semiconductor films 110113 and 110114, the plasma-treated insulating film can also be used as the insulating film 110116. ..

Here, a plasma-treated insulating film may be formed on the surface of the insulating film 110116 by subjecting the surface of the insulating film 110116 to plasma treatment and oxidizing or nitriding the surface of the insulating film 110116. The plasma-treated insulating film is a rare gas (He, Ne) used for plasma treatment.
, Ar, Kr, Xe at least one). Further, the plasma treatment can be similarly performed under the above-mentioned conditions.

Alternatively, the insulating film 110116 may be oxidized by once performing plasma treatment in an oxygen atmosphere, and then nitriding by performing plasma treatment again in a nitrogen atmosphere. In this way, by plasma-treating the insulating film 110116 and oxidizing or nitriding the surface of the insulating film 110116, the surface of the insulating film 110116 can be modified to form a dense film. Since the insulating film obtained by plasma treatment is denser and has less defects such as pinholes as compared with the insulating film formed by the CVD method or the sputtering method, the characteristics of the thin film transistor can be improved.

Next, the gate electrode 110117 is formed (FIG. 102 (F)). Gate electrode 110117
Can be formed by using known means (sputtering method, LPCVD method, plasma CVD method, etc.).

In 110101, the semiconductor film 110115 used as the source region and the drain region can be formed by performing impurity doping after forming the gate electrode 110117.

In 110102, by performing impurity doping after forming the gate electrode 110117, 110114 used as the LDD region and the semiconductor film 110115 used as the semiconductor film source region and drain region can be formed.

In 110103, by performing impurity doping after forming the gate electrode 110117, 110114 used as the LDD region and the semiconductor film 110115 used as the semiconductor film source region and drain region can be formed.

In 110104, the sidewall 110121 is on the side surface of the gate electrode 110117.
110114 used as the LDD region by performing impurity doping after forming
And the semiconductor film 110115 used as the semiconductor film source region and drain region can be formed.

The sidewall 110121 is formed of silicon oxide (SiOx) or silicon nitride (SiNx).
) Can be used. As a method of forming the sidewall 110121 on the side surface of the gate electrode 110117, for example, after forming the gate electrode 110117, silicon oxide (SiOx) or silicon nitride (SiNx) is formed by a known method, and then anisotropic. A method of etching a silicon oxide (SiOx) or silicon nitride (SiNx) film by etching can be used. By doing so, only the side surface of the gate electrode 110117 is silicon oxide (
Since a SiOx) or silicon nitride (SiNx) film can be left, the gate electrode 1101
A sidewall 110121 can be formed on the side surface of the 17.

In 110105, a mask 110122 is formed so as to cover the gate electrode 110117, and then impurity doping is performed to use the mask 110122 as an LDD (Loff) region11.
0114 and the semiconductor film 110115 used as the semiconductor film source region and drain region.
Can be formed.

In 110106, by performing impurity doping after forming the gate electrode 110117, 110114 used as the LDD (Lov) region and the semiconductor film 110115 used as the semiconductor film source region and drain region can be formed.

Next, the insulating film 110118 is formed (FIG. 102 (G)). The insulating film 110118 is formed of silicon oxide (SiOx) or silicon nitride (SiOx) by a known means (sputtering method, plasma CVD method, etc.).
SiNx), Silicon Nitride (SiOxNy) (x> y), Silicon Nitride (SiNxOy)
Insulating film having oxygen or nitrogen such as (x> y) or DLC (diamond-like carbon)
It can be provided by a single-layer structure of a film containing carbon such as, or a laminated structure thereof.

Here, a plasma-treated insulating film may be formed on the surface of the insulating film 110118 by subjecting the surface of the insulating film 110118 to plasma treatment and oxidizing or nitriding the surface of the insulating film 110118. The plasma-treated insulating film is a rare gas (He, Ne) used for plasma treatment.
, Ar, Kr, Xe at least one). Further, the plasma treatment can be similarly performed under the above-mentioned conditions.

Next, the insulating film 110119 is formed. The insulating film 110119 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide (SiOxNy) (x> y), silicon nitride (SiNxOy) (SiNxOy) by a known means (spatter method, plasma CVD method, etc.). In addition to an insulating film having oxygen or nitrogen such as x> y) and a film containing carbon such as DLC (diamond-like carbon), epoxy, polyimide, polyamide, polyvinylphenol, etc. can be used.
It can be provided by a single-layer structure of an organic material such as benzocyclobutene or acrylic or a siloxane resin, or a laminated structure thereof. The siloxane resin corresponds to a resin containing a Si—O—Si bond. The skeleton structure of siloxane is composed of the bonds between silicon (Si) and oxygen (O). As the substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as the substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as the substituent. Further, the plasma-treated insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment, and for example, when Ar is used, plasma-treated insulation is used. Ar is contained in the membrane.

When an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane resin is used as the insulating film 110119, the insulating film 110119 is used.
The surface of the insulating film can be modified by oxidizing or nitriding the surface of the insulating film by plasma treatment. By modifying the surface, the strength of the insulating film 110119 is improved, and it is possible to reduce physical damage such as crack generation during opening formation and film loss during etching. Further, by modifying the surface of the insulating film 110119, the adhesion to the conductive film is improved when the conductive film 110123 is formed on the insulating film 110119.
For example, when nitridation is performed using a siloxane resin as the insulating film 110119 by plasma treatment, the surface of the siloxane resin is nitrided to form a plasma-treated insulating film containing nitrogen or a rare gas, and the physical strength is increased. improves.

Next, in order to form the conductive film 110123 electrically connected to the semiconductor film 110115,
Contact holes are formed in the insulating film 110119, the insulating film 110118, and the insulating film 110116. The shape of the contact hole may be tapered. By doing this,
The coverage of the conductive film 110123 can be improved.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 14)
In this embodiment, a detailed configuration of a light emitting element applicable to a display device will be described.

The light emitting element utilizing electroluminescence is distinguished by whether the light emitting material is an organic compound or an inorganic compound, and the former is generally called an organic EL element and the latter is called an inorganic EL element.

The inorganic EL element is classified into a dispersed inorganic EL element and a thin film type inorganic EL element according to the element configuration. The former has an electroluminescent layer in which particles of the luminescent material are dispersed in a binder, and the latter has an electroluminescent layer made of a thin film of the luminescent material, but is accelerated by a high electric field. It is common in that it requires electroluminescence. The obtained luminescence mechanism includes a donor-acceptor recombination type luminescence that utilizes a donor level and an acceptor level, and a localized luminescence that utilizes a core electron transition of a metal ion. Generally, in distributed inorganic EL, donor-
In many cases, acceptor recombination type light emission and thin film type inorganic EL element are localized type light emission.

The light-emitting material applicable to the present invention is composed of a base material and an impurity element that serves as a light-emitting center.
By changing the impurity elements contained, it is possible to obtain light emission of various colors. As a method for producing the luminescent material, various methods such as a solid phase method and a liquid phase method (coprecipitation method) can be used. Alternatively, a spray pyrolysis method, a multi-decomposition method, a method by a thermal decomposition reaction of a precursor, a reverse micelle method, a method combining these methods and high-temperature firing, a liquid phase method such as a freeze-drying method, and the like can also be used.

In the solid phase method, the base material and the impurity element or the compound containing the impurity element are weighed and mixed in a mortar.
This is a method in which an impurity element is contained in the base material by heating and firing in an electric furnace to react. The firing temperature is preferably 700 to 1500 ° C. This is because if the temperature is too low, the solid phase reaction does not proceed, and if the temperature is too high, the base material is decomposed. Although firing may be performed in a powder state, firing is preferably performed in a pellet state. Although it requires firing at a relatively high temperature, it is a simple method, so it is highly productive and suitable for mass production.

The liquid phase method (coprecipitation method) is a method in which a base material or a compound containing a base material is reacted with an impurity element or a compound containing an impurity element in a solution, dried, and then calcined. The particles of the luminescent material are uniformly distributed, the particle size is small, and the reaction can proceed even at a low firing temperature.

Sulfide, oxide, and nitride can be used as the base material used for the light emitting material.
Examples of the sulfide include zinc sulfide (ZnS), cadmium sulfide (CdS), calcium sulfide (CaS), yttrium sulfide (Y ₂ S ₃ ), gallium sulfide (Ga ₂ S ₃ ), strontium sulfide (SrS), and sulfide. Sulfide (BaS) or the like can be used. Further, as the oxide, for example, zinc oxide (ZnO) _, yttrium oxide ₍ Y2O3) and the like can be used. Further, as the nitride, for example, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN) and the like can be used. Further, zinc selenide (ZnSe), zinc telluride (ZnTe) and the like can also be used, and calcium sulfide-gallium (CaGa ₂ S ₄ ), strontium sulfide-gallium (SrGa ₂ S ₄ ), barium sulfide-gallium (BaGa). It may be a mixed crystal of a ternary system such as ₂ S ₄ ).

Manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (Tm), europium (Eu), cerium (Ce), and placeodium are the emission centers of localized light emission. (Pr) and the like can be used. Halogen elements such as fluorine (F) and chlorine (Cl) may be added as charge compensation.

On the other hand, the first that forms the donor level as the emission center of the donor-acceptor recombination type emission.
A light emitting material containing an impurity element of the above and a second impurity element forming an acceptor level can be used. As the first impurity element, for example, fluorine (F), chlorine (Cl), aluminum (Al) and the like can be used. As the second impurity element, for example, copper (Cu),
Silver (Ag) or the like can be used.

When a donor-acceptor recombination type luminescent material is synthesized by the solid phase method, the parent material, a compound containing a first impurity element or a first impurity element, and a second impurity element or a second are used.
Weigh the compounds containing the impurity elements of the above, mix them in a mortar, and then heat and bake them in an electric furnace. As the base material, the above-mentioned base material can be used, and examples of the first impurity element or the compound containing the first impurity element include fluorine (F), chlorine (Cl), and aluminum sulfide ₍ Al 2S). ₃ ) and the like can be used, and examples of the compound containing the second impurity element or the _second impurity element include copper (Cu), silver (Ag), copper sulfide (Cu 2S), and silver sulfide (Ag). _2S ) and the like can be used. The firing temperature is preferably 700 to 1500 ° C.
This is because if the temperature is too low, the solid phase reaction does not proceed, and if the temperature is too high, the base material is decomposed. Although firing may be performed in a powder state, firing is preferably performed in a pellet state.

Further, as the impurity element when the solid phase reaction is used, a compound composed of the first impurity element and the second impurity element may be used in combination. In this case, the impurity element is easily diffused and the solid phase reaction is easily promoted, so that a uniform light emitting material can be obtained. Further, since no extra impurity element is contained, a highly pure luminescent material can be obtained. As the compound composed of the first impurity element and the second impurity element, for example, copper chloride (CuCl), silver chloride (AgCl) and the like can be used.

The concentration of these impurity elements may be 0.01 to 10 atom% with respect to the base material, preferably in the range of 0.05 to 5 atom%.

In the case of the thin film type inorganic EL, the electroluminescent layer is a layer containing the above-mentioned light emitting material, and is a resistance heating vapor deposition method.
Vacuum vapor deposition method such as electron beam vapor deposition (EB vapor deposition), physical vapor deposition method such as sputtering method (
PVD), organometallic CVD method, hydride transport vacuum CVD method, and other chemical vapor deposition methods (CV)
D), it can be formed by using an atomic epitaxy method (ALE) or the like.

FIGS. 103 (A) to 103 (C) show an example of a thin film type inorganic EL element that can be used as a light emitting element. In FIGS. 103A to 103C, the light emitting element is the first electrode layer 120100.
Includes an electroluminescent layer 120102 and a second electrode layer 120103.

The light emitting element shown in FIGS. 103 (B) and 103 (C) has a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light emitting element of FIG. 103 (A). The light emitting element shown in FIG. 103 (B) has an insulating layer 120104 between the first electrode layer 120100 and the electroluminescent layer 120102, and the light emitting element shown in FIG. 103 (C) has a first electrode layer 120100. And electroluminescent layer 120
Between 102 and the insulating layer 120105, the second electrode layer 120103 and the electroluminescent layer 12010
It has an insulating layer 120106 between the two. As described above, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. again,
The insulating layer may be a single layer or a laminated layer having a plurality of layers.

In FIG. 103 (B), the insulating layer 120104 is in contact with the first electrode layer 120100.
However, the order of the insulating layer and the electroluminescent layer is reversed, and the second electrode layer 120103 is provided.
The insulating layer 120104 may be provided so as to be in contact with the above.

In the case of the dispersed inorganic EL, the particulate luminescent material is dispersed in the binder to form a film-like electroluminescent layer. Process into particles. If particles of a sufficiently desired size cannot be obtained by the method for producing a luminescent material, the particles may be processed into particles by pulverization or the like in a mortar or pestle. What is a binder?
It is a substance for fixing a granular light emitting material in a dispersed state and holding it in a shape as an electroluminescent layer. The luminescent material is uniformly dispersed and fixed in the electroluminescent layer by a binder.

In the case of dispersed inorganic EL, the electroluminescent layer is formed by a droplet ejection method capable of selectively forming an electroluminescent layer, a printing method (screen printing, offset printing, etc.), a coating method such as a spin coating method, or dipping. A method, a dispenser method, or the like can also be used. The film thickness is not particularly limited, but is preferably in the range of 10 to 1000 nm. Further, in the electroluminescent layer containing the light emitting material and the binder, the ratio of the light emitting material may be 50 wt% or more and 80 wt% or less.

FIGS. 104 (A) to 104 (C) show an example of a dispersed inorganic EL element that can be used as a light emitting element. The light emitting element in FIG. 104 (A) has a laminated structure of a first electrode layer 120200, an electroluminescent layer 120202, and a second electrode layer 120203, and a light emitting material 120201 held by a binder in the electroluminescent layer 120202. include.

As the binder that can be used in this embodiment, an insulating material can be used. As the insulating material, an organic material and an inorganic material can be used. Alternatively, a mixed material of an organic material and an inorganic material may be used. As the organic insulating material, a polymer having a relatively high dielectric constant such as a cyanoethyl cellulose resin or a resin such as polyethylene, polypropylene, polystyrene resin, silicone resin, epoxy resin or vinylidene fluoride can be used. Alternatively, aromatic polyamides, polybenzimidazoles (polybenzi)
A heat-resistant polymer such as midazole) or a siloxane resin may be used. The siloxane resin corresponds to a resin containing a Si—O—Si bond. The skeleton structure of siloxane is composed of the bonds between silicon (Si) and oxygen (O). As the substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as the substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as the substituent. Alternatively, a resin material such as a vinyl resin such as polyvinyl alcohol or polyvinyl butyral, a phenol resin, a novolak resin, an acrylic resin, a melamine resin, a urethane resin, or an oxazole resin (polybenzoxazole) may be used. These resins include barium titanate (BaTIO ₃ ) and strontium titanate (SrTiO ₃ ).
) And other high dielectric constant particles can be mixed appropriately to adjust the dielectric constant.

Examples of the inorganic insulating material contained in the binder include silicon oxide (SiOx) and silicon nitride (SiNx).
), Silicon containing oxygen and nitrogen, aluminum nitride (AlN), aluminum containing oxygen and nitrogen, aluminum oxide containing oxygen and nitrogen (Al ₂ O ₃ ), titanium oxide (TIO ₂ ).
, BaTIO ₃ , SrTIO ₃ , Lead Titanate (PbTIO ₃ ), Potassium niobate (KN)
bO ₃ ), lead niobate (PbNbO ₃ ), tantalum oxide (Ta ₂ O ₅ ), barium tantalate (BaTa ₂ O ₆ ), lithium tantalate (LiTaO ₃ ), yttrium oxide (Y)
It can be formed of a material selected from materials including _{2O 3} ), zirconium oxide (ZrO ₂ ), ZnS and other inorganic insulating materials. By including an inorganic material having a high dielectric constant in the organic material (by addition or the like), the dielectric constant of the electroluminescent layer made of the light emitting material and the binder can be further controlled, and the dielectric constant can be further increased. ..

In the fabrication process, the luminescent material is dispersed in a solution containing a binder. As the solvent of the solution containing the binder that can be used in the present embodiment, a method of dissolving the binder material to form an electroluminescent layer (various wet processes) and a solution having a viscosity suitable for a desired film thickness can be prepared. Such a solvent may be appropriately selected. For example, an organic solvent or the like can be used as the solvent. When a siloxane resin is used as a binder, propylene glycol monomethyl ether and propylene glycol monomethyl ether acetate (also referred to as PGMEA)
, 3-Metoshiki-3methyl-1-butanol (also referred to as MMB) and the like can be used as a solvent.

The light emitting element shown in FIGS. 104 (B) and 104 (C) has a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light emitting element of FIG. 104 (A). The light emitting element shown in FIG. 104 (B) has an insulating layer 120204 between the first electrode layer 120200 and the electroluminescent layer 120202, and the light emitting element shown in FIG. 104 (C) has a first electrode layer 120200. And electroluminescent layer 120
Between 202 and the insulating layer 120205, the second electrode layer 120203 and the electroluminescent layer 12020
It has an insulating layer 120206 between the two. As described above, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. Further, the insulating layer may be a single layer or a laminated layer having a plurality of layers.

Further, in FIG. 104 (B), the insulating layer 120204 is in contact with the first electrode layer 120200.
However, the order of the insulating layer and the electroluminescent layer is reversed, and the second electrode layer 120203 is provided.
The insulating layer 120204 may be provided so as to be in contact with the above.

Materials that can be used for the insulating layer, such as the insulating layer 120104 in FIG. 103 and the insulating layer 120204 in FIG. 104, preferably have high dielectric strength and a dense film quality.
Furthermore, it is preferable that the dielectric constant is high. For example, silicon oxide (SiO ₂ ), yttrium oxide (Y ₂ O ₃ ), titanium oxide (TIO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), Barium titanate (BaTi)
O ₃ ), strontium titanate (SrTIO ₃ ), lead titanate (PbTIO ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), etc., a mixed film thereof, or a laminated film of two or more thereof is used. be able to. These insulating films can be formed by sputtering, vapor deposition, CVD, or the like. Further, in the insulating layer, particles of these insulating materials may be dispersed in a binder to form a film. The binder material may be formed by using the same material and method as the binder contained in the electroluminescent layer. The film thickness is not particularly limited, but is preferably 10 to 10.
It is in the range of 00 nm.

The light emitting element shown in the present embodiment can emit light by applying a voltage between a pair of electrode layers sandwiching an electroluminescent layer, but can operate in either DC drive or AC drive.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 15)
In this embodiment, an example of a display device, particularly a case where optical handling is performed, will be described.

The rear projection type display device 130100 shown in FIGS. 105 (A) and 105 (B) includes a projector unit 130111, a mirror 130112, and a screen panel 130101.
In addition, a speaker 130102 and operation switches 130104 may be provided. The projector unit 130111 is a housing 130 of the rear projection type display device 130100.
Mirror 13011 is arranged at the bottom of 110 and projects light that projects an image based on an image signal.
Project toward 2. The rear projection type display device 130100 is a screen panel 130101.
It is configured to display the image projected from the back of.

On the other hand, FIG. 106 shows the front projection type display device 130200. The front projection display device 130200 includes a projector unit 130111 and a projection optical system 130201. The front projection optical system 130200 is configured to project an image on a screen or the like arranged on the front surface.

The configuration of the projector unit 130111 applied to the rear projection type display device 130100 shown in FIG. 105 and the front projection type display device 130200 shown in FIG. 106 will be described below.

FIG. 107 shows a configuration example of the projector unit 130111. The projector unit 130111 includes a light source unit 130301 and a modulation unit 13030.
4 is provided. The light source unit 130301 includes a light source optical system 130303 including lenses and a light source lamp 130302. The light source lamp 130302 is housed in a housing so that stray light does not diffuse. As the light source lamp 130302, for example, a high-pressure mercury lamp or a xenon lamp capable of radiating a large amount of light is used. The light source optical system 130303 is configured by appropriately providing an optical lens, a film having a polarizing function, a film for adjusting a phase difference, an IR film, and the like. And the light source unit 130301
Is arranged so that the synchrotron radiation is incident on the modulation unit 130304. The modulation unit 130304 includes a plurality of display panels 130308, a color filter, a dichroic mirror 130305, a total reflection mirror 130306, a prism 130309, and a projection optical system 13.
It is equipped with 0310. The light emitted from the light source unit 130301 is separated into a plurality of optical paths by the dichroic mirror 130305.

Each optical path is provided with a color filter that transmits light of a predetermined wavelength or wavelength band, and a display panel 130308. The transmissive display panel 130308 modulates the transmitted light based on the video signal. The light of each color transmitted through the display panel 130308 is the prism 13.
An image is displayed on the screen through the projection optical system 130310 incident on 0309. The Fresnel lens may be arranged between the mirror and the screen. Then, the projected light projected by the projector unit 130111 and reflected by the mirror is converted into substantially parallel light by the Fresnel lens and projected on the screen.

The projector unit 130111 shown in FIG. 108 is a reflective display panel 13040.
A configuration including 7, 130408 and 130409 is shown.

The projector unit 130111 shown in FIG. 108 includes a light source unit 130301 and a modulation unit 130400. The light source unit 130301 may have the same configuration as that shown in FIG. 107. The light from the light source unit 130301 is a dichroic mirror 13.
It is divided into a plurality of optical paths by 0401, 130402, and total reflection mirror 130403.
It is incident on the polarizing beam splitters 130404, 130405 and 130406. The polarizing beam splitters 130404, 130405, and 130406 are provided corresponding to the reflective display panels 130407, 130408, and 130409 corresponding to each color. The reflective display panels 130407, 130408, 130409 modulate the reflected light based on the video signal. The light of each color reflected by the reflective display panels 130407, 130408, and 130409 is combined by being incident on the prism 130309 and projected through the projection optical system 130411.

The light emitted from the light source unit 130301 transmits only the light in the red wavelength region by the dichroic mirror 130401 and reflects the light in the green and blue wavelength regions. Further, the dichroic mirror 130402 reflects only light in the green wavelength region. Light in the red wavelength region transmitted through the dichroic mirror 130401 is reflected by the full reflection mirror 130403 and incident on the polarized beam splitter 130404, and light in the blue wavelength region is incident on the polarized beam splitter 130405 and has a green wavelength. The light in the region is the polarized beam splitter 1304
It is incident on 06. The polarization beam splitters 130404, 130405, 130406 are
It has a function of separating incident light into P-polarized light and S-polarized light, and has a function of transmitting only P-polarized light. The reflective display panels 130407, 130408, and 130409 polarized the incident light based on the video signal.

Only the S-polarized light corresponding to each color is incident on the reflective display panels 130407, 130408, and 130409 corresponding to each color. The reflective display panels 130407 and 130408
, 130409 may be a liquid crystal panel. At this time, the liquid crystal panel operates in the electric field controlled birefringence mode (ECB). Further, the liquid crystal molecules are vertically oriented at a certain angle with respect to the substrate. Therefore, in the reflective display panels 130407, 130408, and 130409, the display molecules are oriented so as to reflect the incident light without changing the polarization state when the pixel is in the off state. Further, when the pixel is in the on state, the orientation state of the display molecule changes, and the polarization state of the incident light changes.

The projector unit 130111 shown in FIG. 108 can be applied to the rear projection type display device 130100 shown in FIG. 105 and the front projection type display device 130200 shown in FIG. 106.

The projector unit shown in FIG. 109 shows a single-panel configuration. The projector unit 130111 shown in FIG. 109 (A) has a light source unit 130301 and a display panel 1.
It includes 30507, a projection optical system 130511, and a retardation plate 130504. The projection optical system 130511 is composed of one or a plurality of lenses. The display panel 130507 may be provided with a color filter.

FIG. 109 (B) shows a projector unit 1 that operates in a field sequential manner.
The configuration of 30111 is shown. The field sequential method is a method in which light of each color such as red, green, and blue is sequentially incident on a display panel by shifting the time in time, and color display is performed without a color filter. In particular, when combined with a display panel having a high response speed to changes in the input signal, a high-definition image can be displayed. In FIG. 109 (B), a rotary color filter plate 130505 provided with a plurality of color filters such as red, green, and blue is provided between the light source unit 130301 and the display panel 130508.

The projector unit 130111 shown in FIG. 109 (C) shows a configuration of a color separation method using a macro lens as a color display method. In this method, a microlens array 130506 is provided on the light incident side of the display panel 130509, and light of each color is illuminated from each direction to realize color display. The projector unit 130111 that adopts this method has a feature that the light from the light source unit 130301 can be effectively used because the loss of light due to the color filter is small. FIG. 10
The projector unit 130111 shown in 9 (C) includes a dichroic mirror 130501, a dichroic mirror 130502, and a dichroic mirror 130503 for red light so as to illuminate the display panel 130509 with light of each color from each direction.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 16)
In the present embodiment, an example of the electronic device according to the present invention will be described.

FIG. 110 shows a display panel module in which a display panel 900101 and a circuit board 900111 are combined. The display panel 900101 has a pixel unit 900102, a scanning line driving circuit 900103, and a signal line driving circuit 900104. For example, a control circuit 900112 and a signal division circuit 900113 are formed on the circuit board 900111. The display panel 900101 and the circuit board 900111 are connected by a connection wiring 900114. FPC or the like can be used for the connection wiring.

The display panel 900101 integrally forms a pixel unit 900102 and a part of peripheral drive circuits (a drive circuit having a low operating frequency among a plurality of drive circuits) on a substrate by using a TFT, and a part of the peripheral drive circuits (a plurality of drive circuits). A drive circuit having a high operating frequency among the drive circuits) may be formed on an IC chip, and the IC chip may be mounted on the display panel 900101 by COG (Chip On Glass) or the like. By doing so, the area of the circuit board 900111 can be reduced, and a small display device can be obtained. Alternatively, the IC chip is TAB (Tape Auto B).
It may be mounted on the display panel 900101 by using on) or a printed circuit board. By doing so, the area of the display panel 900101 can be reduced, so that a display device having a small frame size can be obtained.

For example, in order to reduce power consumption, a pixel portion is formed on a glass substrate using a TFT, all peripheral drive circuits are formed on an IC chip, and the IC chip is mounted on a display panel by COG or TAB. You may.

The television receiver can be completed by the display panel module shown in FIG. 110. FIG. 111 is a block diagram showing a main configuration of a television receiver. Tuner 9002
01 receives a video signal and an audio signal. The video signal is the video signal amplifier circuit 900202 and
A video signal processing circuit 900203 that converts the signal output from the video signal amplifier circuit 900202 into a color signal corresponding to each color of red, green, and blue, and a control circuit 900212 for converting the video signal into the input specifications of the drive circuit. Is processed by. Control circuit 9002
12 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 900213 may be provided on the signal line side, and the input digital signal may be divided into m pieces (m is a positive integer) and supplied.

Of the signals received by the tuner 900201, the audio signal is the audio signal amplifier circuit 900205.
The output is supplied to the speaker 900207 via the audio signal processing circuit 900206. The control circuit 900208 inputs the receiving station (reception frequency) and volume control information into the input unit 9.
It receives from 00209 and sends a signal to the tuner 900201 and the audio signal processing circuit 900206.

Further, FIG. 112 (A) shows a television receiver incorporating a display panel module having a form different from that of FIG. 111. In FIG. 112A, the display screen 900302 housed in the housing 900301 is formed of a display panel module. The speaker 90030
3. An operation switch 900304 or the like may be appropriately provided.

Further, FIG. 112B shows a television receiver that can carry only the display wirelessly. A battery and a signal receiver are built in the housing 900123, and the battery drives the display unit 900133 and the speaker unit 900317. The battery can be repeatedly charged with the charger 900310. Further, the charger 900310 can transmit and receive a video signal, and the video signal can be transmitted to the signal receiver of the display. The housing 900123 is controlled by the operation key 900316. Alternatively, FIG.
The device shown in 12 (B) has a housing 9003 by operating the operation key 900316.
It may be a video-audio bidirectional communication device capable of sending a signal from 12 to the charger 900310. Alternatively, by operating the operation key 900316, the housing 9003
It may be a general-purpose remote control device capable of controlling communication of other electronic devices by sending a signal from 12 to the charger 900310 and further causing another electronic device to receive a signal that can be transmitted by the charger 900310. .. The present invention can be applied to the display unit 900313.

FIG. 113A shows a module in which the display panel 900401 and the printed wiring board 900402 are combined. The display panel 900401 includes a pixel unit 900403 provided with a plurality of pixels, a first scanning line driving circuit 900404, and a second scanning line driving circuit 9004.
05 may be provided with a signal line drive circuit 900406 that supplies a video signal to the selected pixels.

The printed wiring board 900402 has a controller 900407 and a central processing unit (CPU).
) 900408, memory 900409, power supply circuit 900410, audio processing circuit 90041
1 and a transmission / reception circuit 900412 and the like are provided. The printed wiring board 900402 and the display panel 900401 are connected by a flexible wiring board (FPC) 900413. The printed wiring board 900413 may be provided with a holding capacity, a buffer circuit, or the like to prevent noise from being generated in the power supply voltage or the signal and an increase in the rise time of the signal. Further, the controller 900407, the voice processing circuit 900411, the memory 90409,
CPU900408, power supply circuit 900410, etc. are COG (Chip On Glass).
It can also be mounted on the display panel 900401 using the s) method. By COG method
The scale of the printed wiring board 900402 can be reduced.

Interface (I / F) unit 900144 provided on the printed wiring board 900402
Various control signals are input and output via. Further, an antenna port 900415 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 900402.

FIG. 113B shows a block diagram of the module shown in FIG. 113A. This module includes VRAM900416, DRAM900417, flash memory 900418, and the like as the memory 9004000. The VRAM 900416 stores image data to be displayed on the panel, the DRAM 900417 stores image data or audio data, and the flash memory stores various programs.

The power supply circuit 900410 includes a display panel 900401, a controller 900407, and a CPU.
900408, voice processing circuit 900411, memory 900409, transmission / reception circuit 90041
Supply the power to operate 2. Further, depending on the specifications of the panel, the power supply circuit 900410 may be provided with a current source.

The CPU900408 has a control signal generation circuit 900420, a decoder 900421, a register 900422, an arithmetic circuit 900423, a RAM90024, an interface 900419 for the CPU 9004000, and the like. Various signals input to the CPU 9004000 via the interface 900419 are once held in the register 900422 and then input to the arithmetic circuit 900423, the decoder 900421, and the like. Arithmetic circuit 9004
In 23, an operation is performed based on the input signal, and a place to send various commands is specified. On the other hand, the signal input to the decoder 900421 is decoded and input to the control signal generation circuit 900420. The control signal generation circuit 900420 generates a signal including various instructions based on the input signal, and the location specified in the arithmetic circuit 900423, specifically, the memory 900.
409, transmission / reception circuit 900412, audio processing circuit 900411, controller 90040
Send to 7 etc.

The memory 900409, the transmission / reception circuit 900412, the voice processing circuit 900411, and the controller 900407 operate according to the instructions received, respectively. The operation will be briefly described below.

The signal input from the input means 900425 is sent to the CPU 900408 mounted on the printed wiring board 900402 via the interface 900414. The control signal generation circuit 900420 is an input means 900425 such as a pointing device or a keyboard.
According to the signal sent from, the image data stored in the VRAM 900416 is converted into a predetermined format and sent to the controller 900407.

The controller 900407 performs data processing on the signal including the image data sent from the CPU 900408 according to the specifications of the panel, and supplies the signal to the display panel 900401. Further, the controller 900407 is a power supply voltage and a CPU input from the power supply circuit 900410.
Based on various signals input from 900408, an Hsync signal, a Vsync signal, a clock signal CLK, an AC voltage (AC Cont), and a switching signal L / R are generated and supplied to the display panel 900401.

In the transmission / reception circuit 900412, signals transmitted / received as radio waves are processed by the antenna 900428, specifically, an isolator, a bandpass filter, and a VCO (Volt).
age Control Oscillator), LPF (Low Pass)
It may include a high frequency circuit such as a filter), a coupler, and a balun. Transmission / reception circuit 90
Among the signals transmitted and received in 0412, the signal including the voice information is sent to the voice processing circuit 900411 according to the command from the CPU900408.

The signal including the voice information sent according to the instruction of the CPU 900408 is the voice processing circuit 9.
It is demodulated into an audio signal in 00411 and sent to the speaker 900427. Further, the audio signal transmitted from the microphone 900426 is modulated by the audio processing circuit 900411 and sent to the transmission / reception circuit 900412 according to a command from the CPU 900408.

The controller 900407, the CPU 900408, the power supply circuit 900410, the audio processing circuit 900411, and the memory 900409 can be implemented as a package of the present embodiment.

Of course, this embodiment is not limited to television receivers, and is used for various purposes such as personal computer monitors, information display boards at railway stations and airports, and advertisement display boards on the streets. Can be applied to.

Next, a configuration example of the mobile phone according to the present invention will be described with reference to FIG. 114.

The display panel 900501 is detachably incorporated into the housing 900530. The shape and dimensions of the housing 900530 can be appropriately changed according to the size of the display panel 900501. The housing 900530 to which the display panel 900501 is fixed is fitted into the printed circuit board 900351 and assembled as a module.

The display panel 900501 is connected to the printed circuit board 900351 via the FPC900513. The printed circuit board 900531 has a speaker 900523 and a microphone 90.
Signal processing circuit 9 including 0533, transmission / reception circuit 900534, CPU, controller, etc.
00535 is formed. Such a module is combined with the input means 900536 and the battery 900537 and housed in the housing 900539. Display panel 900501
The pixel portion of the above is arranged so as to be visible from the opening window formed in the housing 900539.

In the display panel 900501, a pixel portion and a part of peripheral drive circuits (a drive circuit having a low operating frequency among a plurality of drive circuits) are integrally formed on a substrate by using a TFT, and a part of the peripheral drive circuits (a plurality of drives) are integrally formed. A drive circuit having a high operating frequency among the circuits) may be formed on an IC chip, and the IC chip may be mounted on the display panel 900501 by COG (Chip On Glass).
Alternatively, the IC chip may be connected to a glass substrate using a TAB (Tape Auto Bonding) or a printed circuit board. With such a configuration, it is possible to reduce the power consumption of the display device and prolong the usage time by charging the mobile phone once. In addition, the cost of the mobile phone can be reduced.

The mobile phone shown in FIG. 115 includes operation switches 900604 and a microphone 90.
Main body (A) 900601 equipped with 0605 and the like, display panel (A) 900608,
Main unit (B) 9 equipped with a display panel (B) 960609, a speaker 960606, etc.
00602 is connected to the hinge 900610 so as to be openable and closable. Display panel (A) 90
The 0608 and the display panel (B) 960609 are the main body (B) 9 together with the circuit board 960607.
It is housed in the housing 900603 of 00602. The pixel portions of the display panel (A) 960608 and the display panel (B) 960609 are arranged so as to be visible from the opening window formed in the housing 960603.

The display panel (A) 960608 and the display panel (B) 960609 are the mobile phone 90 thereof.
Specifications such as the number of pixels can be appropriately set according to the function of 0600. For example, the display panel (A) 960608 may be used as the main screen, and the display panel (B) 960609 may be used as the sub screen.

The mobile phone according to the present embodiment can be transformed into various modes depending on its function and application.
For example, an image sensor may be incorporated in the portion of the hinge 900610 to form a mobile phone with a camera. Further, even if the operation switches 900604, the display panel (A) 960608, and the display panel (B) 960609 are housed in one housing, the above-mentioned effects can be obtained. Further, even if the configuration of the present embodiment is applied to an information display terminal provided with a plurality of display units, the same effect can be obtained.

The present invention can be applied to various electronic devices. Specifically, it can be applied to a display unit of an electronic device. Such electronic devices include video cameras, digital cameras, goggle-type displays, navigation systems, sound reproduction devices (car audio, audio components, etc.), computers, game devices, mobile information terminals (mobile computers, mobile phones, portable games, etc.). An image playback device (specifically, D) equipped with a machine or electronic book, etc., and a recording medium.
A device provided with a display capable of reproducing a recording medium such as an ultimate Versail Disc (DVD) and displaying the image) and the like.

FIG. 116A is a display, which includes a housing 900711, a support base 900112, a display unit 900713, and the like.

FIG. 116 (B) is a camera, which is a main body 900721, a display unit 900722, and an image receiving unit 900.
723, operation key 900274, external connection port 900275, shutter 900726
Etc. are included.

FIG. 116C is a computer, which includes a main body 900731, a housing 900732, a display unit 900734, a keyboard 900734, an external connection port 900735, a pointing device 900736, and the like.

FIG. 116 (D) is a mobile computer, which is a main body 900741 and a display unit 900741.
2. Includes switch 900743, operation key 900744, infrared port 900745 and the like.

FIG. 116 (E) shows a portable image playback device (for example, a DVD playback device) provided with a recording medium.
The main body 900751, the housing 900752, the display unit A900753, and the display unit B900.
754, a recording medium (DVD or the like) reading unit 900755, an operation key 90076, a speaker unit 900757, and the like are included. The display unit A900753 can mainly display image information, and the display unit B90074 can mainly display character information.

FIG. 116 (F) is a goggle type display, which is a main body 900761 and a display unit 900761.
2. Includes earphones 900763 and support 900764.

FIG. 116 (G) is a portable gaming machine, which includes a housing 90071, a display unit 900772, a speaker unit 900773, an operation key 900774, a storage medium insertion unit 900775, and the like. A portable gaming machine using the display device of the present invention for the display unit 90072 can express vivid colors.

FIG. 116 (H) is a digital camera with a television image receiving function, which is a main body 90041, a display unit 900782, an operation key 900783, a speaker 900744, and a shutter 900781.
5. Includes an image receiving unit 900846, an antenna 900787, and the like.

As shown in FIGS. 116A to 116E, the electronic device according to the present invention is characterized by having a display unit for displaying some information.

Next, an application example of the semiconductor device according to the present invention will be described.

FIG. 117 shows an example in which the semiconductor device according to the present invention is provided in a building. FIG. 117 shows
It includes a housing 900810, a display unit 900111, a remote control device 900812 which is an operation unit, a speaker unit 900713 and the like. The semiconductor device according to the present invention is integrated with the building as a wall-mounted type, and can be installed without requiring a large space for installation.

FIG. 118 shows another example in which the semiconductor device according to the present invention is provided in a building. The display panel 900901 is mounted integrally with the unit bath 900902.
Bathers will be able to view the display panel 900901. The display panel 900901 has a function of displaying information by being operated by a bather, and can be used as an advertisement or an entertainment means.

The semiconductor device according to the present invention can be installed not only in the side wall of the unit bath 900902 shown in FIG. 118 but also in various places. For example, it may be integrated with a part of the mirror surface or the bathtub itself. At this time, the shape of the display panel 900901 may match the shape of the mirror surface or the bathtub.

FIG. 119 shows another example in which the semiconductor device according to the present invention is provided in a building. The display panel 901002 is attached so as to be curved according to the curved surface of the columnar body 901001. Here, the columnar body 901001 will be described as an electric pole.

The display panel 901002 shown in FIG. 119 is provided at a position higher than the human viewpoint.
By installing the display panel 901002 in a building that is repeatedly forested outdoors, such as a utility pole, it is possible to advertise to an unspecified number of viewers. Here, the display panel 90100
In No. 2, the same image can be displayed by external control, and the images can be easily switched instantly, so that extremely efficient information display and advertising effect can be expected. Further, by providing the display panel 901002 with a self-luminous display element, it can be said that it is useful as a display medium having high visibility even at night. In addition, by installing it on a utility pole, the display panel 90
It is easy to secure the power supply means of 1002. It can also be a means of quickly and accurately transmitting information to disaster victims in the event of an emergency such as a disaster.

As the display panel 901002, for example, a display panel that displays an image by providing a switching element such as an organic transistor on a film-shaped substrate and driving the display element can be used.

In the present embodiment, a wall, a columnar body, and a unit bath are taken as examples of buildings, but the present embodiment is not limited to this, and the semiconductor device according to the present invention can be installed in various buildings. ..

Next, an example in which the semiconductor device according to the present invention is provided on a moving body will be described.

FIG. 120 is a diagram showing an example in which the semiconductor device according to the present invention is provided in an automobile. The display panel 901102 is integrally attached to the vehicle body 901101 of the automobile, and can display the operation of the vehicle body and information input from inside and outside the vehicle body on demand. Further, it may have a navigation function.

The semiconductor device according to the present invention can be installed not only in the vehicle body 901101 shown in FIG. 120 but also in various places. For example, it may be integrated with a glass window, a door, a handle, a shift lever, a seat, a rear-view mirror, or the like. At this time, the display panel 901022
The shape of may be matched to the shape of the one to be installed.

FIG. 121 is a diagram showing an example in which the semiconductor device according to the present invention is provided in a train vehicle.

FIG. 121 (a) is a diagram showing an example in which a display panel 901202 is provided on the glass of the door 901201 of a train vehicle. Compared to conventional paper advertisements, there is an advantage that the labor cost required for switching advertisements is not required. Further, since the display panel 901202 can instantly switch the image displayed on the display unit by a signal from the outside, the display panel 901202 can instantly switch the image.
For example, the image of the display panel can be switched at each time when the customer base of train passengers changes, and more effective advertising effect can be expected.

FIG. 121B shows a glass window 901203 in addition to the glass of the train vehicle door 901201.
, And an example showing an example in which the display panel 901202 is provided on the ceiling 901204.
As described above, the semiconductor device according to the present invention can be easily installed in a place where it was difficult to install in the past, so that an effective advertising effect can be obtained. Further, since the semiconductor device according to the present invention can instantly switch the image displayed on the display unit by a signal from the outside, the cost and time for switching the advertisement can be reduced, and the advertisement is more flexible. Operation and information transmission are possible.

The semiconductor device according to the present invention includes a door 901201 and a glass window 901 shown in FIG. 121.
It can be installed not only in 203 and the ceiling 901204 but also in various places. For example, it may be integrated with straps, seats, railings, floors, and the like. At this time, the display panel 9
The shape of 01202 may be adapted to the shape of the object to be installed.

FIG. 122 is a diagram showing an example in which the semiconductor device according to the present invention is provided on a passenger airplane.

FIG. 122 (a) shows a display panel 90130 on the ceiling 901301 above the seat of a passenger airplane.
It is a figure which showed the shape at the time of use when 2 is provided. The display panel 901302 is
It is integrally attached to the ceiling 901301 via the hinge portion 901303, and the expansion and contraction of the hinge portion 901303 allows passengers to view the display panel 901302. The display panel 901302 has a function of displaying information by being operated by a passenger, and can be used as an advertisement or an entertainment means. Further, as shown in FIG. 122 (b), by bending the hinge portion and storing it in the ceiling 901301, safety at the time of takeoff and landing can be considered. By turning on the display element of the display panel in an emergency, it can also be used as an information transmission means and a guide light.

The semiconductor device according to the present invention can be installed not only in the ceiling 901301 shown in FIG. 122 but also in various places. For example, it may be integrated with a seat, a seat table, an accoudoir, a window, or the like. Further, a large display panel that can be viewed by a large number of people at the same time may be installed on the wall of the aircraft. At this time, the shape of the display panel 901302 may be adapted to the shape of the one to be installed.

In the present embodiment, examples of moving objects include train vehicle bodies, automobile bodies, and airplane bodies, but the present invention is not limited to these, and motorcycles, motorcycles (including automobiles, buses, etc.), and motorcycles.
It can be installed on various things such as trains (including monorails and railroads) and ships. Since the semiconductor device according to the present invention can instantly switch the display of the display panel in the moving body by a signal from the outside, the moving body can be mounted by installing the semiconductor device according to the present invention on the moving body. Advertising display board for an unspecified number of customers, information display board in the event of a disaster,
It can be used for such purposes.

In addition, although it has been described using various figures in this embodiment, the contents described in each figure (
(May be part) applies, combines, and applies to the content (may be part) described in another figure.
Or it can be replaced freely. Furthermore, in the figures described so far, more figures can be formed by combining different parts with respect to each part.

Similarly, the content (which may be a part) described in each figure of the present embodiment may be applied, combined, or replaced with respect to the content (which may be a part) described in the figure of another embodiment. Can be done freely. Further, in the figure of the present embodiment, more figures can be formed by combining the parts of another embodiment with respect to each part.

It should be noted that this embodiment is an improvement of the contents (may be a part) described in the other embodiments, as an example in the case of embodying, an example in the case of being slightly deformed, and an example in the case of partially changing. An example of the case,
An example of the case described in detail, an example of the case of application, an example of related parts, and the like are shown. Therefore, the contents described in the other embodiments can be freely applied, combined, or replaced with the present embodiments.

(Embodiment 17)
As shown above, the present specification includes at least the following inventions.

It has a pixel having a liquid crystal element and a drive circuit, and the drive circuit has a first transistor and
The first transistor has a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first electrode is electrically connected to the fourth wiring, the second electrode of the first transistor is electrically connected to the third wiring, and the first electrode of the second transistor is the first. Electrically connected to the wiring of 7, the second electrode of the second transistor is the third.
The gate electrode of the second transistor is electrically connected to the fifth wiring, and the first electrode of the third transistor is electrically connected to the sixth wiring. The second electrode of the third transistor is electrically connected to the gate electrode of the sixth transistor, and the gate electrode of the third transistor is electrically connected to the fourth wiring. The first electrode of the fourth transistor is electrically connected to the seventh wiring, the second electrode of the fourth transistor is electrically connected to the gate electrode of the sixth transistor, and the fourth is electrically connected. The gate electrode of the transistor is electrically connected to the fifth wiring, the first electrode of the fifth transistor is electrically connected to the sixth wiring, and the second electrode of the fifth transistor is electrically connected. The electrode is electrically connected to the gate electrode of the first transistor, the gate electrode of the fifth transistor is electrically connected to the first wiring, and the first electrode of the sixth transistor is the first electrode. The second electrode of the sixth transistor is electrically connected to the wiring of the seventh transistor, the second electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor, and the first electrode of the seventh transistor is the seventh. The second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and the gate electrode of the seventh transistor is electrically connected to the second wiring. The first electrode of the eighth transistor is electrically connected to the seventh wiring, and the second electrode of the eighth transistor is electrically connected to the gate electrode of the sixth transistor. The gate electrode of the eighth transistor is electrically connected to the gate electrode of the first transistor.

In the above configuration, the value of W / L of the first transistor is set to be the maximum among the values of the ratio W / L of the channel length L and the channel width W of the first transistor to the eighth transistor. be able to. Further, in the above configuration, the value of the first transistor W / L may be 2 to 5 times the value of the fifth transistor W / L. Further, the channel length L of the third transistor may be larger than the channel length L of the eighth transistor. Further, a capacitive element may be provided between the second electrode of the first transistor and the gate electrode of the first transistor. Further, the first transistor to the seventh transistor may be provided as an N-channel transistor. Further, the first transistor to the seventh transistor may be formed by using amorphous silicon.

It has a pixel having a liquid crystal element, a first drive circuit, and a second drive circuit, and the first drive circuit includes a first transistor, a second transistor, a third transistor, and a first transistor. 4 transistors, 5th transistor, 6th transistor, 7th transistor,
It has an eighth transistor, the first electrode of the first transistor is electrically connected to the fourth wiring, and the second electrode of the first transistor is electrically connected to the third wiring. The first electrode of the second transistor is electrically connected to the seventh wiring, and the second electrode of the second transistor is electrically connected to the third wiring. The gate electrode of the transistor is electrically connected to the fifth wiring, and the first electrode of the third transistor is the sixth.
The second electrode of the third transistor is electrically connected to the gate electrode of the sixth transistor, and the gate electrode of the third transistor is electrically connected to the fourth of the third transistor.
The first electrode of the fourth transistor is electrically connected to the seventh wiring, and the second electrode of the fourth transistor is the gate of the sixth transistor. Electrically connected to the electrodes, the gate electrode of the fourth transistor is electrically connected to the fifth wiring, and the first electrode of the fifth transistor is electrically connected to the sixth wiring. The second electrode of the fifth transistor is electrically connected to the gate electrode of the first transistor, and the gate electrode of the fifth transistor is electrically connected to the first wiring. The first electrode of the transistor of 6 is electrically connected to the 7th wiring, and the 6th transistor is electrically connected.
The second electrode of the transistor is electrically connected to the gate electrode of the first transistor, the first electrode of the seventh transistor is electrically connected to the seventh wiring, and the seventh.
The second electrode of the transistor is electrically connected to the gate electrode of the first transistor, the gate electrode of the seventh transistor is electrically connected to the second wiring, and the eighth transistor of the eighth transistor is electrically connected. The electrode 1 is electrically connected to the seventh wiring, the second electrode of the eighth transistor is electrically connected to the gate electrode of the sixth transistor, and the gate electrode of the eighth transistor is electrically connected. Is electrically connected to the gate electrode of the first transistor, and the second drive circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth. The 9th transistor, the 14th transistor, the 15th transistor, and the 16th transistor are provided, and the first electrode of the ninth transistor is electrically connected to the twelfth wiring. The second electrode of the transistor is electrically connected to the tenth wiring, the first electrode of the tenth transistor is electrically connected to the fourteenth wiring, and the second electrode of the tenth transistor is electrically connected. Is electrically connected to the tenth wiring, the gate electrode of the tenth transistor is electrically connected to the twelfth wiring, and the first electrode of the eleventh transistor is electrically connected to the thirteenth wiring. The second electrode of the eleventh transistor is electrically connected to the gate electrode of the fourteenth transistor, and the gate electrode of the eleventh transistor is electrically connected to the eleventh wiring. The first electrode of the twelfth transistor is electrically connected to the fourteenth wiring, and the second electrode of the twelfth transistor is electrically connected to the gate electrode of the fourteenth transistor. The gate electrode of the twelfth transistor is electrically connected to the twelfth wiring, the first electrode of the thirteenth transistor is electrically connected to the thirteenth wiring, and the thirteenth transistor is electrically connected. The second electrode of the thirteenth transistor is electrically connected to the gate electrode of the ninth transistor, the gate electrode of the thirteenth transistor is electrically connected to the eighth wiring, and the first of the fourteenth transistor is connected. The electrodes are electrically connected to the 14th wiring and the 1st
The second electrode of the fourth transistor is electrically connected to the gate electrode of the ninth transistor, the first electrode of the fifteenth transistor is electrically connected to the fourteenth wiring, and the fifteenth transistor is electrically connected. The second electrode of the transistor is electrically connected to the gate electrode of the ninth transistor, the gate electrode of the fifteenth transistor is electrically connected to the ninth wiring, and the gate electrode of the sixth transistor is electrically connected. The electrode 1 is electrically connected to the 14th wiring, and the 1st electrode is connected to the 14th wiring.
The second electrode of the sixth transistor is electrically connected to the gate electrode of the fourteenth transistor, and the gate electrode of the sixteenth transistor is electrically connected to the gate electrode of the ninth transistor. ..

Further, the fourth wiring and the eleventh wiring are electrically connected, the fifth wiring and the twelfth wiring are electrically connected, and the sixth wiring and the thirteenth wiring are connected. The wiring may be electrically connected, and the seventh wiring and the fourteenth wiring may be electrically connected. Further, the fourth wiring and the eleventh wiring are provided with the same wiring, the fifth wiring and the twelfth wiring are provided with the same wiring, and the sixth wiring and the thirteenth wiring are provided. The wiring is the same as the wiring, and the 7th
The wiring of No. 14 and the 14th wiring may be provided by the same wiring. Further, the third wiring and the tenth wiring may be electrically connected. Further, the third wiring and the tenth wiring may be provided with the same wiring. Further, among the values of the ratio W / L of the channel length L and the channel width W of the first transistor to the eighth transistor, the value of W / L of the first transistor is maximized, and the ninth transistor is used. Among the values of the ratio W / L of the channel length L and the channel width W of the transistor or the 16th transistor, the value of W / L of the 9th transistor may be the maximum. Further, the value of the first transistor W / L is set to 2 of the value of the fifth transistor W / L.
The value may be doubled to five times, and the value of the ninth transistor W / L may be doubled to five times the value of the twelfth transistor W / L. Further, the channel length L of the third transistor is set to the eighth.
The channel length L of the eleventh transistor may be made larger than the channel length L of the transistor, and the channel length L of the eleventh transistor may be made larger than the channel length L of the sixteenth transistor. In addition, the first
A capacitive element is provided between the second electrode of the transistor and the gate electrode of the first transistor, and between the second electrode of the ninth transistor and the gate electrode of the ninth transistor. A capacitive element may be provided. Further, the first transistor to the sixteenth transistor may be provided as an N-channel transistor. Further, the first transistor to the sixteenth transistor may be provided by using amorphous silicon as a semiconductor layer.

The liquid crystal display device shown in this embodiment is described in the present specification, and therefore has the same function and effect as other embodiments.

10 Wiring 101 Transistor 101 + Vth
101 + α (Vth)
102 wiring 103 wiring 103 wiring 104 wiring 105 transistor 106 transistor 107 transistor 108 transistor 109 transistor 110 transistor 121 wiring 122 wiring 123 wiring 124 wiring 124 node 125 wiring 126 wiring 127 wiring 128 wiring 129 wiring 130 wiring 131 wiring 132 wiring 133 wiring 134 wiring 135 Wiring 136 Wiring 141 Node 142 Node 151 Capacitive element 152 Transistor 211 Signal 212 Signal 213 Signal 214 Signal 215 Signal 216 Signal 221 Signal 222 Signal 223 Signal 225 Signal 227 Signal 228 Signal 234 Signal 241 Potential 242 Potential 501 Transistor 511 Wiring 701 Wiring 701 Wiring 703 Wiring 704 Wiring 705 Wiring 706 Wiring 707 Wiring 708 Wiring 709 Wiring 710 Wiring 717 Wiring 901 Wiring 1011 Resistance element 1012 Resistance element 1021 Transistor 1022 Transistor 1023 Transit 1024 Wire 1101 Flip flip 1111 Wiring 1112 Wiring 1113 Wiring 1115 Wiring 11 1117 Wiring 1211 Signal 1212 Signal 1213 Signal 1216 Signal 1401 Buffer 1701 Signal line drive circuit 1702 Scan line drive circuit 1703 Pixel 1704 Pixel part 1705 Insulation board 1801 Flip flop 1914 Wiring 2221 Signal 2222 Signal 2223 Signal 2225 Signal 2227 Signal 2228 Signal 2401 Flip flop 2402 Flip Flip 2411 Wiring 2412 Wiring 2413 Wiring 2414 Wiring 2415 Wiring 2416 Wiring 2417 Wiring 2418 Wiring 2419 Wiring 2420 Wiring 2424 Wiring 2511 Signal 2512 Signal 2513 Signal 2514 Signal 2515 Signal 2518 Signal 2519 Signal 2595 Wiring 2702 Scanning line drive circuit 2901 Conductive layer 2903 Conductive layer 2904 Conductive layer 2905 Conductive layer 2906 Conductive layer 2907 Conductive layer 2908 Conductive layer 2909 Conductive layer 2910 Conductive layer 2911 Conductive layer 2912 Conductive layer 2913 Conductive layer 2914 Conductive layer 2915 Conductive layer 2916 Conductive layer 2951 Wiring 2952 Wiring 295 3 wiring 2954 wiring 2955 wiring 2965 wiring 2957 wiring 2985 wiring 2960 wiring 2891 semiconductor layer 2982 semiconductor layer 2983 semiconductor layer 2984 semiconductor layer 2985 semiconductor layer 2896 semiconductor layer 2987 semiconductor layer 2988 semiconductor layer 4201 flip flop 4211 wiring 4212 wiring 4213 wiring 4215 wiring 4215 Wiring 4216 Wiring 4217 Wiring 4218 Wiring 4311 Signal 4312 Signal 4313 Signal 4314 Signal 4315 Signal 4401 Transistor 4402 Transistor 4403 Transistor 4404 Transistor 4405 Transistor 4406 Transistor 4407 Transistor 4408 Transistor 4421 Wiring 4421 Signal 4422 Wiring 4422 Signal 4423 Wiring 4423 Signal 4426 Wire 4427 Wire 4427 Signal 4428 Wire 4428 Signal 4492 Wire 4430 Wire 4431 Wire 4432 Wire 4433 Transistor 4441 Node 4442 Node 4503 Transistor 4521 Signal 4522 Signal 4525 Signal 4527 Signal 4528 Signal 4541 Potential 4542 Potential 8000 Buffer 8011 Wire 8012 Transistor 8202 Transistor 8211 Wiring 8212 Wiring 8213 Wiring 8214 Transistor 8301 Transistor 8302 Transistor 8303 Transistor 8304 Transistor 8311 Wiring 8312 Wiring 8313 Wiring 8314 Transistor 8315 Wiring 8316 Wiring 8341 Node 8401 Transistor 8402 Transistor 8403 Transistor 8404 Transistor 8411 Wiring 8412 Wiring 8416 Wiring 8417 Wiring 8417 Transistor 8541 Transistor 8502 Transistor 8503 Transistor 8511 Wiring 8512 Wiring 8513 Wiring 8514 Wiring 8515 Wiring 8516 Wiring 8541 Node 8601 Transistor 8602 Transistor 8603 Transistor 8604 Transistor 8611 Wiring 8612 Wiring 8613 Wiring 8614 Wiring 86 Scan line drive circuit 1902b Scan line drive circuit 1 902b Drive circuit 2002a Scan line drive circuit 2002b Scan line drive circuit 2802a Scan line drive circuit 2802b Scan line drive circuit 2802b Drive circuit 8001a Inverter 8001b Inverter 8001c Inverter 8002a Inverter 8002b Inverter 8002c Inverter 8003a Inverter 8003b Inverter 8003c Inverter

Claims (2)

It has a pixel and a drive circuit that is electrically connected to the pixel via wiring.
The drive circuit has first to ninth transistors.
One of the source or drain of the first transistor is electrically connected to the wiring.
One of the source or drain of the second transistor is electrically connected to the wiring.
One of the source or drain of the third transistor is electrically connected to the gate of the second transistor.
The other of the source or drain of the third transistor is not electrically connected to the gate of the third transistor and is not electrically connected.
One of the source or drain of the fourth transistor is electrically connected to the gate of the second transistor.
One of the source or drain of the fifth transistor is electrically connected to the gate of the first transistor.
The other of the source or drain of the fifth transistor is not electrically connected to the gate of the fifth transistor and is not electrically connected.
One of the source or drain of the sixth transistor is electrically connected to the gate of the first transistor.
The gate of the sixth transistor is electrically connected to the gate of the second transistor.
One of the source or drain of the seventh transistor is electrically connected to the gate of the first transistor.
One of the source or drain of the eighth transistor is electrically connected to the gate of the second transistor.
The gate of the eighth transistor is electrically connected to the gate of the first transistor.
One of the source or drain of the ninth transistor is electrically connected to the wiring.
The gate of the ninth transistor is electrically connected to the gate of the fourth transistor.
The gate of the ninth transistor is not electrically connected to the other of the source or drain of the third transistor.
The other of the source or drain of the first transistor is input with the first signal.
A second signal is input to the gates of the fourth and ninth transistors.
The other of the source or drain of the second transistor is supplied with a power potential and is supplied with a power potential.
The other of the source or drain of the fourth transistor is supplied with the power potential.
The other of the source or drain of the sixth transistor is supplied with the power potential.
The other of the source or drain of the eighth transistor is supplied with the power potential.
The wiring is a display device that outputs an output signal. In claim 1,
A display device in which W (W is the channel width) / L (L is the channel length) of the first transistor is larger than W / L of the second to ninth transistors.

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