JP7078129B2 - Arithmetic processing device and control method of arithmetic processing device - Google Patents

Description

The present invention relates to an arithmetic processing apparatus and a control method for the arithmetic processing apparatus.

In recent years, SIMD (Single Instruction Multiple) that calculates a plurality of data in parallel based on one instruction code in order to efficiently process data used in image processing using a processor such as a CPU (Central Processing Unit). A method called Data) has been proposed. Hereinafter, the operation using SIMD is referred to as a SIMD operation.

For example, the SIMD operation is used in a convolution operation of deep learning. Specifically, the arithmetic processing apparatus that executes deep learning performs SIMD operations such as performing convolution operations in parallel using a plurality of product-sum arithmetic units for one instruction.

On the other hand, when performing a SIMD operation, the table may be referred to according to the value of each element of the array. For example, it is conceivable to obtain the function value individually for each element of the array. In this case, there is a method of approximating the target function for which the function value is to be obtained by a broken line connecting straight lines having different slopes for each section, and calculating the approximate value of each function value using the straight line in the section to which each element belongs. The process of approximating the target function for which the function value is obtained by a polygonal line connecting straight lines having different slopes for each interval may be called linear interpolation.

In such an approximation by a polygonal line, the division to which the graph belongs is determined by the value of the element, so that the division to which the graph belongs is different for each element. Therefore, an approximate value of the function for each element is calculated using a linear equation having a different slope and intercept for each element. Therefore, prepare a look-up table (LUT: Look Up Table) in which the slope and intercept of each division are arranged as a set, and refer to the table by inputting the value obtained by dividing the element value only by the upper digit. A method of calculating a linear equation based on the value obtained from the above to obtain an approximate value can be considered.

For example, in a recent instruction set, an instruction that refers to a look-up table for each element in a SIMD operation may be prepared. Further, the GPU (Graphical Processing Unit) may be equipped with an interpolator dedicated to interpolation calculation.

Further, there is a prior art technique in which a data element stored in one or more table registers to be updated is selected from an index value stored in the index register, and a position in the result register corresponding to the selected data element is determined. .. Further, there is a conventional technique of dividing a register file into four banks, designating a plurality of registers with one operand, and accessing the four registers at the same time.

Japanese Unexamined Patent Publication No. 2005-174294 Japanese Unexamined Patent Publication No. 2002-149400

J. A. Pineiro, S. F. Oberman, J. M. Muller, and J. D. Bruguera, “High-speed function approximation using a minimax quadratic interpolator,” IEEE Trans. Computers, vol. 54, no. 3, pp. 304-318, 2005.

However, conventional techniques may have significant disadvantages. For example, when the instruction provided in the instruction set is used, conventionally, the contents of the address of the corresponding entry in the target table are read from the memory after the value of the element is fixed. In this case, the overhead of address calculation of each element, reading from memory, and data delivery to the position corresponding to the target SIMD element is large, and when the lookup table reference is processed to SIMD at high speed, a large delay may occur. There is.

Further, in the interpolator mounted on the GPU, it is common to add a large dedicated circuit in order to store a table of parameters based on the arithmetic unit. However, there is a great demand to improve the mounting density of the arithmetic unit on the LSI as much as possible, and it is difficult to mount a dedicated interpolator with many additional circuits.

Further, even if the conventional technique of selecting the result register via the updated table register is used, it is difficult to keep the circuit scale small because the area of the table register is secured. Further, even in the conventional technique of accessing a plurality of registers at the same time with one operand, the register size becomes large depending on the size of the table stored in each register, so that the circuit scale becomes large by arranging a plurality of registers. There is a risk of becoming.

The disclosed technique has been made in view of the above, and an object of the present invention is to provide an arithmetic processing apparatus and a control method of the arithmetic processing apparatus in which the processing efficiency is improved while keeping the circuit scale small.

In one embodiment of the arithmetic processing apparatus and the control method of the arithmetic processing apparatus disclosed in the present application, the storage unit has a plurality of element storage areas, and the plurality of arithmetic values are stored one by one in each of the element storage areas. do. The arithmetic unit is a product-sum arithmetic unit having a multiplier and an adder, generates a first selection value based on the input element data, and stores the first selection value in the element storage area based on the first selection value. The process of acquiring the first calculated value from the calculated values and acquiring the calculated result based on the first calculated value is performed by using the multiplier and the adder .

In one aspect, the present invention can improve processing efficiency while keeping the circuit scale small.

FIG. 1 is an overall configuration diagram of an information processing device. FIG. 2 is a detailed circuit diagram of the product-sum calculation unit. FIG. 3 is a diagram showing a polygonal line approximation used in the first embodiment. FIG. 4 is an example of a look-up table used to obtain the function value of the linear approximation function. FIG. 5 is a diagram showing values stored in the element register according to the first embodiment. FIG. 6 is a diagram for explaining the transition of the state of the element register until the value of the intercept corresponding to the given element data is acquired. FIG. 7 is a diagram for explaining the transition of the state of the element register from the acquisition of the intercept value to the acquisition of the operation result. FIG. 8 is a diagram of an example of a program for causing the product-sum calculation unit to perform the operations shown in FIGS. 5 to 7. FIG. 9 is a flowchart of processing of SIMD operation instructions. FIG. 10 is a flowchart of a process for executing a table search operation for each element data in a SIMD operation. FIG. 11 is a diagram showing an example of the values of the table stored in the vector register according to the second embodiment. FIG. 12 is a diagram of an example of a program for causing the product-sum calculation unit to perform an operation for obtaining the power of 2.

Hereinafter, examples of the arithmetic processing apparatus and the control method of the arithmetic processing apparatus disclosed in the present application will be described in detail with reference to the drawings. The following embodiments do not limit the arithmetic processing apparatus and the control method of the arithmetic processing apparatus disclosed in the present application.

FIG. 1 is an overall configuration diagram of an information processing device. The information processing apparatus 50 includes a PCI (Peripheral Component Interconnect) card 1 and a host computer 2. The PCI card 1 and the host computer 2 are connected by a PCI bus, and data is transmitted to and received from each other.

The host computer 2, for example, performs overall management when performing deep learning. When executing deep learning, the host computer 2 instructs the PCI card 1 to execute a predetermined operation in deep learning such as a convolution operation. Further, the host computer 2 instructs the PCI card 1 to execute the SIMD operation such as referring to the table for each element data included in the array used for the SIMD operation and acquiring the function value.

The PCI card 1 receives an instruction from the host computer 2, executes an operation, and outputs the operation result to the host computer 2. As shown in FIG. 1, the PCI card 1 has a plurality of processing units 10, an overall instruction control unit 11, a memory controller 12, a memory 13, and a PCI control unit 14. This PCI card 1 corresponds to an example of a "arithmetic processing device".

The PCI control unit 14 receives from the host computer 2 an operation command instructing execution of an operation and an input of operation data used in the operation. Then, the PCI control unit 14 outputs the acquired arithmetic instructions and arithmetic data to the memory controller 12.

Further, the PCI control unit 14 receives the input of the calculation result for the instructed calculation from the memory controller 12. Then, the PCI control unit 14 outputs the calculation result to the host computer 2.

The memory controller 12 receives input of calculation instructions and calculation data used in the calculation from the PCI control unit 14. Then, the memory controller 12 stores the acquired calculation instruction and calculation data in the memory 13.

Further, the memory controller 12 receives an instruction from the general instruction control unit 11 to store the calculation data used when executing the calculation in the vector register 111. Then, the memory controller 12 stores the designated calculation data in the vector register 111 of the designated product-sum calculation unit 100. Here, when the memory controller 12 transmits data to the processing unit 10 in the subsequent stage among the processing units 10 arranged in series, the memory controller 12 bypasses the product-sum calculation unit 100 and outputs the calculation data to the multiplexer 103.

Further, when the memory controller 12 receives an instruction to store the calculation result from the general instruction control unit 11, the memory controller 12 acquires the calculation result from the vector register 111 of the designated product-sum calculation unit 100 and stores it in the memory 13. Further, when the memory controller 12 receives an instruction from the host computer 2 via the PCI control unit 14, the memory controller 12 reads out the calculation result stored in the memory 13 and outputs it to the PCI control unit 14.

The general instruction control unit 11 manages the entire operation instructed to be executed by the host computer 2. The general instruction control unit 11 receives an instruction from the host computer 2 via the PCI control unit 14, reads the entire instruction sequence stored in the memory 13 one after another, and executes the instruction. The whole instruction includes an instruction to transfer an operation instruction sequence from the memory 13 to the operation instruction buffer 102, an instruction to store operation data from the memory 13 in the vector register 111, and an operation instruction sequence stored in the operation instruction buffer 102 to control the operation instruction. There are an instruction to start execution in the unit 101, an instruction to store the operation result stored in the vector register 111 in the memory 13, an instruction to end the execution of the instruction sequence, and the like.

The general instruction control unit 11 causes the processing unit 10 to execute the operation instruction sequence. When the processing unit 10 is made to execute the calculation, the general instruction control unit 11 instructs the memory controller 12 to acquire the calculation data used when executing the calculation. Further, when the calculation in the processing unit 10 is completed, the general instruction control unit 11 instructs the memory controller 12 to store the calculation result. Further, when all the processes of the operations instructed to be executed are completed, the general instruction control unit 11 notifies the memory controller 12 of the completion of the operations.

Next, the processing unit 10 will be described. As shown in FIG. 1, a plurality of processing units 10 are mounted on one PCI card 1. A plurality of each processing unit 10 are connected in parallel and in series. The number of processing units 10 is 128 in one embodiment. The processing unit 10 includes a product-sum calculation unit 100, a calculation instruction control unit 101, a calculation instruction buffer 102, and a multiplexer 103.

The operation instruction control unit 101 manages and controls the execution process of the operation instruction. The operation command control unit 101 receives instructions for executing individual operations from the overall instruction control unit 11. The instructions that can be executed by the processing unit 10 are called arithmetic instructions in comparison with the whole instructions. The instructions include arithmetic instructions in the narrow sense that cause the product-sum calculation unit to perform operations, as well as general-purpose registers (not shown). It includes operation instructions, branch instructions, repeat instructions, instructions to stop the execution of an instruction sequence, and the like.

The operation instruction control unit 101 acquires the operation instructions stored in the operation instruction buffer 102 in the order of execution. Next, the operation instruction control unit 101 instructs the vector register 111 to output the operation data specified by the acquired operation instruction. Further, the arithmetic instruction control unit 101 outputs an instruction to execute the arithmetic to the multiply-accumulate arithmetic unit 112 according to the acquired arithmetic instruction. After that, the arithmetic instruction control unit 101 loops the arithmetic using the arithmetic result in the multiply-accumulate arithmetic unit 112. Further, the operation instruction control unit 101 issues, for example, an execution instruction of a SIMD operation that refers to a table for each element data and acquires a function value.

The operation instruction buffer 102 is a storage area for storing an operation instruction sequence. The operation instruction buffer 102 stores the operation instruction sequence input from the memory controller 12 in the order of input from the instructed address. After that, in response to the operation instruction acquisition request from the operation instruction control unit 101, the operation instruction buffer 102 outputs the operation instruction of the requested address to the operation instruction control unit 101.

The product-sum calculation unit 100 has a vector register 111 and a product-sum calculation unit 112. However, the vector register 111 included in the product-sum calculation unit 100 corresponds to a part of the entire vector register mounted on the processing unit 10.

The vector register 111 receives the input of the calculation data used when executing the calculation from the memory controller 12, and stores the input calculation data. After that, the vector register 111 receives an instruction from the arithmetic instruction control unit 101 and outputs the arithmetic data used in the arithmetic to the multiply-accumulate arithmetic unit 112. Further, after the loop processing of the calculation by the multiply-accumulate calculator 112 is completed, the vector register 111 receives the calculation result of the product-sum calculator 112. Then, when an instruction to output to the memory 13 is received from the memory controller 12, the vector register 111 outputs the calculation result stored in the instructed area to the multiplexer 103.

Further, in the case of a SIMD operation in which a function value is acquired by referring to a table for each element data, the vector register 111 holds the value of the table corresponding to the section to which the element data belongs.

The product-sum calculation unit 112 receives an instruction to execute a calculation from the calculation instruction control unit 101. Then, the product-sum calculation unit 112 executes the product-sum calculation using the calculation data input from the vector register 111. After that, the product-sum calculation unit 112 outputs the calculation result to the vector register 111. When the cumulative operation is instructed by the instruction, the multiply-accumulate operation unit 112 holds the cumulative operation result in a register (accumulator) in the operation unit and uses it in the subsequent cumulative operation instruction.

In the case of the product-sum accumulation operation, the product-sum calculator 112 repeats the product-sum operation on the value input from the vector register 111 until all the operations are completed. After that, when the loop processing of the product-sum accumulation operation is completed, the product-sum calculation unit 112 outputs the calculation result to the vector register 111 and stores it.

Further, in the case of the SIMD operation in which the function value is acquired by referring to the table for each element data, the multiply-accumulate unit 112 switches the reference destination of the vector register 111 to the coefficient included in the function corresponding to the input element data. At the same time, it is sequentially acquired from the vector register 111. Then, the product-sum calculator 112 calculates the function value for each element data using the acquired factor. After that, the product-sum calculation unit 112 outputs the calculation result to the vector register 111 and stores it.

Here, with reference to FIG. 2, the processing of the SIMD operation for acquiring the function value by referring to the table for each element data by the product-sum calculation unit 100 will be described in detail. FIG. 2 is a detailed circuit diagram of the product-sum calculation unit. In FIG. 2, for easy understanding, a signal input path extending from the arithmetic instruction control unit 101 to the vector register 111A, the product-sum arithmetic unit 112A, and the multiplexer 122A is described. However, in reality, the input path from the arithmetic instruction control unit 101 extends to the other vector registers 111B to 111C, the multiply-accumulate arithmetic units 112B to 112C, and the multiplexers 122B to 122C.

As shown in FIG. 2, the product-sum calculation unit 100 has a plurality of product-sum calculation units 112 shown in FIG. Here, each product-sum calculator 112 is represented as a product-sum calculator 112A to 112C. Further, the product-sum calculation unit 100 has a vector register 111 divided into units called banks. Here, each vector register 111 divided into bank units is represented as vector registers 111A to 111C. The vector registers 111A to 111C correspond to the multiply-accumulate calculators 112A to 112C on a one-to-one basis, respectively. Further, in the product-sum calculation unit 100, the indirect address registers 121A to 121C and the multiplexers 122A to 122C are arranged corresponding to the vector registers 111A to 111C. In the following description, when they are not distinguished, they are referred to as an element register 113, a product-sum calculator 112, an indirect address register 121, and a multiplexer 122.

The vector registers 111A to 111C are, for example, RAM (Random Acccess Memory). In this embodiment, a total of eight vector registers 111A to 111C are arranged. The case where the vector register 111A corresponds to the bank # 0, the vector register 111B corresponds to the bank # 1, and the vector register 111C corresponds to the bank # 7 will be described.

Further, the vector register 111A has a plurality of element registers 113A. Further, the vector register 111B has a plurality of element registers 113B. The vector register 111C has a plurality of element registers 113C. Here, the vector register 111A will be described as an example.

Each element register 113A corresponds to a unit called a line to which a register number is assigned. Here, the numerical value representing the register number is referred to as the "address" of the vector register 111. That is, an address is assigned to each element register 113A. Here, the case where each element register 113A corresponding to the lines ## 0 to ## 511 exists will be described.

The vector register 111A has a read port and a write port for supplying a plurality of operands used for calculation in each cycle to the multiply-accumulate calculator 112A and writing back the calculation result to any element register 113A in each cycle. .. In this embodiment, the vector register 111A has three read ports for the multiply-accumulate unit 112A.

Here, in this embodiment, each read port of the vector register 111A is directly connected to the product-sum calculator 112A, but the connection is not limited to this and may be via a router. When passing through the router, one read port may be connected to the multiply-accumulate calculator 112A to 112C via the router, and the other read port may be directly connected to the product-sum calculator 112A. Further, a plurality of read ports may be connected to the multiply-accumulate calculators 112A to 112C via a router. When passing through a router, the data output from the read port can be supplied as an operand to any of the multiply-accumulate calculators 112A to 112C.

Here, in this embodiment, the acquisition of the function value when the polygonal line approximation shown in FIG. 3 is performed will be described as an example. FIG. 3 is a diagram showing a polygonal line approximation used in the first embodiment.

In this embodiment, the product-sum calculation unit 100 receives an instruction to acquire a function value for a function as shown in the graph 202 obtained by linearly approximating y = f (x) shown in the graph 201. As shown in Graph 202, the function after linear approximation is a linear function of f ₁ (x) = −0.5 (x-1) + 1 in the interval D1. That is, the function after linear approximation is a linear function having a slope of −0.5 and an intercept of 1.5 in the interval D1. The function after linear approximation is a linear function of f ₂ (x) = 0 (x-2) + 0.5 in the interval D2. That is, the function after linear approximation is a linear function having a slope of 0 and an intercept of 0.5 in the interval D2. The function after linear approximation is a linear function of f ₃ (x) = 0.5 (x-3) + 0.5 in the interval D3. That is, the function after linear approximation is a linear function having a slope of 0.5 and an intercept of −1.0 in the interval D3. The function after linear approximation is a linear function of f ₄ (x) = 2 (x-4) + 1 in the interval D4. That is, the function after linear approximation is a linear function having a slope of 2 and an intercept of −7.0 in the interval D4. The function after linear approximation is a linear function of f ₅ (x) = 0.5 (x-5) + 3 in the interval D5. That is, the function after linear approximation is a linear function having a slope of 0.5 and an intercept of 0.5 in the interval D5. Each function after this linear approximation corresponds to an example of "a predetermined number of functions of the same type". In this case, a function of the same type refers to a function having a different coefficient.

When the value of the interval is input, the table used to obtain the function value of the linear approximation function represented by the graph 202 is the look-up table 210 shown in FIG. FIG. 4 is an example of a look-up table used to obtain the function value of the linear approximation function. In this case, the element registers 113A to 113C store the slope value and the intercept value shown in the lookup table 210. The value of each slope and the value of the intercept stored in the vector register 111 correspond to an example of the "calculated value".

More specifically, the values shown in FIG. 5 are stored in the element registers 113A to 113C. FIG. 5 is a diagram showing values stored in the element register according to the first embodiment. In FIG. 5, the vector registers 111A to 111C are represented by the names of banks # 1 to # 7 representing each. Here, the case where the linear approximation function of the graph 202 is divided into 16 sections in total will be described. That is, the linear approximation function is represented by 16 linear functions.

When acquiring the function value of the linear approximation function, as shown in FIG. 5, the linear function in each interval D1 to D5 of the linear approximation function is stored in the element registers 113A to 113C of the vector registers 111A to 111C at the addresses 0x000 to 0x00F. The intercept value of is stored. Here, the element registers 113A to 113C at addresses 0x000 to 0x00F are used as the intercept address unit 301. Further, the values of the slopes of the linear functions in the sections D1 to D5 of the linear approximation function are stored in the element registers 113A to 113C at the addresses 0x010 to 0x01F of the vector registers 111A to 111C. Here, the element registers 113A to 113C at the addresses 0x010 to 0x01F are used as the tilted address unit 302.

In this way, the intercept address unit 301 and the slope address unit 302 store the coefficients of the same linear approximation function at the same positions counted from the beginning. This state corresponds to the state of "continuously holding a predetermined number of coefficients corresponding to each term of each function for each position". In the case of this embodiment, the predetermined number of coefficients are two coefficients, the intercept value and the slope value. Each term of the function corresponds to a term representing the slope and a term representing the intercept in the linear function.

Further, the value of each element data included in the array used for the SIMD operation is stored in the element registers 113A to 113C at the addresses m of the vector registers 111A to 111C by the memory controller 12. More specifically, element data having a fixed decimal value of 16 bits is stored in the lower ranks of the element registers 113A to 113C at the address m. Here, the case where the lower 12 bits of the 16-bit fixed-point value is a fractional part will be described. This fixed-point format may be expressed as "Q12". Further, as the operation progresses, the vector registers 111A to 111C store the intercept address, the intercept value, the slope address, and the function value which is the operation result corresponding to each element data. Here, the case where the multiplication result and the cumulative value are 32-bit fixed-point numbers and the lower 24 bits are decimal numbers will be described. This fixed-point format may be expressed as "Q24".

Further, the vector registers 111A to 111C receive an address input from the corresponding indirect address registers 121A to 121C. Then, the vector registers 111A to 111C output the values stored in the element registers 113A to 113C of the input address to the multiply-accumulate arithmetic units 112A to 112C.

When the calculation is completed, the vector registers 111A to 111C output the calculation result to the memory controller 12 in response to an instruction from the memory controller 12. The vector registers 111A to 111C correspond to an example of the "storage unit". The element registers 113A to 113C correspond to an example of the "element storage area".

The indirect address registers 121A to 121C are, for example, FF (Flip-Flop). When the SIMD calculation using the linear approximation function is executed, the data is not stored in the indirect address registers 121A to 121C before the start of the calculation. Then, the indirect address registers 121A to 121C store indirect addresses indicating the addresses in which the intercepts or slopes in the vector registers 111A to 111C, which are generated in the middle of the operation for obtaining the function value, are stored. After that, the indirect address registers 121A to 121C output the holding values to the vector registers 111A via the multiplexers 122A to 122C. The indirect address registers 121A to 121C correspond to an example of the "indirect storage unit".

The multiplexers 122A to 122C receive two inputs, an input from the indirect address registers 121A to 121C and an input from the memory controller 12. Then, the multiplexers 122A to 122C select one of the two inputs in response to an instruction from the arithmetic instruction control unit 101. After that, the multiplexers 122A to 122C output the selected input to the vector registers 111A to 111C.

Next, the functions of the multiply-accumulate calculators 112A to 112C will be described with reference to FIGS. 6 and 7. FIG. 6 is a diagram for explaining the transition of the state of the element register until the value of the intercept corresponding to the given element data is acquired. Further, FIG. 7 is a diagram for explaining the transition of the state of the element register from the acquisition of the intercept value to the acquisition of the operation result. The multiply-accumulate calculators 112A to 112C correspond to an example of the "calculation unit".

As shown in FIG. 6, the multiply-accumulate calculator 112A shifts the value of the element data stored in the address m of the vector register 111A to the right by 12 bits and acquires the upper 4 bits. Then, the multiply-accumulate calculator 112A stores the acquired 4-bit data in the element register 113A at the address n (step S1). The 4-bit data stored in the element register 113A at the address n is the address of the element register 113A that holds the value of the intercept corresponding to the element data. Hereinafter, the 4-bit data stored in the element register 113A of the address n is referred to as an intercept address. This intercept address corresponds to an example of the "first selection value" and the "first number".

Next, the multiply-accumulate calculator 112 acquires the intercept address stored in the element register 113A of the address n and sets it in the indirect address register 121A (step S2). Next, 1.0, which is a value input from the memory controller 12, is stored in the element register 113A at the address p. After that, the intercept address set in the indirect address register 121A is input to the vector register 111A (step S3), and the multiply-accumulate unit 112 acquires the intercept value output from the element register 113A of the intercept address. .. Further, the product-sum calculator 112 acquires 1.0 from the element register 113A at the address p. Then, the product-sum calculator 112 stores the value obtained by multiplying the intercept value by 1.0 in the element register 113A at the address q (step S4). The value of the intercept stored by the product-sum calculator 112 corresponds to an example of the "first calculated value" and the "first coefficient".

Next, as shown in FIG. 7, the multiply-accumulate calculator 112 acquires the value stored in the element register 113A at the address n. Then, the product-sum calculator 112 adds 16 which is the number of linear functions included in the linear approximation function to the acquired value, and stores it in the element register 113A of the address n again (step S5). At this time, the data stored in the element register 113A at the address n is the address of the element register 113A holding the value of the slope corresponding to the element data. In the following, the value stored in the element register 113A of the address n at this time is referred to as a tilted address. Here, the value of each intercept and the value of the slope are stored in the vector register 111 every 16 pieces. That is, by adding 16, it is possible to generate a tilted address indicating a position in the tilted address section 302 that is the same as the position in the section address section 301 of the element register 113A specified by the intercept address. This tilt address corresponds to an example of the "second selection value" and the "second number".

Next, the multiply-accumulate calculator 112 acquires the tilted address stored in the element register 113A of the address n and sets it in the indirect address register 121A (step S6).

After that, the tilt address set in the indirect address register 121A is input to the vector register 111A (step S7), so that the multiply-accumulate calculator 112 acquires the tilt value output from the element register 113A of the tilt address. .. The value of this slope corresponds to an example of the "second calculated value" and the "second coefficient".

Further, the product-sum calculator 112A acquires element data from the element register 113A at the address m. Further, the multiply-accumulate calculator 112A acquires the intercept value from the element register 113A at the address q. Then, the product-sum calculator 112 multiplies the slope value and the element data, adds the intercept value to the multiplied result, and obtains the function value of the linear approximation function corresponding to the element data. After that, the product-sum calculator 112 stores the obtained function value in the element register 113A at the address q (step S6).

FIG. 8 is a diagram of an example of a program for causing the product-sum calculation unit to perform the operations shown in FIGS. 5 to 7. In the following, a process of causing the product-sum calculation unit 100 to execute the program using the line number on the left end of the paper will be described. In the program of FIG. 8, the element registers 113A of the addresses m, n, p, and q are represented as FR # m, # n, # p, and # q, respectively. Further, the indirect address register 121A is represented as IND_REG.

The first line acquires a fixed-point value from the element register 113A at address m, shifts the acquired fixed-point value to the right by 12 bits, acquires the upper 4 bits, and uses the acquired 4-bit data as the element register at address n. It represents the process of setting to the lower 4 bits of 113A. This 4-bit data is the intercept address.

The second line represents a process of storing the intercept address set in the element register 113A of the address n in the indirect address register 121A.

The third line represents a process of storing 1.0 in the element register 113A at the address p.

The fourth line represents a process of multiplying the value stored in the indirect address register 121A by the value stored in the element register 113A of the address p and storing the multiplication result in the element register 113A of the address q. That is, the fourth line corresponds to the process of storing the intercept value stored in the indirect address register 121A in the element register 113A of the address q. Up to this point, the process shown in FIG. 6 is completed.

The fifth line represents a process of adding 0x010 to the value stored in the element register 113A of the address n and storing the tilted address as the addition result in the indirect address register 121A. 0x010 corresponds to 16 addresses, and the fifth line corresponds to the process of shifting the addresses by 16.

The sixth line corresponds to a process of acquiring the tilted address stored in the element register 113A of the address n and storing it in the indirect address register 121A.

The seventh line represents the following processing. First, one process is to acquire the tilt address stored in the indirect address register 121A, acquire the tilt stored in the element register 113A of the tilt address, and multiply it by the element data stored in the element register 113A of the address m. Is. Next, the second process is a process of adding the multiplication result to the intercept stored in the element register 113A at the address q. As a result, the calculation result is stored in the element register 113A at the address q.

Next, the flow of processing of the SIMD operation instruction will be described with reference to FIG. FIG. 9 is a flowchart of processing of SIMD operation instructions. Here, processing in each vector register 111 represented as an arbitrary bank #i will be described as an example.

The vector register 111 of the bank # i determines whether or not the instruction input from the operation instruction control unit 101 is a read instruction from the indirect address register 121 (step S101).

If the instruction is a read instruction from the indirect address register 121 (step S101: affirmative), the vector register 111 reads the address from the multiplexer 122. Then, the vector register 111 sets the address read from the indirect address register 121 to the read address in the output port corresponding to the input port connected to the multiplexer 122 (step S102).

On the other hand, when the instruction is not a read instruction from the indirect address register 121 (step S101: negation), the vector register 111 performs the following processing. That is, the vector register 111 sets the address given and modified by the instruction to the read address in the output port corresponding to the input port connected to the multiplexer 122 (step S103).

Next, the vector register 111 sets the address given and modified by the instruction to the read address in the other output port (step S104).

The vector register 111 reads out the contents of the element register 113 according to the address set as the read address, outputs the contents from each output port, and sets them as an operand (step S105).

Next, the multiply-accumulate arithmetic unit 112 determines whether or not the instruction input from the arithmetic instruction control unit 101 is a write instruction to the indirect address register 121 (step S106).

If the instruction is not a write instruction to the indirect address register 121 (step S106: negation), the multiply-accumulate unit 112 receives the input of each operand from its own input port corresponding to each output port of the vector register 111. Then, the product-sum calculator 112 executes the operation specified by the instruction using each operand, and sets the operation result in the operation result register owned by itself (step S107).

Next, the multiply-accumulate calculator 112 sets the qualified address given by the instruction as the write address in the write port (step S108).

After that, the multiply-accumulate calculator 112 writes the contents of the calculation result register to the element register 113 designated by the write address using the write port (step S109).

On the other hand, when the instruction is a write instruction to the indirect address register 121 (step S106: affirmative), the vector register 111 sets a predetermined operand in the indirect address register 121 (step S110).

Next, with reference to FIG. 10, the flow of the process of executing the table search operation for each element data in the SIMD operation will be described. FIG. 10 is a flowchart of a process for executing a table search operation for each element data in a SIMD operation.

The administrator arranges the value of the table to be referred to in the operation in the element register 113 having a predetermined number in the vector register 111 (step S201).

The product-sum calculator 112 processes the input value so that it becomes an address used for reference to the vector register 111 (step S202). Here, the input value is, for example, element data at the start of the operation, and is, for example, the operation result during the operation.

After that, the multiply-accumulate calculator 112 stores the address used for reference to the vector register 111 in the vector register 111. The vector register 111 writes an address used for reference to the stored vector register 111 to the indirect address register 121 (step S203).

Next, the multiply-accumulate calculator 112 reads out the contents of the element register 113 with the value stored in the indirect address register 121 as an address, and uses it for the calculation together with other operands (step S204).

After that, the product-sum calculator 112 determines whether or not the calculation is completed (step S205). If the calculation is not completed (step S205: negation), the multiply-accumulate calculator 112 returns to step S202.

On the other hand, when the calculation is completed (step S205: affirmative), the multiply-accumulate calculator 112 stores the calculation result in the vector register 111 and completes the calculation process.

As described above, the product-sum calculation unit according to the present embodiment registers the value of the table in the vector register when executing the calculation by referring to the table, and the element data or other input values. Is used to generate the address used to refer to the vector register by multiply-accumulate operation. Then, the product-sum calculation unit stores the generated address in the indirect address register. Then, the product-sum calculation unit acquires the value of the table from the vector register using the value stored in the indirect address as the read address and performs the calculation. By providing the indirect address register for each bank in this way, it is possible to efficiently refer to the table and execute the calculation with a small number of instructions. Then, different contents can be read out for each bank, and the calculation for each SIMD element data can be processed at high speed. That is, the processing efficiency can be improved while keeping the circuit scale small.

Here, in this embodiment, an operation using a function that performs approximation or interpolation using a polynomial having a different coefficient for each division has been described as an example, but the operation that can be used is not limited to this, and the calculation is performed with reference to a table. Any other operation may be used as long as it is an operation for performing a table search for each element data. For example, in Newton's method or other convergence operations, operations that acquire different initial values and parameters for each division may be used.

Next, Example 2 will be described. The product-sum calculation unit according to this embodiment executes an operation for obtaining a power of 2 using the element data as a power. The information processing apparatus according to this embodiment also has the configurations shown in FIGS. 1 and 2. In this embodiment, the case where each element data used in the SIMD operation has an 8-bit fixed point number will be described. Specifically, each element data is represented using a two's complement representation, and the lower 7 bits are decimals (“Q7 representation”). That is, each element data is represented by an 8-bit representation of sxxxxyyy, and if s = 0, it is a binary number 0. It represents xxxyyyy, and if s = 1, it is a binary number 0. Represents xxxyyyy-1000000000. Further, the calculation result will be described in the case of obtaining in the FP32 format which is a single precision floating point number.

FIG. 11 is a diagram showing an example of table values stored in the vector register according to the second embodiment. As shown in FIG. 11, each element register 113 of the vector register 111 has 16 powers that can be calculated as a power of 2 when the number of the upper 4 bits of the element data is a power number at addresses 00 to 0F. The value of is stored. Further, in the addresses 10 to 1F of the element register 113, 16 values that can be the calculation result of a power of two when the number of the lower 4 bits of the element data is taken as a power are stored. Before executing the operation, the element data is stored in the element register 113 at the address #m.

The product-sum calculator 112 acquires element data from the element register 113 at address #m. Then, the product-sum calculator 112 takes the logical product of the acquired element data and 0x0000000F0, and acquires the data in which the bits lower than the upper 4 bits of the element data are 0. In the following, the data in which the bits lower than the upper 4 bits of the element data are 0 are referred to as data representing the upper 4 bits of the element data. After that, the multiply-accumulate calculator 112 stores the data representing the upper 4 bits of the acquired element data in the element register 113 of the address # x.

Next, the product-sum calculator 112 acquires element data from the element register 113 at address #m. Then, the product-sum calculator 112 takes the acquired element data and the logical product of 0x00000000F, and acquires the data in which the bits higher than the lower 4 bits of the element data are set to 0. In the following, the data in which the bits higher than the lower 4 bits of the element data are 0 are referred to as the data representing the lower 4 bits of the element data. After that, the multiply-accumulate calculator 112 stores the data representing the lower 4 bits of the acquired element data in the element register 113 of the address #y.

Next, the product-sum calculator 112 stores 1.0 in the element register 113 of the address #r, which is a result register.

Next, the multiply-accumulate calculator 112 acquires data representing the upper 4 bits of the element data stored in the element register 113 of the address #x. Then, the multiply-accumulate calculator 112 shifts the upper 4 bits of the element data to the lowest bit, and generates data in which the data in the upper 4 bits at the address #m is moved to the lower 4 bits. After that, the multiply-accumulate calculator 112 stores the data obtained by moving the upper 4 bits to the lower 4 bits in the element register 113 of the address # x.

Further, the multiply-accumulate calculator 112 acquires data representing the lower 4 bits of the element data stored in the element register 113 of the address #y. Then, the multiply-accumulate calculator 112 adds 0x010, which is the first address of the value of the table used for the calculation of the lower 4 bits, to the data representing the lower 4 bits of the element data. After that, the multiply-accumulate calculator 112 stores the data obtained by adding 0x010 to the data representing the lower 4 bits of the element data in the element register 113 of the address #y.

Next, the multiply-accumulate calculator 112 acquires data obtained by moving the upper 4 bits of the element data stored in the element register 113 of the address #x to the lower 4 bits. Next, the product-sum calculator 112 stores the data obtained by moving the upper 4 bits to the lower 4 bits in the indirect address register 121. This data corresponds to the address where the calculation result when the power of 2 is calculated with the upper 4 bits of the element data as the power is stored.

After that, the product-sum calculator 112 acquires the contents of the element register 113 whose address is the value stored in the indirect address register 121. This acquired value corresponds to the calculation result when the power of 2 is calculated with the upper 4 bits of the element data as the power. Then, the product-sum calculator 112 multiplies the acquired value by the value stored in the element register 113 of the address # r and stores it in the element register 113 of the address # r.

Next, the multiply-accumulate calculator 112 acquires a value obtained by adding 0x010 to the data of the lower 4 bits of the element data stored in the element register 113 of the address #y. Next, the multiply-accumulate calculator 112 stores the value obtained by adding 0x010 to the data of the lower 4 bits of the element data in the indirect address register 121. The value obtained by adding 0x010 to the data of the lower 4 bits of the element data corresponds to the address where the calculation result when the power of 2 is calculated with the lower 4 bits of the element data as the power is stored.

After that, the product-sum calculator 112 acquires the contents of the element register 113 whose address is the value stored in the indirect address register 121. This acquired value corresponds to the calculation result when the power of 2 is calculated with the lower 4 bits of the element data as the power. Then, the product-sum calculator 112 multiplies the acquired value by the value stored in the element register 113 of the address # r and stores it in the element register 113 of the address # r. As a result, the operation of the power of 2 with the element data as the power is completed.

Here, the product-sum calculation unit 100 according to this embodiment uses the relationship of EXP2 (X + Y) = EXP2 (X) × EXP2 (Y) to obtain the power of 2 with the element data as the power. Specifically, the product-sum calculation unit 100 decomposes the element data into the sum of the number of the upper 4 bits and the number of the lower 4 bits, and stores the value of the power of 2 having each as the power in the vector register 111. By acquiring from the obtained values and multiplying them, the power of 2 with the element data as the power is obtained.

FIG. 12 is a diagram of an example of a program for causing the product-sum calculation unit to perform an operation for obtaining the power of 2.

The first line represents a process of storing data representing the upper 4 bits of the element data in the element register 113 of the address x.

The second line represents a process of storing data representing the lower 4 bits of the element data in the element register 113 of the address y.

The third line represents a process of storing 1.0 in the element register 113 of address # r, which is a result register.

The fourth line represents a process of shifting the data representing the upper 4 bits of the element data to the lowest.

The fifth line represents a process of adding the address of the start position of the value of the table used for the calculation of the lower 4 bits to the data representing the lower 4 bits of the element data.

The sixth line represents a process of setting the data representing the upper 4 bits of the element data in the indirect address register 121.

The seventh line represents a process of acquiring a value from the element register 113 whose address is the value set in the indirect address register 121 and multiplying it by the value of the element register 113 of the address # r which is the result register.

The eighth line represents a process of setting the value obtained by adding 0x010 to the data representing the lower four bits of the element data in the indirect address register 121.

The ninth line represents a process of acquiring a value from the element register 113 whose address is the value set in the indirect address register 121 and multiplying it by the value of the element register 113 of the address # r which is the result register.

In this case, the data representing the upper 4 bits of the element data corresponds to an example of the "first selection value". Then, the calculation result when the power of 2 is calculated with the upper 4 bits of the element data as the power is an example of the "first calculation value". Further, the data representing the lower 4 bits of the element data corresponds to an example of the "second selection value". Then, the calculation result when the power of 2 is calculated with the upper 4 bits of the element data as the power is an example of the "second calculation value".

As described above, the product-sum calculation unit according to the present embodiment determines a value that can be taken as a result of exponentiation when the number of the upper 4 bits and the number of the lower 4 bits of the element data are each set to the power. Store in a vector register. Then, the product-sum calculation unit according to the present embodiment stores the number of the upper 4 bits and the number of the lower 4 bits of the element data in the indirect address register, searches the vector register using the stored values, and performs the element data. The calculation result of the power of 2 is acquired when the number of the upper 4 bits and the number of the lower 4 bits of are used as the register. After that, the product-sum calculation unit acquires the calculation result of the power of 2 when the element data is used as a power by multiplying the two acquired values.

In this case as well, it is possible to efficiently execute the calculation by referring to the table with a small number of instructions, and it is possible to process the calculation for each SIMD element at high speed. That is, the processing efficiency can be improved while keeping the circuit scale small.

1 PCI card 2 Host computer 10 Processing unit 11 Overall instruction control unit 12 Memory controller 13 Memory 14 PCI control unit 101 Operation instruction control unit 102 Operation instruction buffer 103 Multiplexer 111, 111A to 111C Vector register 112, 112A to 112C Product sum operation unit 113, 113A to 113C Element register 121, 121A to 121C Indirect address register 122, 122A to 122C multiplexer

Claims (6)

A storage unit having a plurality of element storage areas and storing each of the plurality of calculated values in each of the element storage areas.
It is a product-sum calculation machine having a multiplier and an adder, generates a first selection value based on input element data, and of the calculation value stored in the element storage area based on the first selection value. An arithmetic processing apparatus including a arithmetic unit that acquires a first arithmetic value from the inside and acquires an arithmetic result based on the first arithmetic value by using the multiplier and the adder. .. The calculation unit generates a second selection value based on the element data or the first selection value, and acquires the second calculation value from the calculation value stored in the element storage area based on the second selection value. The arithmetic processing apparatus according to claim 1, wherein the arithmetic result is acquired based on the first operational value and the second operational value. The calculation result acquired by the calculation unit is a function of the same type in a predetermined number, and a function corresponding to the element data is selected from the functions including a plurality of coefficients, and the calculation is performed using the selected function. The result,
The element storage areas are numbered sequentially, and the element storage areas in which the numbers are continuous have the predetermined number of coefficients corresponding to each term included in each term continuously for each term. Hold and
The calculation unit generates a first number, which is one of the numbers, based on the element data, acquires a first coefficient stored in the element storage area corresponding to the first number, and obtains the first coefficient. The predetermined number is added to the number to generate the second number, the second coefficient stored in the element storage area corresponding to the second number is acquired, and the element data, the first coefficient and the second coefficient are obtained. The arithmetic processing apparatus according to claim 2, wherein the arithmetic result is acquired based on a coefficient. There are a specific number of the storage units,
In the calculation unit, the specific number is arranged corresponding to each storage unit.
The arithmetic processing apparatus according to claim 1, wherein each arithmetic unit acquires one element data from an array including a plurality of the element data. Further, it has an indirect storage unit that outputs a corresponding value corresponding to the value to be held from the storage unit to the calculation unit by inputting the value to be held into the storage unit.
The storage unit receives the input of the first selection value from the indirect storage unit and outputs the first calculation value to the calculation unit.
The arithmetic processing device according to claim 1, wherein the arithmetic unit acquires the first operational value from the storage unit by storing the first selected value in the indirect storage unit. It is a control method of a storage device having a plurality of element storage areas, and a calculation processing device including a product-sum calculation machine having a multiplier and an adder.
Each of the plurality of calculated values is stored in each of the element storage areas.
Generate the first selection value based on the input element data,
The first calculated value is acquired from the calculated value stored in the element storage area based on the first selected value.
Acquire the calculation result based on the first calculation value.
A control method of an arithmetic processing apparatus, characterized in that processing is performed using the multiplier and the adder .

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