JP7060116B2 - CDR circuit - Google Patents

Description

The present invention relates to a four-phase oscillator and a CDR (Clock and Data Recovery) circuit.

Conventionally, a four-phase oscillator that outputs four-phase clocks having different phases by using LC resonance by an LC resonator in which an inductor (L) and a capacitance (C) are connected in parallel is known (for example). , Patent Document 1). The four-phase oscillator is used, for example, in a CDR circuit provided in a receiving circuit for receiving data in the field of high-speed interconnects that communicate high-speed data by wire or wirelessly. The CDR circuit reproduces the clock and data from the received data signal on which the clock is superimposed.

International Publication No. 2007/072549

A. Pottbacker, et al. , "A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8Gb / s", IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, pp 1747-1751, 1992

By widening the variable range (range in which the capacitance value changes) of the variable capacitance in the LC resonator, the range in which the 4-phase oscillator can oscillate can be widened. When the oscillation range of a 4-phase oscillator becomes wide, one 4-phase oscillator can handle multiple oscillation frequencies (for example, 25 GHz and 28 GHz, or 32 GHz and 36 GHz) without preparing multiple 4-phase oscillators for each frequency. Is possible.

However, when the capacitance value of the variable capacitance becomes large, the Q value (Quality factor) indicating the performance of the LC resonator decreases, and for example, the noise in the clock becomes large. Further, when the size of the variable capacitance increases due to the increase in the capacitance value of the variable capacitance, the parasitic capacitance cannot be ignored and the oscillation range is conversely narrowed.

Therefore, in the present disclosure, a four-phase oscillator and a CDR circuit capable of suppressing a decrease in the Q value and expanding the oscillation range are provided.

In one aspect of the disclosure,
The first oscillator that outputs the first differential signal and
A second oscillator that outputs a second differential signal whose phase is different from that of the first differential signal,
Equipped with a control circuit,
The first oscillator is a first cross-coupled circuit in which a first resonator in which an inductor and a capacitance are connected in parallel and a first pair of transistors connected to the first resonator are cross-coupled. A first tail current source connected to the first pair of transistors, a first input differential pair transistor to which the second differential signal is input, and the first input differential pair. It has a second tail current source connected to the transistor and
The second oscillator is a second cross-coupled circuit in which a second resonator in which an inductor and a capacitance are connected in parallel and a second pair of transistors connected to the second resonator are cross-coupled. A third tail current source connected to the second pair of transistors, a second input differential pair transistor to which the first differential signal is input, and the second input differential pair. It has a fourth tail current source connected to a transistor and
In the control circuit, the difference between the first current value flowed by the first tail current source and the third current value flowed by the third tail current source, and the second current flowed by the second tail current source. By controlling at least one of the difference between the current value of the above and the fourth current value of the fourth tail current source, the frequencies of the first differential signal and the second differential signal are changed. A four-phase oscillator is provided.

Further, in another aspect of the present disclosure,
The first oscillator that outputs the first differential signal and
A second oscillator that outputs a second differential signal whose phase is different from that of the first differential signal,
Equipped with a control circuit,
The first oscillator is a first cross-coupled circuit in which a first resonator in which an inductor and a capacitance are connected in parallel and a first pair of transistors connected to the first resonator are cross-coupled. A first tail current source connected to the first pair of transistors, a first input differential pair transistor to which the second differential signal is input, and the first input differential pair. It has a second tail current source connected to the transistor and
The second oscillator is a second cross-coupled circuit in which a second resonator in which an inductor and a capacitance are connected in parallel and a second pair of transistors connected to the second resonator are cross-coupled. A third tail current source connected to the second pair of transistors, a second input differential pair transistor to which the first differential signal is input, and the second input differential pair. It has a fourth tail current source connected to a transistor and
In the control circuit, the difference between the first current value flowed by the first tail current source and the second current value flowed by the second tail current source, and the third current flowed by the third tail current source. By controlling at least one of the difference between the current value of the above and the fourth current value of the fourth tail current source, the frequencies of the first differential signal and the second differential signal are changed. A four-phase oscillator is provided.

Further, in another aspect of the present disclosure,
A phase frequency detection circuit that outputs a phase control signal according to the phase difference between the received data signal and the clock signal and a frequency control signal corresponding to the frequency difference between the received data signal and the clock signal.
A control voltage generation circuit that generates a control voltage according to the phase control signal and the frequency control signal.
A 4-phase oscillator that outputs the clock signal at a frequency corresponding to the control voltage,
A data generation circuit that reproduces data from the received data signal according to the clock signal is provided.
The four-phase oscillator is
The first oscillator that outputs the first differential signal and
A second oscillator that outputs a second differential signal whose phase is different from that of the first differential signal,
Equipped with a control circuit,
The first oscillator is a first cross-coupled circuit in which a first resonator in which an inductor and a capacitance are connected in parallel and a first pair of transistors connected to the first resonator are cross-coupled. A first tail current source connected to the first pair of transistors, a first input differential pair transistor to which the second differential signal is input, and the first input differential pair. It has a second tail current source connected to the transistor and
The second oscillator is a second cross-coupled circuit in which a second resonator in which an inductor and a capacitance are connected in parallel and a second pair of transistors connected to the second resonator are cross-coupled. A third tail current source connected to the second pair of transistors, a second input differential pair transistor to which the first differential signal is input, and the second input differential pair. It has a fourth tail current source connected to a transistor and
In the control circuit, the difference between the first current value flowed by the first tail current source and the third current value flowed by the third tail current source, and the second current flowed by the second tail current source. By controlling at least one of the difference between the current value of the above and the fourth current value of the fourth tail current source, the frequencies of the first differential signal and the second differential signal are changed. A CDR circuit is provided.

Further, in another aspect of the present disclosure,
A phase frequency detection circuit that outputs a phase control signal according to the phase difference between the received data signal and the clock signal and a frequency control signal corresponding to the frequency difference between the received data signal and the clock signal.
A control voltage generation circuit that generates a control voltage according to the phase control signal and the frequency control signal.
A 4-phase oscillator that outputs the clock signal at a frequency corresponding to the control voltage,
A data generation circuit that reproduces data from the received data signal according to the clock signal is provided.
The four-phase oscillator is
The first oscillator that outputs the first differential signal and
A second oscillator that outputs a second differential signal whose phase is different from that of the first differential signal,
Equipped with a control circuit,
The first oscillator is a first cross-coupled circuit in which a first resonator in which an inductor and a capacitance are connected in parallel and a first pair of transistors connected to the first resonator are cross-coupled. A first tail current source connected to the first pair of transistors, a first input differential pair transistor to which the second differential signal is input, and the first input differential pair. It has a second tail current source connected to the transistor and
The second oscillator is a second cross-coupled circuit in which a second resonator in which an inductor and a capacitance are connected in parallel and a second pair of transistors connected to the second resonator are cross-coupled. A third tail current source connected to the second pair of transistors, a second input differential pair transistor to which the first differential signal is input, and the second input differential pair. It has a fourth tail current source connected to a transistor and
In the control circuit, the difference between the first current value flowed by the first tail current source and the second current value flowed by the second tail current source, and the third current flowed by the third tail current source. By controlling at least one of the difference between the current value of the above and the fourth current value of the fourth tail current source, the frequencies of the first differential signal and the second differential signal are changed. A CDR circuit is provided.

According to the present disclosure, it is possible to suppress a decrease in the Q value and extend the oscillation range.

It is a figure which shows an example of the structure of the 4-phase oscillator which concerns on this disclosure. It is a figure which shows an example of the structure of a resonator. It is a figure which shows an example of the 1st oscillation mode of a 4-phase oscillator. It is a figure which shows an example of the 2nd oscillation mode of a 4-phase oscillator. It is a figure which shows an example of the change of an oscillation frequency. It is a timing chart which shows an example of the frequency change of the 1st differential signal and the 2nd differential signal output by the 4-phase oscillator which concerns on 1st Embodiment. It is a timing chart which shows an example of the frequency change of the 1st differential signal and the 2nd differential signal output by the 4-phase oscillator which concerns on 2nd Embodiment. It is a figure which shows an example of the other circuit configuration of the 4-phase oscillator which concerns on this disclosure. It is a figure which shows an example of the structure of a resonator. It is a figure which shows an example of the structure of the CDR circuit which concerns on this disclosure. It is a figure which shows an example of the structure of a phase frequency detector. It is a figure which shows an example of the structure of an inverter.

Hereinafter, the 4-phase oscillator and the CDR circuit according to the present disclosure will be described with reference to the drawings.

FIG. 1 is a diagram showing an example of a configuration of a four-phase oscillator according to the present disclosure. The four-phase oscillator 41 shown in FIG. 1 includes an I-phase oscillator 10 which is an example of a first oscillator that outputs first differential signals whose phases are 180 degrees out of phase with each other, and a first differential signal and 90 in phase. It includes a Q-phase oscillator 20 which is an example of a second oscillator that outputs a second differential signal different in degrees or −90 degrees, and a control circuit 30.

The I-phase oscillator 10 includes an LC tank 11, a cross-coupled circuit 14, a tail current source 15, first input differential pair transistors 16a and 16b, and a tail current source 17.

The LC tank 11 is an example of a first resonator in which an inductor and a capacitance are connected in parallel. The cross-coupled circuit 14 is an example of the first cross-coupled circuit. The cross-coupled circuit 14 has a configuration in which a pair of transistors 14a and 14b connected to the LC tank 11 are cross-coupled. The pair of transistors 14a and 14b is an example of the first pair of transistors. The tail current source 15 is an example of a first tail current source, and is connected to a pair of transistors 14a and 14b. A second differential signal is input to the first input differential pair transistors 16a and 16b. The tail current source 17 is an example of a second tail current source, and is connected to the first input differential pair transistors 16a and 16b.

The Q-phase oscillator 20 includes an LC tank 21, a cross-coupled circuit 24, a tail current source 25, second input differential pair transistors 26a and 26b, and a tail current source 27.

The LC tank 21 is an example of a second resonator in which an inductor and a capacitance are connected in parallel. The cross-coupled circuit 24 is an example of a second cross-coupled circuit. The cross-coupled circuit 24 has a configuration in which a pair of transistors 24a and 24b connected to the LC tank 21 are cross-coupled. The pair of transistors 24a and 24b is an example of a second pair of transistors. The tail current source 25 is an example of a third tail current source, and is connected to a pair of transistors 24a and 24b. The first differential signal is input to the second input differential pair transistors 26a and 26b. The tail current source 27 is an example of a fourth tail current source, and is connected to the second input differential pair transistors 26a and 26b.

The first input differential pair transistors 16a and 16b are connected in parallel to the first pair of transistors 14a and 14b. The second input differential pair transistors 26a and 26b are connected in parallel to the second pair of transistors 24a and 24b.

The I-phase oscillator 10 includes a pair of output terminals A and C that output a first differential signal, and the Q-phase oscillator 20 includes a pair of output terminals B and D that output a second differential signal. The LC tank 11 is connected between the first output terminal A and the second output terminal C. The LC tank 21 is connected between the third output terminal B and the fourth output terminal D.

The first pair of transistors are oscillation transistors including a first transistor 14a connected to the first output terminal A and a second transistor 14b connected to the second output terminal C. In the first transistor 14a, the gate is connected to the second output terminal C, the drain is connected to the first output terminal A, and the source is connected to the tail current source 15. In the second transistor 14b, the gate is connected to the first output terminal A, the drain is connected to the second output terminal C, and the source is connected to the tail current source 15.

The tail current source 15 passes the first current value I _I1 through the pair of transistors 14a and 14b of the cross-coupled circuit 14. The first current value I _I1 represents the current value of the tail current for oscillation. The tail current source 15 is connected between the common connection point of the sources of the pair of transistors 14a and 14b and the ground.

The first input differential pair transistor is connected in parallel to the third transistor 16a connected to the first transistor 14a and connected to the fourth output terminal D, and connected in parallel to the second transistor 14b. It includes a fourth transistor 16b connected to the output terminal B of 3. The first input differential pair transistor represents an injection transistor. In the third transistor 16a, the gate is connected to the fourth output terminal D, the drain is connected to the first output terminal A, and the source is connected to the tail current source 17. In the fourth transistor 16b, the gate is connected to the third output terminal B, the drain is connected to the second output terminal C, and the source is connected to the tail current source 17.

The tail current source 17 passes a second current value I _I2 through the pair of transistors 16a and 16b. The second current value I _I2 represents the current value of the tail current for injection. The tail current source 17 is connected between the common connection point of the sources of the pair of transistors 16a and 16b and the ground.

The second pair of transistors are oscillation transistors including a fifth transistor 24a connected to the third output terminal B and a sixth transistor 24b connected to the fourth output terminal D. In the fifth transistor 24a, the gate is connected to the fourth output terminal D, the drain is connected to the third output terminal B, and the source is connected to the tail current source 25. In the sixth transistor 24b, the gate is connected to the third output terminal B, the drain is connected to the fourth output terminal D, and the source is connected to the tail current source 25.

The tail current source 25 passes a third current value IQ1 through a pair of _transistors 24a and 24b of the cross-coupled circuit 24. The third current value _IQ1 represents the current value of the tail current for oscillation. The tail current source 25 is connected between the common connection point of the sources of the pair of transistors 24a and 24b and the ground.

The second input differential pair transistor is connected in parallel to the seventh transistor 26a connected to the fifth transistor 24a and connected to the first output terminal A, and connected in parallel to the sixth transistor 24b. It includes an eighth transistor 26b connected to the output terminal C of 2. The second input differential pair transistor represents an injection transistor. In the seventh transistor 26a, the gate is connected to the first output terminal A, the drain is connected to the third output terminal B, and the source is connected to the tail current source 27. In the eighth transistor 26b, the gate is connected to the second output terminal C, the drain is connected to the fourth output terminal D, and the source is connected to the tail current source 27.

The tail current source 27 passes a fourth current value IQ2 through the pair of _transistors 26a and 26b. The fourth current value _IQ2 represents the current value of the injection tail current. The tail current source 27 is connected between the common connection point of the sources of the pair of transistors 26a and 26b and the ground.

The transistors 14a, 14b, 16a, 16b, 24a, 24b, 26a, and 26b are, for example, N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), respectively. Each of these transistors may be an npn-type bipolar transistor, in which case the gate corresponds to the base, the drain corresponds to the collector, and the source corresponds to the emitter.

FIG. 2 is a diagram showing an example of the configuration of the resonator. The LC tank 11A is an example of the LC tank 11 shown in FIG. The LC tank 11A has a configuration in which the inductor 12 and the capacitance 13 are connected in parallel. The inductor 12 has an inductor 12a and an inductor 12b, and is connected between the inductor 12a and the inductor 12b to a power supply line having a power supply voltage Vdd. The output terminal A is connected to the power supply line of the power supply voltage Vdd via the inductor 12a, and the output terminal C is connected to the power supply line of the power supply voltage Vdd via the inductor 12b. The capacity 13 is, for example, a variable capacity whose capacity value changes according to the control voltage Vctt. Specific examples of the capacitance 13 include a varicap, a variable capacitance diode, and the like. The LC tank 21 shown in FIG. 1 also has the same configuration as that of FIG.

FIG. 3 is a diagram showing an example of a first oscillation mode of the 4-phase oscillator according to the present disclosure. FIG. 4 is a diagram showing an example of a second oscillation mode of the 4-phase oscillator according to the present disclosure. The 4-phase oscillator 41 having the configuration shown in the figure can take two types of oscillation modes (rotational modes).

FIG. 3 will be described in order of input / output of the clock voltage signal starting from the output terminal A. The 0-degree clock output from the output terminal A is injected into the Q-phase transistor 26a, and a 90-degree clock whose phase is 90 degrees ahead of the 0-degree clock is output from the output terminal B. The 90-degree clock output from the output terminal B is injected into the I-phase transistor 16b, and a 180-degree clock whose phase is 90 degrees ahead of the 90-degree clock is output from the output terminal C. The 180-degree clock output from the output terminal C is injected into the Q-phase transistor 26b, and a 270-degree clock whose phase is 90 degrees ahead of the 180-degree clock is output from the output terminal D. The 270-degree clock output from the output terminal D is injected into the I-phase transistor 16a, and the 0-degree clock whose phase is 90 degrees ahead of the 270-degree clock is output from the output terminal A.

FIG. 4 will be described in order of input / output of the clock voltage signal starting from the output terminal A. The 0-degree clock output from the output terminal A is injected into the Q-phase transistor 26a, and a 270-degree clock whose phase is 90 degrees behind the 0-degree clock is output from the output terminal B. The 270-degree clock output from the output terminal B is injected into the I-phase transistor 16b, and a 180-degree clock whose phase is 90 degrees behind the 270-degree clock is output from the output terminal C. The 180-degree clock output from the output terminal C is injected into the Q-phase transistor 26b, and a 90-degree clock whose phase is 90 degrees behind the 180-degree clock is output from the output terminal D. The 90-degree clock output from the output terminal D is injected into the I-phase transistor 16a, and a 0-degree clock whose phase is 90 degrees behind the 90-degree clock is output from the output terminal A.

Looking at these rotation modes from the viewpoint of oscillation frequency, the 4-phase oscillator 41 has a design oscillation frequency ω ₀ that matches the resonance frequency of the LC tank in rotation mode 1 and rotation mode 2 by having the configuration shown in the figure. It oscillates at an oscillation frequency deviated from that of (see FIG. 5). That is, the frequency of oscillation differs between the rotation mode 1 and the rotation mode 2. In rotation mode 1, it oscillates at a resonance frequency ω ₉₀ lower than the design oscillation frequency ω ₀ , and in rotation mode 2, it oscillates at a resonance frequency ω ₋₉₀ higher than the design oscillation frequency ω ₀ .

Therefore, the 4-phase oscillator 41 includes a control circuit 30 (see FIG. 1) that performs switching control for switching between the two rotation modes by utilizing the fact that the resonance frequency is skipped between the two rotation modes. The control circuit 30 switches the oscillation frequency of the four-phase (that is, 0 degree, 90 degree, 180 degree, 270 degree) clock output from the four-phase oscillator 41 by switching the rotation mode of the four-phase oscillator 41. Can be done. The switching control function of the control circuit 30 may be realized by a logic circuit, or may be realized by a processor processing a program.

<First Embodiment>
In FIG. 1, the control circuit 30 switches the rotation mode of the 4-phase oscillator 41 by individually controlling the tail current I _I of the I-phase oscillator 10 and the tail current IQ of the _Q -phase oscillator 20. When switching the rotation mode of the 4-phase oscillator 41, the I-phase oscillator 10 and the Q-phase oscillator 20 are configured so that their resonance frequencies are different from each other. For example, the mounting layouts of the I-phase oscillator 10 and the Q-phase oscillator 20 are arranged asymmetrically with each other.

For example, at least one inductor and capacitance of the LC tank 11 and the LC tank 21 are adjusted so that the resonance frequency at which the LC tank 11 resonates and the resonance frequency at which the LC tank 21 resonates are different from each other. By adjusting the LC constant of the LC tank, it becomes easy to make the resonance frequencies of the I-phase oscillator 10 and the Q-phase oscillator 20 different from each other. For example, the resonance frequencies of the I-phase oscillator 10 and the Q-phase oscillator 20 may be designed to be different from each other by differentiating the size and wiring capacitance of the transistors used.

In the control circuit 30, the difference between the first current value I _I1 flowing through the tail current source 15 and the third current value I _Q1 flowing through the tail current source 25 and the second current value I _I 2 flowing through the tail current source 17 At least one of the difference between the current value _IQ2 and the fourth current value IQ2 flowed by the tail current source 27 is controlled. By performing this control, the control circuit 30 changes the frequencies of the first differential signal and the second differential signal. The first differential signal represents the above-mentioned clock output from the pair of output terminals A and C, and the second differential signal represents the above-mentioned clock output from the pair of output terminals B and D.

The control circuit 30 determines, for example, a first differential signal by making the tail current value of the LC tank 11 and the LC tank 21 having the higher resonance frequency higher than the tail current value of the one having the lower resonance frequency. And raise the frequency of the second differential signal.

When the resonance frequency of the LC tank 11 is higher than the resonance frequency of the LC tank 21, the control circuit 30 sets the first current value I _I1 to be larger than the third current value _IQ1 and the second current value I I ₂ . Make it larger than the fourth current value _IQ2 . As a result, the oscillation mode of the 4-phase oscillator 41 is switched to the rotation mode 2, so that the frequencies of the first differential signal and the second differential signal increase (see FIG. 5). On the other hand, in the control circuit 30, when the resonance frequency of the LC tank 11 is higher than the resonance frequency of the LC tank 21, the first current value I _I1 is smaller than the third current value _IQ1 and the second current value I _{Make I2} smaller than the fourth current value _IQ2 . As a result, the oscillation mode of the 4-phase oscillator 41 is switched to the rotation mode 1, so that the frequencies of the first differential signal and the second differential signal are lowered (see FIG. 5).

On the other hand, in the control circuit 30, when the resonance frequency of the LC tank 11 is lower than the resonance frequency of the LC tank 21, the first current value I _I1 is smaller than the third current value _IQ1 and the second current value I _{Make I2} smaller than the fourth current value _IQ2 . As a result, the oscillation mode of the 4-phase oscillator 41 is switched to the rotation mode 2, so that the frequencies of the first differential signal and the second differential signal increase (see FIG. 5). On the other hand, in the control circuit 30, when the resonance frequency of the LC tank 11 is higher than the resonance frequency of the LC tank 21, the first current value I _I1 is larger than the third current value _IQ1 and the second current value I _{Make I2} larger than the fourth current value _IQ2 . As a result, the oscillation mode of the 4-phase oscillator 41 is switched to the rotation mode 1, so that the frequencies of the first differential signal and the second differential signal are lowered (see FIG. 5).

FIG. 6 shows an example of a waveform when the tail current value is changed when the resonance frequency of the first resonator is higher than the resonance frequency of the second resonator in the first embodiment. The upper part of FIG. 6 shows the waveform in the rotation mode 2 and oscillates at 30.6 GHz. The lower part of FIG. 6 shows the waveform in the rotation mode 1 and oscillates at 27 GHz. The frequency difference is 3.6 GHz. As described above, according to the 4-phase oscillator of the present disclosure, since one 4-phase oscillator can handle a plurality of oscillation frequencies, it is possible to suppress a decrease in the Q value and expand the oscillation range. can.

<Second embodiment>
In FIG. 1, the control circuit 30 individually controls the tail current I ₂ of the injection transistor and the tail current I ₁ of the oscillator in each of the I-phase oscillator 10 and the Q-phase oscillator 20, so that the 4-phase oscillator 41 Switch the rotation mode of. In the present embodiment, the resonance frequency at which the LC tank 11 resonates and the resonance frequency at which the LC tank 21 resonates may be the same value or different values.

In the control circuit 30, the difference between the first current value I _I1 flowing through the tail current source 15 and the second current value I _I 2 flowing through the tail current source 17 and the third current value I _Q1 flowing through the tail current source 25 At least one of the difference between the current value _IQ2 and the fourth current value IQ2 flowed by the tail current source 27 is controlled. By performing this control, the control circuit 30 changes the frequencies of the first differential signal and the second differential signal. The first differential signal represents the above-mentioned clock output from the pair of output terminals A and C, and the second differential signal represents the above-mentioned clock output from the pair of output terminals B and D.

The control circuit 30 is at least one of making the first current value I _I1 larger than the second current value I I ₂ and making the third current value I _Q1 larger than the fourth current value IQ ₂ . I do. As a result, the frequencies of the first differential signal and the second differential signal are lowered. On the other hand, the control circuit 30 makes the second current value I I ₂ larger than the first current value I I ₁ and makes the fourth current value _{IQ 2} larger than the third current value _{IQ 1} . Do at least one. As a result, the frequencies of the first differential signal and the second differential signal increase.

FIG. 7 shows an example of a waveform when the tail current value is changed when the resonance frequency of the first resonator is the same as the resonance frequency of the second resonator in the second embodiment. The upper part of FIG. 7 shows the waveform in the rotation mode 2 and oscillates at 31.1 GHz. The lower part of FIG. 7 shows the waveform in the rotation mode 1 and oscillates at 29.3 GHz. The frequency difference is 2.2 GHz. As described above, according to the 4-phase oscillator of the present disclosure, since one 4-phase oscillator can handle a plurality of oscillation frequencies, it is possible to suppress a decrease in the Q value and expand the oscillation range. can.

<Other circuit configurations of 4-phase oscillator>
FIG. 8 is a diagram showing an example of another circuit configuration of the 4-phase oscillator according to the present disclosure. FIG. 9 is a diagram showing an example of the configuration of LC tanks 11 and 21 included in the 4-phase oscillator 42 shown in FIG. In FIG. 8, the inductor in the LC tank is not connected to the power line (see FIG. 2) of the power supply voltage Vdd. The 4-phase oscillator 42 has an I-phase oscillator 10A having a configuration in which the cross-coupled transistors 18a and 18b are connected to the LC tank 11, and a Q-phase having a configuration in which the cross-coupled transistors 28a and 28b are connected to the LC tank 21. It is equipped with an oscillator 20A. Each output terminal A, B, C, D has transistors 18a, 18b, 28a, 28b, respectively, so that the amplitude of the clock signal output from each output terminal A, B, C, D does not exceed the power supply voltage Vdd. It is connected to the power supply line of the power supply voltage Vdd via.

In the transistor 18a, the gate is connected to the second output terminal C, the drain is connected to the first output terminal A, and the source is connected to the power supply line having the power supply voltage Vdd. In the transistor 18b, the gate is connected to the first output terminal A, the drain is connected to the second output terminal C, and the source is connected to the power supply line having the power supply voltage Vdd.

In the transistor 28a, the gate is connected to the fourth output terminal D, the drain is connected to the third output terminal B, and the source is connected to the power supply line having the power supply voltage Vdd. The transistor 28b has a gate connected to a third output terminal B, a drain connected to a fourth output terminal D, and a source connected to a power line having a power supply voltage Vdd.

The transistors 18a, 18b, 28a, and 28b are, for example, P-channel MOSFETs, respectively. Each of these transistors may be a pnp-type bipolar transistor, in which case the gate corresponds to the base, the drain corresponds to the collector, and the source corresponds to the emitter.

<CDR circuit>
FIG. 10 is a diagram showing an example of the configuration of the CDR circuit according to the present disclosure. The CDR circuit 100 reproduces the clock and the data Dout from the received data signal Din on which the clock is superimposed. The CDR circuit 100 includes a PLL (Phase Locked Loop) circuit 110 and a data generation circuit 106. The PLL circuit 110 includes a 4-phase oscillator 104, an inverter 105, a phase frequency detector 101, and a control voltage generation circuit 107. The 4-phase oscillator according to the present disclosure can be applied to the 4-phase oscillator 104. The control voltage generation circuit 107 includes a charge pump 102 and a loop filter 103.

The 4-phase oscillator 104 has, for example, the same configuration as the 4-phase oscillator 41 shown in FIG. 1 (that is, the I-phase oscillator 10, the Q-phase oscillator 20, and the control circuit 30). The I-phase oscillator 10 outputs a first differential signal (0-degree clock and 180-degree clock) from the pair of output terminals A and C. The Q-phase oscillator 20 outputs a second differential signal (90-degree clock and 270-degree clock) from the pair of output terminals B and D.

The inverter 105 is a circuit that outputs a third differential signal in which the phase of the second differential signal output from the output terminals B and D is inverted.

The phase frequency detector 101 uses the first differential signal and the third differential signal to compare the phase of the received data signal Din with the phase of the first differential signal. Further, the phase frequency detector 101 uses the first differential signal and the third differential signal to compare the frequency of the received data signal Din with the frequency of the first differential signal.

The phase frequency detector 101 includes a phase detection signal PDI showing a comparison result between the phase of the received data signal Din and the phase of the first differential signal, a frequency of the received data signal Din, and a frequency of the first differential signal. A frequency detection signal FDO showing the comparison result of is generated. The phase frequency detector 101 outputs the generated phase detection signal PDI and frequency detection signal FDO to the charge pump 102.

FIG. 11 is a diagram showing an example of the configuration of the phase frequency detector. The phase frequency detector 101 includes a first phase detection circuit 121, a second phase detection circuit 122, and a frequency detection circuit 123. As the phase detection circuit 121, the phase detection circuit 122, and the frequency detection circuit 123, for example, the configuration described in Non-Patent Document 1 can be applied. Non-Patent Document 1 describes a differential type first phase detection circuit and a second phase detection circuit formed by two sample hold circuits (latch circuits) and a multiplexer. Further, Non-Patent Document 1 describes a differential type frequency detection circuit formed by two latch circuits and a modified multiplexer.

The received data signal Din input to the phase frequency detector 101 includes differential data signals din and din_ whose phases are inverted from each other. The phase detection circuit 121 outputs a first phase detection signal PDI corresponding to the phase difference between the received data signal Din and the first differential signal. Specifically, in the phase detection circuit 121, whether the change edge of the first differential signal (0 degree clock and 180 degree clock) is advanced or delayed with respect to the change edge of the differential data signals din and din_. The first phase detection signal PDI indicating the above is generated. The phase detection circuit 122 outputs a second phase detection signal PDQ according to the phase difference between the received data signal Din and the third differential signal. Specifically, in the phase detection circuit 122, whether the change edge of the third differential signal (90 degree clock and 270 degree clock) is ahead or behind the change edge of the differential data signals din and din_. The second phase detection signal PDQ indicating is generated.

The frequency detection circuit 123 generates the frequency detection signal FDO from the direction of the change edge of the phase detection signal PDI and the value of the phase detection signal PDQ latched by the change edge of the phase detection signal PDI. The frequency detection signal FDO indicates whether the frequency of the first differential signal is lower or higher than the frequency of the received data signal Din. The frequency detection signal FDO indicates +1 when the frequency of the first differential signal is lower than the frequency of the received data signal Din, -1 when it is higher, and 0 when the frequency is the same. The phase detection signal PDI and the frequency detection signal FDO are supplied to the charge pump 102 (see FIG. 10).

The charge pump 102 uses the phase detection signal PDI and the frequency detection signal FDO supplied from the phase frequency detector 101 to compensate for the phase difference and frequency difference between the received data signal Din and the first differential signal. Generates the signal of. When the charge pump 102 determines that the phase of the first differential signal is behind the phase of the received data signal Din, or the frequency of the first differential signal is lower than the frequency of the received data signal Din, the charge pump 102 determines. The up signal Up is output to the loop filter 103. On the other hand, the charge pump 102 determines that the phase of the first differential signal is ahead of the phase of the received data signal Din, or the frequency of the first differential signal is higher than the frequency of the received data signal Din. At this time, the down signal Down is output to the loop filter 103.

The loop filter 103 supplies a control voltage Vctt for adjusting the frequency and phase of the first differential signal and the second differential signal to the LC tanks 11 and 21 in the 4-phase oscillator 104. The control voltage Vctt allows fine adjustment of the frequency and phase of the first differential signal and the second differential signal.

The loop filter 103 changes the control voltage Vctt supplied to the 4-phase oscillator 104 according to the up signal Up and the down signal Down supplied from the charge pump 102. The loop filter 103 raises the control voltage Vctt supplied to the 4-phase oscillator 104 when the up signal Up is supplied from the charge pump 102. As the control voltage Vctt rises, the phase of the first differential signal advances and the frequency of the first differential signal becomes higher. On the other hand, when the down signal Down is supplied from the charge pump 102, the loop filter 103 lowers the control voltage Vctt supplied to the 4-phase oscillator 104. Due to the decrease in the control voltage Vct, the phase of the first differential signal is delayed and the frequency of the first differential signal is lowered.

The four-phase oscillator 104 has a first differential signal having a frequency and phase finely tuned according to the control voltage Vctt supplied from the loop filter 103, and a first differential signal whose phase is inverted with respect to the first differential signal. Generates 2 differential signals.

The data generation circuit 106 is, for example, a data flip-flop, and reproduces data Dout from the received data signal Din by sampling the received data signal Din according to the first differential signal output from the four-phase oscillator 104.

FIG. 12 is a diagram showing an example of the configuration of the inverter. The inverter 105 has load resistors 111 and 112, N-channel type transistors 113 to 116, and constant current sources 117 and 118. A 90-degree clock output from the output terminal B is input to each gate of the transistors 113 and 116, and a 270-degree clock output from the output terminal D is input to each gate of the transistors 114 and 115. The drains of the transistors 113 and 115 are connected to the power supply line of the power supply voltage Vdd via the load resistance 111, and the drains of the transistors 114 and 116 are connected to the power supply line of the power supply voltage Vdd via the load resistance 112. There is. The sources of the transistors 113 and 114 are connected to the ground via the constant current source 117, and the sources of the transistors 115 and 116 are connected to the ground via the constant current source 118.

The inverter 105 operates either the constant current source 117 or the constant current source 118 based on the rotation mode switching control signal supplied from the control circuit 30 of the four-phase oscillator 104. As a result, the phase of the second differential signal (the phases of the 90-degree clock signal and the 270-degree clock signal) can be inverted in synchronization with the control circuit 30 switching the rotation mode of the 4-phase oscillator 104. can. As a result, the phase of the entire CDR loop of the CDR circuit 100 does not change before and after switching the rotation mode in which the frequencies of the first differential signal and the second differential signal change. Therefore, it is possible to prevent the CDR circuit 100 from malfunctioning when the rotation mode is switched.

For example, when the inverter 105 receives a control signal for switching the oscillation mode of the four-phase oscillator 104 from the rotation mode 1 to the rotation mode 2, the constant current source 117 is turned on and the constant current source 118 is turned off. As a result, the 90-degree clock input to the transistor 113 is supplied to the phase frequency detector 101 via the transistor 113 and the terminal BX. Further, the 270 degree clock input to the transistor 114 is supplied to the phase frequency detector 101 via the transistor 114 and the terminal DX.

On the other hand, when the inverter 105 receives a control signal for switching the oscillation mode of the 4-phase oscillator 104 from the rotation mode 2 to the rotation mode 1, the constant current source 118 is turned on and the constant current source 117 is turned off. As a result, the 90-degree clock input to the transistor 116 is supplied to the phase frequency detector 101 via the transistor 116 and the terminal DX. Further, the 270 degree clock input to the transistor 115 is supplied to the phase frequency detector 101 via the transistor 115 and the terminal BX.

As a result, it is possible to prevent the phase frequency detector 101 from malfunctioning even if the rotation mode in which the frequencies of the first differential signal and the second differential signal change is switched.

Although the four-phase oscillator and the CDR circuit have been described above by embodiment, the present invention is not limited to the above embodiment. Various modifications and improvements, such as combinations and substitutions with some or all of the other embodiments, are possible within the scope of the present invention.

Further, the following additional notes will be disclosed with respect to the above embodiments.
(Appendix 1)
The first oscillator that outputs the first differential signal and
A second oscillator that outputs a second differential signal whose phase is 90 degrees or −90 degrees different from that of the first differential signal.
Equipped with a control circuit,
The first oscillator is a first cross-coupled circuit in which a first resonator in which an inductor and a capacitance are connected in parallel and a first pair of transistors connected to the first resonator are cross-coupled. A first tail current source connected to the first pair of transistors, a first input differential pair transistor to which the second differential signal is input, and the first input differential pair. It has a second tail current source connected to the transistor and
The second oscillator is a second cross-coupled circuit in which a second resonator in which an inductor and a capacitance are connected in parallel and a second pair of transistors connected to the second resonator are cross-coupled. A third tail current source connected to the second pair of transistors, a second input differential pair transistor to which the first differential signal is input, and the second input differential pair. It has a fourth tail current source connected to a transistor and
In the control circuit, the difference between the first current value flowed by the first tail current source and the third current value flowed by the third tail current source, and the second current flowed by the second tail current source. By controlling at least one of the difference between the current value of the above and the fourth current value of the fourth tail current source, the frequencies of the first differential signal and the second differential signal are changed. A 4-phase oscillator.
(Appendix 2)
The four-phase oscillator according to Appendix 1, wherein the first resonance frequency at which the first resonator resonates and the second resonance frequency at which the second resonator resonates are different.
(Appendix 3)
The control circuit is
When the first resonance frequency is higher than the second resonance frequency, the first current value is larger than the third current value and the second current value is larger than the fourth current value. By increasing the frequency, the frequency is increased, and the frequency is increased by making the first current value smaller than the third current value and making the second current value smaller than the fourth current value. Decrease,
When the first resonance frequency is lower than the second resonance frequency, the first current value is smaller than the third current value and the second current value is smaller than the fourth current value. By making the frequency smaller, the frequency is increased, and the frequency is increased by making the first current value larger than the third current value and the second current value larger than the fourth current value. The four-phase oscillator according to Appendix 2, which reduces the voltage.
(Appendix 4)
The first oscillator that outputs the first differential signal and
A second oscillator that outputs a second differential signal whose phase is 90 degrees or −90 degrees different from that of the first differential signal.
Equipped with a control circuit,
The first oscillator is a first cross-coupled circuit in which a first resonator in which an inductor and a capacitance are connected in parallel and a first pair of transistors connected to the first resonator are cross-coupled. A first tail current source connected to the first pair of transistors, a first input differential pair transistor to which the second differential signal is input, and the first input differential pair. It has a second tail current source connected to the transistor and
The second oscillator is a second cross-coupled circuit in which a second resonator in which an inductor and a capacitance are connected in parallel and a second pair of transistors connected to the second resonator are cross-coupled. A third tail current source connected to the second pair of transistors, a second input differential pair transistor to which the first differential signal is input, and the second input differential pair. It has a fourth tail current source connected to a transistor and
In the control circuit, the difference between the first current value flowed by the first tail current source and the second current value flowed by the second tail current source, and the third current flowed by the third tail current source. By controlling at least one of the difference between the current value of the above and the fourth current value of the fourth tail current source, the frequencies of the first differential signal and the second differential signal are changed. A 4-phase oscillator.
(Appendix 5)
The control circuit performs at least one of making the first current value larger than the second current value and making the third current value larger than the fourth current value. , The frequency of the first differential signal and the second differential signal is lowered, the second current value is made larger than the first current value, and the fourth current value is the second. The four-phase oscillator according to Appendix 4, wherein the frequency of the first differential signal and the second differential signal is increased by at least one of increasing the current value of 3.
(Appendix 6)
The first input differential pair transistor is connected in parallel to the first pair of transistors, and the second input differential pair transistor is connected in parallel to the second pair of transistors. The 4-phase transistor according to any one of 1 to 5.
(Appendix 7)
The first resonator is connected between the first output terminal and the second output terminal.
The second resonator is connected between the third output terminal and the fourth output terminal.
The first pair of transistors includes a first transistor connected to the first output terminal and a second transistor connected to the second output terminal.
The first input differential pair transistor is connected in parallel to the second transistor and the third transistor connected in parallel to the first transistor and connected to the fourth output terminal. Including a fourth transistor connected to a third output terminal, including
The second pair of transistors includes a fifth transistor connected to the third output terminal and a sixth transistor connected to the fourth output terminal.
The second input differential pair transistor is connected in parallel to the sixth transistor and the seventh transistor connected in parallel to the fifth transistor and connected to the first output terminal. The four-phase oscillator according to Appendix 6, which includes an eighth transistor connected to a second output terminal.
(Appendix 8)
A four-phase oscillator that outputs a first differential signal and a second differential signal whose phase differs from that of the first differential signal by 90 degrees or −90 degrees.
An inverter that outputs a third differential signal in which the phase of the second differential signal is inverted, and an inverter.
A first phase detection circuit that outputs a first phase detection signal according to the phase difference between the received data signal and the first differential signal, and a first phase detection circuit.
A second phase detection circuit that outputs a second phase detection signal according to the phase difference between the received data signal and the second differential signal, and
A frequency detection circuit that compares the first phase detection signal and the second phase detection signal and outputs a frequency detection signal according to the frequency difference between the received data signal and the first differential signal.
A control voltage generation circuit that generates a control voltage for adjusting the frequency and phase of the first differential signal and the second differential signal according to the first phase detection signal and the frequency detection signal.
A data generation circuit that reproduces data from the received data signal according to the first differential signal is provided.
The four-phase oscillator is
The first oscillator that outputs the first differential signal and
The second oscillator that outputs the second differential signal and
Equipped with a control circuit,
The first oscillator is a first cross-coupled circuit in which a first resonator in which an inductor and a capacitance are connected in parallel and a first pair of transistors connected to the first resonator are cross-coupled. A first tail current source connected to the first pair of transistors, a first input differential pair transistor to which the second differential signal is input, and the first input differential pair. It has a second tail current source connected to the transistor and
The second oscillator is a second cross-coupled circuit in which a second resonator in which an inductor and a capacitance are connected in parallel and a second pair of transistors connected to the second resonator are cross-coupled. A third tail current source connected to the second pair of transistors, a second input differential pair transistor to which the first differential signal is input, and the second input differential pair. It has a fourth tail current source connected to a transistor and
In the control circuit, the difference between the first current value flowed by the first tail current source and the third current value flowed by the third tail current source, and the second current flowed by the second tail current source. By controlling at least one of the difference between the current value of the above and the fourth current value of the fourth tail current source, the frequencies of the first differential signal and the second differential signal are changed. Let me
The inverter is a CDR circuit that inverts the phase of the second differential signal in response to a change in the frequency due to the control circuit.
(Appendix 9)
A four-phase oscillator that outputs a first differential signal and a second differential signal whose phase differs from that of the first differential signal by 90 degrees or −90 degrees.
An inverter that outputs a third differential signal in which the phase of the second differential signal is inverted, and an inverter.
A first phase detection circuit that outputs a first phase detection signal according to the phase difference between the received data signal and the first differential signal, and a first phase detection circuit.
A second phase detection circuit that outputs a second phase detection signal according to the phase difference between the received data signal and the second differential signal, and
A frequency detection circuit that compares the first phase detection signal and the second phase detection signal and outputs a frequency detection signal according to the frequency difference between the received data signal and the first differential signal.
A control voltage generation circuit that generates a control voltage for adjusting the frequency and phase of the first differential signal and the second differential signal according to the first phase detection signal and the frequency detection signal.
A data generation circuit that reproduces data from the received data signal according to the first differential signal is provided.
The four-phase oscillator is
The first oscillator that outputs the first differential signal and
The second oscillator that outputs the second differential signal and
Equipped with a control circuit,
The first oscillator is a first cross-coupled circuit in which a first resonator in which an inductor and a capacitance are connected in parallel and a first pair of transistors connected to the first resonator are cross-coupled. A first tail current source connected to the first pair of transistors, a first input differential pair transistor to which the second differential signal is input, and the first input differential pair. It has a second tail current source connected to the transistor and
The second oscillator is a second cross-coupled circuit in which a second resonator in which an inductor and a capacitance are connected in parallel and a second pair of transistors connected to the second resonator are cross-coupled. A third tail current source connected to the second pair of transistors, a second input differential pair transistor to which the first differential signal is input, and the second input differential pair. It has a fourth tail current source connected to a transistor and
In the control circuit, the difference between the first current value flowed by the first tail current source and the second current value flowed by the second tail current source, and the third current flowed by the third tail current source. By controlling at least one of the difference between the current value of the above and the fourth current value of the fourth tail current source, the frequencies of the first differential signal and the second differential signal are changed. Let me
The inverter is a CDR circuit that inverts the phase of the second differential signal in response to a change in the frequency due to the control circuit.

10 I-phase oscillator 11,21 LC tank 12 inductor 13 capacity 14 cross-coupled circuit 15, 17, 25, 27 tail current source 20 Q-phase oscillator 41, 42 4-phase oscillator 100 CDR circuit 107 control voltage generation circuit 110 PLL circuit

Claims (3)

A four-phase oscillator that outputs a first differential signal and a second differential signal whose phase is different from that of the first differential signal.
An inverter that outputs a third differential signal in which the phase of the second differential signal is inverted, and an inverter.
A first phase detection circuit that outputs a first phase detection signal according to the phase difference between the received data signal and the first differential signal, and a first phase detection circuit.
A second phase detection circuit that outputs a second phase detection signal according to the phase difference between the received data signal and the third differential signal, and
A frequency detection circuit that compares the first phase detection signal and the second phase detection signal and outputs a frequency detection signal according to the frequency difference between the received data signal and the first differential signal.
A control voltage generation circuit that generates a control voltage for adjusting the frequency and phase of the first differential signal and the second differential signal according to the first phase detection signal and the frequency detection signal.
A data generation circuit that reproduces data from the received data signal according to the first differential signal is provided.
The four-phase oscillator is
The first oscillator that outputs the first differential signal and
The second oscillator that outputs the second differential signal and
Equipped with a control circuit,
The first oscillator is a first cross-coupled circuit in which a first resonator in which an inductor and a capacitance are connected in parallel and a first pair of transistors connected to the first resonator are cross-coupled. A first tail current source connected to the first pair of transistors, a first input differential pair transistor to which the second differential signal is input, and the first input differential pair. It has a second tail current source connected to the transistor and
The second oscillator is a second cross-coupled circuit in which a second resonator in which an inductor and a capacitance are connected in parallel and a second pair of transistors connected to the second resonator are cross-coupled. A third tail current source connected to the second pair of transistors, a second input differential pair transistor to which the first differential signal is input, and the second input differential pair. It has a fourth tail current source connected to a transistor and
In the control circuit, the difference between the first current value flowed by the first tail current source and the second current value flowed by the second tail current source, and the third current flowed by the third tail current source. By controlling at least one of the difference between the current value of the above and the fourth current value of the fourth tail current source, the frequencies of the first differential signal and the second differential signal are changed. A CDR circuit. The control circuit performs at least one of making the first current value larger than the second current value and making the third current value larger than the fourth current value. , The frequency of the first differential signal and the second differential signal is lowered to make the second current value larger than the first current value, and the fourth current value is the second. The CDR circuit according to claim 1, wherein the frequency of the first differential signal and the frequency of the second differential signal is increased by performing at least one of making the current value larger than the current value of 3. The inverter
When the frequency rises, a signal in which the phase of one of the second differential signals is inverted is supplied to the second phase detection circuit via the first terminal, and the second differential signal is supplied. A first inversion circuit that supplies a signal in which the phase of the other signal of the signal is inverted to the second phase detection circuit via the second terminal, and
When the frequency drops, a signal in which the phase of the one signal is inverted is supplied to the second phase detection circuit via the second terminal, and a signal in which the phase of the other signal is inverted is supplied. The CDR circuit according to claim 2, further comprising a second inverting circuit that supplies the second phase detection circuit via the first terminal.

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