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JP6993946B2 - Semiconductor element - Google Patents

Semiconductor element Download PDF

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JP6993946B2
JP6993946B2 JP2018154586A JP2018154586A JP6993946B2 JP 6993946 B2 JP6993946 B2 JP 6993946B2 JP 2018154586 A JP2018154586 A JP 2018154586A JP 2018154586 A JP2018154586 A JP 2018154586A JP 6993946 B2 JP6993946 B2 JP 6993946B2
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metal
layer
metal region
metal layer
main component
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JP2020031095A (en
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智洋 谷口
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Priority to US16/181,872 priority patent/US10784109B2/en
Priority to CN201811597724.3A priority patent/CN110854187B/en
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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    • H10D12/441—Vertical IGBTs
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    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
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    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
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    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts

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Description

実施形態は、半導体素子に関する。 The embodiment relates to a semiconductor device.

高電圧、大電流を制御する半導体装置は、２つの電極板間に複数の半導体素子を配置し、電極板を半導体素子に圧接する構成を有するものがある。このような半導体装置に用いられる半導体素子は、電極板から加わる圧力の集中を緩和するために、厚膜の金属電極を有することが好ましい。 Some semiconductor devices that control high voltage and large current have a configuration in which a plurality of semiconductor elements are arranged between two electrode plates and the electrode plates are pressed against the semiconductor elements. The semiconductor element used in such a semiconductor device preferably has a thick metal electrode in order to alleviate the concentration of pressure applied from the electrode plate.

特開昭５９－４６０４７号公報Japanese Unexamined Patent Publication No. 59-46047

実施形態は、電気抵抗が低い厚膜の電極を備えた半導体素子を提供する。 Embodiments provide a semiconductor device with a thick film electrode having low electrical resistance.

実施形態に係る半導体素子は、半導体層と、金属電極と、を備える。前記金属電極は、前記半導体層上に設けられ、前記半導体層に接した第１金属領域と、前記第１金属領域の上に設けられた第２金属領域と、前記第２金属領域の上に設けられた第３金属領域と、を含む。前記第２金属領域は、前記第１金属領域の主成分である金属元素よりも酸化物の標準生成自由エネルギーが大きい金属元素を主成分とする。前記第１金属領域は、アルミニウム（Ａｌ）もしくはチタニウム（Ｔｉ）を主成分として含み、前記第２金属領域は、マグネシウム（Ｍｇ）、リチウム（Ｌｉ）もしくはカルシウム（Ｃａ）のいずれかを主成分として含む。前記第３金属領域は、前記半導体層から前記第２金属領域に向かう方向における前記第１金属領域および前記第２金属領域のトータル厚よりも厚い前記方向の厚さを有する。
The semiconductor element according to the embodiment includes a semiconductor layer and a metal electrode. The metal electrode is provided on the semiconductor layer, on a first metal region in contact with the semiconductor layer, a second metal region provided on the first metal region, and on the second metal region. Includes a third metal region provided. The second metal region is mainly composed of a metal element having a larger standard free energy for forming an oxide than the metal element which is the main component of the first metal region. The first metal region contains aluminum (Al) or titanium (Ti) as a main component, and the second metal region contains either magnesium (Mg), lithium (Li) or calcium (Ca) as a main component. include. The third metal region has a thickness in the direction that is thicker than the total thickness of the first metal region and the second metal region in the direction from the semiconductor layer to the second metal region.

実施形態に係る半導体素子を示す模式断面図である。It is a schematic cross-sectional view which shows the semiconductor element which concerns on embodiment. 実施形態に係る半導体装置を示す模式断面図である。It is a schematic cross-sectional view which shows the semiconductor device which concerns on embodiment. 実施形態に係る半導体素子の製造方法を示すフローチャートである。It is a flowchart which shows the manufacturing method of the semiconductor element which concerns on embodiment. 実施形態に係る半導体素子の製造過程を示す模式断面図である。It is a schematic sectional drawing which shows the manufacturing process of the semiconductor element which concerns on embodiment. 実施形態に係る半導体素子の特性を示す模式断面図である。It is a schematic sectional drawing which shows the characteristic of the semiconductor element which concerns on embodiment.

以下、実施の形態について図面を参照しながら説明する。図面中の同一部分には、同一番号を付してその詳しい説明は適宜省略し、異なる部分について説明する。なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。 Hereinafter, embodiments will be described with reference to the drawings. The same parts in the drawings are designated by the same number, detailed description thereof will be omitted as appropriate, and different parts will be described. It should be noted that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between the parts, and the like are not necessarily the same as the actual ones. Further, even when the same part is represented, the dimensions and ratios may be different from each other depending on the drawing.

さらに、各図中に示すＸ軸、Ｙ軸およびＺ軸を用いて各部分の配置および構成を説明する。Ｘ軸、Ｙ軸、Ｚ軸は、相互に直交し、それぞれＸ方向、Ｙ方向、Ｚ方向を表す。また、Ｚ方向を上方、その反対方向を下方として説明する場合がある。 Further, the arrangement and configuration of each part will be described using the X-axis, Y-axis and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X-direction, the Y-direction, and the Z-direction, respectively. Further, the Z direction may be described as upward, and the opposite direction may be described as downward.

図１は、実施形態に係る半導体素子（以下、半導体チップ１）を示す模式断面図である。半導体チップ１は、例えば、ＩＧＢＴ（Gate Insulated Bipolar Transistor）である。半導体チップ１は、例えば、電力制御用のスイッチング素子として用いられる。 FIG. 1 is a schematic cross-sectional view showing a semiconductor element (hereinafter, semiconductor chip 1) according to an embodiment. The semiconductor chip 1 is, for example, an IGBT (Gate Insulated Bipolar Transistor). The semiconductor chip 1 is used, for example, as a switching element for power control.

図１に示すように、半導体チップ１は、Ｎ形ベース層１０と、Ｎ形ベース層１０の上面１０Ｔ側に設けられたＭＯＳ構造２０と、を含む。また、半導体チップ１は、Ｎ形ベース層１０の下方に設けられたＰ形コレクタ層４０と、Ｎ形バッファ層４５と、を含む。 As shown in FIG. 1, the semiconductor chip 1 includes an N-type base layer 10 and a MOS structure 20 provided on the upper surface 10T side of the N-type base layer 10. Further, the semiconductor chip 1 includes a P-type collector layer 40 provided below the N-type base layer 10 and an N-type buffer layer 45.

Ｎ形ベース層１０は、例えば、Ｎ形シリコン層である。ＭＯＳ構造２０は、Ｐ形ベース層２１と、Ｎ形エミッタ層２３と、ゲート電極２５と、を含む。ゲート電極２５は、例えば、Ｎ形エミッタ層２３の上面からＮ形ベース層１０に至る深さを有するゲートトレンチ中に設けられ、ゲート絶縁膜を介してＰ形ベース層２１に向き合う。 The N-type base layer 10 is, for example, an N-type silicon layer. The MOS structure 20 includes a P-type base layer 21, an N-type emitter layer 23, and a gate electrode 25. The gate electrode 25 is provided in, for example, a gate trench having a depth from the upper surface of the N-type emitter layer 23 to the N-type base layer 10, and faces the P-type base layer 21 via a gate insulating film.

Ｎ形バッファ層４５は、Ｎ形ベース層１０とＰ形コレクタ層４０との間に設けられる。Ｎ形バッファ層４５は、Ｎ形ベース層１０のＮ形不純物濃度よりも高濃度のＮ形不純物を含む。 The N-type buffer layer 45 is provided between the N-type base layer 10 and the P-type collector layer 40. The N-type buffer layer 45 contains N-type impurities having a concentration higher than that of the N-type impurity concentration of the N-type base layer 10.

半導体チップ１は、エミッタ電極３０と、ゲートパッド３５と、コレクタ電極５０と、をさらに含む。 The semiconductor chip 1 further includes an emitter electrode 30, a gate pad 35, and a collector electrode 50.

エミッタ電極３０は、Ｎ形エミッタ層２３およびゲート電極２５の上方に設けられる。エミッタ電極３０は、Ｎ形エミッタ層２３に接する。また、エミッタ電極３０は、Ｐ形コンタクト層２７を介してＰ形ベース層２１に接続される。Ｐ形コンタクト層２７は、例えば、Ｎ形エミッタ層２３中に設けられ、Ｐ形ベース層２１に接する。 The emitter electrode 30 is provided above the N-shaped emitter layer 23 and the gate electrode 25. The emitter electrode 30 is in contact with the N-shaped emitter layer 23. Further, the emitter electrode 30 is connected to the P-type base layer 21 via the P-type contact layer 27. The P-type contact layer 27 is provided in, for example, the N-type emitter layer 23 and is in contact with the P-type base layer 21.

ゲートパッド３５は、絶縁膜３３を介してＮ形ベース層１０の上方に設けられる。ゲートパッド３５は、絶縁膜３３によりＮ形ベース層１０、Ｐ形ベース層２１、Ｎ形エミッタ層２３およびＰ形コンタクト層２７から電気的に絶縁される。また、ゲートパッド３５は、図示しない部分でゲート電極２５に接続される。 The gate pad 35 is provided above the N-shaped base layer 10 via the insulating film 33. The gate pad 35 is electrically insulated from the N-type base layer 10, the P-type base layer 21, the N-type emitter layer 23, and the P-type contact layer 27 by the insulating film 33. Further, the gate pad 35 is connected to the gate electrode 25 at a portion (not shown).

コレクタ電極５０は、Ｎ形ベース層１０の裏面１０Ｂの下方に設けられる。Ｐ形コレクタ層４０は、Ｎ形バッファ層４５とコレクタ電極５０との間に位置し、コレクタ電極５０に接する。 The collector electrode 50 is provided below the back surface 10B of the N-shaped base layer 10. The P-type collector layer 40 is located between the N-type buffer layer 45 and the collector electrode 50, and is in contact with the collector electrode 50.

コレクタ電極５０は、第１金属領域５０Ａと、第２金属領域５０Ｂと、第３金属領域５０Ｃと、を含む。第１金属領域５０Ａは、Ｐ形コレクタ層４０に接し、Ｐ形コレクタ層４０に沿ってＸ方向およびＹ方向に広がる。第１金属領域５０Ａは、例えば、アルミニウム（Ａｌ）もしくはチタニウム（Ｔｉ）を主成分として含む。 The collector electrode 50 includes a first metal region 50A, a second metal region 50B, and a third metal region 50C. The first metal region 50A is in contact with the P-type collector layer 40 and extends in the X and Y directions along the P-type collector layer 40. The first metal region 50A contains, for example, aluminum (Al) or titanium (Ti) as a main component.

第２金属領域５０Ｂは、第１金属領域５０Ａと第３金属領域５０Ｃとの間に設けられる。第２金属領域５０Ｂは、第１金属領域５０Ａの主成分である金属元素よりも酸化物の標準生成自由エネルギーが大きい金属元素を主成分とする。第２金属領域５０Ｂは、例えば、マグネシウム（Ｍｇ）、リチウム（Ｌｉ）、カルシウム（Ｃａ）、アルミニウム（Ａｌ）のいずれかを主成分として含む。第２金属領域５０Ｂは、１４００℃以下の温度領域における酸化物の標準生成自由エネルギーが第１金属領域５０Ａの主成分である金属元素よりも大きい金属元素を主成分として含む。 The second metal region 50B is provided between the first metal region 50A and the third metal region 50C. The second metal region 50B is mainly composed of a metal element having a larger standard free energy for forming an oxide than the metal element which is the main component of the first metal region 50A. The second metal region 50B contains, for example, any one of magnesium (Mg), lithium (Li), calcium (Ca), and aluminum (Al) as a main component. The second metal region 50B contains, as a main component, a metal element whose standard free energy for forming an oxide in a temperature region of 1400 ° C. or lower is larger than that of the metal element which is the main component of the first metal region 50A.

第３金属領域５０Ｃは、第１金属領域５０Ａおよび第２金属領域５０ＢのＺ方向のトータル厚よりも厚いＺ方向の厚さを有するように設けられる。第３金属領域５０Ｃは、例えば、３マイクロメートル（μｍ）以上、２５μｍ以下のＺ方向の厚さを有する。 The third metal region 50C is provided so as to have a thickness in the Z direction that is thicker than the total thickness in the Z direction of the first metal region 50A and the second metal region 50B. The third metal region 50C has, for example, a thickness of 3 micrometers (μm) or more and 25 μm or less in the Z direction.

第３金属領域５０Ｃは、第１金属領域５０Ａの主成分である金属元素と同じ金属元素を主成分として含んでも良い。例えば、第１金属領域５０Ａは、アルミニウム（Ａｌ）を主成分として含み、第３金属領域５０Ｃも、アルミニウム（Ａｌ）を主成分として含む。 The third metal region 50C may contain the same metal element as the metal element which is the main component of the first metal region 50A as a main component. For example, the first metal region 50A contains aluminum (Al) as a main component, and the third metal region 50C also contains aluminum (Al) as a main component.

また、第３金属領域５０Ｃは、第２金属領域５０Ｂの主成分である金属元素と同じ金属元素を含んでも良い。例えば、第１金属領域５０Ａは、チタニウム（Ｔｉ）を主成分として含み、第２金属領域５０Ｂおよび第３金属領域５０Ｃは、アルミニウム（Ａｌ）を主成分として含む。例えば、第１金属領域５０Ａは、チタニウムもしくはチタニウム化合物であり、第２金属領域５０Ｂは、アルミニウム合金であり、第３金属領域５０Ｃは、アルミニウムである。また、第２金属領域５０Ｂおよび第３金属領域５０Ｃは、一体に形成されても良い。 Further, the third metal region 50C may contain the same metal element as the metal element which is the main component of the second metal region 50B. For example, the first metal region 50A contains titanium (Ti) as a main component, and the second metal region 50B and the third metal region 50C contain aluminum (Al) as a main component. For example, the first metal region 50A is titanium or a titanium compound, the second metal region 50B is an aluminum alloy, and the third metal region 50C is aluminum. Further, the second metal region 50B and the third metal region 50C may be integrally formed.

図２は、実施形態に係る半導体装置１００を示す模式断面図である。電力変換用のインバータおよびコンバータなどの機器は、所定の耐圧が得られるように、例えば、複数の半導体装置１００を積層して構成される。 FIG. 2 is a schematic cross-sectional view showing the semiconductor device 100 according to the embodiment. Devices such as inverters and converters for power conversion are configured by stacking, for example, a plurality of semiconductor devices 100 so as to obtain a predetermined withstand voltage.

図２に示すように、半導体装置１００は、半導体チップ１と、第１電極板６０と、第２電極板７０と、を含む。第１電極板６０と第２電極板７０との間に、複数の半導体チップ１が配置される。複数の半導体チップ１は、第１電極板６０および第２電極板７０に並列接続される。第１電極板６０には、例えば、半導体チップ１のコレクタ電極５０が接続される。第２電極板７０には、半導体チップ１のエミッタ電極３０が接続される。 As shown in FIG. 2, the semiconductor device 100 includes a semiconductor chip 1, a first electrode plate 60, and a second electrode plate 70. A plurality of semiconductor chips 1 are arranged between the first electrode plate 60 and the second electrode plate 70. The plurality of semiconductor chips 1 are connected in parallel to the first electrode plate 60 and the second electrode plate 70. For example, the collector electrode 50 of the semiconductor chip 1 is connected to the first electrode plate 60. The emitter electrode 30 of the semiconductor chip 1 is connected to the second electrode plate 70.

図２に示すように、半導体チップ１と第２電極板７０との間には、金属スペーサ７５が配置される。金属スペーサ７５は、半導体チップ１のエミッタ電極３０に接続される。また、金属スペーサ７５は、半導体チップ１と第２電極板７０との間に、ゲート配線７７を配置するスペースを確保できるＺ方向の厚さを有する。ゲート配線７７は、半導体チップ１のゲートパッド３５（図１参照）に接続される。 As shown in FIG. 2, a metal spacer 75 is arranged between the semiconductor chip 1 and the second electrode plate 70. The metal spacer 75 is connected to the emitter electrode 30 of the semiconductor chip 1. Further, the metal spacer 75 has a thickness in the Z direction that can secure a space for arranging the gate wiring 77 between the semiconductor chip 1 and the second electrode plate 70. The gate wiring 77 is connected to the gate pad 35 (see FIG. 1) of the semiconductor chip 1.

半導体装置１００では、例えば、第２電極板７０の上方から加えられる圧力により、第１電極板６０および第２電極板７０に半導体チップ１および金属スペーサ７５を圧接させる構成を有する。例えば、半導体チップ１の物理的な破壊（割れや欠け）を回避するために、コレクタ電極５０は、例えば、５μｍ以上、１５μｍ以下のＺ方向の厚さを有する柔らかい（硬度の低い）金属である。すなわち、加圧時にコレクタ電極５０が変形し、半導体チップ１と第１電極板６０との間の局部的な圧力集中を緩和することができる。同様に、エミッタ電極３０に接する金属スペーサ７５も柔らかい金属材料であることが好ましい。 The semiconductor device 100 has, for example, a configuration in which the semiconductor chip 1 and the metal spacer 75 are pressed against the first electrode plate 60 and the second electrode plate 70 by a pressure applied from above the second electrode plate 70. For example, in order to avoid physical destruction (cracking or chipping) of the semiconductor chip 1, the collector electrode 50 is, for example, a soft (low hardness) metal having a thickness of 5 μm or more and 15 μm or less in the Z direction. .. That is, the collector electrode 50 is deformed during pressurization, and the local pressure concentration between the semiconductor chip 1 and the first electrode plate 60 can be relaxed. Similarly, the metal spacer 75 in contact with the emitter electrode 30 is also preferably made of a soft metal material.

次に、図３、図４（ａ）～（ｃ）および図５を参照して、実施形態に係る半導体チップ１の製造方法を説明する。図３は、半導体チップ１の製造方法を示すフローチャートである。図４（ａ）～（ｃ）は、半導体チップ１の製造過程を示す模式断面図である。図５は、半導体チップ１の特性を示す模式断面図である。 Next, a method for manufacturing the semiconductor chip 1 according to the embodiment will be described with reference to FIGS. 3, 4 (a) to 4 (c) and FIG. FIG. 3 is a flowchart showing a manufacturing method of the semiconductor chip 1. 4 (a) to 4 (c) are schematic cross-sectional views showing a manufacturing process of the semiconductor chip 1. FIG. 5 is a schematic cross-sectional view showing the characteristics of the semiconductor chip 1.

図３のステップＳ０１に示すように、半導体ウェーハＳＷ（図４（ａ）参照）の表面にＭＯＳ構造２０を形成する。半導体ウェーハＳＷは、例えば、Ｎ形シリコンウェーハである。半導体ウェーハＳＷは、シリコンウェーハに限定される訳ではなく、炭化ケイ素（ＳｉＣ）、砒化ガリウム（ＧａＡｓ）および窒化ガリウム（ＧａＮ）などを材料とするものでも良い。また、ＭＯＳ構造は、図１に示したトレンチゲート型構造に限定される訳ではなく、プレーナーゲート型構造であっても良い。 As shown in step S01 of FIG. 3, the MOS structure 20 is formed on the surface of the semiconductor wafer SW (see FIG. 4A). The semiconductor wafer SW is, for example, an N-type silicon wafer. The semiconductor wafer SW is not limited to the silicon wafer, and may be made of silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or the like. Further, the MOS structure is not limited to the trench gate type structure shown in FIG. 1, and may be a planar gate type structure.

続いて、エミッタ電極３０およびゲートパッド３５を形成した後、半導体ウェーハＳＷの裏面を研削、研磨もしくはエッチングし、所定の厚さにする（Ｓ０２）。 Subsequently, after forming the emitter electrode 30 and the gate pad 35, the back surface of the semiconductor wafer SW is ground, polished or etched to obtain a predetermined thickness (S02).

さらに、半導体ウェーハＳＷの裏面側に、Ｐ形コレクタ層４０およびＮ形バッファ層４５を形成する（Ｓ０３）。Ｐ形コレクタ層４０およびＮ形バッファ層４５は、例えば、半導体ウェーハＳＷの裏面にＰ形不純物およびＮ形不純物をイオン注入することにより形成される。 Further, a P-type collector layer 40 and an N-type buffer layer 45 are formed on the back surface side of the semiconductor wafer SW (S03). The P-type collector layer 40 and the N-type buffer layer 45 are formed, for example, by ion-implanting P-type impurities and N-type impurities into the back surface of the semiconductor wafer SW.

次に、半導体ウェーハＳＷの裏面上に第１金属層５１を形成する（Ｓ０４）。
図４（ａ）に示すように、第１金属層５１は、Ｐ形コレクタ層４０の上に形成される。第１金属層５１は、例えば、スパッタ法を用いて形成される。第１金属層５１は、例えば、アルミニウム（Ａｌ）を主成分とする金属層である。また、第１金属層５１は、半導体ウェーハを構成する元素を含んでも良い。例えば、第１金属層５１は、シリコン（Ｓｉ）を含む。第１金属層５１は、例えば、コンタクトアニール時の温度におけるアルミニウムに対するシリコンの固溶限界もしくはそれ以上の割合でシリコンを含むことが好ましい。 Next, the first metal layer 51 is formed on the back surface of the semiconductor wafer SW (S04).
As shown in FIG. 4A, the first metal layer 51 is formed on the P-shaped collector layer 40. The first metal layer 51 is formed, for example, by using a sputtering method. The first metal layer 51 is, for example, a metal layer containing aluminum (Al) as a main component. Further, the first metal layer 51 may contain elements constituting the semiconductor wafer. For example, the first metal layer 51 contains silicon (Si). The first metal layer 51 preferably contains silicon at a ratio of, for example, a solid solution limit of silicon to aluminum at the temperature at the time of contact annealing or higher.

続いて、第１金属層５１の上に第２金属層５３および第３金属層５５を順に形成する（Ｓ０５）。第２金属層５３および第３金属層５５は、例えば、蒸着法を用いて形成される。第２金属層５３は、例えば、マグネシウム（Ｍｇ）を主成分とする金属層である。第３金属層は、例えば、アルミニウム（Ａｌ）を主成分とする金属層である。 Subsequently, the second metal layer 53 and the third metal layer 55 are sequentially formed on the first metal layer 51 (S05). The second metal layer 53 and the third metal layer 55 are formed, for example, by using a vapor deposition method. The second metal layer 53 is, for example, a metal layer containing magnesium (Mg) as a main component. The third metal layer is, for example, a metal layer containing aluminum (Al) as a main component.

図４（ｂ）に示すように、第１金属層５１の上に第２金属層５３を形成する。この際、第１金属層５１の表面に自然酸化膜５７が形成されている場合がある。 As shown in FIG. 4B, the second metal layer 53 is formed on the first metal layer 51. At this time, the natural oxide film 57 may be formed on the surface of the first metal layer 51.

例えば、第１金属層５１の主成分であるアルミニウムが酸化された場合、第１金属層５１の表面には絶縁膜である酸化アルミニウム膜が形成される。第２金属層５３は、アルミニウムよりも酸化物生成の標準自由エネルギーが大きいマグネシウムを主成分とする金属層である。このため、第２金属層５３を構成するマグネシウムの蒸着が開始され、第１金属層に付着する共に、自然酸化膜５７が還元され始める。 For example, when aluminum, which is the main component of the first metal layer 51, is oxidized, an aluminum oxide film, which is an insulating film, is formed on the surface of the first metal layer 51. The second metal layer 53 is a metal layer containing magnesium as a main component, which has a larger standard free energy for oxide formation than aluminum. Therefore, the vapor deposition of magnesium constituting the second metal layer 53 is started, and the natural oxide film 57 starts to be reduced while adhering to the first metal layer.

図４（ｃ）に示すように、第２金属層５３を形成した後、第３金属層５５を連続して形成する。例えば、第３金属層５５を形成する過程において、第１金属層５１と第２金属層５３との間に位置する自然酸化膜５７は還元され、第１金属層５１と第２金属層５３との間の電気抵抗が低減される。これにより、低抵抗のコレクタ電極５０を得ることができる。 As shown in FIG. 4C, after the second metal layer 53 is formed, the third metal layer 55 is continuously formed. For example, in the process of forming the third metal layer 55, the natural oxide film 57 located between the first metal layer 51 and the second metal layer 53 is reduced to form the first metal layer 51 and the second metal layer 53. The electrical resistance between is reduced. Thereby, the collector electrode 50 having low resistance can be obtained.

続いて、熱処理により半導体ウェーハＳＷ（Ｐ形コレクタ層４０）と第１金属層５１との間のオーミックコンタクトを形成する（Ｓ０６）。
例えば、第３金属層５５が高純度のアルミニウム層であり、第２金属層５３を設けない場合には、熱処理の過程において第１金属層５１から第３金属層５５へシリコン原子が拡散する。その結果、アルミニウムを主成分とする第１金属層５１中のシリコン原子の割合が低下し、半導体ウェーハＳＷと第１金属層５１中のアルミニウムの合金化反応が進む。この過程において、第１金属層５１の主成分と同じ金属を主成分とするスパイク状の突起が、半導体ウェーハＳＷと第１金属層５１の界面に形成される。この突起は、例えば、Ｐ形コレクタ層４０を突き抜けてＮ形バッファ層４５に達する場合があり、半導体チップ１の特性を劣化させる。 Subsequently, heat treatment is performed to form ohmic contact between the semiconductor wafer SW (P-type collector layer 40) and the first metal layer 51 (S06).
For example, when the third metal layer 55 is a high-purity aluminum layer and the second metal layer 53 is not provided, silicon atoms diffuse from the first metal layer 51 to the third metal layer 55 in the heat treatment process. As a result, the ratio of silicon atoms in the first metal layer 51 containing aluminum as a main component decreases, and the alloying reaction of aluminum in the semiconductor wafer SW and the first metal layer 51 proceeds. In this process, spike-shaped protrusions containing the same metal as the main component of the first metal layer 51 as the main component are formed at the interface between the semiconductor wafer SW and the first metal layer 51. This protrusion may penetrate the P-type collector layer 40 and reach the N-type buffer layer 45, for example, and deteriorate the characteristics of the semiconductor chip 1.

図５に示すように、第２金属層５３を設けることにより、第１金属層５１から第３金属層５５へのシリコン原子の拡散を抑制することができる。すなわち、第１金属層５１におけるシリコン原子の割合を維持し、半導体ウェーハＳＷと第１金属層５１中のアルミニウムの合金化反応を抑制することができる。これにより、半導体ウェーハＳＷと第１金属層５１との界面を均一に形成し、製造歩留りを向上させることができる。 As shown in FIG. 5, by providing the second metal layer 53, it is possible to suppress the diffusion of silicon atoms from the first metal layer 51 to the third metal layer 55. That is, the ratio of silicon atoms in the first metal layer 51 can be maintained, and the alloying reaction of aluminum in the semiconductor wafer SW and the first metal layer 51 can be suppressed. As a result, the interface between the semiconductor wafer SW and the first metal layer 51 can be uniformly formed, and the manufacturing yield can be improved.

上記の通り、本実施形態に係る半導体素子の製造方法では、スパッタ法を用いて第１金属層５１を形成し、その後、蒸着法を用いて第２金属層５３および第３金属層５５を形成する。例えば、スパッタ法は、所望の組成を有する金属層を再現性良く形成することが可能であり、半導体ウェーハＳＷと第１金属層５１との間に低抵抗のオーミックコンタクトを形成することができる。しかしながら、スパッタ法により厚い金属層を形成するには、長時間を要し、製造効率の点から現実的ではない。このため、第２金属層５３および第３金属層５５は、厚い金属層の形成に適した蒸着法を用いて形成される。 As described above, in the method for manufacturing a semiconductor device according to the present embodiment, the first metal layer 51 is formed by a sputtering method, and then the second metal layer 53 and the third metal layer 55 are formed by a thin film deposition method. do. For example, the sputtering method can form a metal layer having a desired composition with good reproducibility, and can form a low resistance ohmic contact between the semiconductor wafer SW and the first metal layer 51. However, it takes a long time to form a thick metal layer by the sputtering method, which is not realistic in terms of manufacturing efficiency. Therefore, the second metal layer 53 and the third metal layer 55 are formed by using a thin-film deposition method suitable for forming a thick metal layer.

また、蒸着法を用いて形成される第３金属層５５の密度は、スパッタ法を用いて形成され、同じ金属元素を主成分とする第１金属層５１よりも低い金属密度を有する。例えば、アルミニウム（Ａｌ）を主成分とする金属層を用いる場合、スパッタ法を用いて形成された第１金属層５１の方が、蒸着法を用いて形成された第３金属層５５よりも３％以上大きい金属密度を有する。金属密度は、例えば、透過Ｘ線を用いて測定される。 Further, the density of the third metal layer 55 formed by the vapor deposition method is lower than that of the first metal layer 51 formed by the sputtering method and containing the same metal element as a main component. For example, when a metal layer containing aluminum (Al) as a main component is used, the first metal layer 51 formed by the sputtering method is 3 more than the third metal layer 55 formed by the vapor deposition method. Has a metal density greater than%. The metal density is measured, for example, using transmitted X-rays.

一方、第１金属層５１と第２金属層５３を連続的に形成せず、第１金属層５１を形成した後、半導体ウェーハＳＷを外気に晒した場合、第１金属層５１の表面には自然酸化膜５７が形成され、第１金属層５１とその上に形成される金属層との間の電気抵抗が大きくなる。本実施形態では、第１金属層５１の主成分である金属元素よりも酸化物生成の標準自由エネルギーが大きい金属元素を主成分とする第２金属層５３を形成することにより、自然酸化膜５７を還元し、電気的に低抵抗のコレクタ電極５０を形成することができる。 On the other hand, when the semiconductor wafer SW is exposed to the outside air after the first metal layer 51 is formed without forming the first metal layer 51 and the second metal layer 53 continuously, the surface of the first metal layer 51 is exposed to the surface. The natural oxide film 57 is formed, and the electric resistance between the first metal layer 51 and the metal layer formed on the first metal layer 51 increases. In the present embodiment, the natural oxide film 57 is formed by forming the second metal layer 53 containing a metal element having a larger standard free energy for oxide formation than the metal element which is the main component of the first metal layer 51. Can be electrically formed to form a collector electrode 50 having a low resistance.

また、第１金属層５１としてチタニウム（Ｔｉ）を用いた場合には、第２金属層５３としてアルミニウム（Ａｌ）を主成分とする金属層を形成する。これにより、第１金属層５１の表面に形成される酸化チタニウムを還元し、低抵抗のコレクタ電極５０を得ることができる。また、チタニウムを主成分とする第１金属層５１の上に、マグネシウム（Ｍｇ）、リチウム（Ｌｉ）、カルシウム（Ｃａ）、のいずれかを主成分とする第２金属層５３を形成しても良い。 When titanium (Ti) is used as the first metal layer 51, a metal layer containing aluminum (Al) as a main component is formed as the second metal layer 53. As a result, titanium oxide formed on the surface of the first metal layer 51 can be reduced to obtain a collector electrode 50 having low resistance. Further, even if a second metal layer 53 containing any one of magnesium (Mg), lithium (Li), and calcium (Ca) as a main component is formed on the first metal layer 51 containing titanium as a main component. good.

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and variations thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

１…半導体チップ、 １０…Ｎ形ベース層、 １０Ｂ…裏面、 １０Ｔ…上面、 ２０…ＭＯＳ構造、 ２１…Ｐ形ベース層、 ２３…Ｎ形エミッタ層、 ２５…ゲート電極、 ２７…Ｐ形コンタクト層、 ３０…エミッタ電極、 ３３…絶縁膜、 ３５…ゲートパッド、 ４０…Ｐ形コレクタ層、 ４５…Ｎ形バッファ層、 ５０…コレクタ電極、 ５０Ａ…第１金属領域、 ５０Ｂ…第２金属領域、 ５０Ｃ…第３金属領域、 ５１…第１金属層、 ５３…第２金属層、 ５５…第３金属層、 ５７…自然酸化膜、 ６０…第１電極板、 ７０…第２電極板、 ７５…金属スペーサ、 ７７…ゲート配線、 １００…半導体装置、 ＳＷ…半導体ウェーハ 1 ... Semiconductor chip, 10 ... N-type base layer, 10B ... Back surface, 10T ... Top surface, 20 ... MOS structure, 21 ... P-type base layer, 23 ... N-type emitter layer, 25 ... Gate electrode, 27 ... P-type contact layer , 30 ... Emitter electrode, 33 ... Insulation film, 35 ... Gate pad, 40 ... P-type collector layer, 45 ... N-type buffer layer, 50 ... Collector electrode, 50A ... First metal region, 50B ... Second metal region, 50C … Third metal region, 51… first metal layer, 53… second metal layer, 55… third metal layer, 57… natural oxide film, 60… first electrode plate, 70… second electrode plate, 75… metal Spacer, 77 ... Gate wiring, 100 ... Semiconductor device, SW ... Semiconductor wafer

Claims (4)

半導体層と、
前記半導体層上に設けられ、前記半導体層に接した第１金属領域と、前記第１金属領域の上に設けられた第２金属領域と、前記半導体層から前記第２金属領域に向かう方向における前記第１金属領域および前記第２金属領域のトータル厚よりも厚い前記方向の厚さを有し、前記第２金属領域の上に設けられた第３金属領域と、を含む金属電極と、
を備え、
前記第２金属領域は、前記第１金属領域の主成分である金属元素よりも酸化物の標準生成自由エネルギーが大きい金属元素を主成分とし、
前記第１金属領域は、アルミニウム（Ａｌ）もしくはチタニウム（Ｔｉ）を主成分として含み、
前記第２金属領域は、マグネシウム（Ｍｇ）、リチウム（Ｌｉ）もしくはカルシウム（Ｃａ）のいずれかを主成分として含む半導体素子。 With the semiconductor layer,
A first metal region provided on the semiconductor layer and in contact with the semiconductor layer, a second metal region provided on the first metal region, and a direction from the semiconductor layer toward the second metal region. A metal electrode having a thickness in the above direction, which is thicker than the total thickness of the first metal region and the second metal region, and including a third metal region provided on the second metal region.
Equipped with
The second metal region is mainly composed of a metal element having a larger standard free energy for forming an oxide than the metal element which is the main component of the first metal region .
The first metal region contains aluminum (Al) or titanium (Ti) as a main component and contains.
The second metal region is a semiconductor device containing either magnesium (Mg), lithium (Li) or calcium (Ca) as a main component . 前記第３金属領域の主成分である金属元素は、前記第２金属領域の主成分である金属元素とは異なる請求項１記載の半導体素子。 The semiconductor element according to claim 1, wherein the metal element which is the main component of the third metal region is different from the metal element which is the main component of the second metal region. 前記第１金属領域の主成分である金属元素は、前記第３金属領域の主成分である前記金属元素と同じである請求項２記載の半導体素子。 The semiconductor element according to claim 2, wherein the metal element which is the main component of the first metal region is the same as the metal element which is the main component of the third metal region. 前記第１金属領域の金属密度は、前記第３金属領域の金属密度よりも高い請求項３記載の半導体素子。 The semiconductor device according to claim 3, wherein the metal density of the first metal region is higher than the metal density of the third metal region.
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