JP6956036B2 - Semiconductor devices and circuit control methods - Google Patents

Description

The present invention relates to a semiconductor device and a circuit control method, and more particularly to a semiconductor device having a timekeeping circuit having a single power supply operation function and a circuit control method for controlling the semiconductor device.

For example, Patent Document 1 is known as a document relating to a semiconductor device having a built-in timekeeping circuit. The semiconductor device according to Patent Document 1 is connected by switching one of two types of power supply terminals, a main power supply terminal connected to the main power supply and a backup power supply terminal connected to the backup power supply, to an internal power supply node by a switching circuit. It has a predetermined internal circuit that operates, and the switching circuit switches the switching transition time when switching the connection destination of the internal power supply node from the backup power supply terminal to the main power supply terminal, and when switching from the main power supply terminal to the backup power supply terminal. It is longer than the transition time.

The semiconductor device disclosed in Patent Document 1 has two power supplies, a main power supply and a backup power supply, and while suppressing wasteful consumption of the backup power supply, it is caused by undesired power supply switching due to noise during operation with the backup power supply. The purpose is to prevent malfunction of the internal circuit.

On the other hand, as an example of a timekeeping circuit having a single power supply operation function, for example, there is a real-time clock (Real Time Clock, hereinafter “RTC”) circuit. Further, as a semiconductor device having an RTC circuit built-in, for example, an MCU (Micro Controller Unit, so-called microcomputer) is known.

The MCU equipped with the RTC circuit may include a mode (hereinafter, "independent operation mode") in which a decrease in the power supply voltage is detected and the RTC circuit is operated independently in order to suppress the current consumption. FIG. 3 shows an MCU 100 according to a comparative example having a built-in RTC circuit. The MCU 100 includes an independent operation mode of the RTC circuit. As shown in FIG. 3, the MCU 100 has a first power supply PWR1 for operating a CPU (Central Processing Unit), a first regulator circuit 12, a second power supply PWR2 for operating an RTC circuit 42, and a first power supply PWR2. It is configured to include the regulator circuit 40 of 2.

The first regulator circuit 12 mainly drives the CPU 16, the first oscillation circuit 18, the FLASH RAM (FLASH Random Access Memory) 20, and the first power-on reset circuit 22 for the first regulator circuit 12 system circuit. On the other hand, the second regulator circuit 40 mainly drives the RTC circuit 42, the second oscillation circuit 44, the register 46, and the second power-on reset circuit 48 for the second regulator circuit 40 system circuit.

Here, the first power supply PWR1 is connected to a voltage level detection circuit 14 that powers down the first regulator circuit 12 according to the voltage level of the first power supply PWR1 for the independent operation of the RTC circuit 42. .. Even if the frequency information (frequency setting data) of the RTC circuit 42 and control data such as the enable signal of the RTC circuit 42 and the second oscillation circuit 44 are supplied from the CPU 16 to the register 46 and the first power supply PWR1 is powered down. It is held in the register 46 on the second regulator circuit 40 side.

Japanese Unexamined Patent Publication No. 2016-053789

By the way, in particular, since the second power supply PWR2 for operating the RTC circuit 42 generally uses a large-capacity capacitor or a battery having a small capacity, it is required to reduce the current consumption as much as possible. In this regard, the MCU 100 according to the comparative example is a circuit on the premise that the first power supply PWR1 is turned on first, and when the second power supply PWR2 is turned on first, the RTC circuit 42 has a normal frequency. The operation starts without the setting data being provided. Therefore, there is a problem that the RTC circuit 42 continues to consume the current of the power supply in a state where the desired frequency is not carved until the first power supply PWR1 is turned on.

On the other hand, in the semiconductor device according to Patent Document 1, the main power supply and the backup power supply are turned on at the same timing, and the malfunction and unnecessary current consumption that occur when the backup power supply is turned on first are dealt with. Not considered.

The present invention has been made in view of the above points, and is a semiconductor device having a built-in circuit having a single power supply operation function driven by a power supply of a separate system from the main power supply, and consumes current regardless of the order of power-on. It is an object of the present invention to provide a semiconductor device capable of reducing the number of electric currents and a circuit control method.

The semiconductor device according to the present invention has a first power supply, a processing circuit connected to the first power supply to execute a predetermined process, and the first power supply connected to the first power supply and turned on. A first circuit including a first generation circuit that generates the input signal shown, a second power supply, and a stand-alone operation circuit that is connected to the second power supply and operates based on operating conditions sent from the processing circuit. A storage circuit connected to the second power source to store the operating conditions sent from the processing circuit, and a second power source connected to the second power source to generate a state signal indicating an operating state of the second power source. When the holding circuit is connected to the second power source and holds the closing signal based on the state signal, and the holding circuit holds the closing signal, the operating condition is the independent operation. It includes one or more second circuits with control circuits that control them to be sent to the circuits.

In the circuit control method according to the present invention, the first power supply, the processing circuit connected to the first power supply to execute a predetermined process, and the first power supply connected to the first power supply are turned on. A first circuit provided with a first generation circuit for generating an input signal indicating A circuit, a storage circuit connected to the second power source and storing the operating conditions sent from the processing circuit, and a second power source connected to the second power source to generate a state signal indicating an operating state of the second power source. A circuit control method for controlling a semiconductor device including one or a plurality of second circuits including two generation circuits, based on the state signal by a holding circuit connected to the second power source. The input signal is held, and when the input signal is held in the holding circuit, the operating conditions are controlled so as to be sent to the independent operating circuit.

According to the present invention, in a semiconductor device having a built-in circuit having an independent power supply operation function driven by a power source of a system different from that of the main power supply, the semiconductor device capable of reducing current consumption regardless of the order in which the power is turned on. , And a circuit control method can be provided.

It is a block diagram which shows an example of the structure of the semiconductor device which concerns on 1st Embodiment. It is a block diagram which shows an example of the structure of the semiconductor device which concerns on 2nd Embodiment. It is a block diagram which shows an example of the structure of the semiconductor device which concerns on a comparative example.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the following description, as an example of the semiconductor device according to the present invention, the form applied to the MCU and the circuit having the independent power supply operation function according to the present invention (hereinafter, may be referred to as “independent operation circuit”) are applied to the RTC circuit. The form will be described by way of example. In this embodiment, in an MCU having a built-in independent operation circuit, the current consumption in the independent operation mode of the independent operation circuit is reduced.

[First Embodiment]
The semiconductor device and the circuit control method according to the present embodiment will be described with reference to FIG. As shown in FIG. 1, the MCU 10 according to the present embodiment is referred to as a first regulator circuit 12 (in FIG. 1, "REG1") for adjusting the voltage of the first power supply PWR1 and the first power supply PWR1 of the CPU system. (Notation), a second regulator circuit 40 (denoted as "REG2" in FIG. 1) for adjusting the voltage of the second power supply PWR2 and the second power supply PWR2 of the RTC circuit system is provided. Although the circuits of the first power supply PWR1 and the second power supply PWR2 are omitted, they are connected to terminals T1 and T2, respectively. The second power supply PWR2 may be a small capacity battery.

As shown in FIG. 1, the output of the first regulator circuit 12 includes a CPU 16, a first oscillation circuit 18 (denoted as “oscillation circuit 1” in FIG. 1), a FLASH RAM 20, and a first power-on reset. The circuit 22 (denoted as “POR1” in FIG. 1) is connected. It also includes a voltage level detection circuit 14 connected to the first power supply PWR1. The voltage level detection circuit 14 powers down the first regulator circuit 12 when the voltage level of the first power supply PWR1 drops. The first circuit 60 including each of the CPU 16, the first oscillation circuit 18, the FLASH RAM 20, and the first power-on reset circuit 22 corresponds to the “first circuit” according to the present invention.

The CPU 16 is a "processing circuit" according to the present invention that executes various processes in the MCU 10. The first oscillation circuit 18 generates a clock signal that serves as a reference for the operation of the CPU 16. The FLASH RAM 20 develops a program executed by the CPU 16 and stores the processing result. The first power-on reset circuit 22 performs a power-on reset process when the first power supply PWR1 is turned on.

On the other hand, the output of the second regulator circuit 40 includes an RTC circuit 42 (denoted as "RTC" in FIG. 1), a second oscillation circuit 44 (denoted as "oscillation circuit 2" in FIG. 1), and a register 46. , A second power-on reset circuit 48 (denoted as "POR2" in FIG. 1), and a latch circuit 50 are connected. Further, it includes an OR (logical sum) circuit 52 in which the signal from the register 46 and the signal from the latch circuit 50 are input and the output is connected to the RTC circuit 42 and the second oscillation circuit 44. The second circuit 62 including each of the RTC circuit 42, the second oscillation circuit 44, the register 46, the second power-on reset circuit 48, the latch circuit 50, and the OR circuit 52 is the "second circuit" according to the present invention. Corresponds to.

The RTC circuit 42 is a stand-alone operation circuit according to the present embodiment, and operates based on control data such as frequency information and enable signals output from the CPU 16 and held in the register 46. The second oscillation circuit 44 generates a clock signal that serves as a reference for the operation of the RTC circuit 42. The register 46 stores control data (enable signal, frequency information) from the CPU 16. The second power-on reset circuit 48 performs a power-on reset process when the second power supply PWR2 is turned on. The latch circuit 50 is a D-latch type latch circuit, in which the output of the first power-on reset circuit 22 is connected to the data input, the output of the second power-on reset circuit 48 is connected to the clock input, and the Q output. Is connected to the input of the OR circuit 52. The output of the OR circuit 52 is an enable signal for the RTC circuit 42 and the second oscillation circuit 44. The frequency information for the RTC circuit 42 stored in the register 46 is directly supplied to the RTC circuit 52.

That is, the MCU 10 according to the present embodiment adds a latch circuit 50 that latches the state of the first power-on reset circuit 22 under the second regulator circuit 40 with respect to the MCU 100 according to the comparative example. .. The frequency information of the RTC circuit 42 is sent from the register 46 to the RTC circuit 42 in the same manner as the MCU 100. On the other hand, the enable signal for the RTC circuit 42 and the second oscillation circuit 44 is sent via the OR circuit 52. The OR circuit 52 takes an OR of the enable signal from the register 46 and the latch signal which is the output of the latch circuit 50, and uses it as the enable signal.

Next, the operation of the MCU 10 will be described. Here, the first power-on reset circuit 22 and the second power-on reset circuit 48 generate a high-level (hereinafter, “H”) reset signal when the power is turned on, and the power supply exceeds a specified voltage. In the case, it becomes L and the reset is released. Further, the enable signal is enabled at H and disabled at the low level (hereinafter, “L”).

First, when the first power supply PWR1 is turned on first and then the second power supply PWR2 is turned on, control data such as an enable signal and frequency information is sent from the CPU 16 to the register 46, and the register 46 sends this. Hold. At this time, since L is input from the first power-on reset circuit 22 to the data input of the latch circuit 50, the signal that the second power-on reset circuit 48 transitions from L to H is the clock of the latch circuit 50. Upon being input to the input, the latch circuit 50 latches L. Therefore, the enable signal becomes H due to the data held in the register 46, and the second oscillation circuit 44 and the RTC circuit 42 start operating. After that, when the voltage level of the first power supply PWR1 drops, the voltage level detection circuit 14 detects this, and the first regulator circuit 12 powers down, only the second regulator circuit 40 operates and the register 46 The RTC circuit 42 can operate independently based on the control data held in.

Next, when the second power supply PWR2 is turned on first, since the first power-on reset circuit 22 outputs L, this L is latched by the latch circuit 50 and input to the OR circuit 52. .. At this time, since the first power supply PWR1 is not turned on, the control data is not sent to the register 46, so L is output from the register 46, and the enable signal output from the OR circuit 52 becomes L (invalid). Become. Therefore, the RTC circuit 42 and the second oscillation circuit 44 stop operating. As a result, the current consumption can be suppressed.

After that, when the first power supply PWR1 is turned on, control data (frequency information, enable signal, etc.) is sent from the CPU 16 as described above, and is held in the register 46 that receives the control data.
Since the output of the latch circuit 50 remains L, the enable signal becomes H (valid), and the second oscillation circuit 44 and the RTC circuit 42 can start operation. That is, the RTC circuit 42 can operate the timekeeping circuit based on the correct frequency information immediately after the first power supply PWR1 is turned on.

As described in detail above, in the present embodiment, a latch circuit 50 that holds the state of the first power-on reset circuit 22 is added under the second regulator circuit 40, and the output signal thereof and the enable from the CPU 16 are added. The signal obtained by ORing with the signal (the enable signal of the second oscillator circuit 44 and the enable signal of the RTC circuit 42) was used as a new enable signal of the second oscillator circuit 44 and the RTC circuit 42. As a result, even when the second power supply PWR2 is turned on first, the second oscillation circuit 44 and the RTC circuit 42 can be stopped and the current consumption can be suppressed.

[Second Embodiment]
The MCU 10A according to the present embodiment will be described with reference to FIG. In this embodiment, the number of power sources included in the MCU is 3 or more. In the above embodiment, the two power supply configurations have been illustrated and described, but the present embodiment can be applied to a plurality of power supplies by duplicating the configuration of the second power supply PWR2. In FIG. 2, the first power supply PWR1 and the first circuit 60, and the second power supply and the second circuit 62 are the same as the MCU 10 shown in FIG. As shown in FIG. 2, the MCU 10A is further configured to include (N-2) power supplies up to the Nth power supply included in the Nth circuit 62N, and to include N power supplies as a whole. Since the configuration from the third circuit to the Nth circuit is the same as that of the second circuit 62, detailed description thereof will be omitted.

While the first power supply PWR1 for operating the CPU 16 which is the main power supply is not turned on, even if the power is turned on from the second power supply PWR2 to the Nth power supply PWRN (one or more). Since the operation of the RTC circuit 42 to the RTC circuit 42N and the second oscillation circuit 44 to the second oscillation circuit 44N is stopped, the current consumption can be suppressed.

That is, when the power is turned on from the second power supply PWR2 to the Nth power supply PWRN in a state where the power is not turned on to the first power supply PWR1, the first power-on reset circuit 22 outputs L. There is. Therefore, L is latched by the signals of the second power-on reset circuit 48 to the Nth power-on reset circuit 48N, and the RTC circuit 42 to the RTC circuit 42N and the second oscillation circuit 44 to the second oscillation circuit 44N are latched. Stop operation. After that, when the first power supply PWR1 is turned on, each of the second circuit 60 to the Nth circuit 62N receives the control data from the CPU 16 and is held in the register 46N from each register 46. Since the output and OR of the latch circuit 50N are taken from the latch circuit 50, the circuit connected to the second power supply PWR2 to the Nth power supply PWRN operates even when the output of the latch circuit 50N from the latch circuit 50 is L. You can start.

In each of the above embodiments, the RTC circuit has been described as an example of the independent operation circuit, but the present invention is not limited to this, and any functional circuit for the purpose of independent operation can be applied. Further, in each of the above-described embodiments, the MCU has been described as an example of the semiconductor device, but the present invention is not limited to this, and the semiconductor device can be a semiconductor device according to a single operation circuit or the like to which the semiconductor device is applied.

10, 10A, 100 MCU
12 First regulator circuit 14 Voltage level detection circuit 16 CPU
18 First oscillator circuit 20 Flash RAM
22 First power-on reset circuit 40 Second regulator circuit 42 RTC circuit 44 Second oscillation circuit 46 Register 48 Second power-on reset circuit 50 Latch circuit 52 OR circuit 60 First circuit 62 Second circuit 100 MCU
PWR1 1st power supply PWR2 2nd power supply T1, T2 terminals

Claims (3)

A first power source, a processing circuit connected to the first power source to perform a predetermined process, and a first power source connected to the first power source to generate an on signal indicating that the first power source has been turned on. The first circuit with the generation circuit of
A second power supply, a single operating circuit connected to the second power supply and operating based on the operating conditions sent from the processing circuit, and the operating conditions connected to the second power supply and sent from the processing circuit. The storage circuit to be stored, the second generation circuit connected to the second power source to generate a state signal indicating the operating state of the second power source, and the second generation circuit connected to the second power source and based on the state signal. One or a plurality of second units having a holding circuit for holding the input signal and having a control circuit for controlling the operating conditions to be sent to the independent operation circuit when the input signal is held in the holding circuit. Circuits and include semiconductor devices. The processing circuit is a central processing unit.
The first generation circuit is the first power-on reset circuit.
The independent operation circuit is an oscillation circuit and a real-time clock circuit operated by the oscillation circuit.
The storage circuit is a register
The second generation circuit is a second power-on reset circuit.
The operating conditions include an enable signal for the oscillator circuit and the real-time clock circuit, and frequency information of the real-time clock circuit.
The holding circuit is a D-type latch circuit in which the output of the first power-on reset circuit is connected to a data input and the output of the second power-on reset circuit is connected to a clock input, and the control circuit is The semiconductor device according to claim 1, wherein the D-type latch circuit, the enable signal, and the output of the D-type latch circuit are input, and the output is a logical sum circuit as an enable signal for the oscillation circuit and the real-time clock circuit. .. A first power source, a processing circuit connected to the first power source to perform a predetermined process, and a first power source connected to the first power source to generate an on signal indicating that the first power source has been turned on. The first circuit with the generation circuit of
A second power supply, a stand-alone operating circuit connected to the second power supply and operating based on the operating conditions sent from the processing circuit, and the operating conditions connected to the second power supply and sent from the processing circuit. A semiconductor including a storage circuit for storing, one or more second circuits including a second generation circuit connected to the second power source and generating a state signal indicating an operating state of the second power source. It is a circuit control method that controls the device.
The holding circuit connected to the second power source holds the ON signal based on the state signal.
A circuit control method for controlling so that the operating conditions are sent to the independent operating circuit when the input signal is held in the holding circuit.

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