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JP6846484B2 - Substrates for semiconductor devices and their manufacturing methods, semiconductor devices - Google Patents

Substrates for semiconductor devices and their manufacturing methods, semiconductor devices Download PDF

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JP6846484B2
JP6846484B2 JP2019153514A JP2019153514A JP6846484B2 JP 6846484 B2 JP6846484 B2 JP 6846484B2 JP 2019153514 A JP2019153514 A JP 2019153514A JP 2019153514 A JP2019153514 A JP 2019153514A JP 6846484 B2 JP6846484 B2 JP 6846484B2
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semiconductor device
substrate
semiconductor element
resist layer
metal
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JP2020004991A (en
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佑也 五郎丸
佑也 五郎丸
真幸 林田
真幸 林田
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Maxell Ltd
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Maxell Holdings Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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Description

本発明は、底部に電極等の金属部が露出する形態の半導体装置を製造するのに用いる半導体装置用基板に関する。 The present invention relates to a semiconductor device substrate used for manufacturing a semiconductor device in which a metal portion such as an electrode is exposed on the bottom.

半導体素子規制用の基板上に半導体素子を搭載し、半導体素子と外部導出用の金属端子とを配線接続した上で、樹脂等の保護材で半導体素子を含む基板全体を被覆した旧来の構造の半導体装置は、その構造上、小型化には限界があった。これに対し、半導体素子搭載部分や電極部分となる金属部を形成し、この金属部上に半導体素子を搭載し、配線等の処理後、半導体素子や配線等のある金属部の表面側を樹脂等の封止材で封止し、金属部が底部に一部露出した構成とされる半導体装置は、その高さを低くして省スペース化が図れる他、露出した金属部を通じて半導体素子で生じた熱を外部に放出でき、放熱の面で優れるといった特長を有しており、チップサイズなど超小型の半導体装置の分野で利用が進んでいる。 A conventional structure in which a semiconductor element is mounted on a substrate for regulating semiconductor elements, the semiconductor element and a metal terminal for external derivation are connected by wiring, and the entire substrate including the semiconductor element is covered with a protective material such as resin. Due to the structure of semiconductor devices, there is a limit to miniaturization. On the other hand, a metal portion to be a semiconductor element mounting portion or an electrode portion is formed, the semiconductor element is mounted on the metal portion, and after processing such as wiring, the surface side of the metal portion having the semiconductor element or the wiring is made of resin. A semiconductor device that is sealed with a sealing material such as, etc., and has a structure in which the metal part is partially exposed at the bottom, can be reduced in height to save space, and is generated by a semiconductor element through the exposed metal part. It has the advantage of being able to release hot heat to the outside and is excellent in terms of heat dissipation, and is being used in the field of ultra-small semiconductor devices such as chip size.

こうした半導体装置は、主に、導電性を有する母型基板上に半導体素子搭載部分や電極部分となる金属部を、メッキを厚く形成する手法、いわゆる電鋳により、半導体装置の所望個数分まとめて形成し、半導体素子が搭載され配線等の処理を経た金属部の表面側を封止材で封止した後、母型基板のみを除去し、一体にまとまった状態の多数の半導体装置を個別に切り分ける、といった製造過程を経て製造される。このような半導体装置の製造方法の一例として、特開２００２−９１９６号公報や特開２００４−２１４２６５号公報に開示されるものがある。 In such semiconductor devices, a desired number of semiconductor devices are grouped together by a method of forming a thick plating on a metal portion to be a semiconductor element mounting portion or an electrode portion on a conductive mother mold substrate, so-called electrocasting. After forming and sealing the surface side of the metal part on which the semiconductor element is mounted and undergoing processing such as wiring with a sealing material, only the master substrate is removed, and a large number of semiconductor devices in an integrated state are individually formed. It is manufactured through a manufacturing process such as carving. As an example of a method for manufacturing such a semiconductor device, there are those disclosed in JP-A-2002-9196 and JP-A-2004-214265.

特開２００２−９１９６号公報Japanese Unexamined Patent Publication No. 2002-9196 特開２００４−２１４２６５号公報Japanese Unexamined Patent Publication No. 2004-214265

従来の半導体装置の製造方法は前記特許文献に示される構成となっており、母型基板上への金属部の形成にあたり、母型基板における金属部の形成位置に対応するようにレジスト層をあらかじめ形成して、金属部が電解メッキの手法により適切な位置に形成するようにしていた。この金属部には、メッキによる形成に適したニッケル等の金属が使用されており、導電性や配線用ワイヤの接合性を高めるために、金属部表面には一般に金メッキや銀メッキが施されていた。このメッキに対しても、レジスト層が必要箇所以外へのメッキの付着を防ぐ役割を果していた。そして、このレジスト層を溶剤等で除去した上で、母型基板とその表面に形成された金属部が、半導体装置用基板として供給された。この半導体装置用基板を用いて、実際の半導体装置の製造工程において、半導体素子の搭載や配線、封止材による封止等を行うようにしていた。 The conventional method for manufacturing a semiconductor device has the configuration shown in the above patent document, and when forming a metal portion on a master substrate, a resist layer is previously provided so as to correspond to the formation position of the metal portion on the master substrate. It was formed so that the metal part was formed at an appropriate position by the method of electroplating. A metal such as nickel, which is suitable for formation by plating, is used for this metal part, and the surface of the metal part is generally gold-plated or silver-plated in order to improve conductivity and bondability of wiring wires. It was. Also for this plating, the resist layer played a role of preventing the plating from adhering to places other than the required parts. Then, after removing the resist layer with a solvent or the like, the master substrate and the metal portion formed on the surface thereof were supplied as a substrate for a semiconductor device. Using this substrate for a semiconductor device, in the actual manufacturing process of the semiconductor device, the semiconductor element is mounted, the wiring, the sealing with the sealing material, and the like are performed.

近年、上記半導体装置用基板を用いて製造される半導体装置には、該半導体装置が用いられる電子機器のさらなる小型化を実現するために、低背化の要求がますます高まりつつあるが、これまでの構造では、半導体装置からの半導体素子搭載部分や電極部分の脱落を防止するために、半導体素子搭載部分や電極部分をなす金属部の薄型化には限界があり、さらに半導体素子自体も所定の強度を与えるために一定の厚さを確保する必要があり、さらなる薄型化、低背化が困難であるという課題を有していた。なお、半導体素子搭載部分をなくす構造も考えられるが、そうすると、半導体素子を搭載する際に、半導体素子の位置ズレが避けられなかった。 In recent years, semiconductor devices manufactured using the above-mentioned semiconductor device substrates are increasingly required to have a low profile in order to realize further miniaturization of electronic devices in which the semiconductor devices are used. In the structure up to, in order to prevent the semiconductor element mounting portion and the electrode portion from falling off from the semiconductor device, there is a limit to thinning the metal portion forming the semiconductor element mounting portion and the electrode portion, and the semiconductor element itself is also predetermined. It is necessary to secure a certain thickness in order to give the strength of the above, and there is a problem that it is difficult to further reduce the thickness and height. Although a structure in which the semiconductor element mounting portion is eliminated is conceivable, in that case, the position shift of the semiconductor element is unavoidable when the semiconductor element is mounted.

本発明は前記課題を解消するためになされたもので、適切な箇所に規制部を設けて、得られる半導体装置各部の構造を最適化できると共に、効率よく半導体装置を製造できる、半導体装置用基板と当該基板の製造方法、並びに、この半導体装置用基板を用いて製造される半導体装置、及びその製造方法を提供することを目的とする。 The present invention has been made to solve the above problems, and a substrate for a semiconductor device capable of providing a regulating portion at an appropriate position to optimize the structure of each part of the obtained semiconductor device and efficiently manufacturing the semiconductor device. An object of the present invention is to provide a method for manufacturing the substrate, a semiconductor device manufactured by using the substrate for the semiconductor device, and a method for manufacturing the same.

本発明の開示に係る半導体装置用基板は、母型基板１０上に少なくとも電極部１１ｂとなる金属部１１が形成される半導体装置用基板において、母型基板１０上には、半導体素子１４を規制する規制部１１ａが設けられたものである。 The substrate for a semiconductor device according to the disclosure of the present invention is a substrate for a semiconductor device in which at least a metal portion 11 to be an electrode portion 11b is formed on a master substrate 10, and a semiconductor element 14 is regulated on the master substrate 10. The regulation unit 11a is provided.

このように本発明の開示によれば、母型基板１０上に半導体素子１４を規制するための規制部１１ａが設けられることにより、半導体装置用基板を用いた半導体装置の製造にあたり、半導体素子１４を搭載する際に、半導体素子１４の位置ズレを防止することができる。 As described above, according to the disclosure of the present invention, the semiconductor element 14 is provided on the master substrate 10 to regulate the semiconductor element 14, so that the semiconductor element 14 can be manufactured using the semiconductor device substrate. It is possible to prevent the semiconductor element 14 from being displaced when the semiconductor element 14 is mounted.

また、本発明の開示に係る半導体装置用基板は、規制部１１ａが前記金属部１１に貫通孔１１ｅを形成することで設けられたものである。係る貫通孔１１ｅの形状は、半導体素子１４が収容可能な大きさとしている。 Further, the substrate for a semiconductor device according to the disclosure of the present invention is provided by the regulating portion 11a forming a through hole 11e in the metal portion 11. The shape of the through hole 11e is large enough to accommodate the semiconductor element 14.

このように本発明の開示によれば、規制部１１ａが金属部１１に貫通孔１１ｅを形成することで設けられたものであり、該貫通孔貫通孔１１ｅの形状（大きさ）として、半導体素子１４が収容可能な大きさとなるようにすることにより、半導体装置製造の際に、半導体素子１４を貫通孔１１ｅ（規制部１１ａ）内に配設した場合、半導体素子１４の位置ズレを防止できるだけでなく、従来のように半導体素子搭載部の上面に搭載される場合と比べて、配設位置を下げることができ、半導体素子１１上面や、電極部１１ｂと半導体素子１４とを接合するワイヤ等の高さも下がる分、半導体装置の厚さを小さくして製造することができ、半導体装置の低背化を実現できる。また、半導体素子１４の位置が下がって、ワイヤ１５が接合する半導体素子１４と電極部１１ｂの各上面が互いに近付く分、ワイヤ長さも短くすることができ、ワイヤ１５の使用量を削減してコストを低減できる。なお、貫通孔１１ｅの形状は、半導体素子１４と同形状とするのが好ましい。 As described above, according to the disclosure of the present invention, the regulation portion 11a is provided by forming the through hole 11e in the metal portion 11, and the shape (size) of the through hole through hole 11e is a semiconductor device. By making the size 14 accommodating, when the semiconductor element 14 is arranged in the through hole 11e (regulating portion 11a) at the time of manufacturing the semiconductor device, it is possible to prevent the semiconductor element 14 from being displaced. Instead, the arrangement position can be lowered as compared with the case where it is mounted on the upper surface of the semiconductor element mounting portion as in the conventional case, and the upper surface of the semiconductor element 11 or the wire for joining the electrode portion 11b and the semiconductor element 14 can be used. Since the height is also lowered, the thickness of the semiconductor device can be reduced for manufacturing, and the height of the semiconductor device can be reduced. Further, the position of the semiconductor element 14 is lowered, and the wire length can be shortened by the amount that the semiconductor element 14 to which the wire 15 is bonded and the upper surfaces of the electrode portion 11b are brought closer to each other, so that the amount of the wire 15 used can be reduced and the cost can be reduced. Can be reduced. The shape of the through hole 11e is preferably the same as that of the semiconductor element 14.

また、本発明の開示に係る半導体装置用基板は、規制部１１ａの高さ寸法が半導体素子１４の厚み寸法以上に設定されたものである。 Further, in the substrate for a semiconductor device according to the disclosure of the present invention, the height dimension of the regulating portion 11a is set to be equal to or larger than the thickness dimension of the semiconductor element 14.

このように本発明の開示によれば、規制部１１ａの高さ寸法を半導体素子１４の厚み寸法以上に設定することにより、半導体装置製造の際に収容される半導体素子１４の側面全体を規制部１１ａによって規制することができるので、半導体素子１４の位置ズレを防止することができる。さらに、該規制部１１ａが貫通孔１１ｅから成るものであり、貫通孔１１ｅの深さ寸法を半導体素子１４の厚み寸法以上に設定することにより、半導体素子１４の側面全面が規制部１１ａに囲まれて規制されることになるので、半導体素子１４の位置ズレをより確実に防止することができる。 As described above, according to the disclosure of the present invention, by setting the height dimension of the regulating portion 11a to be equal to or larger than the thickness dimension of the semiconductor element 14, the entire side surface of the semiconductor element 14 accommodated in the manufacture of the semiconductor device is regulated. Since it can be regulated by 11a, it is possible to prevent the semiconductor element 14 from being displaced. Further, the regulation portion 11a is composed of the through hole 11e, and by setting the depth dimension of the through hole 11e to be equal to or larger than the thickness dimension of the semiconductor element 14, the entire side surface of the semiconductor element 14 is surrounded by the regulation portion 11a. Therefore, the displacement of the semiconductor element 14 can be prevented more reliably.

また、本発明の開示に係る半導体装置用基板の製造方法は、母型基板１０上に電極部１１ｂ及び半導体素子１４を規制する規制部１１ａとなる金属部１１が設けられた半導体装置用基板の製造方法において、母型基板１０上に金属部１１の形成位置に対応する第一レジスト層１２を形成する工程と、母型基板１０表面の第一レジスト層１２で覆われていない露出領域に金属部１１を形成する工程とを有し、第一レジスト層１２の設定により所定形状の金属部１１を得るものである。 Further, the method for manufacturing a substrate for a semiconductor device according to the disclosure of the present invention is a substrate for a semiconductor device in which an electrode portion 11b and a metal portion 11 serving as a regulating portion 11a for regulating the semiconductor element 14 are provided on a master substrate 10. In the manufacturing method, a step of forming the first resist layer 12 corresponding to the formation position of the metal portion 11 on the master substrate 10 and a metal in an exposed region not covered by the first resist layer 12 on the surface of the master substrate 10. It has a step of forming the portion 11, and obtains a metal portion 11 having a predetermined shape by setting the first resist layer 12.

このように本発明の開示によれば、金属部１１の形成において、第一レジスト層１２を設定することにより、電極部１１ｂ及び規制部１１ａとなる金属部１１を母型基板１０上に正確且つ容易に配置形成することができる。 As described above, according to the disclosure of the present invention, in the formation of the metal portion 11, by setting the first resist layer 12, the metal portion 11 serving as the electrode portion 11b and the regulation portion 11a can be accurately and accurately formed on the master substrate 10. It can be easily arranged and formed.

また、本発明の開示に係る半導体装置用基板の製造方法は、第一レジスト層１２が、半導体素子１４の配置箇所に形成され、金属部１１の形成終了後、最終的に第一レジスト層１２を除去することで、半導体素子配置箇所における、第一レジスト層１２が存在していた部位に貫通孔１１ｅを生じさせるものである。 Further, in the method for manufacturing a substrate for a semiconductor device according to the disclosure of the present invention, the first resist layer 12 is formed at a location where the semiconductor element 14 is arranged, and after the formation of the metal portion 11 is completed, the first resist layer 12 is finally formed. By removing the above, a through hole 11e is generated in the portion where the first resist layer 12 was present at the semiconductor element arrangement location.

このように本発明の開示によれば、第一レジスト層１２を半導体素子１４の配置位置となる部位に配設して、最終的に形成された金属部１１の半導体素子配置位置における第一レジスト層１２の形状に応じた貫通孔１１ｅを生じさせることにより、得られた半導体装置用基板を用いて半導体装置を製造する際に、半導体素子１４を貫通孔１１ｅ内に配置することができ、半導体素子の側面全体を規制することが可能となる。 As described above, according to the disclosure of the present invention, the first resist layer 12 is arranged at the portion to be the arrangement position of the semiconductor element 14, and the first resist at the semiconductor element arrangement position of the finally formed metal portion 11. By generating the through hole 11e according to the shape of the layer 12, the semiconductor element 14 can be arranged in the through hole 11e when manufacturing a semiconductor device using the obtained substrate for the semiconductor device, and the semiconductor. It is possible to regulate the entire side surface of the element.

また、本発明の開示に係る半導体装置用基板の製造方法は、母型基板１０上に第一レジスト層１２を形成した後、少なくとも第一レジスト層１２上に、第二レジスト層１６を形成し、第一レジスト層１２の厚さを越える一方、第二レジスト層１６を越えない厚さで金属部１１を形成することにより、第一レジスト層１２寄りの金属部１１上端周縁には第一レジスト層１２側に張出した略庇状の張出部１１ｃが形成されるものである。 Further, in the method for manufacturing a substrate for a semiconductor device according to the disclosure of the present invention, after forming the first resist layer 12 on the master substrate 10, the second resist layer 16 is formed on at least the first resist layer 12. By forming the metal portion 11 with a thickness exceeding the thickness of the first resist layer 12 but not exceeding the thickness of the second resist layer 16, the first resist is formed on the upper peripheral edge of the metal portion 11 near the first resist layer 12. A substantially erect-shaped overhanging portion 11c is formed overhanging on the layer 12 side.

このように本発明の開示によれば、半導体装置を構成する金属部１１のうち、第一レジスト層１２寄りの金属部１１上端周縁には張出部１１ｃが形成されていることにより、得られた半導体装置用基板を用いて半導体装置を製造する際の封止材１９による封止状態において、封止材１９は張出部１１ｃがくい込み状に位置した状態で硬化しているため、この喰い付き効果により、半導体装置から母型基板１０を引き剥がし除去する時に、金属部１１は封止材１９側に確実に残留し、母型基板１０とともにくっついて引き離されることはなく、金属部１１のズレや欠落等が効果的に防止でき、製造工程時の歩留まりを向上できる。その一方で、第二レジスト層１６寄りの金属部１１上端周縁には張出部１１ｃが形成されていないので、貫通孔１１ｅ内への半導体素子１４の配設をスムーズに行うことができる。 As described above, according to the disclosure of the present invention, among the metal portions 11 constituting the semiconductor device, the overhanging portion 11c is formed on the peripheral edge of the upper end of the metal portion 11 near the first resist layer 12. In the state of being sealed by the sealing material 19 when manufacturing a semiconductor device using the substrate for the semiconductor device, the sealing material 19 is hardened in a state where the overhanging portion 11c is positioned in a bite shape, and thus this bite. Due to the attachment effect, when the master substrate 10 is peeled off and removed from the semiconductor device, the metal portion 11 surely remains on the sealing material 19 side and does not stick to and separate from the master substrate 10 and is not separated from the metal portion 11. Misalignment and chipping can be effectively prevented, and the yield during the manufacturing process can be improved. On the other hand, since the overhanging portion 11c is not formed on the peripheral edge of the upper end of the metal portion 11 near the second resist layer 16, the semiconductor element 14 can be smoothly arranged in the through hole 11e.

また、本発明の開示に係る半導体装置は、半導体素子１４と電気的に接続する電極部１１ｂを有し、半導体素子１４の搭載、半導体素子１４と電極部１１ｂとの電気的接続、封止材１９による封止がなされ、装置底部に電極部１１ｂの裏面側が露出される半導体装置において、半導体素子１４を規制する規制部１１ａが設けられているものである。 Further, the semiconductor device according to the disclosure of the present invention has an electrode portion 11b that is electrically connected to the semiconductor element 14, and is mounted on the semiconductor element 14, electrically connected to the semiconductor element 14 and the electrode portion 11b, and a sealing material. In a semiconductor device that is sealed by 19 and the back surface side of the electrode portion 11b is exposed at the bottom of the device, a regulating portion 11a that regulates the semiconductor element 14 is provided.

このように本発明の開示によれば、半導体素子１４を規制する規制部１１ａが設けられていることにより、半導体素子１４を規制部１１ａによって規制することができ、半導体素子１４の位置ズレを防止することができる。 As described above, according to the disclosure of the present invention, since the regulation unit 11a for regulating the semiconductor element 14 is provided, the semiconductor element 14 can be regulated by the regulation unit 11a, and the displacement of the semiconductor element 14 is prevented. can do.

また、本発明の開示に係る半導体装置は、規制部１１ａが半導体素子１４と電極部１１ｂとを接合するワイヤ１５のループ頂部１５’の直下位置に設けられたものである。 Further, in the semiconductor device according to the disclosure of the present invention, the regulation portion 11a is provided at a position directly below the loop top 15'of the wire 15 for joining the semiconductor element 14 and the electrode portion 11b.

このように本発明の開示によれば、規制部１１ａをワイヤ１５のループ頂部１５’の直下位置と重なるように配置することにより、規制部１１ａによる半導体素子１４の位置ズレを防止することができ、しかも、規制部１１ａとワイヤ１５とが最も離れた位置関係とすることができるので、規制部１１ａとワイヤ１５との接触を可及的に防止することができる。 As described above, according to the disclosure of the present invention, by arranging the regulating portion 11a so as to overlap the position directly below the loop top 15'of the wire 15, it is possible to prevent the semiconductor element 14 from being displaced by the regulating portion 11a. Moreover, since the restricting portion 11a and the wire 15 can be in the most distant positional relationship, contact between the regulating portion 11a and the wire 15 can be prevented as much as possible.

本発明の第１実施形態に係る半導体装置用基板の要部拡大図である。It is an enlarged view of the main part of the substrate for a semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置用基板の製造方法における工程説明図である。It is a process explanatory drawing in the manufacturing method of the substrate for a semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置用基板の製造方法における工程説明図である。It is a process explanatory drawing in the manufacturing method of the substrate for a semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置用基板の製造方法における工程説明図である。It is a process explanatory drawing in the manufacturing method of the substrate for a semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置用基板の製造方法における工程説明図である。It is a process explanatory drawing in the manufacturing method of the substrate for a semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and bottom view of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置の別実施例の断面図及び底面図である。It is sectional drawing and bottom view of another Example of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第２実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and bottom view of the semiconductor device which concerns on 2nd Embodiment of this invention. 本発明の第３実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and bottom view of the semiconductor device which concerns on 3rd Embodiment of this invention. 本発明の第４実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and bottom view of the semiconductor device which concerns on 4th Embodiment of this invention. 本発明の第５実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and bottom view of the semiconductor device which concerns on 5th Embodiment of this invention. 本発明の第５実施形態に係る半導体装置の別実施例の断面図及び底面図である。It is sectional drawing and bottom view of another Example of the semiconductor device which concerns on 5th Embodiment of this invention. 本発明の第６実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and bottom view of the semiconductor device which concerns on 6th Embodiment of this invention. 本発明に係る規制部と半導体素子の配置状態説明図である。It is explanatory drawing of the arrangement state of the regulation part and the semiconductor element which concerns on this invention.

（第１実施形態）
以下、本発明の第１の実施形態に係る半導体装置用基板を図１ないし図７に基づいて説明する。前記各図において本実施形態に係る半導体装置用基板１は、導電性を有する材質からなる母型基板１０と、この母型基板１０上に形成され、本基板を用いて製造される半導体装置７０の少なくとも電極部１１ｂとなる金属部１１と、金属部１１表面にメッキにより形成される表面金属層１３とを備える構成である。 (First Embodiment)
Hereinafter, the semiconductor device substrate according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 7. In each of the above figures, the semiconductor device substrate 1 according to the present embodiment is a master substrate 10 made of a conductive material and a semiconductor device 70 formed on the master substrate 10 and manufactured by using the substrate. It is configured to include at least a metal portion 11 serving as an electrode portion 11b, and a surface metal layer 13 formed by plating on the surface of the metal portion 11.

この半導体装置用基板１を用いて製造される半導体装置７０は、図６に示すように、半導体装置用基板１から得られる金属部１１及び表面金属層１３に加えて、金属部１１のうちの電極部１１ｂと電気的に接続する半導体素子１４と、この半導体素子１４と電極部１１ｂとを接合するワイヤ１５と、半導体素子１４やワイヤ１５を含む金属部１１の表面側を覆って封止する封止材１９とを備える構成である。 As shown in FIG. 6, in the semiconductor device 70 manufactured by using the semiconductor device substrate 1, in addition to the metal portion 11 and the surface metal layer 13 obtained from the semiconductor device substrate 1, the metal portion 11 is included. The semiconductor element 14 that is electrically connected to the electrode portion 11b, the wire 15 that joins the semiconductor element 14 and the electrode portion 11b, and the surface side of the metal portion 11 including the semiconductor element 14 and the wire 15 are covered and sealed. It is configured to include a sealing material 19.

この半導体装置７０では、底部に金属部１１の裏面側が電極や放熱パッド等として露出した状態となり（図６（Ｂ）参照）、この露出する金属部１１の裏面側と、装置外装の一部として現れる封止材１９の裏面側とが略同一平面上に位置する構成である。半導体装置７０における底部以外の各面は、装置外装をなす封止材１９のみがそれぞれ現れた状態となっている。 In the semiconductor device 70, the back surface side of the metal portion 11 is exposed as an electrode, a heat dissipation pad, or the like on the bottom portion (see FIG. 6B), and the back surface side of the exposed metal portion 11 and a part of the device exterior are used. The structure is such that the back surface side of the sealing material 19 that appears is located on substantially the same plane. On each surface of the semiconductor device 70 other than the bottom, only the sealing material 19 forming the exterior of the device appears.

前記半導体装置用基板１は、母型基板１０上に、金属部１１の配置部分が露出されるように第一レジスト層１２に引き続き第二レジスト層１６を形成した後、メッキにより金属部１１を形成し、さらに、金属部１１表面にメッキにより表面金属層１３を形成した後、第一レジスト層１２及び第二レジスト層１６を除去することで製造されるものである。 In the semiconductor device substrate 1, the second resist layer 16 is formed on the master substrate 10 following the first resist layer 12 so that the arrangement portion of the metal portion 11 is exposed, and then the metal portion 11 is plated. It is produced by forming the surface metal layer 13 by plating on the surface of the metal portion 11, and then removing the first resist layer 12 and the second resist layer 16.

また、この半導体装置用基板１を用いた半導体装置の製造の際は、この半導体装置用基板１に対し、半導体素子１４の搭載及び配線、封止材１９による封止がなされ、封止の後、半導体装置部分から母型基板１０を除去して半導体装置７０を得る仕組みである。 Further, when manufacturing a semiconductor device using the semiconductor device substrate 1, the semiconductor device substrate 1 is mounted and wired with a semiconductor element 14 and sealed with a sealing material 19, and after sealing. , The mechanism is such that the master substrate 10 is removed from the semiconductor device portion to obtain the semiconductor device 70.

母型基板１０は、ステンレス（ＳＵＳ４３０等）やアルミニウム、銅等の導電性の金属板（厚さ約０．１ｍｍ）で形成され、半導体装置の製造工程で除去されるまで、半導体装置用基板１の要部をなすものであり、半導体装置用基板製造工程の各段階で、表面側に第一レジスト層１２、金属部１１が形成され、また裏面側にレジスト層１８が配設される。金属部１１の形成の際には、この母型基板１０を介した通電がなされることで、母型基板１０表面の第一レジスト層１２に覆われない通電可能な部分（露出領域）に電解メッキで金属部１１が形成されることとなる。また、表面金属層１３のメッキの際も、電解メッキとする場合には、母型基板１０を介して通電がなされる。 The base substrate 10 is made of a conductive metal plate (thickness of about 0.1 mm) such as stainless steel (SUS430, etc.), aluminum, copper, etc., and is a substrate for a semiconductor device 1 until it is removed in the manufacturing process of the semiconductor device. The first resist layer 12 and the metal portion 11 are formed on the front surface side, and the resist layer 18 is arranged on the back surface side at each stage of the substrate manufacturing process for semiconductor devices. When the metal portion 11 is formed, electricity is applied through the master substrate 10 to electrolyze the energizable portion (exposed region) on the surface of the master substrate 10 that is not covered by the first resist layer 12. The metal portion 11 is formed by plating. Further, also when plating the surface metal layer 13, in the case of electrolytic plating, energization is performed via the master substrate 10.

一方、半導体装置用基板１を用いた半導体装置の製造工程では、母型基板１０上の金属部１１表面側が封止材１９で覆われ（図５（Ｂ）参照）、母型基板１０で金属部１１及び封止材１９を支持しなくても十分な強度が得られたら、母型基板１０が除去される（図５（Ｃ）参照）。母型基板１０がステンレスの場合には、力を加えて半導体装置側から物理的に引き剥がして除去する方法が採られ、また、母型基板１０が銅等の場合、薬液を用いて溶解除去するエッチングの方法が用いられる。エッチングの場合、母型基板１０は溶解するが金属部１１のニッケル等の材質が冒されないような選択エッチング性を有するエッチング液を用いることとなる。この母型基板１０が除去されると、半導体装置底部に、金属部１１（電極部１１ｂ）及び封止材１９の各裏面が同一平面上に露出した状態が得られる。 On the other hand, in the manufacturing process of the semiconductor device using the semiconductor device substrate 1, the surface side of the metal portion 11 on the master substrate 10 is covered with the sealing material 19 (see FIG. 5B), and the master substrate 10 is made of metal. When sufficient strength is obtained without supporting the portion 11 and the sealing material 19, the master substrate 10 is removed (see FIG. 5C). When the master substrate 10 is stainless steel, a method of physically peeling it off from the semiconductor device side by applying force is adopted, and when the master substrate 10 is copper or the like, it is dissolved and removed using a chemical solution. Etching method is used. In the case of etching, an etching solution having selective etching property is used so that the master substrate 10 is melted but the material such as nickel of the metal portion 11 is not affected. When the master substrate 10 is removed, a state is obtained in which the back surfaces of the metal portion 11 (electrode portion 11b) and the sealing material 19 are exposed on the same plane at the bottom of the semiconductor device.

前記金属部１１は、電解メッキに適したニッケルや銅、又はニッケル−コバルト等のニッケル合金からなり、母型基板１０上の第一レジスト層１２から露出する部分に、電解メッキで形成される構成である。半導体装置用基板１において、金属部１１は、母型基板１０表面で、一又は複数配置される電極部１１ｂを一つの単位として、製造する半導体装置の数だけ多数整列状態で並べられた形態で形成されることとなる。 The metal portion 11 is made of nickel or copper suitable for electrolytic plating, or a nickel alloy such as nickel-cobalt, and is formed by electroplating on a portion exposed from the first resist layer 12 on the master substrate 10. Is. In the semiconductor device substrate 1, the metal portions 11 are arranged on the surface of the master substrate 10 in an aligned state as many as the number of semiconductor devices to be manufactured, with one or a plurality of electrode portions 11b as one unit. It will be formed.

この金属部１１は、第一レジスト層１２の厚さを越える厚さ（例えば、厚さ約６０〜８０μｍ）で、且つ上端周縁には第一レジスト層１２表面側に張出した略庇状の張出し部１１ｃを有する形状として形成される。張出し部１１ｃは、電解メッキの際、金属部１１を第一レジスト層１２の厚さまで形成した後も電解メッキを継続して、金属部の成長を厚さ方向に加えて第一レジスト層１２による制限のない他の向きにも進行させることで、第一レジスト層１２を越えた金属部１１上端部から第一レジスト層１２側へ張出した形状として得られるものである。この張出し部１１ｃは、封止材１９による封止に伴って、封止材１９で挟まれて固定された状態（アンカー効果）となる。 The metal portion 11 has a thickness exceeding the thickness of the first resist layer 12 (for example, a thickness of about 60 to 80 μm), and has a substantially eaves-like overhang extending toward the surface side of the first resist layer 12 on the upper peripheral periphery. It is formed as a shape having a portion 11c. The overhanging portion 11c is formed by the first resist layer 12 by continuing the electrolytic plating even after the metal portion 11 is formed to the thickness of the first resist layer 12 at the time of electrolytic plating, and adding the growth of the metal portion in the thickness direction. By advancing in other directions without limitation, it is obtained as a shape protruding from the upper end of the metal portion 11 beyond the first resist layer 12 toward the first resist layer 12. The overhanging portion 11c is sandwiched and fixed by the sealing material 19 as it is sealed by the sealing material 19 (anchor effect).

この他、金属部１１として、半導体装置製造の際に半導体素子１４を規制するための規制部１１ａが設けられる。具体的には、半導体素子１４の配置箇所にあたる金属部１１に貫通孔１１ｅを形成することで規制部１１ａとしている。この規制部１１ａは、第一レジスト層１２を形成した後、規制部１１ａに対応する箇所に第二レジスト層１６を配設し、係る個所の第一レジスト層１２及び第二レジスト層１６を除去することで貫通孔１１ｅが生じ、規制部１１ａとなるものであり、半導体素子１４を規制するのに必要な強度を維持する厚さとされる。係る規制部１１ａによって半導体素子１４を規制することができ、半導体素子１４を搭載する際に、半導体素子１４の位置ズレを防止することができる。この規制部１１ａの裏面も、電極部１１ｂと同様に、封止材１９の裏面と同一平面上に露出されることになる。 In addition, as the metal portion 11, a regulating portion 11a for regulating the semiconductor element 14 at the time of manufacturing a semiconductor device is provided. Specifically, the regulation portion 11a is formed by forming a through hole 11e in the metal portion 11 corresponding to the arrangement location of the semiconductor element 14. After forming the first resist layer 12, the regulating portion 11a disposes the second resist layer 16 at a portion corresponding to the regulating portion 11a, and removes the first resist layer 12 and the second resist layer 16 at the location. By doing so, a through hole 11e is generated, which serves as a regulating portion 11a, and has a thickness that maintains the strength required to regulate the semiconductor element 14. The semiconductor element 14 can be regulated by the regulating unit 11a, and the position shift of the semiconductor element 14 can be prevented when the semiconductor element 14 is mounted. The back surface of the regulating portion 11a is also exposed on the same plane as the back surface of the sealing material 19 as in the electrode portion 11b.

金属部１１は、大部分を電解メッキに適したニッケルやニッケル合金等で形成されるが、金属部１１の裏面側には、半導体装置実装時のハンダ付けを適切に行えるようにするために、ニッケル等の主材質部よりハンダぬれ性の良好な金属、例えば金や銀、錫、パラジウム、ハンダ等の薄膜１１ｄが配設される構成である。この薄膜１１ｄの厚さは０．０１〜１μｍ程度とするのが好ましい。 Most of the metal portion 11 is formed of nickel, nickel alloy, or the like suitable for electrolytic plating, but the back surface side of the metal portion 11 is provided so that soldering at the time of mounting a semiconductor device can be appropriately performed. A metal having good solder wettability, for example, a thin film 11d such as gold, silver, tin, palladium, or solder is arranged from the main material portion such as nickel. The thickness of the thin film 11d is preferably about 0.01 to 1 μm.

金属部１１形成の際には、あらかじめ薄膜１１ｄが母型基板１０上の第一レジスト層１２のない部分（露出領域）にメッキ等により形成された後、この薄膜１１ｄ上にさらにメッキ等によりニッケル等の主材質部が形成されることとなる（図４（Ｂ）参照）。この薄膜１１ｄには、母型基板１０のエッチングによる除去の際に、エッチング液による金属部１１の侵食劣化を防ぐ機能を与えることもできる。 When forming the metal portion 11, the thin film 11d is formed in advance on the master substrate 10 by plating or the like on the portion (exposed region) where the first resist layer 12 is not present, and then nickel is further formed on the thin film 11d by plating or the like. Etc. will be formed (see FIG. 4 (B)). The thin film 11d can also be provided with a function of preventing erosion deterioration of the metal portion 11 by the etching solution when the master substrate 10 is removed by etching.

なお、この金属部１１裏面側の薄膜形成は、前記ハンダ付け対策を目的とする場合、メッキで金属部１１主材質部を形成する前に限られるものではなく、半導体装置７０の完成後、封止材１９から露出した金属部１１の裏面にメッキにより薄膜を形成するようにしてもかまわない。 The thin film formation on the back surface side of the metal portion 11 is not limited to before the main material portion of the metal portion 11 is formed by plating for the purpose of the soldering countermeasure, and is sealed after the completion of the semiconductor device 70. A thin film may be formed by plating on the back surface of the metal portion 11 exposed from the stopper 19.

前記第一レジスト層１２は、金属部１１の電解メッキや表面金属層１３のメッキで使用するメッキ液に対する耐溶解性を備えた絶縁性材で形成され、母型基板１０上にあらかじめ設定される金属部１１の配置部分を露出するように対応させて配設され、金属部１１及び表面金属層１３の形成後には除去されるものである（図４（Ｃ）参照）。 The first resist layer 12 is formed of an insulating material having solubility resistance to a plating solution used for electrolytic plating of the metal portion 11 and plating of the surface metal layer 13, and is preset on the master substrate 10. The metal portion 11 is arranged so as to be exposed so as to be exposed, and is removed after the metal portion 11 and the surface metal layer 13 are formed (see FIG. 4C).

この第一レジスト層１２は、母型基板１０上に金属部１１の形成に先立って配設され、詳細には、アルカリ現像タイプの感光性レジスト材を母型基板１０に所定の厚さ、例えば約５０μｍの厚さとなるようにして密着配設し、半導体装置７０の金属部１１位置に対応する所定パターンのマスクフィルム５０を載せた状態で紫外線照射による露光での硬化（図２（Ｃ）参照）、非照射部分のレジスト材を除去する現像等の処理を経て、金属部１１の配置部分が露出されるような形状で形成される。 The first resist layer 12 is disposed on the master substrate 10 prior to the formation of the metal portion 11. Specifically, an alkali-developed type photosensitive resist material is applied to the master substrate 10 to a predetermined thickness, for example. It is closely arranged so as to have a thickness of about 50 μm, and is cured by exposure to ultraviolet irradiation with a mask film 50 having a predetermined pattern corresponding to the position of the metal portion 11 of the semiconductor device 70 (see FIG. 2C). ), It is formed in a shape so that the arranged portion of the metal portion 11 is exposed through a process such as development for removing the resist material of the non-irradiated portion.

また、第二レジスト層１６は、前記第一レジスト層１２同様にメッキ液に対する耐溶解性を備えた絶縁性材で形成され、第一レジスト層１２を形成した後で、あらかじめ設定される金属部１１の規制部１１ａに対応させて配設され、金属部１１及び表面金属層１３の形成後には除去されるものである。この第二レジスト層１６としては、第一レジスト層１２の場合と同様、アルカリ現像タイプの感光性レジスト材等を用いることができる。このレジスト材を母型基板１０や第一レジスト層１２の各表面に所定の厚さ、例えば約３０μｍを超える厚さとなるように形成し、金属部１１の規制部１１ａ配置位置に対応する所定パターンのマスクフィルム５１を載せた状態で、紫外線照射による露光で硬化させる処理を経ると、母型基板１０や第一レジスト層１２上に固定状態の第二レジスト層１６が形成されることとなる。これら第一レジスト層１２及び第二レジスト層１６により、金属部１１の規制部１１ａに相当する部分で電解メッキが進行せず、金属部１１の欠けた部分、すなわち貫通孔１１ｅの規制部１１ａが設けられる。 Further, the second resist layer 16 is formed of an insulating material having solubility resistance to a plating solution like the first resist layer 12, and a metal portion set in advance after the first resist layer 12 is formed. It is arranged so as to correspond to the regulating portion 11a of 11, and is removed after the metal portion 11 and the surface metal layer 13 are formed. As the second resist layer 16, an alkali-developed photosensitive resist material or the like can be used as in the case of the first resist layer 12. This resist material is formed on each surface of the master substrate 10 and the first resist layer 12 so as to have a predetermined thickness, for example, a thickness exceeding about 30 μm, and a predetermined pattern corresponding to the arrangement position of the restricting portion 11a of the metal portion 11 When the mask film 51 is placed on the mask film 51 and cured by exposure to ultraviolet rays, a fixed second resist layer 16 is formed on the master substrate 10 and the first resist layer 12. Due to the first resist layer 12 and the second resist layer 16, electrolytic plating does not proceed in the portion corresponding to the regulation portion 11a of the metal portion 11, and the chipped portion of the metal portion 11, that is, the regulation portion 11a of the through hole 11e is formed. It will be provided.

なお、この第一レジスト層１２や第二レジスト層１６については、感光性レジストに限られるものではなく、メッキ液に対し変質せず強度の高い塗膜が得られる塗料を、母型基板１０上における金属部１１の配置部分が露出されるように、電着塗装等により必要な塗膜厚さとなるように塗装して形成することもできる。 The first resist layer 12 and the second resist layer 16 are not limited to the photosensitive resist, and a paint that does not deteriorate with respect to the plating solution and can obtain a high-strength coating film is applied on the master substrate 10. It can also be formed by coating so that the arrangement portion of the metal portion 11 in the above is exposed so as to have a required coating thickness by electrodeposition coating or the like.

一方、この表面側の第一レジスト層１２や第二レジスト層１６とは別に、母型基板１０の裏面側にも、レジスト層１８が形成される構成である（図２参照）。裏面側のレジスト層１８は、硬化状態でメッキ液への耐性のある材質で、且つ不要となったら容易に溶解除去可能なレジスト材、例えば厚さ約５０μｍのアルカリ現像タイプの感光性フィルムレジストを熱圧着等により配設し、そのままマスクなしに紫外線照射による露光等の処理を経て、裏面全面にわたり硬化形成されるものとすることができる。なお、レジスト層１８については、レジストに限られるものではなく、例えばカバーフィルムであっても良く、要は絶縁性を有するものであれば良い。 On the other hand, apart from the first resist layer 12 and the second resist layer 16 on the front surface side, the resist layer 18 is also formed on the back surface side of the master substrate 10 (see FIG. 2). The resist layer 18 on the back surface side is a resist material that is resistant to the plating solution in a cured state and can be easily dissolved and removed when it is no longer needed, for example, an alkali-developed photosensitive film resist having a thickness of about 50 μm. It can be disposed by heat-bonding or the like, and can be cured and formed over the entire back surface through treatments such as exposure by ultraviolet irradiation without a mask. The resist layer 18 is not limited to the resist, and may be, for example, a cover film, as long as it has an insulating property.

表面金属層１３は、配線用のワイヤ１５をなす金線等との接合性に優れる金や銀、パラジウム等からなるメッキ膜として形成される。この表面金属層１３は、母型基板１０ごとのメッキにより金属部１１の表面に所定の厚さ、例えば、金メッキの場合は約０．１〜１μｍ、銀メッキの場合は約１〜１０μｍの厚さのメッキとして形成される。この表面金属層１３のメッキの際、母型基板１０の裏面側はレジスト層１８で覆われていることから、メッキの付着等は生じない（図４（Ｂ）参照）。なお、この表面金属層１３へのメッキに際しては、金属部１１のメッキの場合とはメッキ液を異ならせるなど、メッキの金属に対応するメッキ液を使用することとなる。 The surface metal layer 13 is formed as a plating film made of gold, silver, palladium, or the like having excellent bondability with a gold wire or the like forming the wiring wire 15. The surface metal layer 13 has a predetermined thickness on the surface of the metal portion 11 by plating each master substrate 10, for example, about 0.1 to 1 μm in the case of gold plating and about 1 to 10 μm in the case of silver plating. Formed as a metal plating. When the surface metal layer 13 is plated, the back surface side of the master substrate 10 is covered with the resist layer 18, so that the plating does not adhere (see FIG. 4B). When plating the surface metal layer 13, a plating solution corresponding to the metal to be plated is used, for example, the plating solution is different from that in the case of plating the metal portion 11.

この表面金属層１３のメッキを形成する際は、金属部１１がニッケルの場合、メッキが密着しにくいため、通常、表面金属層１３のメッキの前にあらかじめ金属部１１表面に下地メッキ（銅ストライク、ニッケルストライク、銀ストライク、又は金ストライク）を行い、表面金属層１３の金属部１１への密着性を高めることが望ましい。 When forming the plating of the surface metal layer 13, if the metal portion 11 is nickel, the plating is difficult to adhere to. Therefore, usually, the surface of the metal portion 11 is pre-plated (copper strike) before the surface metal layer 13 is plated. , Nickel strike, silver strike, or gold strike) to improve the adhesion of the surface metal layer 13 to the metal portion 11.

半導体素子１４は、微細な電子回路が形成されたいわゆるチップであり、金、銅等の導電性線材からなる配線（ボンディング）用のワイヤ１５が、半導体素子１４表面に設けられた電極と金属部１１のうちの電極部１１ｂとにそれぞれ接合され、半導体素子１４と電極部１１ｂとを電気的に接続することとなる。 The semiconductor element 14 is a so-called chip in which a fine electronic circuit is formed, and a wire 15 for wiring (bonding) made of a conductive wire rod such as gold or copper is provided on the surface of the semiconductor element 14 with an electrode and a metal portion. Each of the 11 is bonded to the electrode portion 11b, and the semiconductor element 14 and the electrode portion 11b are electrically connected to each other.

この時、半導体素子１４は規制部１１ａによって規制された状態となっていることから、半導体素子の位置ズレを防止することができる。しかも、規制部１１ａは金属部１１に貫通孔１１ｅを形成することで得ることができ、この貫通孔１１ｅ内に半導体素子１４を配置させれば、半導体素子１４は規制部１１ａに囲まれた状態で配置されることになるので、半導体素子１４の位置ズレをより確実に防止することができる。また、従来のように半導体素子搭載部の上面に搭載される場合と比べて、配設位置を下げることができ、半導体素子１４上面や接合されるワイヤ１５も下がる分、半導体装置７０の厚さを小さくして製造することができ、半導体装置７０の低背化を実現できる。また、半導体素子１４の位置が下がって、ワイヤ１５が接合する半導体素子１４と電極部１１ｂの各上面が近付く分、ワイヤ１５の長さも短くすることができ、ワイヤ１５の使用量を削減してコストを低減できる。なお、貫通孔１１ｅ内に半導体素子１４を配置するようにした場合には、半導体素子１４の裏面も半導体装置７０の底部から露出されることになる。 At this time, since the semiconductor element 14 is in a state of being regulated by the regulating unit 11a, it is possible to prevent the semiconductor element from being displaced. Moreover, the regulating portion 11a can be obtained by forming a through hole 11e in the metal portion 11, and if the semiconductor element 14 is arranged in the through hole 11e, the semiconductor element 14 is surrounded by the regulating portion 11a. Since the semiconductor elements 14 are arranged in the above position, the displacement of the semiconductor element 14 can be prevented more reliably. Further, as compared with the case where the semiconductor element is mounted on the upper surface of the semiconductor element mounting portion as in the conventional case, the arrangement position can be lowered, and the upper surface of the semiconductor element 14 and the wire 15 to be joined are also lowered, so that the thickness of the semiconductor device 70 is reduced. Can be manufactured in a small size, and the height of the semiconductor device 70 can be reduced. Further, as the position of the semiconductor element 14 is lowered and the upper surfaces of the semiconductor element 14 to which the wire 15 is bonded and the upper surfaces of the electrode portions 11b are brought closer to each other, the length of the wire 15 can be shortened, and the amount of the wire 15 used can be reduced. The cost can be reduced. When the semiconductor element 14 is arranged in the through hole 11e, the back surface of the semiconductor element 14 is also exposed from the bottom of the semiconductor device 70.

前記封止材１９は、物理的強度の高い熱硬化性エポキシ樹脂等であり、金属部１１表面側の半導体素子１４やワイヤ１５を覆った状態で封止し、半導体素子１４やワイヤ１５等の構造的に弱い部分を外部から隔離した保護状態とするものである。なお、半導体素子１４がＬＥＤ等の発光素子の場合、透光性の材質が用いられる。 The sealing material 19 is a thermosetting epoxy resin or the like having high physical strength, and is sealed while covering the semiconductor element 14 or the wire 15 on the surface side of the metal portion 11, and the semiconductor element 14 or the wire 15 or the like is sealed. The structurally weak part is protected from the outside. When the semiconductor element 14 is a light emitting element such as an LED, a translucent material is used.

この封止材１９を用いる封止工程は、半導体装置用基板１に対して行われ、母型基板１０の表面側における金属部１１等のある半導体装置となる範囲を、上型となる金型で覆った上で、この金型と母型基板１０の間に封止材１９を圧入し、封止材１９を硬化させることで封止が完了となる。ただし、封止工程では、一つの半導体装置となる半導体素子搭載部１１ａや複数の電極部１１ｂが多数整列状態のままで一様に封止されるため、半導体装置は封止材１９を介して多数つながった状態となっている。 The sealing step using the sealing material 19 is performed on the semiconductor device substrate 1, and the range of the semiconductor device having the metal portion 11 and the like on the surface side of the master substrate 10 is set as the upper mold. After covering with, the sealing material 19 is press-fitted between the mold and the master substrate 10 and the sealing material 19 is cured to complete the sealing. However, in the sealing step, since the semiconductor element mounting portions 11a and the plurality of electrode portions 11b, which are one semiconductor device, are uniformly sealed in a state of being aligned in large numbers, the semiconductor device is uniformly sealed via the sealing material 19. Many are connected.

この封止材１９は、十分な物理的強度を有しており、半導体装置７０の外装の一部として十分に内部を保護する機能を果し、母型基板１０を半導体装置側から引き剥がすなど力を加えて物理的に除去する場合にも、割れ等の破損もなく金属部１１との一体化状態を維持することとなる。 The encapsulant 19 has sufficient physical strength, functions to sufficiently protect the inside as a part of the exterior of the semiconductor device 70, and peels off the master substrate 10 from the semiconductor device side. Even when it is physically removed by applying a force, the integrated state with the metal portion 11 is maintained without damage such as cracking.

次に、本実施形態に係る半導体装置用基板の製造及び半導体装置用基板を用いた半導体装置製造の各工程について説明する。 Next, each process of manufacturing the semiconductor device substrate and manufacturing the semiconductor device using the semiconductor device substrate according to the present embodiment will be described.

半導体装置用基板の製造工程として、まず、母型基板１０を用意し（図２（Ａ）、母型基板１０上にあらかじめ設定される金属部１１の非配置部分に対応させて第一レジスト層１２を配設する。具体的には、母型基板１０の表面側に、形成する金属部１１の形状や高さ（例えば約５０μｍ）に対応するように、感光性レジスト材１２ａを配設する（図２（Ｂ）参照）。感光性レジスト材１２ａに対しては、金属部１１の配置位置に対応する所定パターンのマスクフィルム５０を載せた状態で、紫外線照射による露光での硬化（図２（Ｃ）参照）、非照射部分のレジスト剤を除去する現像等の処理を行い、金属部１１の配置部分が露出する第一レジスト層１２を形成する（図３（Ａ）参照）。また、母型基板１０の裏面側にも感光性レジスト材を表面側同様に配設し、このレジスト材全面に対して露光等の処理を経て、裏面全面にわたりレジスト層１８を形成する（図２（Ｃ）参照）。 As a manufacturing process of a substrate for a semiconductor device, first, a master substrate 10 is prepared (FIG. 2 (A)), and a first resist layer is made corresponding to a non-arranged portion of a metal portion 11 preset on the master substrate 10. 12 is arranged. Specifically, the photosensitive resist material 12a is arranged on the surface side of the master substrate 10 so as to correspond to the shape and height (for example, about 50 μm) of the metal portion 11 to be formed. (See FIG. 2B). The photosensitive resist material 12a is cured by exposure to ultraviolet irradiation with a mask film 50 having a predetermined pattern corresponding to the arrangement position of the metal portion 11 placed on the photosensitive resist material 12a (FIG. 2). (See (C)), a process such as development for removing the resist agent in the non-irradiated portion is performed to form the first resist layer 12 in which the arranged portion of the metal portion 11 is exposed (see FIG. 3 (A)). A photosensitive resist material is also arranged on the back surface side of the master substrate 10 in the same manner as on the front surface side, and the entire surface of the resist material is subjected to a treatment such as exposure to form a resist layer 18 over the entire back surface (FIG. 2 (C)). )reference).

第一レジスト層１２を形成したら、所定厚さまで形成された第一レジスト層１２の上に、金属部１１における規制部１１ａに対応させて第二レジスト層１６を配設する。具体的には、母型基板１０と第一レジスト層１２の表面側に、感光性レジスト材１６ａを、貫通孔１１ｅを有する規制部１１ａの高さ（深さ）より大きい所定厚さ（例えば約３０μｍ）となるようにして密着配設する（図３（Ｂ）参照）。この感光性レジスト材に対し、規制部１１ａ（貫通孔１１ｅ）の配置位置に対応する所定パターンのマスクフィルム５１を載せた状態で、紫外線照射による露光（図３（Ｃ）参照）、非照射部分のレジスト剤を除去する現像等の処理を行い、規制部１１ａ（貫通孔１１ｅ）を生じさせる箇所に対応させた第二レジスト層１６を形成する（図４（Ａ）参照）。なお、貫通孔１１ｅは、第一レジスト層１２及び第二レジスト層１６を形成することで設けられているが、第二レジスト層１６のみの形成で設けることもできる。具体的には、第一レジスト層１２を形成する工程において、貫通孔１１ｅを生じさせる箇所における感光性レジスト材１２ａの露光を行わず、第二レジスト層１６を形成する工程において、貫通孔１１ｅを生じさせる箇所における感光性レジスト材１６ａを露光・現像することで貫通孔１１ｅを設けることができる。また、貫通孔１１ｅの大きさが規制部１１ａの第一レジスト層１２側への張出し量に比べて十分大きい場合には、第二レジスト層１６を設けずに第一レジスト層１２のみを貫通孔１１ｅを設ける位置に形成するようにしてもよい。 After the first resist layer 12 is formed, the second resist layer 16 is arranged on the first resist layer 12 formed to a predetermined thickness so as to correspond to the regulation portion 11a in the metal portion 11. Specifically, a photosensitive resist material 16a is placed on the surface side of the base substrate 10 and the first resist layer 12 to have a predetermined thickness (for example, about) larger than the height (depth) of the regulating portion 11a having the through holes 11e. It is closely arranged so as to be 30 μm) (see FIG. 3 (B)). An exposure by ultraviolet irradiation (see FIG. 3C) and a non-irradiated portion with a mask film 51 having a predetermined pattern corresponding to the arrangement position of the regulation portion 11a (through hole 11e) placed on the photosensitive resist material. The second resist layer 16 corresponding to the portion where the regulation portion 11a (through hole 11e) is generated is formed by performing a process such as development for removing the resist agent (see FIG. 4 (A)). The through hole 11e is provided by forming the first resist layer 12 and the second resist layer 16, but it can also be provided by forming only the second resist layer 16. Specifically, in the step of forming the first resist layer 12, the photosensitive resist material 12a is not exposed at the portion where the through hole 11e is generated, and in the step of forming the second resist layer 16, the through hole 11e is formed. Through holes 11e can be provided by exposing and developing the photosensitive resist material 16a at the generated portion. Further, when the size of the through hole 11e is sufficiently larger than the amount of extension of the regulating portion 11a to the first resist layer 12 side, only the first resist layer 12 is formed through the through hole without providing the second resist layer 16. It may be formed at a position where 11e is provided.

こうして、金属部１１のメッキで使用するメッキ液に対する耐溶解性を備えたレジスト層１２・１６を形成したら、母型基板１０表面の第一レジスト層１２及び第二レジスト層１６で覆われていない露出部分に対し、必要に応じて表面酸化被膜除去や表面活性化処理を行う。具体的には、母型基板１０及び金属部１１（薄膜１１ｄ）の材質によって、脱脂、酸浸漬、化学エッチング、電解処理、ストライクメッキなどを選択して行う。なお、化学エッチングは、母型基板１０自体を溶解して、その表面の酸化被膜（不活性膜）を除去するものであり、係る表面は粗面となる。 In this way, when the resist layers 12 and 16 having solubility resistance to the plating solution used for plating the metal portion 11 are formed, they are not covered with the first resist layer 12 and the second resist layer 16 on the surface of the master substrate 10. If necessary, the exposed portion is subjected to surface oxide film removal and surface activation treatment. Specifically, degreasing, acid immersion, chemical etching, electrolytic treatment, strike plating and the like are selected and performed depending on the materials of the base substrate 10 and the metal portion 11 (thin film 11d). In the chemical etching, the matrix substrate 10 itself is dissolved to remove the oxide film (inactive film) on the surface thereof, and the surface thereof becomes a rough surface.

その後、この露出部分にメッキ等によりハンダぬれ性改善用の金の薄膜１１ｄを、例えば０．０１〜１μｍ厚で形成する（図４（Ｂ）参照）。そして、この薄膜１１ｄ上に、電解メッキによりニッケルを積層して金属部１１を形成する（図４（Ｂ）参照）。 Then, a gold thin film 11d for improving solder wettability is formed on the exposed portion by plating or the like to have a thickness of, for example, 0.01 to 1 μm (see FIG. 4B). Then, nickel is laminated on the thin film 11d by electrolytic plating to form the metal portion 11 (see FIG. 4B).

この金属部１１の形成工程で、金属部１１は、第一レジスト層１２の厚さを越える一方、第二レジスト層１６の上面を越えない厚さとして形成され、第二レジスト層１６の側面に接する部位を伴う一方、第一レジスト層１２寄りの金属部１１上端周縁には第一レジスト層１２側に張出した略庇状の張出し部１１ｃが形成され、第二レジスト層１６の配置された箇所に金属部１１は形成されない。金属部１１は、母型基板１０表面において、一又は複数配置される電極部１１ｂを一つの単位として、製造する半導体装置の数だけ多数整列状態で並べられた形態で形成されることとなる。 In the step of forming the metal portion 11, the metal portion 11 is formed so as to have a thickness that exceeds the thickness of the first resist layer 12 but does not exceed the upper surface of the second resist layer 16, and is formed on the side surface of the second resist layer 16. A substantially erect-shaped overhanging portion 11c overhanging the first resist layer 12 is formed on the peripheral edge of the upper end of the metal portion 11 near the first resist layer 12, and a portion where the second resist layer 16 is arranged is formed. The metal portion 11 is not formed on the surface. The metal portion 11 is formed on the surface of the master substrate 10 in a form in which one or a plurality of electrode portions 11b are arranged in an aligned state as many as the number of semiconductor devices to be manufactured, with one or a plurality of electrode portions 11b as one unit.

所望の厚さ及び形状の金属部１１が得られたら、母型基板１０ごとのメッキ浴浸漬により、金属部１１の表面に、表面金属層１３を所定の厚さ、例えば銀メッキの場合、厚さ約０．１〜０．５μｍとなるように形成する（図４（Ｂ）参照）。メッキ浴に用いられるメッキ液に対し、第一レジスト層１２及び第二レジスト層１６は十分な耐性を有しているため、変質等が生じることはなく、レジスト層としての機能を維持し、必要箇所以外へのメッキ付着を防ぐことができる。また、この表面金属層１３のメッキの際、母型基板１０の裏面側はレジスト層１８で覆われていることから、メッキの付着はない。 When the metal portion 11 having a desired thickness and shape is obtained, the surface metal layer 13 is formed on the surface of the metal portion 11 by dipping in a plating bath for each master substrate 10 to a predetermined thickness, for example, in the case of silver plating. It is formed so as to have a size of about 0.1 to 0.5 μm (see FIG. 4 (B)). Since the first resist layer 12 and the second resist layer 16 have sufficient resistance to the plating solution used in the plating bath, deterioration does not occur, and the function as a resist layer is maintained and necessary. It is possible to prevent plating from adhering to areas other than the locations. Further, when the surface metal layer 13 is plated, the back surface side of the master substrate 10 is covered with the resist layer 18, so that the plating does not adhere.

表面金属層１３を形成後、母型基板１０表面側の第一レジスト層１２、第二レジスト層１６、及び裏面側のレジスト層１８をそれぞれ除去（溶解除去、膨潤除去）すると（図４（Ｃ）参照）、半導体装置用基板１が完成する。この時、第二レジスト層１６及びその下に形成されている第一レジスト層１２が除去することで、貫通孔１１ｅを有する規制部１１ａが現れる。 After forming the surface metal layer 13, the first resist layer 12, the second resist layer 16 on the front surface side of the master substrate 10 and the resist layer 18 on the back surface side are removed (dissolved and removed, swelled and removed) (FIG. 4 (C)). ), The substrate 1 for the semiconductor device is completed. At this time, by removing the second resist layer 16 and the first resist layer 12 formed under the second resist layer 16, the regulating portion 11a having the through hole 11e appears.

続いて、得られた半導体装置用基板１を用いた半導体装置の製造について説明すると、まず、半導体装置用基板１における貫通孔１１ｅ内に、半導体素子１４を挿入搭載し、規制部１１ａによって半導体素子１４を規制固定状態とする。そして、半導体素子１４表面の電極と、これに対応する各電極部１１ｂとに、金線等のワイヤ１５を接合し、半導体素子１４と各電極部１１ｂとを電気的接続状態とする（図５（Ａ）参照）。この配線による電気的接続は、超音波ボンディング装置等により実施される。電極部１１ｂの表面には表面金属層１３が形成されているため、ワイヤ１５との接合を確実なものとすることができ、接続の信頼性を高められる。なお、ワイヤ１５によって半導体素子１４と電極部１１ｂとを接続する時に、半導体素子１４がその配置箇所から脱落するおそれがあるが、これを防ぐために、半導体素子１４の裏面や半導体素子１４の配置箇所に予め仮接着剤（ダイアタッチフィルム、樹脂フィルム、樹脂ペーストなど）を設けておくと良い。 Next, the manufacture of the semiconductor device using the obtained semiconductor device substrate 1 will be described. First, the semiconductor element 14 is inserted and mounted in the through hole 11e of the semiconductor device substrate 1, and the semiconductor element 11a is used by the regulating unit 11a. 14 is set to the regulated fixed state. Then, a wire 15 such as a gold wire is bonded to the electrodes on the surface of the semiconductor element 14 and the corresponding electrode portions 11b to bring the semiconductor element 14 and each electrode portion 11b into an electrically connected state (FIG. 5). (A)). The electrical connection by this wiring is carried out by an ultrasonic bonding apparatus or the like. Since the surface metal layer 13 is formed on the surface of the electrode portion 11b, the bonding with the wire 15 can be ensured, and the reliability of the connection can be enhanced. When the semiconductor element 14 and the electrode portion 11b are connected by the wire 15, the semiconductor element 14 may fall off from the arrangement location. In order to prevent this, the back surface of the semiconductor element 14 or the arrangement location of the semiconductor element 14 may occur. It is advisable to provide a temporary adhesive (diatouch film, resin film, resin paste, etc.) in advance.

半導体素子１４と各電極部１１ｂとの接続が完了したら、母型基板１０の表面側における金属部１１等のある半導体装置となる範囲を、熱硬化性エポキシ樹脂等の封止材１９で封止し、半導体素子１４やワイヤ１５を外部から隔離した保護状態とする（図５（Ｂ）参照）。詳細には、母型基板１０の表面側を上型となるモールド金型に装着し、母型基板１０に下型の役割を担わせつつ、モールド金型内に封止材１９となるエポキシ樹脂を圧入するという過程で封止が実行され、母型基板１０上では、一つの半導体装置となる複数の電極部１１ｂが多数整列状態のままで一様に封止され、半導体装置が多数つながった状態で現れることとなる。 When the connection between the semiconductor element 14 and each electrode portion 11b is completed, the range of the semiconductor device having the metal portion 11 or the like on the surface side of the master substrate 10 is sealed with a sealing material 19 such as a thermosetting epoxy resin. Then, the semiconductor element 14 and the wire 15 are put into a protected state isolated from the outside (see FIG. 5B). Specifically, an epoxy resin that serves as a sealing material 19 in the mold while mounting the surface side of the master substrate 10 on a mold mold that is an upper mold and allowing the master substrate 10 to play the role of a lower mold. Sealing was executed in the process of press-fitting, and on the master substrate 10, a large number of electrode portions 11b serving as one semiconductor device were uniformly sealed in an aligned state, and a large number of semiconductor devices were connected. It will appear in the state.

この多数つながった状態の半導体装置が得られたら、母型基板１０を除去し、各半導体装置の底部に金属部１１の裏面側及び半導体素子１４の裏面側が露出した状態を得る（図５（Ｃ）参照）。ステンレス製である母型基板１０の除去には、半導体装置側から母型基板１０を物理的に引き剥がして除去する方法を用いる。母型基板１０に強度及び剥離性に優れるステンレスを用いることで、半導体装置側から母型基板１０を引き剥がして速やかに分離除去することができる。 When a large number of connected semiconductor devices are obtained, the master substrate 10 is removed to obtain a state in which the back surface side of the metal portion 11 and the back surface side of the semiconductor element 14 are exposed at the bottom of each semiconductor device (FIG. 5 (C)). )reference). To remove the master substrate 10 made of stainless steel, a method of physically peeling the master substrate 10 from the semiconductor device side to remove it is used. By using stainless steel having excellent strength and peelability for the master substrate 10, the master substrate 10 can be peeled off from the semiconductor device side and quickly separated and removed.

この他、母型基板１０を除去する方法として、母型基板１０をエッチング（溶解）させる方法を用いることもできる。このエッチングの場合、母型基板１０は溶解するが薄膜１１ｄや金属部１１の材質が冒されないような選択エッチング性を有するエッチング液を用いることとなる。溶解させて除去する場合では、半導体装置側に過大な力が加わらないため、母型基板１０の除去に伴う悪影響が生じる確率を小さくできる。 In addition, as a method for removing the master substrate 10, a method of etching (melting) the master substrate 10 can also be used. In the case of this etching, an etching solution having selective etching property is used so that the matrix substrate 10 is dissolved but the materials of the thin film 11d and the metal portion 11 are not affected. In the case of melting and removing, since an excessive force is not applied to the semiconductor device side, the probability that an adverse effect due to the removal of the master substrate 10 will occur can be reduced.

母型基板１０を除去された半導体装置の底部では、露出する金属部１１の裏面側と、封止材１９の裏面側とが略同一平面上に位置する状態となっている。母型基板１０の除去後、多数つながった状態の半導体装置を一つ一つ切り離せば、一つの半導体装置７０としての完成品となる。 At the bottom of the semiconductor device from which the master substrate 10 has been removed, the back surface side of the exposed metal portion 11 and the back surface side of the sealing material 19 are located on substantially the same plane. After removing the master substrate 10, if a large number of connected semiconductor devices are separated one by one, a finished product as one semiconductor device 70 can be obtained.

得られた半導体装置７０内部において、金属部１１の上端周縁を張出し部１１ｃとして略庇状に張り出し形成し、封止材１９による封止状態で、この張出し部１１ｃが封止材１９に囲まれて固定されていることから、樹脂同士で密着し強固に一体化した封止材１９に張出し部１１が食込んで、金属部１１に加わる外力に対する抵抗体の役割を果たすこととなり、母型基板１０にステンレス等を用い、半導体装置側から母型基板１０を物理的に引き剥がして除去する場合など、金属部１１裏面側に装置外装から引離そうとする外力が加わっても、該張出し部１１が金属部１１の移動を妨げ、金属部１１の他部分に対するズレ等をなくすことができ、製造時における歩留りを向上させられると共に、半導体装置としての強度を高められ、使用時の耐久性や半導体装置動作の信頼性も高められる。 Inside the obtained semiconductor device 70, the upper end peripheral edge of the metal portion 11 is formed as an overhanging portion 11c in a substantially eaves-like shape, and the overhanging portion 11c is surrounded by the sealing material 19 in a sealed state by the sealing material 19. Since the resin is fixed to each other, the overhanging portion 11 bites into the sealing material 19 which is firmly integrated with the resins, and acts as a resistor against an external force applied to the metal portion 11. Even if an external force is applied to the back side of the metal portion 11 to separate it from the exterior of the device, such as when stainless steel or the like is used for 10 and the master substrate 10 is physically peeled off from the semiconductor device side to remove it, the overhanging portion 11 hinders the movement of the metal portion 11, can eliminate the deviation of the metal portion 11 with respect to other parts, improve the yield at the time of manufacturing, enhance the strength as a semiconductor device, and improve the durability at the time of use. The reliability of semiconductor device operation is also improved.

このように、本実施形態に係る半導体装置用基板１は、母型基板１０上に規制部１１ａを設けることから、この半導体装置用基板１を用いた半導体装置７０の製造にあたり、半導体素子１４の位置ズレを防止することができる。そして、規制部１１ａを半導体装置製造工程で半導体素子１４を挿入、規制可能な大きさの貫通孔１１ｅとすることから、この半導体装置用基板１を用いた半導体装置７０の製造にあたり、従来のように半導体素子搭載部の上面に搭載される場合と比べて、半導体素子１４の搭載位置を下げることができ、半導体素子１４上面や、電極部１１ｂと半導体素子１４とを接合するワイヤ１５等の高さも下がる分、半導体装置７０の厚さを小さくして製造することができ、半導体装置７０の低背化を実現できる。また、半導体素子１４の位置が下がって、ワイヤ１５が接合する半導体素子１４と電極部１１ｂの各上面が互いに近付く分、ワイヤ長さも短くすることができ、ワイヤ使用量を削減してコスト低減にも寄与できる。 As described above, since the semiconductor device substrate 1 according to the present embodiment is provided with the regulation portion 11a on the master substrate 10, the semiconductor element 14 is used in manufacturing the semiconductor device 70 using the semiconductor device substrate 1. It is possible to prevent misalignment. Then, since the semiconductor element 14 is inserted into the regulating portion 11a in the semiconductor device manufacturing process to form a through hole 11e having a size that can be regulated, the semiconductor device 70 is manufactured using the semiconductor device substrate 1 as in the conventional case. The mounting position of the semiconductor element 14 can be lowered as compared with the case where the semiconductor element 14 is mounted on the upper surface of the semiconductor element mounting portion, and the height of the upper surface of the semiconductor element 14 and the wire 15 for joining the electrode portion 11b and the semiconductor element 14 is high. The thickness of the semiconductor device 70 can be reduced by the amount of the reduction, and the height of the semiconductor device 70 can be reduced. Further, the position of the semiconductor element 14 is lowered, and the wire length can be shortened by the amount that the semiconductor element 14 to which the wire 15 is bonded and the upper surfaces of the electrode portion 11b are brought closer to each other, so that the amount of wire used can be reduced and the cost can be reduced. Can also contribute.

ここで、本実施形態の半導体装置用基板１は、貫通孔１１ｅの形状をストレート状としているが、テーパ状としても良い。このテーパ状の貫通孔として、母型基板の表面側（半導体装置の裏面側）に向かって拡がるテーパ状の貫通孔とすれば、半導体装置の製造にあたり、係る貫通孔内に半導体素子を挿入後、半導体素子が脱落しにくい構造とすることができる。また、母型基板の表面側（半導体装置の裏面側）に向かって窄まるテーパ状の貫通孔とすれば、半導体装置の製造にあたり、係る貫通孔内への半導体素子の挿入がしやすい構造とすることができる。 Here, in the semiconductor device substrate 1 of the present embodiment, the shape of the through hole 11e is straight, but it may be tapered. If the tapered through hole is a tapered through hole that expands toward the front surface side (back surface side of the semiconductor device) of the master substrate, the semiconductor device is manufactured after the semiconductor element is inserted into the through hole. , The structure can be such that the semiconductor element does not easily fall off. Further, if the tapered through hole narrows toward the front surface side (back surface side of the semiconductor device) of the master substrate, the structure is such that the semiconductor element can be easily inserted into the through hole in the manufacture of the semiconductor device. can do.

また、図７に示すように、母型基板１０の表面側（半導体装置７１の裏面側）に向かって窄まるテーパ状の貫通孔１１ｅの中途（壁面）に半導体素子１４を配設することもできる。係る構造によっても、半導体素子１４の位置ズレの防止及び半導体装置の低背化の実現が可能となる。このテーパ状の貫通孔１１ｅは、第一レジスト層１２及び第二レジスト層１６を所望のテーパ形状に対応させて形成することで、容易に得ることができる。なお、図７に示す半導体装置７１は、その底部から半導体素子１４が露出されているが、半導体素子１４の底部とテーパ状の貫通孔内壁とで囲まれる空間に封止材１９を封入させることで、半導体装置の底部から半導体素子１４が露出されない構成（半導体素子１４の裏面が封止材１９で覆われた構成）とすることもできる。 Further, as shown in FIG. 7, the semiconductor element 14 may be arranged in the middle (wall surface) of the tapered through hole 11e that narrows toward the front surface side (back surface side of the semiconductor device 71) of the master substrate 10. it can. With such a structure, it is possible to prevent the semiconductor element 14 from being displaced and to reduce the height of the semiconductor device. The tapered through hole 11e can be easily obtained by forming the first resist layer 12 and the second resist layer 16 in correspondence with a desired tapered shape. In the semiconductor device 71 shown in FIG. 7, the semiconductor element 14 is exposed from the bottom thereof, but the sealing material 19 is sealed in a space surrounded by the bottom portion of the semiconductor element 14 and the inner wall of the tapered through hole. Therefore, the semiconductor element 14 may not be exposed from the bottom of the semiconductor device (the back surface of the semiconductor element 14 is covered with the sealing material 19).

（第２実施形態）
第２実施形態に係る半導体装置用基板は、上記第１実施形態同様に、母型基板１０と、電極部１１ｂと、規制部１１ａとを備えるものである。図８は、係る構成の半導体装置用基板を用いて製造した半導体装置７２を示している。図８に示すように、規制部１１ａの高さ（貫通孔１１ｅの深さ）が半導体素子１４の厚さ以上に設定されているものである。 (Second Embodiment)
The semiconductor device substrate according to the second embodiment includes a master substrate 10, an electrode portion 11b, and a regulation portion 11a, as in the first embodiment. FIG. 8 shows a semiconductor device 72 manufactured by using a semiconductor device substrate having such a configuration. As shown in FIG. 8, the height of the regulating portion 11a (depth of the through hole 11e) is set to be equal to or larger than the thickness of the semiconductor element 14.

このように、規制部１１ａの高さ寸法を半導体素子１４の厚さ寸法以上に設定されていることで、半導体素子１４の側面全体を規制部１１ａによって規制することができるので、半導体素子１４の位置ズレを防止することができる。また、該規制部１１ａが貫通孔１１ｅから成るものであると、半導体素子１４の側面全面が規制部１１ａに覆われて規制されることになるので、より確実に半導体素子１４の位置ズレを防止することができる。また、半導体素子１４の側面が規制部１１ａと対向配置されることになるので、放熱性を向上することができる。 By setting the height dimension of the regulating portion 11a to be equal to or larger than the thickness dimension of the semiconductor element 14 in this way, the entire side surface of the semiconductor element 14 can be regulated by the regulating portion 11a. It is possible to prevent misalignment. Further, if the regulating portion 11a is composed of the through hole 11e, the entire side surface of the semiconductor element 14 is covered with the regulating portion 11a and regulated, so that the displacement of the semiconductor element 14 is more reliably prevented. can do. Further, since the side surface of the semiconductor element 14 is arranged to face the regulating portion 11a, heat dissipation can be improved.

なお、所望の高さ（深さ）の規制部１１ａ（貫通孔１１ｅ）を得るためには、上記第１実施形態における半導体装置用基板の製造工程の第一レジスト層１２・第二レジスト層１６を形成する工程（図２（Ｂ）〜図４（Ａ）参照）において、母型基板１０上に形成される第一レジスト層１２及び／又は第二レジスト層１６の厚さを調整、すなわち、第一レジスト層１２及び／又は第二レジスト層１６の厚さを半導体素子１４の厚さ以上に設定することで容易に得られる。 In order to obtain the regulation portion 11a (through hole 11e) having a desired height (depth), the first resist layer 12 and the second resist layer 16 in the process of manufacturing the substrate for a semiconductor device according to the first embodiment. In the step of forming (see FIGS. 2B to 4A), the thickness of the first resist layer 12 and / or the second resist layer 16 formed on the master substrate 10 is adjusted, that is, It can be easily obtained by setting the thickness of the first resist layer 12 and / or the second resist layer 16 to be equal to or larger than the thickness of the semiconductor element 14.

（第３実施形態）
上記実施形態における半導体装置用基板においては、母型基板１０上に電極部１１ｂと規制部１１ａとを別々に設け、この半導体装置用基板を用いた半導体装置の製造工程にて、規制部１１ａに規制されるように半導体素子１４を搭載しているが、第３実施形態に係る半導体装置用基板は、電極部１１ｂに規制部１１ａを兼ねさせる構成としているものである。 (Third Embodiment)
In the semiconductor device substrate according to the above embodiment, the electrode portion 11b and the regulation portion 11a are separately provided on the master substrate 10, and the regulation portion 11a is used in the manufacturing process of the semiconductor device using the semiconductor device substrate. Although the semiconductor element 14 is mounted so as to be regulated, the semiconductor device substrate according to the third embodiment has a configuration in which the electrode portion 11b also serves as the regulating portion 11a.

本実施形態に係る半導体装置用基板は、上記実施形態同様、母型基板１０と、電極部１１ｂとを備えるものであり、異なる点として、電極部１１ｂが上記実施形態における規制部１１ａを兼ねている。そして、各電極部１１ｂ間が貫通孔１１ｅに相当することになり、この電極部１１ｂ間に半導体素子１４を配設する。係る電極部１１は、後の半導体装置製造工程で行われる半導体素子１４の配置予定箇所であって、半導体素子１４の外径以上の間隔をあけて母型基板１０上に形成されるものである。図９は、係る構成の半導体装置用基板を用いて製造した半導体装置７３を示している。 The substrate for a semiconductor device according to the present embodiment includes the master substrate 10 and the electrode portion 11b as in the above embodiment, and the difference is that the electrode portion 11b also serves as the regulation portion 11a in the above embodiment. There is. Then, the space between the electrode portions 11b corresponds to the through hole 11e, and the semiconductor element 14 is arranged between the electrode portions 11b. The electrode portion 11 is a place where the semiconductor element 14 is scheduled to be arranged, which will be performed in a later semiconductor device manufacturing process, and is formed on the master substrate 10 at intervals equal to or larger than the outer diameter of the semiconductor element 14. .. FIG. 9 shows a semiconductor device 73 manufactured by using a semiconductor device substrate having such a configuration.

このように、電極部１１ｂに規制部１１ａを兼ねさせた構成とすることで、電極部と規制部とを別々に形成した構成と比べて、規制部の形成を省略することができるので、半導体装置の構成をよりコンパクトにすることができる。また、規制部の形成を省略することにより、規制部の形成領域分だけ母型基板１０上に形成される一つの半導体装置としての取り数を増やすことが可能となり、コストダウンが図れる。 In this way, by making the electrode portion 11b also serve as the regulation portion 11a, the formation of the regulation portion can be omitted as compared with the configuration in which the electrode portion and the regulation portion are separately formed. The configuration of the device can be made more compact. Further, by omitting the formation of the regulation portion, it is possible to increase the number of semiconductor devices formed on the master substrate 10 by the formation region of the regulation portion, and the cost can be reduced.

なお、本実施形態に係る半導体装置用基板の製造工程について説明すると、上記第１実施形態における半導体装置用基板の製造工程において、母型基板１０上に第一レジスト層１２（及び第二レジスト層１６）を形成する工程での規制部１１ａに対応するレジストパターンの形成を省略することで形成できる。その他の点は、上記第１実施形態と同様である。また、続く半導体装置用基板を用いた半導体装置の製造工程についても、上記第１実施形態と同様である。 The manufacturing process of the semiconductor device substrate according to the present embodiment will be described. In the manufacturing process of the semiconductor device substrate according to the first embodiment, the first resist layer 12 (and the second resist layer) are placed on the master substrate 10. It can be formed by omitting the formation of the resist pattern corresponding to the regulation portion 11a in the step of forming 16). Other points are the same as those in the first embodiment. Further, the subsequent manufacturing process of the semiconductor device using the semiconductor device substrate is the same as that of the first embodiment.

（第４実施形態）
第４実施形態に係る半導体装置用基板は、上記実施形態同様に、母型基板１０と、電極部１１ｂと、規制部１１ａとを備えるものである。図１０は、係る構成の半導体装置用基板を用いて製造した半導体装置７４を示している。該規制部１１ａは、ワイヤ１５のループ頂部１５’の直下位置に重なるように配設されている。つまり、規制部１１ａとワイヤ１５のループ頂部１５’とは、半導体装置（半導体装置用基板）の高さ方向において、直線上に位置している。ここで、ループ頂部１５’とは、半導体素子１４の電極と金属電極部１１ｂとを接続するワイヤ１４の最頂点の部分を言う。 (Fourth Embodiment)
The substrate for a semiconductor device according to the fourth embodiment includes a master substrate 10, an electrode portion 11b, and a regulation portion 11a, as in the above embodiment. FIG. 10 shows a semiconductor device 74 manufactured by using a semiconductor device substrate having such a configuration. The restricting portion 11a is arranged so as to overlap the position directly below the loop top 15'of the wire 15. That is, the regulation portion 11a and the loop top portion 15'of the wire 15 are located on a straight line in the height direction of the semiconductor device (semiconductor device substrate). Here, the loop top 15'refers to the most apex portion of the wire 14 that connects the electrode of the semiconductor element 14 and the metal electrode portion 11b.

このように、規制部１１ａをワイヤ１５のループ頂部１５’の直下位置に配置させることで、半導体素子１４の位置ズレを防止することができるとともに、規制部１１ａとワイヤ１５とが接触することを可及的に防止することができる。 By arranging the regulating portion 11a at a position directly below the loop top 15'of the wire 15 in this way, it is possible to prevent the semiconductor element 14 from being displaced, and to prevent the regulating portion 11a and the wire 15 from coming into contact with each other. It can be prevented as much as possible.

なお、係る構成の半導体装置用基板を得るためには、上記第１実施形態における半導体装置用基板の製造工程において、母型基板１０上に配設される半導体素子１４の配置領域部分に対応する第一レジスト層１２及び／又は第二レジスト層１６の形状や厚さを調整することで容易に得られる。 In order to obtain a semiconductor device substrate having such a configuration, it corresponds to an arrangement region portion of the semiconductor element 14 arranged on the master substrate 10 in the process of manufacturing the semiconductor device substrate according to the first embodiment. It can be easily obtained by adjusting the shape and thickness of the first resist layer 12 and / or the second resist layer 16.

（第５実施形態）
第５実施形態に係る半導体装置用基板は、母型基板１０と、電極部１１ｂと、規制部１１ａとを備えるものであり、規制部１１ａとして貫通孔１１ｅが形成されており、該貫通孔１１ｅと重なるように凹部１１ｆが設けられているものである。この凹部１１ｆの底面（底面積）は貫通孔１１ｅの開口（開口面積）より大きいものである。図１１は、係る構成の半導体装置用基板を用いて製造した半導体装置７５を示している。 (Fifth Embodiment)
The substrate for a semiconductor device according to the fifth embodiment includes a master substrate 10, an electrode portion 11b, and a regulation portion 11a, and a through hole 11e is formed as the regulation portion 11a, and the through hole 11e is formed. The recess 11f is provided so as to overlap with the recess 11f. The bottom surface (bottom area) of the recess 11f is larger than the opening (opening area) of the through hole 11e. FIG. 11 shows a semiconductor device 75 manufactured by using a semiconductor device substrate having such a configuration.

このように、貫通孔１１ｅと重なるように凹部１１ｆを設けた構成とすることで、凹部１１ｆの内面による半導体素子１４の位置ズレ防止や半導体装置の低背化ができる。しかも、貫通孔１１ｅを覆うように凹部１１ｆの底面上に半導体素子１４を配設することで、半導体素子１４を半導体装置７０の底部（封止材１９の裏面）から奥まった位置に配置させることができ、半導体素子１４を外力から保護することができる。 In this way, by providing the recess 11f so as to overlap the through hole 11e, it is possible to prevent the semiconductor element 14 from being displaced due to the inner surface of the recess 11f and to reduce the height of the semiconductor device. Moreover, by disposing the semiconductor element 14 on the bottom surface of the recess 11f so as to cover the through hole 11e, the semiconductor element 14 is arranged at a position recessed from the bottom portion (back surface of the sealing material 19) of the semiconductor device 70. The semiconductor element 14 can be protected from an external force.

なお、係る構成の半導体装置用基板を得るためには、上記第１実施形態における半導体装置用基板の製造工程において、母型基板１０上に形成される規制部１１ａ（貫通孔１１ｅ）に対応する第一レジスト層１２及び／又は第二レジスト層１６の形状や厚さを調整することで容易に得られる。 In order to obtain a semiconductor device substrate having such a configuration, it corresponds to the regulation portion 11a (through hole 11e) formed on the master substrate 10 in the manufacturing process of the semiconductor device substrate in the first embodiment. It can be easily obtained by adjusting the shape and thickness of the first resist layer 12 and / or the second resist layer 16.

半導体装置７５の底部において、貫通孔１１ｅからは半導体素子１４の裏面が露出されるが、上記第１実施形態のように、貫通孔１１ｅ内に封止材１９を封入させることで、図１２に示すように、底部から半導体素子１４が露出されない構成（半導体素子１４の裏面が封止材１９で覆われた構成）の半導体装置７６とすることもできる。 At the bottom of the semiconductor device 75, the back surface of the semiconductor element 14 is exposed from the through hole 11e. However, as in the first embodiment, by enclosing the sealing material 19 in the through hole 11e, FIG. 12 shows. As shown, the semiconductor device 76 may have a configuration in which the semiconductor element 14 is not exposed from the bottom (a configuration in which the back surface of the semiconductor element 14 is covered with a sealing material 19).

（第６実施形態）
第６実施形態に係る半導体装置用基板は、母型基板１０と、電極部１１ｂとを備えるものであり、電極部１１ｂが規制部１１ａを兼ねており（電極部１１間が貫通孔１１ｅに相当）、電極部１１ｂの上部には、延設部２０が一体的に設けられているものである。図１３は、係る構成の半導体装置用基板を用いて製造した半導体装置７７を示している。延設部２０は、半導体素子１４に向かって延びるように設けられており、延設部２０と半導体素子１４の電極とが電気的に接続されている。 (Sixth Embodiment)
The substrate for a semiconductor device according to the sixth embodiment includes a master substrate 10 and an electrode portion 11b, and the electrode portion 11b also serves as a regulation portion 11a (the space between the electrode portions 11 corresponds to a through hole 11e). ), An extension portion 20 is integrally provided on the upper portion of the electrode portion 11b. FIG. 13 shows a semiconductor device 77 manufactured by using a semiconductor device substrate having such a configuration. The extension portion 20 is provided so as to extend toward the semiconductor element 14, and the extension portion 20 and the electrodes of the semiconductor element 14 are electrically connected to each other.

このように、電極部１１ｂ（規制部１１ａ）の上部に延設部２０が設けられた構成とすることで、電極部１１ｂ（規制部１１ａ）によって半導体素子１４の側面を規制するだけでなく、延設部２０によって半導体素子１４の上面も規制することができるので、半導体素子１４の各面から位置ズレを抑制できる。 In this way, by providing the extension portion 20 on the upper portion of the electrode portion 11b (regulation portion 11a), the electrode portion 11b (regulation portion 11a) not only regulates the side surface of the semiconductor element 14 but also regulates the side surface of the semiconductor element 14. Since the upper surface of the semiconductor element 14 can also be regulated by the extending portion 20, the positional deviation from each surface of the semiconductor element 14 can be suppressed.

なお、係る構成の半導体装置用基板を得るためには、上記第１実施形態における半導体装置用基板の製造工程において、母型基板１０上に電極部１１ｂ（規制部１１ａ）を形成し、電極部１１ｂ間に半導体素子１４を配置させた後、延設部２０を形成するために、電極部１１ｂ（規制部１１ａ）上面及び半導体素子１４上面が露出されるようにレジスト層を形成した後にメッキすることで得られる。 In order to obtain a semiconductor device substrate having such a configuration, an electrode portion 11b (regulation portion 11a) is formed on the master substrate 10 in the manufacturing process of the semiconductor device substrate according to the first embodiment, and the electrode portion is formed. After arranging the semiconductor element 14 between 11b, in order to form the extending portion 20, a resist layer is formed so that the upper surface of the electrode portion 11b (regulating portion 11a) and the upper surface of the semiconductor element 14 are exposed, and then plated. It can be obtained by.

上記実施形態においては、図１４（Ａ）に示すように、規制部１１ａの半導体素子１４と対向する側（第二レジスト層１６の側面に接する側）の上端周縁には張出部１１ｃが形成されていないが、図１４（Ｂ）に示すように、規制部１１ａの半導体素子１４と対向する側にも張出部１１ｃを形成しても良い。この場合、第一レジスト層１２上に形成していた第二レジスト層１６の形成を省略する、つまり、図３（Ａ）に示すように、母型基板１０上に第一レジスト層１２を形成した後に、第二レジスト層１６を形成せずに、第一レジスト層１２の厚さを越えるまでメッキすると良い。また、金属部１１（規制部１１ａ、電極部１１ｂ）の上端周縁に張出部１１ｃを形成しないストレート状にしても良い（図１４（Ｃ）参照）。この場合、図３（Ａ）に示すように、母型基板１０上に第一レジスト層１２を形成後、第一レジスト層１２の厚さを越えないようにメッキすると良い。 In the above embodiment, as shown in FIG. 14A, an overhanging portion 11c is formed on the upper peripheral edge of the regulation portion 11a on the side facing the semiconductor element 14 (the side in contact with the side surface of the second resist layer 16). However, as shown in FIG. 14B, the overhanging portion 11c may be formed on the side of the regulating portion 11a facing the semiconductor element 14. In this case, the formation of the second resist layer 16 formed on the first resist layer 12 is omitted, that is, the first resist layer 12 is formed on the master substrate 10 as shown in FIG. 3 (A). After that, it is preferable to plate until the thickness of the first resist layer 12 is exceeded without forming the second resist layer 16. Further, the metal portion 11 (regulating portion 11a, electrode portion 11b) may have a straight shape in which the overhanging portion 11c is not formed on the upper peripheral periphery (see FIG. 14C). In this case, as shown in FIG. 3A, after forming the first resist layer 12 on the master substrate 10, it is preferable to plate the first resist layer 12 so as not to exceed the thickness of the first resist layer 12.

また、上記実施形態において、第一レジスト層１２及び第二レジスト層１６を形成する際には、感光性レジスト材１２ａを配設して露光・現像を行った後に感光性レジスト材１６ａを配設しているが、感光性レジスト材１２ａを配設して露光した後に、現像を行わないまま感光性レジスト材１６ａを配設し、露光してから、感光性レジスト材１２ａと感光性レジスト材１６ａとを一緒に現像するようにしても良い。また、第一レジスト層１２及び第二レジスト層１６を形成するにあたり、マスクフィルム５０・５１を用いて露光しているが、直描装置によって露光しても良い。 Further, in the above embodiment, when the first resist layer 12 and the second resist layer 16 are formed, the photosensitive resist material 12a is disposed, exposed and developed, and then the photosensitive resist material 16a is disposed. However, after the photosensitive resist material 12a is arranged and exposed, the photosensitive resist material 16a is arranged and exposed without development, and then the photosensitive resist material 12a and the photosensitive resist material 16a are exposed. May be developed together with. Further, in forming the first resist layer 12 and the second resist layer 16, the mask films 50 and 51 are used for exposure, but they may be exposed by a direct drawing device.

また、上記実施形態において、貫通孔１１ｅ内に半導体素子１４を配設する場合に、貫通孔１１ｅ内面と半導体素子１４外面との間に隙間があっても良いし、貫通孔１１ｅ内面と半導体素子１４外面との間に隙間がなく、規制部１１ａと半導体素子１４とが密接して配設されてあっても良い。 Further, in the above embodiment, when the semiconductor element 14 is arranged in the through hole 11e, there may be a gap between the inner surface of the through hole 11e and the outer surface of the semiconductor element 14, or the inner surface of the through hole 11e and the semiconductor element. There may be no gap between the outer surface of the 14 and the regulating portion 11a and the semiconductor element 14 may be closely arranged.

また、アースをとるために、規制部１１ａを接地電極として兼用させ、アースワイヤ（グランドワイヤ）を規制部１１ａと接続するようにしても良い。 Further, in order to provide grounding, the regulating portion 11a may also be used as a grounding electrode, and the ground wire (ground wire) may be connected to the regulating portion 11a.

１ 半導体装置用基板
１０ 母型基板
１１ 金属部
１１ａ 規制部
１１ｂ 電極部
１１ｃ 張出し部
１１ｄ 薄膜
１１ｅ 貫通孔
１１ｆ 凹部
１２ 第一レジスト層
１２ａ レジスト材
１３ 表面金属層
１４ 半導体素子
１５ ワイヤ
１６ 第二レジスト層
１６ａ レジスト材
１８ レジスト層
１９ 封止材
２０ 延設部
７０〜７７ 半導体装置 1 Substrate for semiconductor devices 10 Master substrate 11 Metal part 11a Restriction part 11b Electrode part 11c Overhang part 11d Thin film 11e Through hole 11f Recess 12 First resist layer 12a Resist material 13 Surface metal layer 14 Semiconductor element 15 Wire 16 Second resist layer 16a Resist material 18 Resist layer 19 Encapsulant 20 Extension 70-77 Semiconductor device

Claims (7)

母型基板上に少なくとも電極部となる金属部が形成される半導体装置用基板において、
前記母型基板上には、半導体素子を規制する規制部が設けられており、
前記規制部の半導体素子と対向する側の上端に張出し部が形成され、前記張出し部が前記半導体素子の外周面と対向するように設定されていることを特徴とする半導体装置用基板。 In a substrate for a semiconductor device in which at least a metal portion to be an electrode portion is formed on a master substrate.
A regulation unit that regulates semiconductor elements is provided on the master substrate.
Said overhang portion is formed on the semiconductor element facing to that side upper end of the restricting portion, the substrate for a semiconductor device characterized by being configured to face the outer peripheral surface of the overhang of the semiconductor device. 前記規制部は、前記金属部に貫通孔を形成することで設けられていることを特徴とする請求項１に記載の半導体装置用基板。 The substrate for a semiconductor device according to claim 1, wherein the regulating portion is provided by forming a through hole in the metal portion. 前記張出し部は、前記貫通孔が形成された前記金属部の外周および内周に形成されていることを特徴とする請求項２に記載の半導体装置用基板。 The substrate for a semiconductor device according to claim 2, wherein the overhanging portion is formed on the outer periphery and the inner circumference of the metal portion in which the through hole is formed. 母型基板上に少なくとも電極部となる金属部と半導体素子を規制する規制部とが設けられ、前記規制部が前記金属部に貫通孔を形成することで設けられており、前記貫通孔が形成された前記金属部の外周および内周の上端に張出し部が形成され、前記内周の上端に形成された前記張出し部が前記半導体素子の外周面と対向するように設定されている半導体装置用基板の製造方法において、
前記母型基板上に、前記金属部の形成位置に対応する第一レジスト層を形成する工程と、
前記母型基板表面の前記第一レジスト層で覆われていない露出領域に、前記金属部を前記第一レジスト層の厚さを越えて形成する工程と、
前記第一レジスト層を除去する工程とを有することを特徴とする半導体装置用基板の製造方法。 A regulating portion for regulating the metal portion and the semi-conductor element to be at least the electrode portion is provided matrix substrate, wherein the regulating portion is provided by forming a through hole in the metal part, wherein the through hole A semiconductor device in which an overhanging portion is formed on the outer periphery and the upper end of the inner circumference of the formed metal portion, and the overhanging portion formed on the upper end of the inner circumference is set to face the outer peripheral surface of the semiconductor element. In the manufacturing method of the substrate for
A step of forming a first resist layer corresponding to the formation position of the metal portion on the master substrate, and
A step of forming the metal portion in an exposed region on the surface of the master substrate that is not covered with the first resist layer, exceeding the thickness of the first resist layer.
A method for manufacturing a substrate for a semiconductor device, which comprises a step of removing the first resist layer. 半導体素子と電気的に接続された電極部が封止材によって封止され、装置底部に前記電極部の裏面側が露出される半導体装置において、
前記半導体素子を規制する規制部が設けられており、
前記半導体素子は、前記規制部に囲まれた状態で配置され、
前記規制部の半導体素子と対向する側の上端に張出し部が形成され、前記張出し部が前記半導体素子の外周面と対向配置されていることを特徴とする半導体装置。 In a semiconductor device in which an electrode portion electrically connected to a semiconductor element is sealed with a sealing material and the back surface side of the electrode portion is exposed at the bottom of the device.
A regulatory unit that regulates the semiconductor element is provided.
The semiconductor element is arranged so as to be surrounded by the regulation portion.
The semiconductor device characterized by overhang the upper end of the semiconductor element facing to that side of the regulating portion is formed, the overhang portion is the outer peripheral surface and opposite arrangement of the semiconductor device. 前記規制部は、金属部に貫通孔を形成することで設けられていることを特徴とする請求項５に記載の半導体装置。 The semiconductor device according to claim 5, wherein the regulating portion is provided by forming a through hole in the metal portion. 前記張出し部は、前記規制部の外周および内周の上端に張出し部が形成されていることを特徴とする請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the overhanging portion has an overhanging portion formed at the upper end of the outer periphery and the inner circumference of the restricting portion.
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