JP6709425B2 - Semiconductor device - Google Patents

Description

The present invention relates to a vertical semiconductor equipment of the carrier is moved to the semiconductor in a thickness direction.

The thickness of the vertical semiconductor device in which a current flows in the thickness direction of the semiconductor layer is determined by the electric field distribution that is determined in principle, and the thickness required for the breakdown voltage is determined. However, the vertical type semiconductor device can have a lower resistance as it becomes thinner, but if the resistance is made lower, the withstand voltage lowers. Therefore, there are known conventional semiconductor devices described in Patent Document 1 and Non-Patent Document 1, which have been studied so as to have a high breakdown voltage even if the thickness is smaller than the thickness limit required for the breakdown voltage.

In the semiconductor device described in Patent Document 1, a semiconductor substrate has a strip shape in a substrate cross section, and a pn column having a repeating pattern of p-conductivity type and n-conductivity type is formed on a substrate surface, and the pn column is a constituent element. As a part of the above, a plurality of remaining constituent elements of the same semiconductor device are formed in a region having a repeated pattern, and individual semiconductor devices are cut into chips from the region where the plurality of same semiconductor devices are formed. It will be. In this patent document 1, the stripe-shaped trench is formed so as to be orthogonal to the pn column so that the tip of the trench protrudes into the pn column without performing precise alignment. Since the depletion of the pn column is not affected and almost the same breakdown voltage is obtained, a vertical MOSFET with high breakdown voltage and low on-resistance can be obtained.

Furthermore, Non-Patent Document 1 describes a method in which the electric field distribution is changed by combining a low-concentration layer and a high-concentration layer to reduce the thickness of the semiconductor device below a required thickness limit.

JP 2004-356577 A

M. Tsukuda et al., "Critical IGBT Design Regarding EMI and Switching Losses", ISPSD2008, 2008, p185-188

However, since the semiconductor device described in Patent Document 1 adopts the super junction structure, there is a problem that the manufacturing process becomes long.
Further, according to Non-Patent Document 1, by combining the low concentration layer and the high concentration layer, the manufacturing process becomes complicated and long.

Therefore, there is a demand for a semiconductor device which has a simple structure and is capable of achieving both higher breakdown voltage and lower resistance.

Accordingly, the present invention aims at providing a semiconductor equipment capable of achieving a high breakdown voltage and low resistance.

According to the present invention, a semiconductor layer of a first conductivity type, a first electrode and a second electrode arranged on both sides of the semiconductor layer in the thickness direction, and a semiconductor layer formed along the thickness direction of the semiconductor layer are formed. Vertical semiconductor device including an insulating film and a third electrode that is formed along the insulating film and has the same polarity as the first electrode that attracts minority carriers in the semiconductor layer when in a non-conducting state The interface between the semiconductor layer and the insulating film forms an uneven surface.

According to the semiconductor device of the present invention, by including the third electrode having the same polarity as the first electrode in which minority carriers are attracted in the semiconductor layer and the insulating film having an uneven surface at the interface with the semiconductor layer, The electric field distribution in the non-conducting state changes in a constant direction along the thickness direction. Therefore, as compared with a semiconductor device having an insulating film whose interface with the semiconductor layer is flat, the thickness of the semiconductor layer can be reduced if the withstand voltage is the same.

The insulating film and the third electrode may be formed inside a trench formed in the semiconductor layer. By forming the insulating film and the third electrode in the trench formed in the semiconductor layer, the insulating film and the third electrode can be easily formed along the thickness direction of the semiconductor layer.

The third electrode may be formed of a semiconductor electrode made of a semiconductor film. By forming the third electrode by a semiconductor electrode, the third electrode can be formed even in a narrow region formed inside the trench.

When the ratio of the height difference of the uneven surface of the insulating film divided by the repeating interval of the convex portions is set to be larger than 0.05, the noise voltage can be sharply improved.
Even if the height difference of the uneven surface of the insulating film is larger than 0.1 μm, the noise voltage can be rapidly improved. Therefore, on the uneven surface of the insulating film, it is preferable that the ratio of the height difference divided by the repeating interval of the protrusions is larger than 0.05, or the height difference is larger than 0.1 μm. ..

When the uneven surface is formed in a continuous triangular shape, it is possible to produce an effective shape at high speed by the Bosch process or the like.

When the first electrode is in contact with the semiconductor layer, a unipolar semiconductor device can be obtained. Further, since the semiconductor layer of the second conductivity type is formed between the semiconductor layer and the first electrode, a bipolar semiconductor device can be obtained.

The present invention provides a semiconductor layer having the same breakdown voltage as compared with a conventional semiconductor device having no insulating film and a third electrode and a conventional semiconductor device having an insulating film having a flat interface with the semiconductor layer. Since it is possible to reduce the thickness, it is possible to achieve high breakdown voltage and low resistance.

FIG. 3 is a cross-sectional view showing the Schottky barrier diode according to the first embodiment of the present invention. (A)-(D) is a figure for demonstrating the manufacturing method of the Schottky barrier diode shown in FIG. (A)-(D) is a figure for demonstrating the manufacturing method of the Schottky barrier diode following FIG. (A) is a diagram showing a trench formed by etching by a Bosch process, and (B) is an enlarged view of an interface portion between the insulating film of (A) and the silicon substrate. It is a figure which shows typically the structure of a Schottky barrier diode, and the electric field distribution of a non-conduction state, (A) is a figure of the Schottky barrier diode of a non-trench structure, (B) is the conventional Schottky barrier of a trench structure. FIG. 1C is a diagram of a diode, and FIG. 1C is a diagram of a Schottky barrier diode having a trench structure according to the first embodiment of the present invention. It is sectional drawing which shows the PIN diode which concerns on Embodiment 2 of this invention. (A)-(D) is a figure for demonstrating the manufacturing method of the PIN diode shown in FIG. (A)-(D) is a figure for demonstrating the manufacturing method of the PIN diode following FIG. It is sectional drawing for demonstrating the simulation model of a PIN diode. It is a graph which shows the reverse recovery loss with respect to the forward voltage of an invention product and a comparative product. 6 is a graph showing the chip area with respect to the forward voltage of the invention product and the comparative product. It is a figure which shows the waveform of the voltage and the electric current at the time of switching, (A) is a figure which shows the waveform of the comparative product A, (B) is a figure which shows the waveform of the comparative product B, (C) shows the waveform of an invention product. It is a figure. It is a figure for demonstrating the diffusion degree of the hole with time progress after the reverse recovery of the comparative product A, the comparative product B, and the invention product. 6 is a graph showing the relationship between the difference in height of the uneven surface of the insulating film in the invention product and the ratio of the repeating interval of the convex portions, and the maximum value of the noise voltage. 7 is a graph showing the relationship between the difference in height of the insulating film and the maximum value of noise voltage in the invention product. FIG. 7 is a cross-sectional view showing a first modification example of the PIN diode according to the second embodiment shown in FIG. 6. FIG. 13 is a cross-sectional view showing a second modification of the PIN diode according to the second embodiment shown in FIG. 6. It is sectional drawing which shows the IGBT which concerns on Embodiment 3 of this invention. FIG. 9 is a cross-sectional view showing a power MOSFET according to a fourth embodiment of the present invention. (A) is a figure which shows a groove-shaped trench, (B) is a figure which shows a dot-shaped trench. It is sectional drawing of the modification of the Schottky barrier diode shown in FIG.

(Embodiment 1)
A semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. The semiconductor device according to the first embodiment is a Schottky barrier diode (hereinafter, the Schottky barrier diode is abbreviated as SBD) which is an example of a unipolar semiconductor device.
The SBD 100 shown in FIG. 1 includes a silicon substrate 101 which is a semiconductor layer, a cathode layer 103 formed on the main surface of the silicon substrate 101, an anode electrode 104 and a cathode electrode arranged on both sides of the silicon substrate 101 in the thickness direction F1. And 105.

The silicon substrate 101 is formed of an N-type semiconductor substrate of the first conductivity type. The silicon substrate 101 can be formed of only a silicon substrate, but may be formed by forming an epi layer on a wafer to be a silicon substrate.
A plurality of trenches 106 are formed in the silicon substrate 101. The trench 106 is a groove whose depth direction is the thickness direction F1 of the silicon substrate 101.

An insulating film 107 is formed on the inner surface of the trench 106 so as to cover the entire area thereof. The insulating film 107 can be formed of, for example, a silicon oxide film.

The anode electrode 104 is formed so as to be in contact with the silicon substrate 101. The cathode electrode 105 is formed so as to be in contact with the cathode layer 103. The cathode electrode 105 functions as a second electrode.
The anode electrode 104 includes a metal electrode 104b that functions as a first electrode and a semiconductor electrode 104a that functions as a third electrode.

The metal electrode 104b is formed so as to cover the semiconductor electrode 104a and also cover the silicon substrate 101. The metal electrode 104b can be an aluminum electrode.
The semiconductor electrode 104a is arranged inside the insulating film 107 and is formed so as to close the opening of the insulating film 107. The semiconductor electrode 104a can be formed of a semiconductor film, and can be, for example, a polysilicon electrode. The semiconductor electrode 104a has the same polarity because it is in contact with and electrically connected to the metal electrode 104b.

The SBD 100 becomes non-conductive when the forward voltage and the reverse voltage are applied to the anode electrode 104 and the cathode electrode 105. At this time, holes, which are minority carriers of the N-type semiconductor of the silicon substrate 101, are attracted to the metal electrode 104b of the anode electrode 104.

The cathode electrode 105 is a metal electrode formed so as to cover the entire area of the cathode layer 103. The cathode electrode 105 can be an aluminum electrode.

Here, the interface between the silicon substrate 101 and the insulating film 107 will be described.
At the interface between the silicon substrate 101 and the insulating film 107, the recessed surface of the insulating film 107 in which the protrusion of the silicon substrate 101 fits and the protruding portion of the insulating film 107 that fits in the recess of the silicon substrate 101 are alternately repeated to form the uneven surface S1. It is formed by. On the uneven surface S1, triangular protrusions are continuously arranged in the depth direction.
It is desirable that the uneven surface S1 has a depth from the top of the convex portion 107b of the insulating film 107 to the bottom of the concave portion 107a that is deeper than 0.1 μm. Further, it is desirable that the repeating interval of the convex portions 107b is 2 μm.

A method of manufacturing the SBD 100 according to the first embodiment of the present invention configured as above will be described with reference to the drawings.
First, as shown in FIG. 2A, a photoresist 112 is formed on one surface of a silicon substrate 110 in a wafer state.
Next, as shown in FIG. 2B, the region of the groove to be the trench 106 is removed from the photoresist 112, and the trench 106 is formed in the silicon substrate 110 by the Bosch process. As a result, the silicon substrate 101 as the SBD 100 (see FIG. 1) is obtained.

The Bosch process is a method in which a groove having a high aspect ratio is formed by repeating etching and protection of the side wall surface from etching and alternating isotropic etching and anisotropic etching. Thus, by forming the trenches 106 in the silicon substrate 110 by the Bosch process, the uneven surface S1 is formed on the side wall surface 106a.

Next, as shown in FIG. 2C, after removing the photoresist, an insulating film 113 is formed in the region on the silicon substrate 101 and in the trench 106.
Next, as shown in FIG. 2D, after the insulating film 113 is polished until the silicon substrate 101 is exposed, etching is performed to leave the thickness of the insulating film 113 on the sidewall surface and the bottom surface of the trench 106. A groove 114 is formed along the groove direction of the trench 106 to form an insulating film 107. By forming the insulating film 107 inside the trench 106, unevenness corresponding to the uneven surface S1 of the sidewall surface of the trench 106 can be formed in the insulating film 107.

Next, after forming a polysilicon layer on the insulating film 107, an unnecessary portion is removed by etching to form a semiconductor electrode 104a made of polysilicon, as shown in FIG. By using the polysilicon electrode as the semiconductor electrode 104a, an electrode can be formed even if the groove 114 has a narrow groove width (see FIG. 2D). By thus forming the trench 106 and forming the insulating film 107 and the semiconductor electrode 104a inside the trench 106, the insulating film 107 and the semiconductor electrode 104a can be easily arranged along the thickness direction of the silicon substrate 101. can do.

Next, as shown in FIG. 3B, the metal electrode 104b is formed on the semiconductor electrode 104a to form the anode electrode 104.
Next, as shown in FIG. 3C, a cathode layer 103 is formed on the other surface of the silicon substrate 101, which is the opposite side to the anode electrode 104 side.
Then, as shown in FIG. 3D, the cathode electrode 105 is formed on the cathode layer 103 to complete the SBD 100.

FIG. 4 is a photograph showing a state in which the trench 106 is formed on the silicon substrate 101 by the Bosch process. In the example shown in FIG. 4A, a trench formed by etching a silicon substrate by etching by a Bosch process is filled with resin for photography. As can be seen from the photograph shown in FIG. 4B, the curved surface slightly concave on the silicon substrate side is a continuous saw-tooth uneven surface.
Since the unevenness due to the Bosch process causes deterioration of the electrical characteristics and reliability of the power semiconductor, it is usually flattened by digging a trench under conditions where unevenness is difficult to form or using sacrificial oxidation or chemical solution treatment after the Bosch process. To be done. However, in the present invention, since the uneven shape due to the insulating film (oxide film) is used in the non-conduction state, it is desirable that the carrier moving speed is slower and that the reliability can be prevented from being lowered by the thick oxide film. Therefore, it is possible to improve the characteristics of the power semiconductor by utilizing this uneven shape, which is generally considered to have an adverse effect.

It is preferable that the insulating film 107 formed of an oxide film such as a silicon oxide film has a large thickness because the withstand voltage is increased. For example, if the thickness of the oxide film is 1 μm, a withstand voltage of 1 kV can be secured. Therefore, it is desirable that the insulating film 107 has a thickness that satisfies the oxide film thickness (μm)/maximum voltage (kV)≧1.
With the insulating film 107 having such a thickness, when a voltage is applied to the anode electrode 104 and the cathode electrode 105, it is possible to prevent dielectric breakdown even if the maximum voltage is applied to the insulating film 107. ..

The electric field distribution of the STB 100 thus manufactured will be described with reference to the drawings.
In FIG. 5, in order to compare the STB 100 shown in FIG. 1 with the STB 100, a semiconductor electrode that functions as a third electrode and a non-trench structure SBD 100 a that does not have an insulating film, and an interface between the silicon substrate and the insulating film have an uneven surface. The electric field distribution in a non-conducting state with the flat surface SBD 100b is not shown.

The electric field distribution in the SBD 100a shown in FIG. 5A decreases proportionally as it progresses in the thickness direction (depth direction) from the main junction between the anode electrode A1 and the silicon substrate SB1 to the cathode electrode C1. Since the integral value of the electric field distribution is a voltage, the thickness of the silicon substrate SB1 required for the withstand voltage can be determined by setting a triangle of the area of the voltage required for the withstand voltage and taking noise suppression into consideration.

In the SBD 100b shown in FIG. 5B, the voltage applied to the semiconductor electrode 104a and the voltage applied to the insulating film 107 change the voltage applied to the silicon substrate SB2. Therefore, the electric field distribution in the SBD 100b becomes a concave shape that decreases as it progresses in the thickness direction (depth direction) of the silicon substrate SB2, but gradually increases from the middle. Therefore, if the area of the voltage distribution showing the voltage is the same, the silicon obtained from the electric field distribution shown in FIG. 5B from the thickness of the silicon substrate SB1 obtained from the triangular electric field distribution shown in FIG. The thickness of the substrate SB2 can be made thinner.

In the SBD 100 according to the first embodiment shown in FIG. 5C, the uneven surface S1 is formed at the interface between the insulating film 107 and the silicon substrate 101. Therefore, the electric field distribution in the SBD 100 not only changes the voltage applied to the silicon substrate 101 by applying a voltage to the insulating film 107, but also affects the silicon substrate SB2 due to the uneven surface S1 as in FIG. 5B. The strength changes in the thickness direction (depth direction) so that the strength becomes constant. Therefore, if the area of the electric field distribution showing the voltage is the same as the thickness of the silicon substrate SB2 obtained from the electric field distribution shown in FIG. 5B, the silicon substrate 101 obtained from the electric field distribution shown in FIG. The thickness can be further reduced.

Since the resistance of the SBD is proportional to the thickness of the silicon substrate, the SBD 100 according to the first embodiment has the same high breakdown voltage as the SBD 100a shown in FIG. 5A and the SBD 100b shown in FIG. Since it is possible to reduce the resistance, it is possible to reduce the resistance.
The silicon substrate 101 in the SBD 100 shown in FIG. 5C and the silicon substrate SB2 in the SBD 100b shown in FIG. 5B may have a higher concentration than the impurity concentration of the silicon substrate SB1 in the SBD 100a shown in FIG. 5A. it can. Therefore, the silicon substrate 101 can have a lower resistance value per unit length than the SBD 100a.

As described above, in the SBD 100 according to the first embodiment of the present invention, the interface between the silicon substrate 101 and the insulating film 107 is formed on the uneven surface S1. Both low resistance can be achieved. Further, since the uneven surface S1 is formed in a continuous triangular shape, it is possible to produce an effective shape at high speed by the Bosch process or the like.

(Embodiment 2)
A semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. The semiconductor device according to the second embodiment is a PIN diode which is an example of a bipolar semiconductor device. In FIG. 6, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.
The PIN diode 200 shown in FIG. 6 is formed on the silicon substrate 101 which is a semiconductor layer, the anode layer 102 formed on one side of the silicon substrate 101 in the thickness direction F1 and the other side of the silicon substrate 101 in the thickness direction F1. And a cathode layer 103, and an anode electrode 104 and a cathode electrode 105 arranged on both sides in the thickness direction F1.

The silicon substrate 101 is formed of an N ⁻ type semiconductor substrate and functions as a high resistance region of the PIN diode 200. The high resistance region can be formed only by the silicon substrate 101 as in the first embodiment, but may be formed by forming an epi layer on the silicon substrate. The anode layer 102 is a second conductivity type P-type semiconductor layer formed in the remaining region of the silicon substrate 101 in which the trench 106 is formed.

A method of manufacturing PIN diode 200 according to the second embodiment of the present invention configured as described above will be described.
First, as shown in FIG. 7A, a P-type layer 111 to be the anode layer 102 is formed on one surface side of the silicon substrate 110 to be the high resistance region.
Next, as shown in FIG. 7B, a photoresist 112 is formed on the P-type layer 111, exposing a region of the groove to be the trench 106, and the P-type layer is formed on the silicon substrate 110 by the Bosch process. A trench 106 penetrating 111 (anode layer 102) is formed. As a result, the silicon substrate 101 as the PIN diode 200 (see FIG. 6) is obtained. By forming the trench 106 in the silicon substrate 101 by the Bosch process, the uneven surface S1 is formed on the side wall surface 106a.

Next, as shown in FIG. 7C, after removing the photoresist, an insulating film 113 is formed in the region on the P-type layer 111 and in the trench 106.
Next, as shown in FIG. 7D, after the insulating film 113 is polished until the P-type layer 111 is exposed, etching is performed so as to leave a thickness on the sidewall surface and the bottom surface of the trench 106, and the trench 106. A groove 114 is formed along the groove direction of, and an insulating film 107 is formed. By forming the insulating film 107 inside the trench 106, unevenness corresponding to the uneven surface S1 of the sidewall surface of the trench 106 can be formed in the insulating film 107.

Next, after a polysilicon layer is formed over the P-type layer 111 and the insulating film 107, unnecessary portions are removed by etching as shown in FIG. 8A, so that the semiconductor electrode 104a made of polysilicon is formed. Form.

Next, as shown in FIG. 8B, a metal electrode 104b is formed on the anode layer 102 and the semiconductor electrode 104a to form the anode electrode 104.
Next, as shown in FIG. 8C, a cathode layer 103 is formed on the other surface of the silicon substrate 101, which is opposite to the anode layer 102 side.
Then, as shown in FIG. 8D, a cathode electrode 105 is formed on the cathode layer 103 to complete the process.

Note that in this embodiment mode, the P-type layer 111 is formed on one surface of the silicon substrate 110 shown in FIG. 7A to form the trench 106 shown in FIG. 7B. Although the insulating film 113 (insulating film 107) shown in (D) is formed, the trench 106 and the insulating film 113 are formed before forming the P-type layer 111, and then the P-type layer 111 is formed. You may.

The PIN diode 200 according to the second embodiment of the present invention manufactured as described above is provided with the silicon substrate 101, the insulating film 107 by the trench 106, and the semiconductor electrode 104a functioning as the third electrode. In the state, the electric field distribution is as shown in FIG. Therefore, the PIN diode 200 can achieve higher voltage and lower resistance.
Next, the operation of PIN diode 200 according to the second embodiment of the present invention will be described with reference to the drawings.
For example, when a forward voltage is applied between the anode electrode 104 and the cathode electrode 105 shown in FIG. 6, holes flow into the silicon substrate 101 from the anode layer 102 and electrons from the cathode layer 103 generate electrons in the silicon substrate 101. Flow into.

In this state, when the voltage is switched to the reverse voltage, holes which are minority carriers from the silicon substrate 101 are attracted to the metal electrode 104b of the anode electrode 104 and move from the silicon substrate 101 to the anode layer 102. At that time, in the central portion between the trenches 106, since there is nothing that is hindered by the movement of holes, the holes move at the speed obtained by the maximum drift speed.
However, at the interface between the silicon substrate 101 and the insulating film 107 along the thickness direction F1, when a voltage is applied to the anode electrode 104, it is attracted toward the insulating film 107 side of the anode electrode 104 toward the semiconductor electrode 104a. Since the interface between the insulating film 107 and the silicon substrate 101 is the uneven surface S1, holes, which are carriers, enter the concave portion 107a formed by the insulating film 107 on the uneven surface S1.
When the holes enter the concave portions 107a, the convex portions 107b of the insulating film 107 hinder the movement toward the metal electrode 104b.

Since the movement of the holes (carriers) is hindered, the movement speed (drift speed) of the holes decreases, so that the state with a slight resistance is maintained. Therefore, when the PIN diode 200 changes from the energized state to the non-conducting state, it is possible to reduce the noise and the switching loss. Therefore, PIN diode 200 according to the second embodiment can achieve higher performance.

(Example)
Here, the PIN diode 200 according to the second embodiment was simulated by TCAD to verify the performance.
FIG. 9 shows a simulation model of a PIN diode as an invention product. In the simulation model shown in FIG. 9, the thickness T1 of the silicon substrate having a higher doping concentration than that of the non-trench type is set to 50 μm. The distance L1 from the trench to the midpoint between the cells was set to 20 μm. The trench width W1 was 20 μm, the insulating film thickness T3 was 7 μm, and the electrode (second electrode) thickness T4 was 6 μm. Further, the repeating interval W2 of the convex portions of the insulating film facing the silicon substrate was 2 μm, and the height H (height difference) of the convex portions was 0.5 μm. The thickness T2 of the silicon substrate from the cathode to the bottom surface of the insulating film was 10 μm.

For comparison, a conventional PIN diode (vertical PIN diode) in which a trench and an insulating film formed inside the trench and electrodes were omitted on a silicon substrate was simulated as a comparative product.
The silicon substrate of the comparative product had a thickness of 80 μm so that noise was not generated during switching.

The simulation conditions were that the applied voltage was higher than 600 V, the forward current was 100 A, the junction temperature Tj was RT, and the parasitic inductance Ls was 50 nH.
The result of the simulation is shown in FIG. It can be seen from the graph shown in FIG. 10 that the invention product has half the reverse recovery loss as compared with the comparative product.

Further, as shown in FIG. 11, it can be seen that the chip size area of the invention product can be reduced by about 2/3 of that of the comparison product if the forward voltage is the same.
Next, FIG. 12 shows waveforms of noise during switching when the silicon substrates have the same thickness. 12A to 12C are graphs showing the states of current and voltage when the energized state is changed to the cutoff state.

In FIG. 12A, the comparative product (conventional PIN diode) shown in FIGS. 10 and 11 is referred to as a comparative product A, and in FIG. A PIN diode having no uneven surface at the interface between the silicon substrate and the silicon substrate was used as a comparative product B for simulation.
In the comparative product A shown in FIG. 12A and the comparative product B shown in FIG. 12B, carriers accumulated in the silicon substrate are rapidly discharged from the silicon substrate after the reverse recovery, so that a wavy voltage causes noise. You can see that it appears.

However, in the invention product shown in FIG. 9, as described above, since the carrier is captured by the uneven surface formed at the interface between the insulating film and the silicon substrate, the carrier stays on the uneven surface, and the carrier after reverse recovery is recovered. It takes time to move. Therefore, as shown in FIG. 12C, it is understood that the invention product can suppress the voltage fluctuation after the reverse recovery as compared with the comparison products A and B.

Regarding the carrier movement time, as shown in FIG. 13, it can be seen that in Comparative Products A and B, the holes gradually diffuse and the density becomes low 40 ns after the reverse recovery. However, in the invention product, the hole density gradually decreases after 40 ns after the reverse recovery, but it can be seen that a region having a high hole density remains in the silicon substrate even after 100 ns has passed. From this, it is understood that the invention product requires a long time for the movement of holes. Therefore, the invention product can suppress the loss at the time of reverse recovery.

Here, FIG. 14 shows the relationship between the noise voltage and the ratio of the height difference of the uneven surface of the insulating film and the repeating interval of the convex portions.
In FIG. 14, when the ratio of the height difference (height H of the convex portion) divided by the repeating interval W2 of the convex portions is larger than 0.05, the maximum value of the noise voltage sharply decreases. I understand. Therefore, it is desirable that the ratio obtained by dividing the difference in height by the repeating interval of the convex portions is larger than 0.05.

Further, regarding the difference in height in the insulating film, as shown in FIG. 15, when the depth from the top of the convex portion to the bottom of the concave portion of the insulating film is deeper than 0.1 μm, the maximum value of the noise voltage sharply increases. You can see that it is decreasing. Therefore, it is desirable that the height difference in the insulating film be larger than 0.1 μm.

(First Modification of Second Embodiment)
A first modification of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. In addition, in FIG. 16, the same components as those in FIG.
As shown in FIG. 16, in the PIN diode 200X, the interface between the insulating film 113 and the silicon substrate 101 forms an uneven surface S2. In this uneven surface S2, rectangular protrusions are continuously arranged in the depth direction. As with the uneven surface S1 (see FIG. 1), the uneven surface S2 preferably has a depth of 0.1 μm or more from the top of the convex portion 107c of the insulating film 107 to the bottom of the concave portion 107d.
By doing so, carriers (holes) are captured by the uneven surface S2 formed at the interface between the insulating film 107 and the silicon substrate 101, similarly to the PIN diode 200 (see FIG. 6), so that the carrier is formed on the uneven surface S2. As a result, the time required for movement after reverse recovery is high. Therefore, it can be expected that the PIN diode 200X can suppress the voltage fluctuation after the reverse recovery.

(Second Modification of Second Embodiment)
A second modification of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. In FIG. 17, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.
As shown in FIG. 17, in the PIN diode 200Y, the P-type layer 108 is arranged so as to be in contact with the bottom surface of the trench 106 (insulating film 107). The possibility of destruction can be reduced.
Therefore, PIN diode 200Y can achieve a high breakdown voltage and improve reliability while obtaining the effect of PIN diode 200 according to the second embodiment.

(Embodiment 3)
A semiconductor device according to the third embodiment of the present invention will be described with reference to the drawings. In FIG. 18, the same components as those in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted.

The semiconductor device according to the third embodiment is an IGBT which is an example of a bipolar power semiconductor device.
The IGBT 300 shown in FIG. 18 is selectively formed on the surface side of a low-concentration N-type layer (N base layer 301), which is an example of a semiconductor layer in which carriers move in the thickness direction F1, and a wide space and a narrow space are alternately arranged. The trenches 302 and 303, the gate insulating films 304 and 305 formed on the surfaces of the trenches 302 and 303, and the gate electrodes (control electrodes) 306 and 307 made of polysilicon formed inside the gate insulating films 304 and 305. A P base layer (P well layer) 308 selectively formed between adjacent trenches having a narrow interval, and a high-concentration N source layer 309 selectively formed on the surface of the P base layer 308. It is provided with a first main electrode (emitter electrode 310) connected to both the P base layer 308 and the N source layer 309.

A MOS transistor structure is formed on the surface portions of the N source layer 309, the P base layer 308, and the N base layer 301, and a P-type layer having a depth similar to that of a trench between adjacent trenches with a wide interval ( The P-type layer 311) whose potential is not fixed is formed in a state where it is not connected to the emitter electrode 310 or is connected to the emitter electrode 310 with high resistance.

Further, the IGBT 300 has an N buffer layer 312 having a higher impurity concentration than that of the N base layer 301, which is uniformly formed on the back surface side of the N base layer 301, and a high layer which is uniformly formed on the surface of the N buffer layer 312. A P-type layer (P emitter layer 313) having a concentration and a second main electrode (collector electrode 314) uniformly formed on the surface of the P emitter layer 313 are provided.

In this IGBT 300, the trench 106 is formed in the N base layer 301 as in the first and second embodiments. The trench 106 is a groove whose depth direction is the thickness direction F1 of the N base layer 301.
An insulating film 107 is formed on the inner surface of the trench 106 so as to cover the entire area thereof, extends from the opening edge of the trench 106, and is connected to the gate insulating films 304 and 305.
A semiconductor electrode 104a that is a part of the emitter electrode 310 is formed inside the insulating film 107 and in the opening of the insulating film 107. Further, the emitter electrode 310 extends to above the semiconductor electrode 104a and covers the semiconductor electrode 104a.
Further, the interface between the trench 106 and the N base layer 301 forms an uneven surface S1.

Since the interface between the trench 106 and the N base layer 301 is the uneven surface S1, when the holes, which are minority carriers, move in the direction of the emitter electrode 310, the holes are of the semiconductor electrode 104a of the emitter electrode 310. Direction toward the insulating film 107 side.
Since the interface between the insulating film 107 and the N base layer 301 is the uneven surface S1, holes enter the concave portion 107a of the insulating film 107 on the uneven surface S1. When the holes enter the concave portions 107a, the convex portions 107b of the insulating film 107 hinder the movement toward the metal electrode 104b.
Therefore, the IGBT 300 can achieve the effect of the SBD 100 according to the first embodiment, reduce noise when the energized state changes to the cutoff state, and reduce the switching loss.

(Embodiment 4)
A semiconductor device according to Embodiment 4 of the present invention will be described with reference to the drawings. Note that, in FIG. 19, the same components as those in FIG. 18 are denoted by the same reference numerals, and description thereof will be omitted.
The semiconductor device according to the fourth embodiment is a power MOSFET that is an example of a unipolar power semiconductor device.
In the MOSFET 400 shown in FIG. 19, the interface between the insulating film 107 and the N base layer 301 forms the uneven surface S1 similarly to the IGBT 300 according to the third embodiment (see FIG. 18).

Since the interface between the insulating film 107 and the N base layer 301 forms the uneven surface S1, the electric field distribution in the MOSFET 400 in the thickness direction (depth direction) of the N base layer 301 is the same as in the SBD according to the first embodiment. The intensity changes toward a constant value. Therefore, the thickness of the N base layer 301 can be reduced as compared with a case where the interface between the insulating film and the N base layer does not have an uneven surface.
Therefore, the MOSFET 400 has both a high breakdown voltage and a low resistance even though it has a simple structure.

Note that in Embodiments 1 to 4, the trench 106 can be a linear groove as shown in FIG. 20A, but when viewed from the opening side as shown in FIG. The dot-shaped trench 109 in which a plurality of circular bottomed holes are formed may be used. The metal electrode 104b is formed of an aluminum electrode which is an example of a metal electrode, and the semiconductor electrode 104a is formed of a polysilicon electrode which is an example of a semiconductor electrode, but the second electrode is formed of the same metal electrode as the first electrode. It may be formed.

Further, in the semiconductor device according to Embodiments 1 to 4 of the present invention, the semiconductor electrode 104a functioning as the third electrode directly has the same polarity as the metal electrode 104b functioning as the first electrode. Since the third electrode may be electrically connected and have the same polarity, the semiconductor electrode 104a and the metal electrode 104b may be non-conducting in the semiconductor device, but may have the same polarity by being connected externally. it can.

For example, like the SBD 100X shown in FIG. 21, the anode electrode 104X1 functioning as the first electrode is separated from the semiconductor electrode 104X2 functioning as the third electrode. However, the anode electrode 104X1 and the semiconductor electrode 104X2 can have the same polarity by being electrically connected to the outside of the SBD 100X.

Further, although the trench was formed from the first electrode (metal electrode 104b) side, in the third electrode (semiconductor electrode), if the same polarity as the first electrode in which minority carriers are attracted, It may be formed from the two-electrode (cathode electrode 105, collector electrode 314) side.

Further, the semiconductor layer used as the silicon substrate 101 may be a compound semiconductor such as SiC or GaN, in addition to silicon.

The present invention is suitable for unipolar type and bipolar type semiconductor devices, and is particularly suitable for power semiconductor devices.

100,100X SBD (Schottky barrier diode)
100a, 100b Conventional Schottky barrier diode 101, SB1, SB2 Silicon substrate 102, A1, A2 Anode layer 103, C1, C2 Cathode layer 104, 104X1 Anode electrode 104b Metal electrode 104a, 104X2 Semiconductor electrode 105 Cathode electrode 106 Trench 106a side Wall surface 107 Insulating film 107a Recesses 107b, 107c Convex part 108 P-type layer 109 Trench 110 Silicon substrate 111 P-type layer 112 Photoresist 113 Insulating film 114 Groove 200, 200X, 200Y PIN diode 300 IGBT
301 N Base Layer 302, 303 Trench 304, 305 Gate Insulating Film 306, 307 Gate Electrode 308 P Base Layer 309 N Source Layer 310 Emitter Electrode 311 P-Type Layer 312 N Buffer Layer 313 P Emitter Layer 314 Collector Electrode 400 MOSFET
F1 Thickness direction S1, S2 Uneven surface L1 Distance W1 Groove width W2 Interval T1 to T4 Thickness H Height

Claims (7)

A first conductivity type semiconductor layer;
A first electrode and a second electrode arranged on both sides of the semiconductor layer in the thickness direction,
An insulating film formed in the semiconductor layer along the thickness direction of the semiconductor layer,
A vertical semiconductor device comprising: a third electrode that is formed along the insulating film and has the same polarity as the first electrode that attracts minority carriers in the semiconductor layer when in a non-conduction state,
The interface between the semiconductor layer and the insulating film forms an uneven surface ,
In the semiconductor device , the uneven surface of the insulating film has a height difference that is greater than 0.05, which is obtained by dividing the height difference by the repeating interval of the convex portions . A first conductivity type semiconductor layer;
A first electrode and a second electrode arranged on both sides of the semiconductor layer in the thickness direction,
An insulating film formed in the semiconductor layer along the thickness direction of the semiconductor layer,
A vertical semiconductor device comprising: a third electrode that is formed along the insulating film and has the same polarity as the first electrode that attracts minority carriers in the semiconductor layer when in a non-conduction state,
The interface between the semiconductor layer and the insulating film forms an uneven surface ,
The unevenness surface of the insulating film is a semiconductor device in which a height difference is larger than 0.1 μm . The insulation and the third electrode film, a semiconductor device positioned claims 1 or 2, wherein the inside of the trench formed in the semiconductor layer. The third electrode, the semiconductor device according to claim 1 which is formed by a semiconductor electrode according to the semiconductor film to one of claims 3. The uneven surface, the semiconductor device according to claim 1 which is formed into a continuous triangular shape in any of claims 4. The semiconductor device according to any one of the paragraphs claims 1-5 in which the unipolar type by the first electrode is in contact with the semiconductor layer. It said that the semiconductor layer of the second conductivity type is formed between the semiconductor layer and the first electrode, the semiconductor device according to any one of the paragraphs claims 1-5 which is a bipolar type.